Data processing method and device, electronic equipment and vehicle
By continuing to enable UART interrupts and disabling preset interrupts when the system disables target interrupts, the problem of being unable to locate fault information in the event of hardware interrupt deadlock is solved, and fault information can be sent without an emulator, reducing the impact on the normal operation of the system.
Patent Information
- Application Number
- CN202410318486.7
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-03-19
- Publication Date
- 2025-09-26
AI Technical Summary
When the system disables hardware interrupts and runs in a deadlock, the existing technology requires additional hardware simulator support to locate the fault message, and cannot send the fault information under the condition that the simulator is lacking or cannot be connected.
During the process of testing the program code of the application to be tested, if the currently executed operation is to turn off the target interrupt, the UART is controlled to continue to turn on the UART interrupt and turn off the preset interrupts except the UART interrupt; when the application to be tested is in the target state, the test data is obtained through the UART, and the UART interrupt and the preset interrupt are continued to be turned on.
It effectively reduces the interference of serial UART interrupts in the normal code execution process, and can locate abnormal information through simple serial port commands when the current state of the system cannot be located, reducing the impact on the normal operation of the system without the need for additional hardware emulator support.
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Figure CN120705026A_ABST
Abstract
Description
Technical Field
[0001] The present application relates to the field of computer processing technology, and in particular to a data processing method, device, electronic equipment and vehicle. Background Art
[0002] Operating system abnormalities and unresponsive serial ports typically occur because the system has disabled hardware interrupts and is locked, causing the system to remain in an interrupt-disabled state and unable to report serial interrupts. Consequently, the system freezes, and any character commands entered into the serial port are unresponsive, making it impossible to locate the software error. Furthermore, because the system does not enter the expected chip-configured exception handler, it is impossible to retrieve or export any current information.
[0003] Currently, when the system closes hardware interrupts and runs in a deadlock, it is mainly necessary to connect a hardware debugging emulator, such as JLINK, LauterBach, etc., to send serial port information.
[0004] However, this method requires additional hardware simulator support. If the simulator is lacking or cannot be connected, the fault message cannot be sent. Summary of the Invention
[0005] In view of this, the present application provides a data processing method, device, electronic device and vehicle, the main purpose of which is to improve the technical problem that the current existing technology requires additional hardware simulator support and cannot send fault messages when the simulator is lacking or cannot be connected.
[0006] In a first aspect, the present application provides a data processing method, comprising:
[0007] During the process of testing the program code of the application to be tested, if the currently executed operation is to disable the target interrupt, controlling the UART to continue to enable the UART interrupt and disable preset interrupts other than the UART interrupt; wherein the target interrupt includes the UART interrupt and the preset interrupt;
[0008] When the application to be tested is in a target state, test data of the application to be tested within a preset time period is obtained through the UART, UART interrupt is continuously enabled, and the preset interrupt is enabled; wherein the target state includes any one of an infinite loop and a deadlock.
[0009] In a second aspect, the present application provides a data processing device, comprising:
[0010] The control module is configured to, during the process of testing the program code of the application to be tested, control the UART to continue to enable the UART interrupt and disable preset interrupts other than the UART interrupt if the currently executed operation is to disable the target interrupt; wherein the target interrupt includes the UART interrupt and the preset interrupt;
[0011] The acquisition module is configured to obtain the test data of the application to be tested within a preset time period through the UART when the application to be tested is in a target state, continue to enable the UART interrupt, and enable the preset interrupt; wherein the target state includes any one of an infinite loop and a deadlock.
[0012] In a third aspect, the present application provides a computer-readable storage medium having a computer program stored thereon, which implements the method described in the first aspect when the computer program is executed by a processor.
[0013] In a fourth aspect, the present application provides an electronic device comprising a storage medium, a processor, and a computer program stored on the storage medium and executable on the processor, wherein the processor implements the method described in the first aspect when executing the computer program.
[0014] In a fifth aspect, the present application provides a vehicle, comprising: the device as described in the second aspect, or the electronic device as described in the fourth aspect.
[0015] By means of the above technical solution, the present application provides a data processing method, device, electronic device and vehicle. First, during the process of testing the program code of the application to be tested, if the currently executed operation is to disable the target interrupt, the UART is controlled to continue to enable the UART interrupt and disable preset interrupts other than the UART interrupt; wherein the target interrupt includes the UART interrupt and the preset interrupt; when the application to be tested is in the target state, the test data of the application to be tested within a preset time period is obtained through the UART, the UART interrupt is continued to be enabled, and the preset interrupt is enabled; wherein the target state includes any one of an infinite loop and a deadlock. Compared with the current existing technology, this embodiment can effectively reduce the interference of serial port UART interrupts in the normal code execution process by continuing to enable the UART interrupt and disabling preset interrupts other than the UART interrupt when executing the operation of disabling the target interrupt; since the operating system cannot obtain system information when the interrupt is disabled and deadlocked, this embodiment can locate abnormal information through simple serial port commands under the condition that the current state of the system cannot be located, and reasonably use UART interrupts to locate abnormal deadlock problems under the premise of reducing the impact on the normal operation of the system. The purpose of locating the deadlock problem of shutting down interrupts is achieved, and the impact on the normal code execution process is reduced. The fault information can be sent without the support of additional hardware emulators.
[0016] The above description is only an overview of the technical solution of the present application. In order to more clearly understand the technical means of the present application, it can be implemented in accordance with the contents of the specification. In order to make the above and other purposes, features and advantages of the present application more obvious and easy to understand, the specific implementation methods of the present application are listed below. BRIEF DESCRIPTION OF THE DRAWINGS
[0017] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present application and, together with the description, serve to explain the principles of the present application.
[0018] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, for ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.
[0019] Figure 1 A flow chart of a data processing method provided in an embodiment of the present application is shown;
[0020] Figure 2 A flow chart of a data processing method provided in an embodiment of the present application is shown;
[0021] Figure 3 A schematic diagram showing an example provided by an embodiment of the present application is shown;
[0022] Figure 4 A schematic diagram showing an example provided by an embodiment of the present application is shown;
[0023] Figure 5 A schematic diagram showing an example provided by an embodiment of the present application is shown;
[0024] Figure 6 A schematic diagram showing an example of a process provided by an embodiment of the present application
[0025] Figure 7 A structural diagram of a data processing device provided in an embodiment of the present application is shown. DETAILED DESCRIPTION
[0026] In order to more clearly understand the above-mentioned objectives, features and advantages of the present application, the scheme of the present application will be further described below. It should be noted that, in the absence of conflict, the embodiments of the present application and the features therein can be combined with each other.
[0027] In order to improve the current existing technology, additional hardware simulator support is required. If the simulator is lacking or cannot be connected, the fault message cannot be sent. This embodiment provides a data processing method, such as Figure 1 As shown, the method includes:
[0028] Step 101 : During the process of testing the program code of the application to be tested, if the currently executed operation is to disable the target interrupt, the UART is controlled to continue to enable the UART interrupt and disable the preset interrupts except the UART interrupt.
[0029] Among them, the target interrupt includes UART interrupt and preset interrupt.
[0030] In an embodiment of the present application, the application to be tested may be an application of a vehicle operating system, an application of a car computer operating system, and so on. Accordingly, the target interrupts are all interrupts in the program code of the application to be tested. There is a unified switch interrupt call entry for UART interrupts and preset interrupts. For example, the target switch interrupt call entry may be irq_disable.
[0031] In this embodiment, the Universal Asynchronous Receiver / Transmitter (UART) is a key module for asynchronous communication between devices. It is used to control the chip between the computer and serial devices. It provides an RS-232C data terminal equipment interface, so that the computer can communicate with a modem or other serial devices using the RS-232C interface.
[0032] Step 102: When the application to be tested is in the target state, test data of the application to be tested within a preset time period is obtained through the UART, and the UART interrupt is continued to be enabled, as well as the preset interrupt.
[0033] The target state includes any one of an infinite loop and a deadlock.
[0034] Optionally, the preset time period can be any time period during which the system is in the target state, and is not limited in the embodiments of the present application. For example, the end time of the preset time period is the actual time when the application under test is in the target state, and the start time of the preset time period is a specified time whose difference from the actual time is a preset value.
[0035] For example, taking the preset value of 5s as an example, if the actual time is 14:42:46 on March 19, 2024, the specified time is 14:42:41 on March 19, 2024, that is, the preset time period is the time period with 14:42:41 on March 19, 2024 as the starting point and 14:42:46 on March 19, 2024 as the end point.
[0036] In some examples, enabling a UART interrupt can be done by configuring the UART interrupt request as a Fast Interrupt Request (FIQ). In ARM, FIQ mode is a privileged mode and also an exception mode. It is used for high-speed data transmission or channel processing and is entered when a Fast Interrupt Request (FIQ) is triggered.
[0037] Accordingly, there are significant differences between FIQ and IRQ (external interrupt mode). FIQ mode must be processed as quickly as possible and exited after completion. IRQ mode can be interrupted by FIQ mode, but IRQ cannot interrupt FIQ mode. To make FIQ mode more responsive, FIQ mode has more shadow registers. FIQ mode must disable interrupts; if an interrupt routine must re-enable interrupts, IRQ mode should be used instead of FIQ mode.
[0038] Among them, the FIQ interrupt request can run normally when the system turns off hardware interrupts and runs deadlock.
[0039] For this embodiment, a hardware interrupt is an asynchronous signal indicating a need for attention or a change in the execution of a synchronous event. Hardware interrupts are a way to avoid wasting valuable processor time in a polling loop, waiting for external events. They can be implemented in hardware as a standalone control line system or integrated into the memory subsystem. Accordingly, a signal interruption occurs when a communication tool fails, preventing data from being transmitted normally.
[0040] Furthermore, deadlock, here referring to process deadlock, is a computer technology term. It is a state in operating systems or software: in a multitasking system, when one or more processes are waiting for system resources, and the resources are occupied by the process itself or another process, a deadlock occurs.
[0041] In an embodiment of the present application, when the system turns off hardware interrupts and runs in a deadlock, it is equivalent to a program failure that cannot be run. FIQ interrupt requests can run normally and issue a fault message when the system turns off hardware interrupts and runs in a deadlock.
[0042] In some examples, the fault information may include the corresponding fault location, fault condition, fault cause, and other information when the system turns off hardware interrupts and runs in a deadlock. The specific content of the fault information can be set according to needs.
[0043] Furthermore, the UART sends the operating system's fault information to the terminal device. After the terminal device receives the fault information, the programmer can perform system fault processing based on the fault information.
[0044] This embodiment effectively reduces interference from serial UART interrupts in the normal code execution process by continuing to enable UART interrupts and disabling all other preset interrupts except for the target interrupt while executing the operation to disable the target interrupt. Since the operating system cannot obtain system information when the interrupt is deadlocked, this embodiment can locate abnormal information through simple serial port commands even when the current system status cannot be determined. Furthermore, the UART interrupt is rationally used to locate abnormal deadlock issues while minimizing the impact on the normal operation of the system. This achieves the purpose of locating interrupt deadlock issues while reducing the impact on the normal code execution process, and can complete the transmission of fault information without the support of additional hardware emulators.
[0045] Further, as a refinement and extension of the above embodiment, in order to fully illustrate the specific implementation process of the method of the embodiment of the present disclosure, the embodiment of the present application provides the following Figure 2 The specific method shown includes:
[0046] Step 201 : During the process of testing the program code of the application to be tested, if the currently executed operation is to disable a target interrupt, obtain other interrupts having the same priority as the target interrupt.
[0047] Step 202: Adjust the priority of the UART interrupt among other interrupts from the first priority to the second priority, and control the UART to continue to enable the UART interrupt.
[0048] It should be noted that the first priority is lower than the second priority.
[0049] In an embodiment of the present application, the interrupt controller is an electronic device that serves as a priority arbiter. Specific functions may include: an 8-bit interrupt request register (IRR). It registers interrupt requests from external devices. A priority arbiter. It distinguishes between interrupt sources with requests in the IRR and interrupt sources being serviced to determine the interrupt request with the highest priority. An 8-bit interrupt in service register (ISR). Corresponding to each bit of the IRR, it records the interrupt request currently being processed. An interrupt mask register (IMR). The IMR is 8 bits. When the corresponding position is 1, the interrupt request of the corresponding bit in the IRR can be masked. A bus buffer. It is connected to the system's data bus and is an 8-bit bidirectional tri-state buffer. Writing command words to the 8259A and reading status information are both transmitted through this buffer. A read / write control logic. This logic circuit receives the port address signal and the CPU's read / write control signals IOW and IOR to generate corresponding control signals to control the writing of command words and the reading of status words. A cascade buffer and comparator. It is used to store and compare the identification codes of the slave chips 8259A in the system. Control logic. The control logic includes a set of registers used to store the 8259A's command words, enabling control of various operating modes. It also includes interrupt request and response circuits, which send interrupt requests to the CPU when an interrupt is requested and receive interrupt response signals from the CPU when it responds to an interrupt.
[0050] Step 203: other interrupts with the first priority level are used as preset interrupts, and the preset interrupts are disabled.
[0051] Optionally, step 203 may specifically include: obtaining all switch interrupt call entries; unifying all switch interrupt call entries to obtain a target switch interrupt call entry; using the target switch interrupt call entry to set other interrupts with the first priority as preset interrupts, and turning off the preset interrupts.
[0052] In an embodiment of the present application, the operating system may include many switch interrupt call entries. Unifying the switch interrupt call entries can simplify the subsequent procedures for changing the UART interrupt request at the entry and improve efficiency.
[0053] For example, the operating system switch interrupt is unified into a call entry, such as the interface irq_disable or irq_enable, and the internal implementation only turns off the normal interrupt irq. When the system is initialized during runtime, all module interrupts, including UART interrupts, are set to normal UART interrupts by default.
[0054] Step 204 : When the application to be tested is in the target state, obtain test data of the application to be tested within a preset time period through the UART, continue to enable the UART interrupt, and enable the preset interrupt.
[0055] The target state includes any one of an infinite loop and a deadlock.
[0056] Optionally, step 204 may specifically include: when the application to be tested is in the target state, obtaining test data of the application to be tested within a preset time period through UART, adjusting the priority of the UART interrupt from the second priority to the first priority, controlling the universal asynchronous receiver and transmitter UART to continue to enable the UART interrupt, and enabling the preset interrupt.
[0057] In an embodiment of the present application, the method of this embodiment further includes: performing data analysis on the test data to obtain at least one problem point in the program code.
[0058] Exemplarily, the irq_disable process may include: turning off all ordinary irq interrupts; configuring the UART interrupt (such as interrupt number 40) as a fiq interrupt through the group register of the GIC interrupt controller (Generic Interrupt Controller) such as GICD_IGROUPR, so that the UART serial port interrupt request is higher than the ordinary irq interrupt. Accordingly, the irq_enable process may include: setting the uart interrupt (such as interrupt number 40) back to the ordinary irq interrupt through the group register of the GIC interrupt controller (Generic Interrupt Controller) such as GICD_IGROUPR; turning on and enabling all ordinary irq interrupts.
[0059] Among them, the FIQ interrupt request can run normally when the system turns off hardware interrupts and runs deadlock.
[0060] In an embodiment of the present application, the FIQ of the UART will be pre-configured at the target interrupt call entry and the target interrupt call exit. Two operating conditions will occur during the operation of the operating system. One operating condition is that the operating system turns off the hardware interrupt and runs deadlocked during the operation. In this case, the UART interrupt request will be triggered to change to FIQ. The UART can send the operating system's fault information to the terminal device. The terminal device receives the sent fault information, and the programmer will process the system according to the received fault information; the other situation is that the operating system does not turn off the hardware interrupt and runs deadlocked during the operation. The operating system program runs normally. When it runs to the target interrupt call entry, the UART interrupt request will be changed from IRQ to FIQ. After the change, the program continues to run. When it runs to the target interrupt call exit, the UART interrupt request will be changed from FIQ to IRQ again.
[0061] In some cases, operating system anomalies and unresponsive serial ports often occur because the system has disabled hardware interrupts and is locked, causing the system to remain in an interrupt-disabled state and unable to report serial interrupts. Consequently, the system freezes, and any character commands entered into the serial port are unresponsive, making it impossible to locate the software error. Furthermore, because the system does not enter the expected chip-defined exception handler, it is impossible to retrieve or export any current information.
[0062] Generally, locating this problem requires connecting to a hardware debugging emulator, such as JLINK or LauterBach. This method requires additional hardware emulator support. If the emulator is not available or cannot be connected, the problem cannot be located.
[0063] Currently, a software-based approach utilizes the high-priority FIQ fast interrupt provided by the chip. For example, ARM chips define its trigger priority as higher than all standard IRQ interrupts. This approach involves setting the serial port UART interrupt as a FIQ interrupt, while setting the interrupts for other modules required for system operation as IRQs. Disabling interrupts in the system only disables the IRQ, not the FIQ. During system operation anomalies, the UART FIQ interrupt can respond normally, allowing the FIQ to trigger commands and even retrieve system-related information. However, this design results in an excessively high UART interrupt request, surpassing the priority of other modules during normal system operation, potentially impacting system operation even during normal serial port use.
[0064] like Figure 3 This is the solution to the problem. Shutting down the dead loop is a common and difficult-to-locate problem in system operation. It is usually caused by code or logic problems. In this case, an external simulator is generally used to analyze the current scene through the simulator's supporting tools.
[0065] In fact, you can also Figure 4 The software solution shown in the figure promotes special modules such as UART interrupts to FIQ high-priority interrupts. When the interrupt operation is disabled, only low-priority common interrupts are disabled. When the interrupt is deadlocked, the UART interrupt can still be triggered to interrupt the crash site and analyze it, but there will be problems such as Figure 5 The problem shown is that when the program is running normally, the UART interrupt request is too high, which may affect the normal operation of the program.
[0066] Compared with the current existing technology, this embodiment can effectively reduce the interference of serial UART interrupts in the normal code execution process by continuing to enable UART interrupts and disabling preset interrupts other than the UART interrupt when executing the operation of disabling the target interrupt. Since the operating system cannot obtain system information when the interrupt is deadlocked, this embodiment can locate abnormal information through simple serial port commands under the condition that the current state of the system cannot be located, and reasonably use UART interrupts to locate abnormal deadlock problems under the premise of reducing the normal operation of the system. After the interrupt is enabled, the UART interrupt is immediately restored to a normal IRQ interrupt; the purpose of locating the deadlock problem of disabling interrupts is achieved, and the impact on the normal code execution process is reduced. The fault information can be sent without the support of additional hardware emulators.
[0067] Furthermore, in order to fully illustrate the specific implementation process of the method of this embodiment, this embodiment provides the following examples, such as Figure 6 As shown, but not limited to.
[0068] Obtain all switch interrupt call entries contained in the operating system; uniformly process all switch interrupt call entries to obtain a target switch interrupt call entry. In response to the initialization of the operating system, determine the interrupt request corresponding to the operating system as an interrupt request IRQ, wherein the UART with the interrupt request IRQ cannot operate normally when the system turns off hardware interrupts and runs in a deadlock. Obtain the first interrupt information corresponding to the universal asynchronous receiver transmitter UART from the target switch interrupt call entry contained in the operating system; determine the first interrupt number corresponding to the first interrupt information, and determine the first change position for changing the interrupt request through the first interrupt number; change the UART interrupt request from IRQ to FIQ at the first change position through the group register of the interrupt controller GIC; obtain the second interrupt information corresponding to the UART in the target switch interrupt call exit corresponding to the target switch interrupt call entry; determine the second interrupt number corresponding to the second interrupt information, and determine the second change position for changing the interrupt request through the second interrupt number; change the UART interrupt request from FIQ to IRQ at the second change position through the group register of the GIC. In response to the operating system disabling hardware interrupts and running in a deadlock, triggering the operation of a UART with an interrupt request of FIQ, wherein the UART with an interrupt request of FIQ can operate normally when the system disabling hardware interrupts and running in a deadlock; sending the operating system's fault information to the terminal device through the UART with an interrupt request of FIQ.
[0069] For example, the operating system switch interrupt is unified into a call entry, such as the interface irq_disable / irq_enable, and the internal implementation only turns off the normal interrupt irq;
[0070] When the system is initialized during runtime, all module interrupts, including UART interrupts, are set to normal UART interrupts by default;
[0071] At the unified entry irq_disable, the UART interrupt is set as a FIQ interrupt separately, and the UART interrupt is set back to the IRQ interrupt at irq_enable; wherein, the irq_disable process includes: turning off all ordinary irq interrupts; configuring the uart interrupt (such as interrupt number 40) as a fiq interrupt through the group register of the GIC interrupt controller (Generic Interrupt Controller) such as GICD_IGROUPR, then the UART serial port interrupt request is higher than the ordinary irq interrupt; the irq_enable process includes: setting the uart interrupt (such as interrupt number 40) back to the ordinary irq interrupt through the group register of the GIC interrupt controller (Generic Interrupt Controller) such as GICD_IGROUPR; turning on and enabling all ordinary irq interrupts.
[0072] When a deadlock occurs due to interrupt shutdown, the exception scene can still be obtained and analyzed by activating FIQ through UART.
[0073] That is, only at the system interrupt disable entry point, the UART is set as a high-priority FIQ interrupt, and during normal operation, it remains a normal interrupt. This can not only locate the problem of interrupt disablement deadloop through the UART, but also reduce the impact on normal system operation.
[0074] Compared with the current existing technology, this embodiment can effectively reduce the interference of serial UART interrupts in the normal code execution process by continuing to enable UART interrupts and disabling preset interrupts other than the UART interrupt when executing the operation of disabling the target interrupt. Since the operating system cannot obtain system information when the interrupt is deadlocked, this embodiment can locate abnormal information through simple serial port commands under the condition that the current state of the system cannot be located, and reasonably use UART interrupts to locate abnormal deadlock problems under the premise of reducing the normal operation of the system. After the interrupt is enabled, the UART interrupt is immediately restored to a normal IRQ interrupt; the purpose of locating the deadlock problem of disabling interrupts is achieved, and the impact on the normal code execution process is reduced. The fault information can be sent without the support of additional hardware emulators.
[0075] Further, as Figure 1 and Figure 2 The specific implementation of the method shown in this embodiment provides a data processing device, such as Figure 7 As shown, the device includes: a control module 31 and an acquisition module 32.
[0076] The control module 31 is configured to, during the process of testing the program code of the application to be tested, control the UART to continue to enable the UART interrupt and disable preset interrupts other than the UART interrupt if the currently executed operation is to disable the target interrupt; wherein the target interrupt includes the UART interrupt and the preset interrupt;
[0077] The acquisition module 32 is configured to obtain the test data of the application to be tested within a preset time period through the UART when the application to be tested is in a target state, continue to enable the UART interrupt, and enable the preset interrupt; wherein the target state includes any one of an infinite loop and a deadlock.
[0078] In a specific application scenario, the control module 31 is specifically configured to, during the process of testing the program code of the application to be tested, if the currently executed operation is to turn off the target interrupt, obtain other interrupts with the same priority as the target interrupt; adjust the priority of the UART interrupt among the other interrupts from the first priority to the second priority, and control the universal asynchronous receiver transmitter UART to continue to turn on the UART interrupt; use the other interrupt with the first priority as a preset interrupt, and turn off the preset interrupt.
[0079] In a specific application scenario, the acquisition module 32 is specifically configured to obtain the test data of the application to be tested within a preset time period through the UART when the application to be tested is in the target state, adjust the priority of the UART interrupt from the second priority to the first priority, control the universal asynchronous receiver and transmitter UART to continue to enable the UART interrupt, and enable the preset interrupt.
[0080] In a specific application scenario, the control module 31 is specifically configured to obtain all switch interrupt call entries; unify all the switch interrupt call entries to obtain a target switch interrupt call entry; use the target switch interrupt call entry to set the other interrupt with the first priority as a preset interrupt, and turn off the preset interrupt.
[0081] In a specific application scenario, the first priority is lower than the second priority.
[0082] In a specific application scenario, the acquisition module 32 is further configured to perform data analysis on the test data to obtain at least one problem point in the program code.
[0083] It should be noted that for other corresponding descriptions of the functional units involved in the data processing device provided in this embodiment, please refer to Figure 1 and Figure 2 The corresponding description in will not be repeated here.
[0084] Based on the above Figure 1 and Figure 2 The method shown in FIG. 1 is a method for performing the above-mentioned operation. Accordingly, the embodiment of the present disclosure further provides a computer-readable storage medium having a computer program stored thereon. When the computer program is executed by a processor, the above-mentioned operation is performed. Figure 1 and Figure 2 The method shown.
[0085] Based on this understanding, the technical solution of the present disclosure can be embodied in the form of a software product, which can be stored in a non-volatile storage medium (which can be a CD-ROM, USB flash drive, mobile hard disk, etc.), and includes a number of instructions for enabling a computer device (which can be a personal computer, server, or network device, etc.) to execute the methods of various implementation scenarios of the present disclosure.
[0086] Based on the above Figure 1 and Figure 2 The method shown, and Figure 7 In order to achieve the above-mentioned purpose, the embodiment of the present disclosure further provides an electronic device that can be configured on a computer terminal, etc. The device includes a storage medium and a processor; the storage medium is used to store a computer program; the processor is used to execute the computer program to achieve the above-mentioned Figure 1 and Figure 2 The method shown.
[0087] In some embodiments, the physical device may further include a user interface, a network interface, a camera, a radio frequency (RF) circuit, a sensor, an audio circuit, a Wi-Fi module, etc. The user interface may include a display, an input unit such as a keyboard, etc. Optional user interfaces may also include a USB interface, a card reader interface, etc. In some embodiments, the network interface may include a standard wired interface, a wireless interface (such as a Wi-Fi interface), etc.
[0088] Those skilled in the art will understand that the above-mentioned physical device structure provided in the embodiments of the present disclosure does not constitute a limitation on the physical device, and may include more or fewer components, or a combination of certain components, or different component arrangements.
[0089] The storage medium may also include an operating system and a network communication module. The operating system is a program that manages the hardware and software resources of the physical device, supporting the execution of information processing programs and other software and / or programs. The network communication module is used to enable communication between components within the storage medium, as well as with other hardware and software within the physical information processing device.
[0090] Based on the above electronic device, the embodiment of the present disclosure further provides a vehicle, which may specifically include: Figure 6 The device shown or the electronic device as described above. The vehicle can be a new energy vehicle or a traditional vehicle.
[0091] Through the description of the above disclosed implementation methods, those skilled in the art can clearly understand that the present disclosure can be implemented by means of software plus the necessary general hardware platform, or can be implemented by hardware. Compared with the current existing technology, this embodiment can effectively reduce the interference of serial port UART interrupts in the normal code execution process by continuing to turn on the UART interrupt and turning off the preset interrupts other than the UART interrupt when executing the operation of turning off the target interrupt; because the operating system cannot obtain system information when the interrupt is deadlocked, this embodiment can locate abnormal information through simple serial port commands under the condition that the current state of the system cannot be located, and reasonably use UART interrupts to locate abnormal deadlock problems under the premise of reducing the normal operation of the system. It not only achieves the purpose of locating the deadlock problem of turning off the interrupt, but also reduces the impact on the normal code execution process, and can complete the sending of fault information without the support of additional hardware emulators.
[0092] It should be noted that, in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations. Moreover, the term "comprises" or any other variant thereof is intended to cover non-exclusive inclusion, so that a process, method, article or device that includes a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the sentence "comprise a..." do not exclude the presence of other identical elements in the process, method, article or device that includes the elements.
[0093] The foregoing description is intended only to provide specific embodiments of the present disclosure, intended to enable those skilled in the art to understand and implement the present disclosure. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the present disclosure. Therefore, the present disclosure is not intended to be limited to the embodiments described herein, but rather to be construed in the broadest manner consistent with the principles and novel features claimed herein.
Claims
1. A data processing method, characterized in that: include: During the process of testing the program code of the application to be tested, if the currently executed operation is to disable a target interrupt, controlling a universal asynchronous receiver transmitter (UART) to continue enabling the UART interrupt and disabling preset interrupts other than the UART interrupt; wherein the target interrupt includes the UART interrupt and the preset interrupt; When the application to be tested is in a target state, test data of the application to be tested within a preset time period is obtained through the UART, UART interrupt is continuously enabled, and the preset interrupt is enabled; wherein the target state includes any one of an infinite loop and a deadlock.
2. The method according to claim 1, characterized in that In the process of testing the program code of the application to be tested, if the currently executed operation is to disable the target interrupt, controlling the universal asynchronous receiver transmitter UART to continue to enable the UART interrupt and disable preset interrupts other than the UART interrupt, including: In the process of testing the program code of the application to be tested, if the currently executed operation is to disable the target interrupt, obtaining other interrupts with the same priority as the target interrupt; Adjusting the priority of the UART interrupt in the other interrupts from the first priority to the second priority, and controlling the universal asynchronous receiver transmitter UART to continue to enable the UART interrupt; The other interrupt with the first priority is used as a preset interrupt, and the preset interrupt is disabled.
3. The method according to claim 2, characterized in that When the application to be tested is in a target state, obtaining test data of the application to be tested within a preset time period through the UART, continuing to enable the UART interrupt, and enabling the preset interrupt, including: When the application to be tested is in the target state, the test data of the application to be tested within a preset time period is obtained through the UART, the priority of the UART interrupt is adjusted from the second priority to the first priority, the UART is controlled to continue to enable the UART interrupt, and the preset interrupt is enabled.
4. The method according to claim 2, characterized in that The step of using the other interrupt with the first priority as a preset interrupt and disabling the preset interrupt includes: Get all switch interrupt call entries; Unifying all the switch interrupt call entries to obtain a target switch interrupt call entry; The other interrupt with the first priority is used as a preset interrupt through the target switch interrupt call entry, and the preset interrupt is turned off.
5. The method according to claim 2 or 3, characterized in that The first priority is lower than the second priority.
6. The method according to claim 1, characterized in that The method further comprises: The test data is analyzed to obtain at least one problem point in the program code.
7. A data processing device, characterized in that: The device comprises: The control module is configured to, during the process of testing the program code of the application to be tested, control the UART to continue to enable the UART interrupt and disable preset interrupts other than the UART interrupt if the currently executed operation is to disable the target interrupt; wherein the target interrupt includes the UART interrupt and the preset interrupt; The acquisition module is configured to obtain the test data of the application to be tested within a preset time period through the UART when the application to be tested is in a target state, continue to enable the UART interrupt, and enable the preset interrupt; wherein the target state includes any one of an infinite loop and a deadlock.
8. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the method according to any one of claims 1 to 6 is implemented.
9. An electronic device comprising a storage medium, a processor, and a computer program stored on the storage medium and executable on the processor, wherein: When the processor executes the computer program, the method according to any one of claims 1 to 6 is implemented.
10. A vehicle, characterized in that: include: The apparatus according to claim 7, or the electronic device according to claim 9.