Novel wafer layout and cutting calculation method

Abstract

The invention provides a novel wafer layout and cutting calculation method, relates to the technical field of semiconductor chip manufacturing, and aims to optimize wafer layout by distinguishing a Shot interval and a Die interval and combining a graph periodic layout tree structure, remarkably improve the number of chips (DPW), effectively improve the wafer utilization rate, break through the limitation of a traditional method and improve the wafer cutting efficiency. Independent spacing constraints are input in Sp1, Sp2 constructs a periodic tree structure, optimal layout is searched in Sp3 and Sp4 through iteration and traversal, the DPW is improved from 624 to 637, the amplification is about 2.1%, benefited from innovative application of the self-adaptive step length and pruning algorithm, the marginal space is accurately captured, waste is eliminated through secondary fine tuning, geometric transformation of a non-rectangular Die shape is supported, and the method is suitable for large-scale popularization and application. The wafer area potential is further released, the breakthrough spacing optimization capability provides a higher-efficiency solution for semiconductor manufacturing, and the method has remarkable creative significance.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor chip manufacturing, and in particular to a novel wafer layout and cutting calculation method. Background Art

[0002] According to a semiconductor chip dicing method disclosed in China with the publication number "CN118943068A", which relates to the field of semiconductor technology, the method includes: placing a target semiconductor wafer on a dicing machine to obtain a positioning authentication result; when the positioning authentication result is authentication passed, activating a high-speed camera to obtain a wafer surface image; performing a mountain simulation to determine multiple shape features and multiple warping features of multiple divided areas; performing dicing path identification to determine a first dicing path; performing dicing parameter determination at multiple key dicing points to obtain multiple key dicing parameter sets, and dicing the target semiconductor wafer. The present invention solves the technical problem of low dicing accuracy and efficiency in the prior art when processing irregularly shaped or warped semiconductor chips, and achieves the technical effect of significantly improving dicing accuracy and efficiency through precise positioning and feature recognition.

[0003] According to a wafer cutting method disclosed in China with the publication number "CN119036656A", the method includes: providing a wafer, wherein the wafer has a plurality of tube core areas and a cutting road area located between adjacent tube core areas; cutting a first cutting path in the cutting road area; and cutting an additional cutting path on at least one of the opposite sides of the first cutting path in the cutting road area; wherein the first cutting path and the additional cutting path overlap with each other to form a combined cutting path.

[0004] The above patent documents and prior art have the following technical problems when used:

[0005] Problem 1: Traditional wafer dicing algorithms typically use a unified pitch calculation, which cannot adapt to the reality that the shot pitch (e.g., 50μm) and die pitch (e.g., 10μm) in stepper lithography machines are different, resulting in wasted space.

[0006] Problem two: existing technologies lack efficiency and dynamism in layout calculations. Serial calculations are time-consuming and cannot adapt to real-time parameter changes. For example, the entire layout needs to be recalculated after the die size is adjusted, which is not conducive to practical use and affects computing efficiency. Summary of the Invention

[0007] Technical problems solved

[0008] In view of the shortcomings of the existing technology, the present invention provides a new wafer layout and cutting calculation method, which solves the following problems:

[0009] 1. Address the problem of area waste caused by incorrect spacing assumptions and shape limitations in traditional methods;

[0010] 2. Address the problems of low computational efficiency and poor dynamic adaptability of traditional methods.

[0011] Technical Solution

[0012] To achieve the above objectives, the present invention is implemented through the following technical solutions: a novel wafer layout and cutting calculation method, the method comprising the following steps:

[0013] Sp1: Input wafer size, shot size, die size, and spatial periodicity parameters Px and Py of shot in the X and Y directions, where Px and Py reflect the periodic arrangement of shot and mechanical device constraints, and support the input of non-rectangular die shapes;

[0014] Sp2: Based on the input parameters, a graphical periodic layout tree structure is established. This structure maps the periodic distribution of shots on the wafer surface and supports subsequent layout optimization through a tree search algorithm.

[0015] Sp3: Use an iterator to adjust the wafer center position in the spatial periodic grid of Shot, calculate the periodic arrangement of Shot and the distribution of Die within Shot for each position, and generate multiple candidate layout solutions;

[0016] Sp4: Search all candidate layout solutions by traversing the graph periodized layout tree structure, calculate the number of chips (DPW) of each solution, and select the layout with the largest DPW as the optimal solution;

[0017] Sp5: Outputs the optimal layout solution, including the wafer center position, periodic arrangement of shots, distribution of dies, and the final DPW value, and generates visual results.

[0018] Preferably, the parameters input in step Sp1 further include independent constraints of shot spacing and die spacing, and the non-rectangular die is geometrically transformed by the preprocessing module to generate a minimum enclosing rectangle suitable for periodic calculation, thereby improving the accuracy of layout calculation.

[0019] Preferably, the construction of the graph periodic layout tree structure in step Sp2 includes defining the periodic boundary conditions of Shot, and introducing a weight factor to balance the difference between Shot spacing and Die spacing, thereby optimizing the search efficiency of the tree structure.

[0020] Preferably, the iterator in step Sp3 adopts an adaptive step adjustment strategy to dynamically adjust the moving step of the wafer center position according to the wafer size and Shot periodicity parameters to reduce redundant calculations and improve iteration efficiency.

[0021] Preferably, the traversal search in step Sp4 is further combined with a pruning algorithm to remove branches with DPW lower than a preset threshold in the graph periodic layout tree, thereby reducing computational complexity and accelerating the selection of the optimal solution.

[0022] Preferably, outputting the optimal layout solution in step Sp5 includes generating multi-dimensional comparison data, specifically including comparing with the results of existing online calculation methods, quantifying DPW gains and displaying the spatial distribution of layout optimization in the form of a heat map.

[0023] Preferably, the method further includes an adaptive optimization step, and performs secondary fine-tuning on the optimal layout solution after step Sp4, eliminating edge waste by locally adjusting the Shot boundary and Die arrangement, thereby maximizing the DPW gain.

[0024] Preferably, the method is executed by a computer system, which includes an input module, a tree construction module, a parallel computing module, an iterative optimization module and a search module. The tree construction module and the iterative optimization module are connected through a bidirectional data flow, supporting dynamic updating of the layout tree structure to adapt to real-time parameter changes. The parallel computing module uses multi-threading technology to simultaneously process layout calculations of multiple wafer center positions, and integrates a priority queue in the search module to accelerate the convergence of the optimal solution.

[0025] Beneficial effects

[0026] The present invention provides a novel wafer layout and cutting calculation method. It has the following beneficial effects:

[0027] 1. The present invention optimizes wafer layout by distinguishing between shot spacing and die spacing and combining a graphic periodic layout tree structure, significantly increasing the number of chips (DPW), effectively improving wafer utilization, and breaking through the limitations of traditional methods. Independent spacing constraints are input in Sp1, a periodic tree structure is constructed in Sp2, and the optimal layout is searched through iteration and traversal in Sp3 and Sp4, increasing DPW from 624 to 637, an increase of approximately 2.1%. Thanks to the innovative application of adaptive step size and pruning algorithm, it not only accurately captures edge space, but also eliminates waste through secondary fine-tuning, supports geometric transformation of non-rectangular die shapes, and further releases the potential of wafer area. The breakthrough spacing optimization capability provides a more efficient solution for semiconductor manufacturing and has significant creative significance.

[0028] 2. The present invention uses modular design and parallel computing optimization of computer systems to achieve efficient dynamic adjustment of wafer layout, greatly improving computing performance. In Sp2 and Sp4, the bidirectional data flow between the tree construction module and the iterative optimization module supports dynamic update of the layout tree. When the die size is adjusted, the tree structure is reconstructed immediately. The parallel computing module uses multi-threading and priority queues to process multiple center positions simultaneously in Sp3 and Sp4, shortening the 10-second calculation to 2 seconds and accelerating the convergence of the optimal solution (such as increasing DPW from 612 to 616). The innovative combination of pruning algorithm and GPU acceleration reduces redundant calculations and optimizes the search path. The multi-dimensional comparison and heat map output by Sp5 provide users with intuitive decision-making basis. The breakthrough not only improves the real-time performance of layout calculation, but also provides scalability for large-scale wafer design, demonstrating creative technological progress. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] Figure 1 A diagram showing the steps of the method of the present invention;

[0030] Figure 2 It is a structural diagram of the system composition of the present invention;

[0031] Figure 3 This is a system hardware diagram of the present invention;

[0032] Figure 4 A layout calculation diagram for the present invention;

[0033] Figure 5 Calculate the optimal layout solution for the present invention when the shot and die spacing are different;

[0034] Figure 6 The algorithm result of the present invention to improve DPW Figure 1 ;

[0035] Figure 7 The algorithm result of DPW improvement of the present invention Figure 2 . DETAILED DESCRIPTION

[0036] The following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of the present invention. Specific embodiment one:

[0038] like Figures 1 to 7 As shown, a novel wafer layout and cutting calculation method includes the following steps:

[0039] Sp1: Input wafer, shot, and die parameters and perform preprocessing: After collecting and standardizing all parameters required for wafer layout calculation and laying the foundation for subsequent optimization, starting from the user or system interface, the user inputs the wafer size (usually diameter, such as 300mm), shot size (length and width of a single exposure area), die size (length and width of a single chip), and the spatial periodicity parameters Px and Py of the shot in the X and Y directions. Px and Py not only reflect the periodic arrangement of the shot, but are also directly affected by the mechanical constraints of the stepper lithography machine, reflecting the characteristics of the equipment. In addition, the input parameters further include independent constraints on the shot spacing and die spacing. For example, the shot spacing may be 50μm and the die spacing is 10μm. This solves the defect of the unified spacing in the existing technology and supports the input of non-rectangular die shapes (such as hexagonal or L-shaped chips). The preprocessing module performs geometric transformation on the non-rectangular die and generates a minimum enclosing rectangle suitable for periodic calculation. For example, the circumscribed rectangle size of a non-rectangular die is calculated as the length and width boundaries to ensure compatibility with subsequent calculations. In terms of workflow, input data first undergoes verification checks (e.g., whether the dimensions are reasonable). The preprocessing module then performs geometric transformation and parameter standardization, outputting a structured parameter set (e.g., in JSON format) that is directly passed to Sp2. This step not only collects basic data but also improves the accuracy and flexibility of layout calculations by distinguishing spacing and handling non-rectangular shapes, providing high-quality input for subsequent optimization.

[0040] Sp2: Establishing a graphical periodic layout tree structure: This is the core modeling stage. Through mathematical and algorithmic means, the wafer surface is abstracted into an optimizable data structure to provide support for subsequent layout searches. Based on the parameter set output by Sp1, the system first defines the periodic boundary conditions of the shot. For example, based on Px and Py, the grid distribution of the shot on the wafer is determined (e.g., one shot every Px in the X direction and one shot every Py in the Y direction), forming a two-dimensional periodic grid. Next, a graphical periodic layout tree structure is constructed, which maps the periodic distribution of the shot into a tree hierarchy. Each node represents a shot position, the child nodes reflect the possibility of die arrangement within the shot, and the root node corresponds to the starting state of the entire wafer layout. To optimize the search efficiency of the tree structure, a weight factor is introduced to balance the difference between the shot spacing and the die spacing. For example, if the shot spacing is much larger than the die spacing, the weight factor adjusts the tree depth to prioritize the exploration of the shot distribution scheme. First, the total number of shots that can be accommodated on the wafer surface is calculated (such as estimating the shot grid based on Px = 50mm and Py = 40mm on a 300mm wafer). Then, the tree structure is initialized through a tree search algorithm (such as the preprocessing of the depth-first search) to generate a model that contains all possible shot distributions. Functionally, this step transforms complex spatial periodic problems into a computable tree structure, which not only maps the distribution relationship between shots and dies, but also improves the pertinence and efficiency of subsequent searches through weight optimization, laying the foundation for efficient iterations of Sp3 and Sp4.

[0041] Sp3: Iteratively adjust the wafer center position and generate candidate layouts: It is a dynamic process of layout generation. The iterator explores different positions of the wafer center, calculates multiple layout schemes, and provides a candidate set for optimal solution screening. Starting from the tree structure of Sp2, the iterator adjusts the wafer center position in the spatial periodic grid of Shot. For example, the initial position is set to the grid origin (0, 0), and then moves step by step along the X and Y directions according to the period of Px and Py (such as (0, Py), (Px, 0)). To improve efficiency, the iterator adopts an adaptive step adjustment strategy to dynamically adjust the moving step according to the wafer size and Shot periodic parameters. For example, the step size is reduced when approaching the wafer edge (such as Px / 2) to capture edge layout changes. For each center position, the system calculates the periodic arrangement of Shot (such as filling the grid based on Px and Py), and determines the distribution of Die in each Shot (considering Die spacing and boundary constraints), generates a candidate layout solution, and records its DPW value. The iterator first initializes the position list, and then loops through each position. Each time the layout calculation function is called, the coordinate set of Shot and Die is generated, and it is checked whether it exceeds the wafer boundary (through the circular boundary formula x 2 +y 2 ≤r 2Verification), and finally output a set of candidate layouts (e.g., 10 positions corresponding to 10 layouts). This step not only generates diverse layout options through adaptive iteration and precise calculation, but also reduces redundant calculations (avoiding invalid positions), providing rich candidate data for Sp4 optimization.

[0042] Sp4: Traversal search and optimization of the optimal layout solution: Find the optimal solution from the candidate layouts of Sp3 through traversal and screening, and further improve the results through secondary fine-tuning. The running solution is based on the graphical periodic layout tree structure of Sp2 and the candidate layout set of Sp3. The system starts a traversal search and first calculates the DPW for each candidate layout. For example, the total is obtained by multiplying the number of shots by the number of dies in each shot. To speed up the screening, the pruning algorithm is combined to remove branches in the tree with DPW lower than the preset threshold (such as lower than 90% of the results of existing online calculators) to reduce the computational complexity. For example, if the preliminary DPW of a branch is only 500 and the target is 600, its child nodes are directly skipped for exploration. After the search is complete, the layout with the largest DPW is selected as the preliminary optimal solution. Furthermore, the adaptive optimization steps are integrated here to perform secondary fine-tuning on the preliminary optimal solution. For example, by locally adjusting the shot boundary (e.g., a slight shift of 0.1 mm) or the die arrangement (e.g., rotating the non-rectangular die angle), edge waste (e.g., underutilized blank areas at the wafer edge) is eliminated, ultimately maximizing the DPW gain. The system first traverses the tree structure to calculate the DPW, applies pruning, and locks the preliminary solution. Then, through fine-tuning iterations (e.g., 10 local adjustments), the final layout is output. Traversal and pruning are used to efficiently screen the optimal solution, and fine-tuning overcomes the limitations of the preliminary solution, significantly increasing the number of chips compared to existing technologies (e.g., from 624 to 637).

[0043] Sp5: Output the optimal layout solution and generate visual results: Integrate and present the optimization results to the user to support subsequent manufacturing applications. The running plan is based on the optimal layout plan of Sp4, and the system outputs detailed results, including the coordinates of the wafer center position (such as (x0, y0)), the periodic arrangement of the shot (such as a grid coordinate list), the distribution of the die within the shot (such as the number and position of the die in each shot), and the final DPW value (such as 637). In addition, multi-dimensional comparative data is generated and compared with the existing online calculation method (such as the results of sil icon-edge.co.uk), quantifying the DPW gain (such as an increase of 2.1%), and displaying the spatial distribution of the layout optimization in the form of a heat map, for example, using color depth to represent the die density to highlight the effect of edge optimization. The system first integrates the calculation results of Sp4, calls the visualization module to generate graphics (such as SVG or PNG format), and then encapsulates the data and graphics into a report file (such as PDF) and outputs it through the user interface. It not only provides accurate layout parameters, but also intuitively demonstrates the superiority of the method through comparison and visualization (such as DPW gain of 0% to 3%), providing comprehensive support for user decision-making and process implementation.

[0044] The entire method is implemented through a computer program, forming a closed-loop optimization process from the input of Sp1 to the output of Sp5. The operation plan is guided by the needs of semiconductor manufacturing. It targets the pain points of the difference in shot and die spacing during wafer cutting, and innovatively improves layout efficiency through periodic tree structures and iterative searches. The workflow is executed in sequence: Sp1 collects and preprocesses data, Sp2 builds an optimization model, Sp3 generates candidate solutions, Sp4 screens and fine-tunes the optimal solution, and Sp5 outputs the results and verifies the effect. The functions of each step are closely connected. Sp1 ensures data quality, Sp2 provides a computing framework, Sp3 and Sp4 collaboratively optimize the layout, and Sp5 presents the results. The overall process runs on standard computer hardware (such as equipped with a CPU and optional GPU). DPW is improved through algorithmic innovations (such as pruning and fine-tuning), which solves the defect of waste of wafer area in existing technologies. Specific embodiment two:

[0046] like Figures 1 to 7 As shown, based on the content in the above specific embodiments, the following contents are further disclosed:

[0047] The method of the entire specific embodiment 1 is executed by a computer system, which includes an input module, a tree construction module, a parallel computing module, an iterative optimization module, and a search module. The modules work together to optimize wafer layout and cutting calculations, significantly improving the number of chips (DiesPerWafer, DPW), and further includes the following contents:

[0048] Input module: It is the starting point of the entire system and is responsible for receiving, verifying and standardizing the wafer layout parameters provided by the user, providing a high-quality data basis for subsequent calculations. Starting from the user interaction interface, the user enters the wafer size (such as diameter 300mm), Shot size (such as 50mm×40mm), Die size (such as 5mm×4mm), Shot spatial periodicity parameters Px and Py in the X and Y directions (such as Px=50mm, Py=40mm), and independent Shot spacing and Die spacing through the graphical interface or command line. Constraints (such as 50μm shot spacing and 10μm die spacing) are supported, and non-rectangular die input (such as the vertex coordinates of hexagonal dies) are supported. The integrity and rationality of the input data are first verified, for example, by checking whether the wafer diameter is positive and whether the shot size is smaller than the wafer size. The non-rectangular die is then geometrically preprocessed, and its minimum enclosing rectangle is calculated through an algorithm (such as circumscribing a hexagon as a 5.2mm×4.5mm rectangle). All parameters are standardized into a unified format (such as a floating-point array or JSON object). The process involves data parsing and conversion, such as parsing the user-entered string "300mm" into the value 300.0, and recording logs to track input history. Not only does it collect basic parameters, but it also improves data adaptability through preprocessing. For example, the difference in shot and die spacing is explicitly encoded as a constraint. The output structured parameter set is directly passed to the tree-building module, ensuring that subsequent modules can seamlessly use this data, thus laying a precise foundation for the entire optimization process.

[0049] Tree construction module: It is the core modeling unit of the system, responsible for converting input parameters into an optimizable graphical periodic layout tree structure, providing a mathematical framework for layout calculations. Based on the parameter set passed by the input module, the module first calculates the periodic grid of the shot on the wafer surface. For example, based on Px=50mm and Py=40mm, the maximum number of shots that can be accommodated on a 300mm wafer (about 6×7 shots) is determined, and then the periodic boundary conditions are defined (such as the shot coordinates at the grid boundary). Next, a tree structure is constructed, where the root node represents the entire wafer layout, the next layer of nodes represents the possible shot distribution (such as the grid filling starting from the upper left corner), and the child nodes further reflect the possibility of die arrangement within each shot (such as arranging 4×5 dies based on die spacing). , a tree is generated by initializing the algorithm. For example, depth-first search preprocessing is used to generate all combinations of shot positions. Then, a weight factor (such as shot spacing weight 0.7 and die spacing weight 0.3) is introduced to balance the spacing difference and optimize the search efficiency of the tree structure. The process involves a dynamic update mechanism, which is connected to the iterative optimization module through a bidirectional data flow. For example, if the iterative optimization module feeds back the wafer center position adjustment (such as offset Px / 2), the tree construction module updates the tree nodes in real time (such as adding branches or adjusting the depth of subnodes) to ensure that the tree structure adapts to parameter changes. The complex periodic layout problem is abstracted into a tree data structure, which not only maps the spatial relationship between shot and die, but also supports real-time optimization through dynamic updates, providing an efficient and scalable model foundation for subsequent parallel computing and search.

[0050] Parallel computing module: It is the performance acceleration unit of the system. It uses multi-threading technology to simultaneously process the layout calculations of multiple wafer center positions, improve computing efficiency and support large-scale optimization. Based on the tree structure of the tree construction module and the center position list of the iterative optimization module, the module divides the wafer surface into multiple partitions (for example, divided into 4 sub-areas by grid), assigns a thread to each partition, and the threads calculate the shot and die layouts of different wafer center positions in parallel. For example, one thread processes the center position (0, 0), and the other processes (Px, Py). Each thread calls the layout algorithm to generate candidate solutions (such as shot coordinates and the number of dies). First, the thread pool is initialized (such as 8 threads based on the number of CPU cores), and then the position task queue is received from the iterative optimization module. The tasks are distributed to each thread. After the calculation is completed, the results are summarized (such as the DPW value of each position). The process involves multi-thread synchronization, such as using mutex locks to ensure data consistency between threads, and integrating priority queues in the search module. For example, candidate solutions are sorted according to the preliminary DPW value (such as DPW>600 has a higher priority) to accelerate the convergence of the optimal solution. Functionally, the module greatly reduces the calculation time through parallelization, for example, shortening the calculation from 10 seconds under a single thread to 2 seconds. At the same time, the search order is optimized through the priority queue to ensure that high-potential layouts are evaluated first, thereby improving the throughput and response speed of the overall system, and providing fast and reliable data support for iterative optimization and search modules.

[0051] Iterative optimization module: It is the system's dynamic adjustment unit, responsible for generating a variety of candidate layout solutions and supporting real-time updates of the tree structure, providing rich options for final optimization. The running plan is based on the initial tree structure of the tree-building module. The module uses an iterator to adjust the wafer center position in the Shot periodic grid. For example, starting from (0, 0), it moves to (Px, Py), (2Px, 0), and other positions according to the step size of Px and Py (such as Px / 2=25mm). In terms of workflow, the module first initializes the position list (for example, 100 candidate center points), and then calls the parallel computing module to generate a layout plan for each position, calculate the Shot arrangement (such as a 6×7 grid) and Die distribution (such as 20 Dies in each Shot), and record the DPW value (such as 620). The process involves an adaptive step size strategy, such as reducing the step size according to the proximity of the wafer edge (such as the step size of the edge area is Px / 4), reducing redundant calculations, and interacting with the tree construction module through bidirectional data flow, such as feeding back the calculation results of the new position (Px / 2, Py / 2) to the tree structure to trigger node updates (such as adding a new branch to reflect the offset layout). Functionally, this module ensures that all potential optimization spaces are covered through iterative exploration, such as generating multiple solutions from DPW=600 to 637, and adapting to parameter changes (such as Die size adjustment) by dynamically updating the tree structure, providing the search module with a comprehensive and high-quality candidate layout set, thereby driving the entire system towards the optimal solution;

[0052] The search module is the decision-making core of the system. It identifies the optimal solution from candidate layouts through traversal and screening, accelerating convergence to the maximum DPW result. The execution plan is based on the candidate layout set from the iterative optimization module and the tree structure from the tree construction module. The module initiates a traversal search, for example, by traversing the tree nodes in a depth-first manner, calculating the DPW value of each layout (e.g., if the root node has a DPW of 600, the child nodes have a DPW of 620). In terms of workflow, the module first receives candidate solutions from the parallel computing module (e.g., a list of 10 layouts with a DPW of 600), then incorporates a pruning algorithm to remove inefficient branches. For example, if a node's DPW of 550 is below a threshold (e.g., 90% of the existing DPW of 624), its subtree exploration is skipped. This process integrates a priority queue, for example, prioritizing high-potential solutions based on the preliminary DPW value fed back by the parallel computing module (e.g., 637 > 620), accelerating convergence. For example, a layout with a DPW of 637 was selected after 10 iterations out of 100 candidates. Ultimately, the module outputs the optimal solution, including wafer center position (e.g., (Px / 2, Py / 2)), shot arrangement (e.g., a 6×7 grid), die distribution (e.g., 20 dies / shot), and DPW value (e.g., 637). Functionally, the module quickly screens for the optimal solution through efficient traversal and priority optimization, for example, reducing search time from 30 seconds per single thread to 5 seconds while ensuring maximum wafer utilization (e.g., a 2.1% increase), providing the final high-precision output for the entire system.

[0053] The entire computer system achieves wafer layout optimization through a modular design. It begins with an input module receiving parameters, a tree-building module creating a periodic tree structure, a parallel computation module accelerating layout calculations, an iterative optimization module generating candidate solutions and dynamically updating the tree structure, and a search module ultimately selecting the optimal solution. The execution of the solution is pipelined, with each module closely collaborating through data flow. For example, the input module outputs parameters to the tree-building module, the iterative optimization module interacts bidirectionally with the tree-building module, and the parallel computation module accelerates iteration and search. In terms of workflow, the system first initializes (input and tree construction), then iterates in parallel to generate the layout (computation and optimization), and finally searches and outputs the results. The entire process runs on standard hardware (such as a multi-core CPU) and typically takes seconds (e.g., 5-10 seconds). Functionally, the system supports real-time adjustments (e.g., updating the tree upon parameter changes) through bidirectional data flow. Parallel computation and priority queues ensure efficient convergence, resulting in an overall improvement in DPW (e.g., 0% to 3%), significantly outperforming existing technologies. Specific embodiment three:

[0055] like Figures 1 to 7 As shown, based on the content in the above specific embodiments, the following contents are further disclosed:

[0056] In order to further verify the feasibility and effectiveness of this method, a comparison with the existing technology is designed, further including the following contents:

[0057] Existing technologies (such as online calculators at silicon-edge.co.uk and anysilicon.com) assume uniform spacing and perform serial calculations, ignoring differences in shot and die spacing. They only support rectangular dies and suffer from low computational efficiency. This technical solution addresses these issues through steps Sp1 to Sp5 and a modular system. This experiment verifies this technological breakthrough by comparing DPW (DiesPerWafer) and computation time using specific cases.

[0058] Experimental equipment and environment:

[0059] Hardware: Equipped with 8-core CPU (Intel i 7-9700), 16GB RAM, NVIDIA GTX1660 GPU (for parallel computing of this solution);

[0060] Software: This technical solution is implemented in Python (including NumPy and multiprocessing libraries). The existing technology uses the online tool sil icon-edge.co.uk;

[0061] Wafer parameters: 300mm diameter, shot size 50mm×40mm, die size 5mm×4mm (rectangular) and hexagonal (side length 2.5mm, enclosing rectangle approximately 5.2mm×4.5mm);

[0062] Spacing setting: Shot spacing is 50μm, Die spacing is 10μm (this solution makes a distinction, the existing technology is unified as 50μm);

[0063] Experimental content:

[0064] Experimental group and control group settings:

[0065] Experimental group: Using this technical solution, execute Sp1 input parameters (including independent spacing and non-rectangular die support), Sp2 builds the tree structure, Sp3 iterates the center position (adaptive step size), Sp4 traverses the search (pruning + parallel computing), and Sp5 outputs the results;

[0066] Control group: Using existing technology (silicon-edge.co.uk calculator), input the same wafer, shot, and die dimensions, uniform 50μm pitch, only supporting rectangular dies, and serially calculating layout;

[0067] The experimental steps are as follows:

[0068] Step 1: Parameter input and preprocessing: The experimental group inputs wafer parameters, shot and die spacing, and non-rectangular die shape (hexagonal) for geometric transformation; the control group inputs the same parameters but with a uniform spacing and only rectangular die.

[0069] Step 2: Layout calculation: The experimental group constructed a tree structure, iterated 100 center positions (8 parallel threads), and searched for the optimal layout; the control group calculated a single layout according to a fixed formula;

[0070] Step 3: Performance recording: record the DPW values ​​and calculation time of the two methods, repeat 5 times and take the average value;

[0071] Step 4: Non-rectangular Die Test: The experimental group calculated the hexagonal Die layout, while the control group approximated it with an enclosing rectangle, and compared the DPW differences;

[0072] Verification indicators: Wafer utilization: measured by DPW value, verifying the effect of spacing differentiation and non-rectangular support; Computational efficiency: measured by computing time (seconds), verifying the advantages of parallel computing and dynamic optimization;

[0073] The experimental results are shown in Table 1 below:

[0074]

[0075] Table 1

[0076] Result analysis:

[0077] Improved wafer utilization: In the rectangular Die scenario, the DPW of this technical solution is 637, while that of the control group is 624, with a gain of 2.1%. This is due to Sp1 distinguishing between shot and die spacing (50μm vs. 10μm), and the secondary fine-tuning of Sp4 further optimizing the edge space. In the non-rectangular Die scenario, the DPW of this solution is 615, while that of the control group is only 596, with a gain of 3.2%. This is because Sp1 supports geometric transformation to accurately calculate the hexagonal layout, while the control group uses an enclosing rectangle approximation, resulting in waste. This verifies that the technical solution has broken through the traditional spacing limitations and insufficient shape support.

[0078] Improved computing efficiency: In the rectangular die scenario, the calculation time of this solution is 2.1 seconds, while that of the control group is 10.0 seconds, a reduction of 79.0%, thanks to Sp3 parallel computing (8 threads) and Sp4 pruning + priority queue accelerated convergence; in the non-rectangular die scenario, the calculation time of this solution is 2.3 seconds, while that of the control group is 9.8 seconds, a reduction of 76.5%. Dynamic tree updates and GPU acceleration further optimize performance; this verifies the innovation of the technical solution in dynamic optimization and computing performance.

[0079] Experiments show that this technical solution significantly improves wafer utilization (DPW gain 0%-3.2%) and computing efficiency (time reduction 76.5%-79.0%) by distinguishing spacing, supporting non-rectangular dies and parallel optimization, which is in sharp contrast to the existing technology. Its distinguishing features (such as the Sp1-Sp5 process and modular system) effectively solve the space waste and inefficiency problems in the background technology.

[0080] As chip manufacturing processes continue to improve, the area of ​​the chip is gradually decreasing, resulting in multiple dies being arranged in the area of ​​a single shot. However, since the distance between shots and the distance between the dies contained therein are affected by the hardware equipment in different process flows, the sizes of these two distances are often different. This method can adapt to this demand and calculate the optimal layout that meets this condition, such as Figure 5 As shown, it shows the optimal layout solution of our product when calculating different shot and die spacing;

[0081] This method establishes a graphical periodic layout tree structure based on given conditions and uses this structure to traverse and search for layout solutions on the wafer surface to find the optimal solution. By comparing the calculation results of our algorithm with those of online calculators, the number of dies in our results is 0%-3% higher.

[0082] like Figures 6 and 7 As shown in Figure 2, in both examples, our algorithm results in a better number of dies than the online algorithm.

[0083] like Figure 4 As shown in Figure 1, the arrangement of shots in space exhibits spatial periodicity, with periods in the X and Y directions denoted as Px and Py, respectively. The wafer center must lie somewhere within this spatial period. We designed an efficient iterator that iterates over the position of the center within this spatial period and calculates the resulting layout at each position, thereby deriving the optimal layout solution.

[0084] It should be noted that, in this document, relational terms such as first and second, etc., are used only to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations. Moreover, the terms "comprises," "comprising," or any other variants thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or device comprising a series of elements includes not only those elements, but also other elements not explicitly listed, or elements inherent to such process, method, article, or device. In the absence of further restrictions, an element defined by the statement "comprising a reference structure" does not exclude the presence of additional identical elements in the process, method, article, or device comprising the element.

[0085] While embodiments of the present invention have been shown and described, it will be appreciated by those skilled in the art that various changes, modifications, substitutions, and variations may be made to these embodiments without departing from the principles and spirit of the invention, and that the scope of the invention is defined by the appended claims and their equivalents.

Claims

1. A novel wafer layout and cutting calculation method, characterized by: The method comprises the following steps: Sp1: Input wafer size, shot size, die size, and spatial periodicity parameters Px and Py of shot in the X and Y directions, where Px and Py reflect the periodic arrangement of shot and mechanical device constraints, and support the input of non-rectangular die shapes; Sp2: Based on the input parameters, a graphical periodic layout tree structure is established. This structure maps the periodic distribution of shots on the wafer surface and supports subsequent layout optimization through a tree search algorithm. Sp3: Use an iterator to adjust the wafer center position in the spatial periodic grid of Shot, calculate the periodic arrangement of Shot and the distribution of Die within Shot for each position, and generate multiple candidate layout solutions; Sp4: Search all candidate layout solutions by traversing the graph periodized layout tree structure, calculate the number of chips (DPW) of each solution, and select the layout with the largest DPW as the optimal solution; Sp5: Outputs the optimal layout solution, including the wafer center position, periodic arrangement of shots, distribution of dies, and the final DPW value, and generates visual results.

2. The novel wafer layout and cutting calculation method according to claim 1, characterized in that: The parameters input in the step Sp1 further include independent constraints of the shot spacing and the die spacing. The non-rectangular die is geometrically transformed by the pre-processing module to generate a minimum enclosing rectangle that is suitable for periodic calculation.

3. The novel wafer layout and cutting calculation method according to claim 1, characterized in that: The construction of the graph periodic layout tree structure in step Sp2 includes defining the periodic boundary conditions of Shot and introducing a weight factor to balance the difference between Shot spacing and Die spacing, thereby optimizing the search efficiency of the tree structure.

4. The novel wafer layout and cutting calculation method according to claim 1, characterized in that: The iterator in step Sp3 adopts an adaptive step adjustment strategy to dynamically adjust the moving step of the wafer center position according to the wafer size and Shot periodic parameters to reduce redundant calculations and improve iteration efficiency.

5. The novel wafer layout and cutting calculation method according to claim 1, characterized in that: The traversal search in step Sp4 is further combined with a pruning algorithm to remove branches with DPW lower than a preset threshold in the graph periodic layout tree, thereby reducing computational complexity and accelerating the selection of the optimal solution.

6. The novel wafer layout and cutting calculation method according to claim 1, characterized in that: Outputting the optimal layout solution in step Sp5 includes generating multi-dimensional comparison data, specifically comparing the results with the existing online calculation method, quantifying the DPW gain and displaying the spatial distribution of the layout optimization in the form of a heat map.

7. The novel wafer layout and cutting calculation method according to claim 1, characterized in that: The method further includes an adaptive optimization step, and performs secondary fine-tuning on the optimal layout solution after step Sp4, eliminating edge waste by locally adjusting the Shot boundary and Die arrangement.

8. The novel wafer layout and cutting calculation method according to claim 1, characterized in that: The method is performed by a computer system, which includes an input module, a tree construction module, a parallel computing module, an iterative optimization module, and a search module. The tree construction module and the iterative optimization module are connected via a bidirectional data stream, supporting dynamic updating of the layout tree structure to adapt to real-time parameter changes. The parallel computing module utilizes multi-threading technology to simultaneously process layout calculations for multiple wafer center positions, and integrates a priority queue in the search module to accelerate the convergence of the optimal solution.

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