Method for manufacturing wiring board

Abstract

The invention provides a method for manufacturing a wiring substrate, and the yield in the manufacturing of the wiring substrate is improved. A method of manufacturing a wiring board according to an embodiment includes the steps of: preparing a glass substrate including one surface having a product region; and three or more conductor layers (12) and insulating layers (11) are laminated on only one surface within the range of the product area. The difference between the thermal expansion coefficients of the glass substrate and the insulating layers (11) is 13 ppm / DEG C or less, the shape of each product region is a rectangle having a size of each side of 80-240 mm, and the step of laminating the conductor layers (12) includes forming a resist layer having a resist pattern, the minimum width of the wiring included in the conductor layers (12) being 2 [mu] m or less, and the minimum width of the wiring included in the conductor layers (12) being 2 [mu] m or less. The minimum value of the interval between the wirings is 2 [mu] m or less, and the step of forming the resist layer includes exposure by direct imaging exposure.

Description

Technical Field

[0001] The present invention relates to a method for manufacturing a wiring substrate. Background Art

[0002] Patent Document 1 discloses a method for manufacturing a wiring substrate comprising a second wiring substrate and a first wiring substrate. The first wiring substrate is formed by laminating an insulating resin and a wiring layer on a support substrate comprising a glass substrate. The wiring layer on the insulating resin is formed by filling the openings in a resist pattern with a conductor. After the first and second wiring substrates are bonded, the support substrate is removed.

[0003] Patent Document 1: Japanese Patent Application Laid-Open No. 2020-4926

[0004] In the wiring substrate manufacturing method disclosed in Patent Document 1, when laminating insulating resin and wiring layers on a supporting substrate, the supporting substrate, insulating resin, and wiring layers are believed to warp. This is believed to cause defects in patterning the wiring layers, potentially reducing the yield rate in wiring substrate manufacturing. Summary of the Invention

[0005] The manufacturing method of the wiring substrate of the present invention includes the following steps: preparing a glass substrate having one surface and another surface on the opposite side of the one surface, the one surface having one or more product areas; and stacking a conductor layer and an insulating layer only on the one surface within the range of the one or more product areas to form a laminated portion. The step of stacking the conductor layer and the insulating layer includes the following steps: alternately stacking three or more conductor layers and three or more insulating layers, the difference between the thermal expansion coefficient of the glass substrate and the thermal expansion coefficient of each insulating layer is 13 ppm / °C or less, the shape of each product area is a rectangle with each side being 80 mm or more and 240 mm or less when viewed from above, the step of stacking the conductor layer includes the following steps: forming a resist layer having a resist pattern, forming a conductor pattern according to the resist pattern, the step of stacking the conductor layer includes the following steps: forming the minimum width of the wiring included in the conductor pattern to be less than 2 μm, and forming the minimum spacing between the wiring to be less than 2 μm, and the step of forming a resist layer having the resist pattern includes the following steps: exposing the resist layer by direct imaging exposure.

[0006] According to the embodiment of the present invention, the degree of warping that may occur in the step of forming the build-up portion can be suppressed, and the wiring board can be manufactured efficiently with a good yield. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Figure 1 This is a cross-sectional view showing an example of a wiring board manufactured by a manufacturing method according to an embodiment of the present invention.

[0008] Figure 2 This is a cross-sectional view showing another example of a wiring board manufactured by the manufacturing method according to one embodiment of the present invention.

[0009] Figure 3A This is a diagram showing an example of a method for manufacturing a wiring board according to an embodiment of the present invention.

[0010] Figure 3B This is a diagram showing an example of a method for manufacturing a wiring board according to an embodiment of the present invention.

[0011] Figure 3C This is a diagram showing an example of a method for manufacturing a wiring board according to an embodiment of the present invention.

[0012] Figure 3D This is a diagram showing an example of a method for manufacturing a wiring board according to an embodiment of the present invention.

[0013] Figure 3E This is a diagram showing an example of a method for manufacturing a wiring board according to an embodiment of the present invention.

[0014] Figure 3F This is a diagram showing an example of a method for manufacturing a wiring board according to an embodiment of the present invention.

[0015] Figure 3G This is a diagram showing an example of a method for manufacturing a wiring board according to an embodiment of the present invention.

[0016] Figure 3H This is a diagram showing an example of a method for manufacturing a wiring board according to an embodiment of the present invention.

[0017] Figure 3I This is a diagram showing an example of a method for manufacturing a wiring board according to an embodiment of the present invention.

[0018] Figure 3J This is a diagram showing an example of a method for manufacturing a wiring board according to an embodiment of the present invention.

[0019] Figure 3K This is a diagram showing an example of a method for manufacturing a wiring board according to an embodiment of the present invention.

[0020] Figure 3L This is a diagram showing an example of a method for manufacturing a wiring board according to an embodiment of the present invention.

[0021] Figure 3M This is a diagram showing an example of a method for manufacturing a wiring board according to an embodiment of the present invention.

[0022] Figure 3NThis is a diagram showing an example of a method for manufacturing a wiring board according to an embodiment of the present invention.

[0023] Figure 3O This is a diagram showing an example of a method for manufacturing a wiring board according to an embodiment of the present invention.

[0024] Figure 3P This is a diagram showing an example of a method for manufacturing a wiring board according to an embodiment of the present invention.

[0025] Label Description

[0026] 1: Wiring substrate; 10: First build-up portion; 20: Second build-up portion; 30: Third build-up portion; 11: Insulating layer (first insulating layer); 12: Conductor layer (first conductor layer); 21: Insulating layer (second insulating layer); 22: Conductor layer (second conductor layer); 31: Insulating layer (third insulating layer); 32: Conductor layer (third conductor layer); 121, 221: Metal film layer; 122, 222: Plated film layer; 12p, 32p: Conductor pad; FW: Wiring (fine wiring); SP1: First supporting substrate; GS1: Core material (glass substrate); GS1A: One surface; GS1B: The other surface; SP2: Second supporting substrate; RL1: Anti-etching layer (first anti-etching layer). DETAILED DESCRIPTION

[0027] Hereinafter, a method for manufacturing a wiring substrate according to the present invention will be described with reference to the accompanying drawings. Figure 1 1 is a cross-sectional view showing a wiring substrate 1 as an example of a wiring substrate manufactured by a manufacturing method according to an embodiment. The wiring substrate 1 is merely an example of a wiring substrate to be manufactured. The laminated structure of the wiring substrate to be manufactured and the number of conductor layers and insulating layers are not limited to Figure 1 The laminated structure of the wiring substrate 1 and the number of conductor layers and insulating layers included in the wiring substrate 1 are shown. In addition, the referenced drawings are not intended to show the exact ratio of each component, but are depicted in a manner that facilitates understanding of the characteristics of the present invention.

[0028] The wiring substrate 1 has a laminated structure including a laminated portion composed of a plurality of conductor layers and insulating layers alternately laminated. The laminated portion constituting the wiring substrate 1 has two surfaces (a first surface 1F and a second surface 1B opposite to the first surface 1F) perpendicular to its thickness direction. Figure 1 As shown, the build-up portion of the wiring board manufactured by the wiring board manufacturing method according to one embodiment includes at least build-up portion 10. The surface (first surface 10F) of build-up portion 10 constitutes first surface 1F.

[0029] The build-up portion 10 has a second surface 10B as a surface opposite to the first surface 10F. Figure 1As shown, wiring substrate 1 may further include build-up sections 20 and 30 formed of alternately stacked insulating layers and conductive layers on second surface 10B of build-up section 10. Hereinafter, in the description of wiring substrate 1, build-up section 10 is referred to as first build-up section 10, build-up section 20 is referred to as second build-up section 20, and build-up section 30 is referred to as third build-up section 30.

[0030] Second build-up section 20 has a first surface 20F and a second surface 20B, which is the surface opposite to first surface 20F. Third build-up section 30 has a first surface 30F and a second surface 30B, which is the surface opposite to first surface 30F. As shown in the figure, when the wiring substrate includes second build-up section 20 and third build-up section 30 in addition to first build-up section 10, first surface 20F of second build-up section 20 is arranged to face second surface 10B of first build-up section 10, and first surface 30F of third build-up section 30 is arranged to face second surface 20B of second build-up section 20.

[0031] When wiring substrate 1 includes second build-up section 20 and third build-up section 30 in addition to first build-up section 10, second surface 1B of wiring substrate 1 can be constituted by the surface (second surface 30B) of third build-up section 30. Alternatively, when third build-up section 30 is not formed and the build-up section of the wiring substrate is constituted by first build-up section 10 and second build-up section 20, second surface 1B can be constituted by the surface (second surface 20B) of second build-up section 20. Figure 2 As will be described later, when second build-up section 20 and third build-up section 30 are not formed and the build-up section of the wiring substrate consists of first build-up section 10, second surface 1B can be formed by the surface (second surface 10B) of first build-up section 10. Wiring substrate 1 is formed as a coreless wiring substrate that does not include a core layer.

[0032] First build-up section 10 includes relatively fine wiring, enabling a relatively high-density circuit wiring. First build-up section 10 includes alternately stacked insulating layers (first insulating layers) 11 and conductive layers (first conductive layers) 12. In a wiring board manufactured using the wiring board manufacturing method of one embodiment, first build-up section 10 includes at least three first insulating layers 11 and at least three first conductive layers 12. In the illustrated example, first build-up section 10 includes five first insulating layers 11 and six first conductive layers 12.

[0033] Conductive layers 12, which are opposed to each other with first insulating layer 11 interposed therebetween, are connected to each other by via-hole conductors (first via-hole conductors) 13. First conductive layer 12 is patterned to have a predetermined conductive pattern. First surface 10F of first build-up portion 10 is composed of the surface (upper surface) of first conductive layer 12 and the surface (upper surface) of first insulating layer 11 exposed from the pattern of conductive layer 12. Second surface 10B of first build-up portion 10 is composed of the surface (lower surface) of insulating layer 11 and the surface (lower surface and side surfaces) of conductive layer 12. In the illustrated example, conductive layer 12 constituting first surface 10F is formed into a pattern including a plurality of conductive pads 12p.

[0034] In addition, Figure 1 In the description of wiring board 1 shown, first surface 10F of first build-up section 10, that is, the side of first surface 1F constituting the build-up section of wiring board 1, is referred to as "upper" or "upper side," and second surface 1B of wiring board 1 is referred to as "lower" or "lower side." Furthermore, in each component, the surface facing first surface 1F is also referred to as the "upper surface," and the surface facing second surface 1B is also referred to as the "lower surface."

[0035] In the example shown in the figure, the conductor pad 12p is the uppermost surface of the first buildup portion 10, i.e., the outermost surface of the wiring substrate 1, and constitutes the component mounting surface of the wiring substrate 1 to which external electronic components can be connected. The component mounting surface of the wiring substrate 1 may also have multiple component mounting areas. For example, Figure 1 As shown in the example, two component mounting areas may be formed corresponding to the areas where the electronic components E1 and E2 are to be mounted. In the example shown in the figure, when the external electronic component is mounted on the wiring substrate 1, the upper surface of the exposed conductor pad 12p can be electrically and mechanically connected to the external electronic component via a conductive bonding material such as solder (not shown) between the connection pads of the external electronic component. At this time, a plating layer (not shown) such as a nickel layer and a tin layer may be pre-formed on the upper surface of the conductor pad 12p. As the electronic components E1 and E2 that can be mounted on the wiring substrate 1, for example, electronic components such as active components such as semiconductor integrated circuit devices and transistors are exemplified.

[0036] The first insulating layer 11 of the first laminated portion 10 can be formed using an insulating resin such as epoxy resin or phenolic resin. The first insulating layer 11 can include any one of fluororesin, liquid crystal polymer (LCP), polytetrafluoroethylene (PTFE), polyester resin (PE), and modified polyimide resin (MPI). Figure 3A to Figure 3PAs described later, the material constituting first insulating layer 11 is selected such that the difference in thermal expansion coefficient between first build-up portion 10 and the glass substrate formed thereon is within a predetermined range. For example, a resin material having a thermal expansion coefficient of 25 ppm / °C or less is preferably selected as the material constituting first insulating layer 11.

[0037] Examples of the conductor constituting the conductor layer 12 and the via conductor 13 include copper, nickel, and the like, and copper is preferably used. Figure 1 , for ease of viewing, the conductor layer 12 and the via conductor 13 are shown as a single layer, but the conductor layer 12 and the via conductor 13 may have a multilayer structure. For example, the conductor layer 12 and the via conductor 13 may have a two-layer structure including a metal film layer (e.g., a sputtered film layer or a chemically plated film layer) and a plated film layer (e.g., an electroplated film layer).

[0038] The via conductor 13 that penetrates the insulating layer 11 in the thickness direction is formed by filling the through hole 11a that penetrates the insulating layer 11 with a conductor. Figure 1 In the example, the via conductor 13 is formed integrally with the conductor layer 12 provided on the lower side thereof. Therefore, the via conductor 13 and the conductor layer 12 can be formed by the same metal film layer and the plated film layer. The through hole 11a is formed, for example, so that the aspect ratio of the via conductor 13 (the height from the upper surface of the lower conductor layer 12 to which the via conductor 13 is connected to the lower surface of the upper conductor layer 12 / the diameter of the via conductor 13 on the upper surface of the lower conductor layer 12) is greater than or equal to about 0.5 and less than or equal to about 1.0. In addition, the via diameter of the via conductor 13 (the diameter of the via conductor 13 on the upper surface of the lower conductor layer 12 to which the via conductor 13 is connected) is approximately 10 μm. In addition, although the term "diameter" is used, the planar shape of the via conductor 13 is not necessarily limited to a circle. "Diameter" refers to the distance between the two longest points on the outer periphery in the horizontal cross section of the via conductor 13.

[0039] Conductor layer 12 constituting first build-up section 10 can include fine wiring FW, which is high-density wiring with relatively small wiring width and inter-wiring distance (inter-wiring spacing). Fine wiring FW can have the smallest wiring width and inter-wiring distance among the wiring constituting wiring substrate 1. Fine wiring FW included in first build-up section 10 can have a wiring width smaller than the wiring width of wiring that can be included in conductor layer 22 of second build-up section 20 and the wiring that can be included in conductor layer 32 of third build-up section 30, described later. Fine wiring FW included in first build-up section 10 can have a wiring spacing smaller than the wiring spacing (inter-wiring distance) of wiring that can be included in conductor layer 22 of second build-up section 20 and the wiring that can be included in conductor layer 32 of third build-up section 30, described later.

[0040] Specifically, for example, the minimum value of the wiring width of the fine wiring FW is 2 μm or less, and the minimum value of the wiring spacing is 2 μm or less. By providing the first buildup portion 10 with the fine wiring FW, wiring with more appropriate characteristics corresponding to the electrical signals that can be transmitted by the wiring in the first buildup portion 10 can sometimes be provided. In addition, from the same point of view, the aspect ratio of the fine wiring FW that can be included in the first conductor layer 12 is, for example, greater than 2.0 and less than 4.0. In detail, as shown in FIG. Figure 3A to Figure 3P As will be described later, the wiring substrate 1 including such relatively fine wiring FW is formed more accurately.

[0041] When the conductor layer 12 is formed to include fine wiring FW as described above, it is sometimes preferable to also form via conductors 13 at fine pitches, connecting the opposing conductor layers 12 across the insulating layer 11. Small-diameter through-holes 11a for the via conductors 13 can be formed in the insulating layer 11. Therefore, the insulating layer 11 may contain inorganic fillers such as fine particles composed of silicon dioxide (SiO2), aluminum oxide, or mullite. However, in order to facilitate the formation of small-diameter through-holes 11a, it is sometimes preferable to exclude inorganic fillers from the insulating layer 11.

[0042] In first build-up section 10 including conductive layer 12 containing fine wiring FW, insulating layer 11 has a thickness of, for example, approximately 7.5 μm to 10 μm. Insulating layer 11 preferably does not include a core material (reinforcement material) such as glass fiber or aramid fiber. Conductive layer 12 has a thickness of, for example, 7 μm or less.

[0043] The second build-up section 20 includes alternately stacked insulating layers (second insulating layers) 21 and conductive layers (second conductive layers) 22. Via conductors 23 are formed in the second insulating layers 21, penetrating each second insulating layer 21 and connecting the conductive layers opposite each other across the second insulating layers 21. Each conductive layer 22 is patterned to have a predetermined conductive pattern. The third build-up section 30 includes alternately stacked insulating layers (third insulating layers) 31 and conductive layers (third conductive layers) 32. Via conductors 33 are formed in the third insulating layers 31, penetrating each third insulating layer 31 and connecting the conductive layers opposite each other across the third insulating layers 31. Each conductive layer 32 is patterned to have a predetermined conductive pattern.

[0044] The insulating layer 21 constituting the second laminate portion 20 and the insulating layer 31 constituting the third laminate portion 30 can be formed using the same insulating resin as the insulating layer 11. The insulating layers 21 and 31 may also include a core material (reinforcement material) composed of glass fiber or aramid fiber. In the illustrated example, the insulating layer 31 of the third laminate portion 30 includes a core material composed of glass fiber. The insulating layers 21 and 31 may also include an inorganic filler (not shown) composed of microparticles such as silica (SiO2), alumina or mullite. The conductor layer 22 of the second laminate portion 20, the conductor layer 32 of the third laminate portion 30, and each via conductor 23 and 33 can be formed using any metal such as copper or nickel, similar to the conductor layer 12 and the via conductor 13.

[0045] As described above, the wiring widths and spacings of the wiring included in conductor layer 22 of second build-up section 20 and conductor layer 32 of third build-up section 30 may sometimes be larger than those of the wiring included in conductor layer 12 of first build-up section 10. For example, the minimum wiring width of the wiring included in conductor layer 22 is approximately 4 μm, and the minimum spacing is approximately 6 μm. Furthermore, insulating layers 21 and 31 are formed thicker than insulating layer 11. The thickness of insulating layer 21 can be, for example, approximately 20 μm to 30 μm. The thickness of insulating layer 31 can be, for example, not less than 100 μm and not more than 200 μm.

[0046] Furthermore, the thickness of the conductive layers 22 and 32 is formed thicker than that of the conductive layer 12, and can be, for example, 10 μm or greater. The thickness of the conductive layer 32 can be, for example, approximately 20 μm. The via diameter of the via conductor 23 formed in the insulating layer 21 (the diameter of the via conductor 23 on the upper surface of the lower conductive layer 22 to which the via conductor 23 is connected) is, for example, approximately 50 μm. The via diameter of the via conductor 33 formed in the insulating layer 31 (the diameter of the via conductor 33 on the upper surface of the conductive layer 32) is approximately 100 μm.

[0047] Similar to conductor layer 12 and via conductor 13, conductor layers 22, 32 and via conductors 23, 33 may also have a multilayer structure, for example, a two-layer structure including a metal film layer and a plated film layer. Second build-up section 20 and third build-up section 30 do not include fine wiring patterns like fine wiring FW of first build-up section 10. In this case, the metal film layer in the two-layer structure of conductor layer 22 and via conductor 23, and conductor layer 32 and via conductor 33 may be a chemically plated film layer (e.g., a chemically plated copper film layer), and the plated film layer may be an electroplated film layer (e.g., an electroplated copper film layer).

[0048] exist Figure 1In the example shown in FIG. 1 , wiring substrate 1 further includes a solder resist layer SR formed on second surface 1B formed by insulating layer 31 and conductive layer 32. Solder resist layer SR is formed using, for example, a photosensitive polyimide resin or epoxy resin. Openings SRa are formed in solder resist layer SR, and conductive pads 32p of conductive layer 32 of third build-up portion 30 are exposed through openings SRa.

[0049] When wiring substrate 1 itself is mounted on an external element, such as an external wiring substrate (e.g., a motherboard of any electrical device), second surface 1B of wiring substrate 1, which is opposite to the component mounting surface of wiring substrate 1, can be a connection surface for connection to the external element. Conductor pad 32p can be connected to any substrate, electrical component, or mechanical component. Furthermore, wiring substrate 1 has a rectangular shape with each side measuring at least 80 mm and no more than 240 mm when viewed from above. Here, "viewed from above" means observing the object with a line of sight parallel to the thickness direction of wiring substrate 1.

[0050] exist Figure 2 , wiring substrate 1a is shown as another example of a wiring substrate manufactured by the manufacturing method of the embodiment. Wiring substrate 1a includes: a first build-up portion 10 having a first surface 10F and a second surface 10B; and a solder resist layer SR covering second surface 10B. Conductor layer 12 is exposed from an opening SRa formed in solder resist layer SR. That is, first surface 1F of wiring substrate 1a is composed of first surface 10F of first build-up portion 10, and second surface 1B of wiring substrate 1a is composed of second surface 10B of first build-up portion 10. In the case where a wiring substrate manufactured by the manufacturing method of a wiring substrate of the embodiment does not have a build-up portion other than first build-up portion 10, it can have the form of wiring substrate 1a shown in the figure.

[0051] Next, refer to Figure 3A to Figure 3P , to manufacture Figure 1 The manufacturing method of the wiring substrate of the embodiment is described by taking the case of the wiring substrate 1 shown in FIG. As long as there is no special description of the various components formed in the manufacturing method described below, they can be used in the Figure 1 The first build-up portion 10 is formed from the materials exemplified as the materials of the corresponding structural elements in the description of the wiring substrate 1. Furthermore, in the subsequent description of the method for manufacturing the wiring substrate 1, the side closer to the core material GS1 constituting the first support substrate SP1 is referred to as "lower" or "lower side," and the side farther from the first support substrate SP1 is referred to as "upper" or "upper side." The first build-up portion 10 is formed on the surface of the first support substrate SP1. Therefore, the surface of each element constituting the wiring substrate 1 that faces the first support substrate SP1 is referred to as the "lower surface," and the surface that faces the side opposite to the first support substrate SP1 is also referred to as the "upper surface."

[0052] First, if Figure 3AAs shown, prepare the first supporting substrate SP1. The first supporting substrate SP1 has a first surface SP1a and a second surface SP1b on the opposite side of the first surface SP1a as two surfaces perpendicular to its thickness direction. The first supporting substrate SP1 includes a core material GS1, and the core material GS1 has one surface GS1A and another surface GS1B on the opposite side of the one surface GS1A. In addition to the core material GS1, the first supporting substrate SP1 also includes a first metal film layer ML1 stacked on the surface of one surface GS1A of the core material GS1 and a second metal film layer ML2 stacked on the metal film layer ML1 via an adhesive layer AL1. The core material GS1 is a glass substrate made of glass material, and therefore, the core material GS1 is also called a glass substrate GS1. The first metal film layer ML1 and the second metal film layer ML2 are metal film layers formed, for example, by chemical plating or sputtering. In the example shown in the figure, the second surface SP1b of the first supporting substrate SP1 is composed of the other surface GS1B of the core material GS1.

[0053] In addition, the following Figure 3A as well as Figure 3B to Figure 3P In the figure, a single wiring substrate is formed on the first surface SP1a of the first support substrate SP1 to illustrate a method for manufacturing a wiring substrate. However, multiple wiring substrates can be formed on the first support substrate SP1. Specifically, the first surface SP1a of the first support substrate SP1 has one or more continuous product areas, and a laminate (build-up portion) is formed on the first surface SP1a, each of which includes a wiring substrate. When the first surface SP1a has multiple product areas, the wiring substrates are manufactured by dividing the formed laminate into sections corresponding to the product areas.

[0054] As the material used for the glass substrate GS1 constituting the first support substrate SP1, a material having a thermal expansion coefficient similar to that of the insulating layer 11 (see FIG. 1 ) stacked on the first support substrate SP1 is used. Figure 3C to Figure 3J ) has a glass material having a thermal expansion coefficient that satisfies a prescribed relationship. Specifically, as the material used for the glass substrate GS1, a material is used in which the difference in thermal expansion coefficient between the material constituting the glass substrate GS1 and the material constituting the insulating layer 11 is 13ppm / °C or less. The glass material used for the glass substrate GS1 may have a thermal expansion coefficient of 8ppm / °C or more, for example. Specifically, as the glass material used for the glass substrate GS1, borosilicate glass may be used, for example. The first metal film layer ML1 and the second metal film layer ML2 are respectively depicted as single layers in the figure, but may also include multiple layers. For example, the first metal film layer ML1 and the second metal film layer ML2 may have a double-layer structure consisting of a titanium layer and a copper layer, respectively. The adhesive layer AL1 may, for example, contain an azobenzene-based polymer adhesive that can be attached or detached by light irradiation.

[0055] Reference Figure 3B to Figure 3J The formation of the first laminated portion 10 described later is only implemented on the upper side of one surface GS1A of the glass substrate GS1. Therefore, the first surface SP1a of the first supporting substrate SP1 preferably has good flatness. The first surface SP1a of the first supporting substrate SP1, for example, has a flatness of ±2.5μm or less. In addition, "flatness" here refers to an indicator that can display the smoothness (uniformity) of a plane in a numerical value, in accordance with or in compliance with JISB0621-1984. Therefore, a flatness of ±2.5μm or less means that the concavity or convexity in the thickness direction of the supporting substrate SP1 relative to the imaginary plane serving as a reference is 2.5μm or less. In addition, the first supporting substrate SP1 is preferably less likely to warp during the formation process of the laminated portion on the first surface SP1a. From the viewpoint of suppressing the warping, the glass substrate GS1 constituting the first supporting substrate SP1 can have a thickness of, for example, 0.7mm or more.

[0056] Then, if Figure 3B As shown, a conductor layer 12 having a plurality of conductor pads 12p is formed on the first surface SP1a of the first support substrate SP1. In forming the conductor layer 12 in contact with the first support substrate SP1, a plating resist is formed on the metal film layer ML2, for example, and openings corresponding to the formation areas of the pattern of the conductor pads 12p are formed in the plating resist by, for example, photolithography. Next, a plated film layer 122 is formed in the openings by electroplating using the metal film layer ML2 as a seed layer. After the plated film layer 122 is formed, the plating resist is removed to form a Figure 3B The status shown.

[0057] Then, if Figure 3C As shown, an insulating layer 11 is laminated to cover the upper surface and side surfaces of the conductive layer 12 and the first surface SP1a of the first support substrate SP1 exposed from the conductive pattern of the conductive layer 12. The insulating layer 11 is formed by thermocompression bonding a resin formed into a film. In forming the insulating layer 11, a material having a thermal expansion coefficient that differs from that of the glass substrate GS1 by 13 ppm / °C or less is used. Therefore, the insulating layer 11 and the reference substrate GS1 are formed on the glass substrate GS1. Figure 3D to Figure 3H In the step of forming the conductive layer 12 on the insulating layer 11 described later, the degree of warping that may occur due to the difference in thermal expansion coefficient between the glass substrate GS1 and the insulating layer 11 can be suppressed to a relatively low level.

[0058] As the insulating layer 11, insulating resins such as epoxy resin and phenolic resin can be used. Fluororesin, liquid crystal polymer (LCP), polytetrafluoroethylene (PTFE), polyester resin (PE), and modified polyimide resin (MPI) can also be used. The insulating layer 11 is formed to have a thickness of about 7.5 μm to 10 μm. As mentioned above, the thermal expansion coefficient of the glass substrate GS1 is, for example, 8 ppm / °C or more. As the resin material constituting the first insulating layer 11, for example, a resin material with a thermal expansion coefficient of 25 ppm / °C or less can be preferably used.

[0059] Next, the via conductor 13 (see Figure 3G ) is formed at a formation position by irradiation with, for example, a carbon dioxide laser, an excimer laser, or the like. As described above, in the method for manufacturing a wiring substrate of the embodiment, the degree of warping that may be caused by the difference in thermal expansion coefficient between the glass substrate GS1 and the insulating layer 11 is relatively small, and the surface of the insulating layer 11 has relatively good flatness. Therefore, it is considered that the through hole 11a can be formed relatively accurately at a position corresponding to the portion where the via conductor 13 is to be formed. The through hole 11a can be formed so that the depth of the through hole 11a / the diameter of the through hole 11a is greater than or equal to about 0.5 and less than or equal to about 1.0. Here, the "depth of the through hole 11a" refers to the shortest distance between the upper surface of the conductor layer 12 and the upper surface of the insulating layer 11, and the "diameter of the through hole 11a" refers to the distance between the two longest points on the outer periphery of the through hole 11a on the upper surface of the insulating layer 11 when viewed from above. The through hole 11a can be formed to have a diameter of about 10 μm.

[0060] Although not shown in the figure, the formation of the through hole 11a based on the irradiation of a laser such as a carbon dioxide laser is sometimes performed by protecting the upper surface of the insulating layer 11 with a protective film such as a polyethylene terephthalate (PET) film while irradiating the laser. In addition, after the through hole 11a is formed, in order to prevent the decrease in the adhesion during the formation of the conductor layer 12 caused by the processing modified product generated at the bottom of the through hole 11, a desmearing process is sometimes performed. The desmearing process is preferably a dry desmearing process using plasma gas. The desmearing process can also be performed while protecting the surface of the insulating layer 11 while a protective film such as a polyethylene terephthalate (PET) film is formed on the surface of the insulating layer 11.

[0061] Then, if Figure 3DAs shown, a metal film layer 121 is formed on the inner wall of the through hole 11a and on the surface of the insulating layer 11 by chemical plating or sputtering. Preferably, the metal film layer 121 can be a sputtered film formed by sputtering. In addition, when a protective film is provided on the surface of the insulating layer 11 during the formation of the through hole 11a and / or the desmear treatment, the protective film can be stripped and removed before the formation of the metal film layer 121.

[0062] Then, if Figure 3E As shown, a dry film resist containing, for example, a photosensitive epoxy resin is adhered to the metal film layer 121, and the resist layer RL1 is formed in contact with the upper surface of the metal film layer 121. Next, the resist layer RL1 is exposed. In the manufacturing method of the wiring substrate of the embodiment, in the process of exposing the resist layer RL1, direct imaging exposure with relatively high resolution is implemented. In the direct imaging exposure, no photomask is used, and the resist layer RL1 is directly irradiated with irradiation light L. As the light source of the irradiation light L, for example, a semiconductor laser or an ultra-high pressure mercury lamp with a wavelength of 350nm to 410nm can be used. According to the conductor pattern of the first conductor layer 12 to be formed on the insulating layer 11 (refer to Figure 3H ) corresponding to the drawing pattern, scanning the irradiation light L. In addition, the exposure amount can be determined by the illuminance of the exposure light source and the scanning speed of the irradiation light L.

[0063] In the manufacturing method of the wiring substrate, the product areas in the first surface SP1a of the first supporting substrate SP1 each have a rectangular shape with each side having a size of 80 mm or more and 240 mm or less when viewed from above. Therefore, the laminate (laminated portion) formed within the range of one or more product areas of the first surface SP1a of the first supporting substrate SP1 has a rectangular shape with each side having a size of 80 mm or more when viewed from above. In this way, in the case of manufacturing a laminate of a relatively large size, in the formation of the resist layer RL1, in the exposure using a photomask whose range that can be exposed in one exposure is limited, it is necessary to repeatedly perform exposure in different ranges, and sometimes the working hours in the exposure process increase. In contrast, in direct imaging exposure, the entire range of the wiring substrate is scanned by the irradiation light in one exposure, so that the increase in the working hours in the exposure process can be suppressed, and therefore, the manufacturing yield of the wiring substrate can sometimes be improved.

[0064] Then, if Figure 3F As shown, a conductor pattern corresponding to the first conductor layer 12 to be formed on the insulating layer 11 is formed on the resist layer RL1 (see Figure 3HSpecifically, after the exposure step of the resist layer RL1 is completed, the resist layer RL1 is developed using a developer consisting of an aqueous sodium carbonate solution, for example, which may contain a surfactant, a defoaming agent, and a small amount of an organic solvent for promoting development, to form an opening RL1o. The conductor pattern of the first conductor layer 12 to be formed on the insulating layer 11 includes the wiring FW (see Figure 3H ), the openings RL1o corresponding to the wirings FW can be formed so that the minimum value of the width of the openings is 2 μm or less, and the minimum value of the interval between the openings is 2 μm or less.

[0065] As described above, in the manufacturing method of the wiring substrate of the embodiment, the difference in thermal expansion coefficient between the glass substrate GS1 and the insulating layer 11 is relatively small, being 13 ppm / °C or less, and the degree of warping that may occur in the first support substrate SP1 and the insulating layer 11 during the manufacturing process of the wiring substrate is relatively small. Figure 3E At the time of exposure of the resist layer RL1, the resist layer RL1 has a relatively good flatness. Figure 3H ) is scanned with a drawing pattern that more accurately corresponds to the conductor pattern of the resist layer RL1 on the insulating layer 11. Therefore, it is considered that the opening RL1o formed in the resist layer RL1 by development is aligned with the first conductor layer 12 to be formed (see Figure 3H )'s conductor pattern more accurately corresponds.

[0066] Then, if Figure 3G As shown, by electroplating the metal film layer 121 as a power supply layer, a plated film layer 122 is formed in the opening RL1o of the resist layer RL1. The interior of the through hole 11a is completely filled with the plated film 122, forming a via conductor 13.

[0067] Next, after removing the resist layer RL1 using an alkaline stripping solution, the portion of the metal film layer 121 not covered by the plated film layer 122 is removed by etching. Figure 3H As shown, a conductor layer 12 having a two-layer structure consisting of a metal film layer 121 and a plated film layer 122 is formed with fine wiring FW. The conductor layer 12 can be formed to have a thickness of 7 μm or less, for example. The wiring FW can be formed to have a minimum wiring width of 2 μm or less, a minimum wiring spacing of 2 μm or less, and an aspect ratio of 2.0 or more and 4.0 or less. As described above, Figure 3F As described above, it is considered that by forming the opening RL1o in the resist layer RL1 so as to relatively accurately correspond to the conductor pattern to be formed, the conductor layer 12 having such relatively fine wiring FW can be formed more accurately.

[0068] Then, if Figure 3I As shown, a desired number of insulating layers 11 and conductor layers 12, as well as via conductors 13 penetrating each insulating layer 11, are formed on the conductor layer 12 and the insulating layer 11 using the same method as described above for forming the insulating layer 11, the conductor layer 12, and the via conductors 13. In the wiring substrate manufacturing method of the embodiment, at least three insulating layers 11 and at least three conductor layers 12 are formed on the first support substrate SP1. As the number of insulating layers 11 and conductor layers 12 stacked on the first support substrate SP1 increases, the degree of warping caused by the difference in thermal expansion coefficient between the insulating layer 11 and the glass substrate GS1 may increase. However, in the wiring substrate manufacturing method of the embodiment, the difference in thermal expansion coefficient between each insulating layer 11 and the glass substrate GS1 is relatively small, at or below 13 ppm / °C. Therefore, even if the number of insulating layers 11 stacked increases, the resulting warping is suppressed to a relatively small level. When a plurality of insulating layers 11 and a plurality of conductive layers 12 are formed on the support substrate SP1 , the above-described accurate formation of the through-holes 11 a and accurate formation of the conductive layers 12 can be achieved.

[0069] Then, if Figure 3J As shown, the insulating layer 11 and the conductive layer 12, the topmost insulating layer 11 and the conductive layer 12 of the first build-up portion 10, are formed on the upper side of the conductive layer 12. The formation of the first build-up portion 10 on the first surface SP1a of the first supporting substrate SP1 is completed. As shown in the figure, the topmost conductive layer 12, which does not include the wiring FW, can be formed by the same method as that for forming the insulating layer 11 and the conductive layer 12 on the insulating layer 11 (a method including direct imaging exposure of a resist layer), but can also be formed by a method including forming a resist pattern by exposing the resist layer using a photomask. At the time of forming the first build-up portion 10, the flatness of the surface facing the glass substrate (i.e., the surface in contact with the first surface SP1a of the supporting substrate SP1) of the laminate (build-up portion) formed on the first surface SP1a of the first supporting substrate SP1 is, for example, ±2.5 μm or less.

[0070] Furthermore, in the method for manufacturing a wiring substrate according to the embodiment, in forming the plurality of conductive layers 12 constituting first build-up portion 10, any conductive layer among conductive layers 12 formed on insulating layer 11 may be formed by a method including direct imaging exposure of a resist layer. Thus, for example, in the illustrated example, the lowermost conductive layer 12 (conductive layer 12 in contact with first supporting substrate SP1) in first build-up portion 10 that does not include wiring FW may be formed by a method including forming a resist pattern by exposing the resist layer using a photomask, or may be formed by a method including direct imaging exposure.

[0071] Then, if Figure 3K As shown, the second build-up part 20 is stacked on the uppermost insulating layer 11 and the conductive layer 12 in the first build-up part 10 (see FIG. Figure 3N ). The thickness of insulating layer 21 may differ from that of insulating layer 11 constituting first build-up portion 10. Insulating layer 21 may be formed to a thickness of, for example, approximately 20 μm to 30 μm. Insulating layer 21 may be made of the same insulating resin as that constituting insulating layer 11. A film 21F made of a resin such as polyethylene terephthalate is laminated on insulating layer 21 and releasably bonded to insulating layer 21.

[0072] Then, if Figure 3L As shown, the first laminated portion 10 including the insulating layer 21 and the film 21F is adhered to both sides of the two main surfaces (surfaces perpendicular to the thickness direction) of the second supporting substrate SP2 via the first supporting substrate SP1. The main surface of the second supporting substrate SP2 is bonded to the second surface SP1b of the first supporting substrate SP1 via an adhesive layer AL2 composed of an optional adhesive. The second supporting substrate SP2 may be, for example, a glass substrate similar to the core material GS1 of the first supporting substrate SP1. Alternatively, a CCL (Copper Clad Laminate) comprising an insulating layer and copper foil thermally pressed onto both sides may be used for the second supporting substrate SP2.

[0073] Then, film 21F is peeled off from insulating layer 21. Next, through-holes 21a are formed in insulating layer 21, for example, by laser irradiation, and via conductors 23 having a two-layer structure consisting of a metal film layer 221 and a plated film layer 222 are formed on insulating layer 21 using a so-called semi-additive process. Specifically, metal film layer 221 is formed within through-holes 21a and on the surface of insulating layer 21, for example, by chemical plating. A plating resist (not shown) having openings corresponding to the conductor pattern to be included in conductor layer 22 is provided on metal film layer 221. Then, through electroplating using metal film layer 221 as a power supply layer, plated film layer 222 is formed within the openings in the plating resist, forming via conductors 23 within through-holes 21a. The plating resist is then removed, and the exposed portions of metal film layer 221 not covered by plated film layer 222 are removed by etching. Conductor layer 22 can be formed to a thickness of, for example, 10 μm or greater. The conductor layer 22 can be formed to have wiring with a minimum wiring width of approximately 4 μm and a minimum wiring spacing of approximately 6 μm. In forming the conductor layer 22, the above-described direct imaging exposure method can be used to form the openings in the plating resist. Alternatively, exposure using a photomask can be used.

[0074] In addition, Figure 3M And the following references Figure 3N~Figure 3P, the laminate formed on one surface of the second support substrate SP2 is shown, and the laminate that can be formed on the opposite surface is omitted. However, the laminate of the illustrated form and number is also formed on the opposite surface of the second support substrate SP2.

[0075] Then, if Figure 3N As shown, by repeatedly performing the steps of forming the above-mentioned insulating layer 21, the conductive layer 22 and the via-hole conductor 23, the desired number of insulating layers 21 and the conductive layer 22 and the via-hole conductor 23 penetrating each insulating layer 21 are formed. The second built-up part 20 is formed on the first built-up part 10. Figure 3N And the following Figure 3O and Figure 3P In the figure, the metal film layer and the plated film layer are not depicted, and the conductor layers 12 and 22 are not depicted. Figure 1 Likewise depicted as a single layer.

[0076] In manufacturing Figure 1 In the case of the wiring substrate 1 shown, after the first build-up section 10 is stacked on the first support substrate SP1, the second build-up section 20 is formed on the first support substrate SP1 via the first build-up section 10. It is believed that by directly forming the second build-up section 20 on the first build-up section 10, whose degree of warping is relatively suppressed, the second build-up section 20 can also be formed to have good flatness.

[0077] Then, if Figure 3O As shown, the insulating layer 31, the conductive layer 32, and the via-hole conductor 33 that penetrates the insulating layer 31 of the third build-up section 30 are formed on the uppermost insulating layer 21 and the conductive layer 22 of the second build-up section 20 using the same method as the method for forming the insulating layer 21, the conductive layer 22, and the via-hole conductor 23. As the insulating resin forming the insulating layer 31, a prepreg comprising an insulating resin such as epoxy resin or BT resin impregnated in a reinforcing material (core material) composed of glass fiber can be used. As shown in the figure, the third build-up section 30 is formed, which includes two insulating layers 31 and two conductive layers 32. Next, a solder resist layer SR is formed by forming a photosensitive epoxy resin or polyimide resin layer on the surface of the insulating layer 31 and the conductive layer 32. Then, an opening SRa is formed by photolithography technology to expose the conductive pad 32p.

[0078] Then, if Figure 3P As shown, the first support substrate SP1 and the second support substrate SP2 are removed from the laminate including the first build-up portion 10. When the first support substrate SP1 is removed from the first build-up portion 10, the adhesive layer AL1 is softened by irradiating it with, for example, a laser, and then the second metal film layer ML2 of the first support substrate SP1 is peeled off from the adhesive layer AL1. The lower surface of the second metal film layer ML2 under the conductor pad 12p is exposed. In addition, although Figure 3P Although not shown in the figure, the removal of the first support substrate SP1 is also carried out on the surface of the second support substrate SP2 opposite to the surface shown in the figure. Next, the second metal film layer ML2 is removed by etching. The lower surface of the conductor pad 12p and the lower surface of the insulating layer 11 are exposed. In addition, the stacked body that can include multiple wiring substrates is divided into each product area to form individual independent wiring substrates. Completed Figure 1 The wiring substrate 1 is shown.

[0079] The manufacturing method of the wiring substrate of the embodiment is not limited to the Figure 3A to Figure 3P The conditions, sequence, etc. of the described method can be arbitrarily changed. In addition, certain steps can be omitted, and other steps can be added. The manufacturing method of the wiring substrate of the embodiment includes at least the following steps: alternately stacking three or more conductor layers and three or more insulating layers only on one surface of a glass substrate, the difference in thermal expansion coefficient between the glass substrate and the insulating layer is 13 ppm / °C or less, and the stacking of the conductor layers includes forming a resist pattern using direct imaging exposure. For example, a solder resist layer having an opening that exposes the conductor pad 12p can be formed on the conductor pad 12p and the insulating layer 11 exposed after the second metal film layer ML2 is removed by etching. Furthermore, a conductor bump connected to the conductor pad 12p can be formed in the opening of the solder resist layer. A plating layer including a nickel layer and a tin layer can also be formed on the surface of the conductor bump. The second and third build-up layers can also be omitted, and a fourth build-up layer can be formed in addition to the second and third build-up layers.

Claims

1. A method for manufacturing a wiring substrate, comprising the following steps: preparing a glass substrate having one surface and another surface opposite to the one surface, the one surface having one or more product areas; and Conductor layers and insulating layers are stacked only on the one surface within the range of the one or more product areas to form a build-up portion, in, The step of stacking the conductor layer and the insulating layer includes the following steps: alternately stacking three or more conductor layers and three or more insulating layers, The difference between the thermal expansion coefficient of the glass substrate and the thermal expansion coefficient of each of the insulating layers is 13 ppm / °C or less. The shape of each product area is a rectangle with each side being greater than or equal to 80 mm and less than or equal to 240 mm in plan view. The step of stacking the conductor layer includes the steps of: forming a resist layer having a resist pattern, forming a conductor pattern according to the resist pattern, The step of stacking the conductor layer includes the steps of: forming the minimum value of the width of the wiring included in the conductor pattern to be less than 2 μm, forming the minimum value of the spacing between the wiring to be less than 2 μm, The step of forming a resist layer having the resist pattern includes the step of exposing the resist layer by direct imaging exposure.

2. The method for manufacturing a wiring substrate according to claim 1, wherein: The thermal expansion coefficient of the glass substrate is greater than 8 ppm / °C.

3. The method for manufacturing a wiring substrate according to claim 1, wherein: The thickness of the glass substrate is greater than 0.7 mm.

4. The method for manufacturing a wiring substrate according to claim 1, wherein: The glass substrate includes borosilicate glass.

5. The method for manufacturing a wiring substrate according to claim 1, wherein: The thermal expansion coefficient of each of the insulating layers is 25 ppm / ° C. or less.

6. The method for manufacturing a wiring substrate according to claim 1, wherein: The flatness of the surface of the build-up portion facing the glass substrate is ±2.5 mm or less.

7. The method for manufacturing a wiring substrate according to claim 1, wherein: The conductive layer is formed to include wiring having an aspect ratio of 2.0 to 4.

0.

8. The method for manufacturing a wiring substrate according to claim 1, wherein: This method for manufacturing a wiring substrate includes the step of forming a build-up portion including an insulating layer having a thickness different from that of the insulating layer on a side of the build-up portion opposite to the glass substrate.

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