Instruction processing method and device, electronic equipment and readable storage medium

Abstract

The embodiment of the invention provides an instruction processing method and device, electronic equipment and a readable storage medium, and relates to the technical field of computers. The method comprises the following steps: selecting n instructions from an instruction stream as to-be-decoded instructions of a current round, and decoding the to-be-decoded instructions by using n decoding units to obtain a microinstruction sequence; n is an integer not less than 2. According to the input width of the renaming unit, transmitting the microinstruction in the preset cache and the microinstruction in the microinstruction sequence to the renaming unit; the preset cache is used for storing microinstructions which are not transmitted in the last round. And writing untransmitted microinstructions in the microinstruction sequence into a preset cache. In the embodiment of the invention, the n instructions are reselected from the instruction stream to serve as the instructions to be decoded of the next round, and the step of decoding the instructions to be decoded by using the n decoding units is returned to be continuously executed until the stop condition is met, so that the decoding throughput and the decoding efficiency can be improved.

Description

Technical Field

[0001] Embodiments of the present invention relate to the field of computer technology, and in particular, to an instruction processing method, device, electronic device, and readable storage medium. Background Art

[0002] The instruction processing involves decoding the instructions. After decoding the instructions, microinstructions are obtained. The microinstructions are passed to the renaming unit for renaming operations and then executed in subsequent links.

[0003] In the prior art, after one instruction is decoded and all microinstructions obtained from the instruction are transferred to the renaming unit, the next instruction decoding begins. In this method, the instruction decoding efficiency is low and the decoding throughput is low.

[0004] The number of microinstructions obtained by decoding different instructions varies, which leads to the fact that the decoding throughput in the instruction decoding stage is not fixed and a stable decoding throughput cannot be guaranteed. Summary of the Invention

[0005] Embodiments of the present invention provide an instruction processing method, device, electronic device, and readable storage medium, which can solve the problems of low instruction decoding efficiency and low decoding throughput.

[0006] In order to solve the above problems, an embodiment of the present invention discloses an instruction processing method, which includes: Selecting n instructions from the instruction stream as instructions to be decoded in the current round, and decoding the instructions to be decoded using n decoding units to obtain a microinstruction sequence; wherein n is an integer not less than 2; delivering microinstructions in a preset cache and microinstructions in the microinstruction sequence to the renaming unit according to an input width of the renaming unit; the preset cache is used to store microinstructions that were not delivered in the previous round; The undelivered microinstructions in the microinstruction sequence are written into the preset cache, and n instructions are reselected from the instruction stream as instructions to be decoded in the next round, and the step of decoding the instructions to be decoded using n decoding units is returned to until a stop condition is reached.

[0007] On the other hand, an embodiment of the present invention discloses an instruction processing device, comprising: A first processing module is configured to select n instructions from an instruction stream as instructions to be decoded in a current round, and decode the instructions to be decoded using n decoding units to obtain a microinstruction sequence; wherein n is an integer not less than 2; a transfer module, configured to transfer microinstructions in a preset cache and microinstructions in the microinstruction sequence to the renaming unit according to an input width of the renaming unit; the preset cache is used to store microinstructions that were not transferred in the previous round; A writing module, configured to write the undelivered microinstructions in the microinstruction sequence into the preset cache; The second processing module is used to reselect n instructions from the instruction stream as instructions to be decoded in the next round, and return to the step of decoding the instructions to be decoded by using n decoding units until a stop condition is reached.

[0008] On the other hand, an embodiment of the present invention discloses an electronic device, comprising: a processor, a memory, a communication interface and a communication bus, wherein the processor, the memory and the communication interface communicate with each other through the communication bus; the memory is used to store executable instructions, and the executable instructions enable the processor to execute the aforementioned method.

[0009] An embodiment of the present invention further discloses a readable storage medium having executable instructions stored thereon. When executed by one or more processors, the processors are enabled to execute the method described above.

[0010] Embodiments of the present invention include the following advantages: In the instruction processing method provided by the embodiment of the present invention, n instructions are selected from an instruction stream as instructions to be decoded in the current round, and n decoding units are used to decode the instructions to be decoded to obtain a microinstruction sequence; n is an integer not less than 2. According to the input width of the renaming unit, microinstructions in a preset cache and microinstructions in the microinstruction sequence are transferred to the renaming unit; the preset cache is used to store microinstructions not transferred in the previous round. The microinstructions not transferred in the microinstruction sequence are written to the preset cache. N instructions are reselected from the instruction stream as instructions to be decoded in the next round, and the step of decoding the instructions to be decoded using n decoding units is returned to continue execution until a stop condition is reached. In this way, each time n instructions are decoded, the number of microinstructions in the microinstruction sequence obtained in the current round can be increased, so that sufficient microinstructions can be transferred to the renaming unit, thereby improving decoding throughput and decoding efficiency.

[0011] And each time the microinstructions are passed to the renaming unit according to the input width of the renaming unit, that is, the input width microinstructions are passed to the renaming unit each time, avoiding the problem of decoding a single instruction, the decoding throughput is not fixed, and the stable decoding throughput cannot be guaranteed. At the same time, by introducing a preset cache, the microinstructions that were not passed in the previous round are stored, and the microinstructions in the preset cache are continued to be passed to the renaming unit in the current round. This makes it possible to pass these microinstructions to the renaming unit in the current round without re-decoding the instructions corresponding to the microinstructions in the preset cache, thereby improving the overall processing efficiency to a certain extent. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments of the present invention. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative labor.

[0013] Figure 1 This is a flowchart of a method for processing instructions provided by an embodiment of the present invention; Figure 2 This is a schematic diagram of a re-decoding determination process provided by an embodiment of the present invention; Figure 3 This is a schematic diagram related to the number of microinstructions provided by an embodiment of the present invention; Figure 4 is a schematic diagram related to another microinstruction quantity provided by an embodiment of the present invention; Figure 5 This is a schematic diagram of a processing process provided by an embodiment of the present invention; Figure 6 is another processing process schematic diagram provided by an embodiment of the present invention; Figure 7 is another processing process schematic diagram provided by an embodiment of the present invention; Figure 8 is a schematic diagram of an initial one-hot encoding shown in an embodiment of the present invention; Figure 9 This is a selection diagram provided by an embodiment of the present invention; Figure 10 This is a schematic diagram of instruction processing shown in an embodiment of the present invention; Figure 11 This is a schematic diagram of a microinstruction transmission provided by an embodiment of the present invention; Figure 12 is a block diagram of an instruction processing device provided by an embodiment of the present invention; Figure 13 It is a structural diagram of an electronic device provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0014] The following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of them. All other embodiments obtained by ordinary technicians in this field based on the embodiments of the present invention without making any creative efforts shall fall within the scope of protection of the present invention.

[0015] First, the application scenarios involved in the embodiments of the present invention are described. When a network-on-chip (NOC) processes instructions, it first fetches instructions and then performs decoding. Instruction fetching refers to the process of retrieving instructions from memory. Decoding refers to the process of parsing the instructions fetched during the instruction fetch phase and translating them into the control signals required for instruction scheduling and execution. Decoding throughput refers to the number of microinstructions actually processed per cycle, that is, the number of microinstructions actually passed to the rename unit. The instruction processing method provided in the embodiments of the present invention can be applied to the Vector Instruction Extension (RVV) instruction set. RVV includes vector instructions such as vector addition, vector subtraction, vector multiplication, vector division, bitwise logical operation, comparison, shift, maximum and minimum, data shuffle, and reduction. RVV instructions do not encode vector configuration within the instructions. Instead, independent vector configuration instructions are used to set the vector configuration register (VTYPE CSR). Vector configuration instructions, such as VSETVL, VSETVLI, and VSETIVLI, are used to set the vector configuration. The vector configuration register is a register defined in RVV that controls vector configuration. The VTYPE register includes the vector length multiplier (LMUL) field and the selected element width (SEW) field.

[0016] Both LMUL and SEW are 3 bits. SEW specifies the bit width of the vector instruction operand, while LMUL specifies the number of vector registers used in the vector instruction operand. For example, the vector addition instruction vadd.vv v4,v8,v12, when LMUL = 4, adds the corresponding elements of the four pairs of vector registers v8 to v11 and v12 to v15, respectively, and writes the results to registers v4 to v7. In other words, the vadd.vv v4,v8,v12 instruction with LMUL = 4 is equivalent to the four instructions "vadd.vv v4,v8,v12," "vadd.vv v5,v9,v13," "vadd.vv v6,v10,v14," and "vadd.vv v7,v11,v15" when LMUL = 1. A larger LMUL value indicates a greater number of microinstructions decoded from the instruction.

[0017] The prior art uses a "delayed decoding" approach, that is, decoding one by one. This design can only process one vector instruction at a time. If there are unprocessed instructions in the decoding stage, the decoding stage must be blocked. The decoding stage can only receive the next instruction that needs to be decoded after the instruction is completely split into microinstructions and enters the renaming stage. And only one instruction is processed at a time. When the input width of the renaming unit is large, the number of generated microinstructions is insufficient to the input width, which will result in an inability to pass enough microinstructions to the renaming unit, and thus lead to low decoding throughput when processing the instruction stream. And the decoding throughput of the decoding stage will change with the change of the LMUL of the instruction. There are differences in the number of microinstructions obtained by decoding different instructions, which results in the decoding throughput of the instruction decoding stage being non-fixed, and a stable decoding throughput cannot be guaranteed.

[0018] Specifically, when LMUL is small, the number of generated microinstructions is small, resulting in a correspondingly low decoding throughput, which cannot support the decoding throughput required by high-performance processors. LMUL poses difficulties in the design of high-performance vector microarchitectures, and achieving high-throughput instruction decoding has become a technical problem that needs to be solved urgently.

[0019] The instruction processing method provided by the embodiment of the present invention is described in detail below.

[0020] Reference Figure 1 , shows a flowchart of the steps of an instruction processing method provided by an embodiment of the present invention, such as Figure 1 As shown, the method may specifically include the following steps: Step 101: select n instructions from the instruction stream as instructions to be decoded in the current round, and use n decoding units to decode the instructions to be decoded to obtain a microinstruction sequence; n is an integer not less than 2.

[0021] Step 102: delivering the microinstructions in a preset cache and the microinstructions in the microinstruction sequence to the renaming unit according to the input width of the renaming unit; the preset cache is used to store the microinstructions that were not delivered in the previous round.

[0022] Step 103: Write the undelivered microinstructions in the microinstruction sequence into the preset cache.

[0023] Step 104 : reselect n instructions from the instruction stream as instructions to be decoded in the next round, and return to the step of decoding the instructions to be decoded by using n decoding units until a stop condition is reached.

[0024] In an embodiment of the present invention, the instructions included in the instruction stream are instructions to be decoded, that is, pre-decoding instructions. The instructions in the instruction stream can be represented as MOP (Macro Operation). Microinstructions can also be called instruction micro-operations. After decoding an instruction, at least one microinstruction is generated. The microinstructions can be represented as UOP (Micro Operation). N decoding units constitute a decoding unit group. The n decoding units are multiple parallel decoding units. One decoding unit is a decoding channel (DecodeChannel). The number of decoding units n included in the decoding unit group is the decoding input width (MopWidth). MopWidth can be used to represent the maximum number of instructions that the decoding unit group can process simultaneously. The first instruction of the n instructions enters the first decoding unit, and the subsequent instructions of the N instructions enter the decoding units subsequent to the first decoding unit in sequence.

[0025] The input width of the renaming unit is the decoding output width (UopWidth), and UopWidth refers to the maximum number of microinstructions that the decoding unit group can output to the renaming unit. The specific values ​​of the decoding input width and the decoding output width can be set according to actual conditions, and the embodiment of the present invention does not limit this. For example, in one embodiment, MopWidth can be 8, and UopWidth can be 8. Furthermore, the microinstructions generated by all decoding units based on the instructions of the current round constitute the microinstruction sequence of the current round. Among them, for any decoding unit, the specific implementation method of the decoding unit decoding instructions into microinstructions can refer to the existing method, and the embodiment of the present invention does not limit this.

[0026] The preset buffer can be represented as DecodeBuffer. The preset buffer can be a storage unit. The size of the preset buffer (BufferSize) can be set based on UopWidth. The size of the preset buffer is used to represent the maximum number of microinstructions that can be stored in the preset buffer. For example, BufferSize can be less than the input width of the rename unit. This ensures that at least one microinstruction in the microinstruction sequence generated by the current round can be delivered each time. The instruction stream includes multiple instructions to be decoded. The instruction stream may include vector instructions. For example, the instruction stream is a mixed instruction stream including multiple scalar instructions and vector instructions. The scalar instructions and vector instructions in the instruction stream can be ordered arbitrarily. In actual application scenarios, the number of instructions included in the instruction stream is greater than n. Therefore, multiple rounds are required to complete the processing of the instruction stream. One round corresponds to one clock cycle. Every n instructions in the instruction stream serve as input to a round, that is, one round processes n instructions in the instruction stream.

[0027] For example, assuming that the instruction stream includes 32 instructions: instruction 1 to instruction 32, then in the first round, instructions 1 to instruction 8 can be processed, in the second round, instructions 9 to instruction 16 can be processed, in the third round, instructions 17 to instruction 24 can be processed, and in the fourth round, instructions 25 to instruction 32 can be processed. In this example, the first round is the first round. When entering the second round, the current round is the second round. Accordingly, the previous round is the first round, and the next round is the third round. When entering the third round, the current round is the third round. Accordingly, the previous round is the second round, and the next round is the fourth round. When entering the fourth round, the current round is the fourth round. Accordingly, the previous round is the third round. After completing the fourth round, since there are no remaining instructions, if the preset cache is currently empty, the processing flow ends directly. If the preset cache is not empty, the microinstructions in the preset cache are passed to the renaming unit in the next clock cycle (i.e., the next round) until the preset cache is empty, terminating the processing flow. That is, in this embodiment of the present invention, the stopping condition is pre-set, and the stopping condition is that there are no remaining instructions in the instruction stream and the preset cache is empty. This ensures that the microinstructions obtained by decoding all instructions in the instruction stream are passed to the renaming unit. It should be noted that if there are fewer than n remaining instructions, all remaining instructions can be used as instructions to be decoded in the next round.

[0028] It is understandable that when the current round is the first round, there is no previous round, and accordingly, the preset cache is empty. Accordingly, when the microinstructions in the preset cache and the microinstructions in the microinstruction sequence are transferred to the renaming unit, the microinstructions transferred to the renaming unit this time are all in the microinstruction sequence.

[0029] In an embodiment of the present invention, a preset cache is set to store microinstructions that have completed splitting within a round but cannot enter the renaming stage due to the input width of the renaming unit. In the current round, the microinstructions in the preset cache will be controlled to enter the renaming stage first, and at the same time, the microinstructions in the microinstruction sequence generated in the current round will be supplemented according to the input width of the renaming unit, and the input width of the renaming unit output in each round will be determined. The microinstructions ensure that the decoding throughput is fixed to the input width of the renaming unit. Of course, the microinstructions generated in the current round that have not been passed to the renaming unit will also be written to the preset cache. After the next round is started, the current round becomes the previous round, thereby ensuring that the preset cache stores the microinstructions that were not passed in the previous round.

[0030] In summary, in the instruction processing method provided by the embodiment of the present invention, n instructions are selected from the instruction stream as the instructions to be decoded in the current round, and n decoding units are used to decode the instructions to be decoded to obtain a microinstruction sequence; n is an integer not less than 2. According to the input width of the renaming unit, the microinstructions in the preset cache and the microinstructions in the microinstruction sequence are passed to the renaming unit; the preset cache is used to store the microinstructions that were not passed in the previous round. The microinstructions that were not passed in the microinstruction sequence are written to the preset cache. N instructions are reselected from the instruction stream as the instructions to be decoded in the next round, and the step of decoding the instructions to be decoded using n decoding units is returned to continue execution until the stop condition is reached. In this way, each time n instructions are decoded, the number of microinstructions in the microinstruction sequence obtained in the current round can be increased, so that sufficient microinstructions can be passed to the renaming unit, thereby improving the decoding throughput and improving the decoding efficiency.

[0031] And each time the microinstructions are passed to the renaming unit according to the input width of the renaming unit, that is, the input width microinstructions are passed to the renaming unit each time, avoiding the problem of decoding a single instruction, the decoding throughput is not fixed, and the stable decoding throughput cannot be guaranteed. At the same time, by introducing a preset cache, the microinstructions that were not passed in the previous round are stored, and the microinstructions in the preset cache are continued to be passed to the renaming unit in the current round. This makes it possible to pass these microinstructions to the renaming unit in the current round without re-decoding the instructions corresponding to the microinstructions in the preset cache, thereby improving the overall processing efficiency to a certain extent.

[0032] Optionally, the step of transferring the microinstructions in the preset cache and the microinstructions in the microinstruction sequence to the renaming unit according to the input width of the renaming unit specifically includes: Step 1021 : Use the microinstructions in the preset cache as first target microinstructions, and use the first p-q microinstructions in the microinstruction sequence as second target microinstructions.

[0033] Step 1022: Pass the first target microinstruction and the second target microinstruction to the renaming unit; p is the input width, and q is the number of the first target microinstructions.

[0034] Let q represent the number of microinstructions currently stored in the preset cache in the current round. The specific value of q may be different for different rounds. p-q represents the value of p minus q, and p represents the input width of the renaming unit, that is, the above-mentioned decoding output width. Since at most p microinstructions are passed to the renaming unit in each round, while ensuring that all q microinstructions stored in the preset cache in the previous round are passed in the current round, p-q microinstructions in the microinstruction sequence are supplemented, that is, the first target microinstruction and the second target microinstruction (the first p-q microinstructions in the microinstruction sequence) are passed to the renaming unit.

[0035] In an embodiment of the present invention, the microinstructions in the preset cache are used as the first target microinstructions, and the first p-q microinstructions in the microinstruction sequence are used as the second target microinstructions. The first and second target microinstructions are then passed to the rename unit. This ensures that each time the microinstructions in the preset cache are passed first, the p microinstructions are passed to the rename unit in conjunction with the current round of microinstruction sequence, thereby ensuring decoding throughput when processing the instruction stream.

[0036] Optionally, in a first implementation manner, the step of writing the undelivered microinstructions in the microinstruction sequence into the preset cache includes: Step 1031 : Starting from the first decoding unit among the n decoding units, sequentially accumulate the number of microinstructions generated by the decoding units for q.

[0037] Step 1032: When the accumulated value is not less than p, the instruction processed by the last decoding unit participating in the accumulation is used as the end instruction of the current round.

[0038] Step 1033: Write the microinstructions remaining in the microinstruction sequence that correspond to the end instruction of the current round into the preset cache.

[0039] The end instruction is the instruction corresponding to the last microinstruction among the first p-q microinstructions (i.e., the second target microinstruction). In this implementation, when some of the multiple microinstructions generated by an instruction are passed to the rename unit, the remaining microinstructions generated by the instruction that were not passed are written to a preset cache. Since the preset cache is essentially a storage unit, storing new data in the preset cache incurs additional power consumption. Therefore, this implementation adopts a more conservative approach. If none of the microinstructions generated by the instruction can enter the rename phase in the current round, the microinstructions are not written to the preset cache, and the instruction is re-decoded in the next round. This reduces power consumption during the decoding phase. If only some of the microinstructions generated by the instruction can enter the rename phase, while the rest cannot, the remaining microinstructions are written to the preset cache. This prevents the instructions that entered the rename phase from being stored and re-decoded in the decoding phase, thus avoiding blocking the decoding unit due to too many microinstructions generated from a single instruction. Accordingly, in this implementation, BufferSize can be 1 less than the maximum number of microinstructions split from a single instruction. For example, BufferSize is 7. This ensures that the preset cache can meet the storage requirements.

[0040] Specifically, a parallel microinstruction number calculation component can be set up for n decoding units in advance to parallelly calculate the number of microinstructions obtained by each decoding unit decoding the instruction, that is, to obtain the number of microinstructions generated by each decoding unit. According to the preset order of the decoding unit, the number of microinstructions generated by the decoding unit is accumulated for q in sequence. After each accumulation, it is detected whether the accumulated value meets the condition of being not less than p. If so, the accumulation operation is stopped, indicating that some microinstructions processed by the currently accumulated decoding unit may be unable to enter the renaming stage. Therefore, the instruction processed by the currently accumulated decoding unit (that is, the instruction processed by the last decoding unit participating in the accumulation) is used as the end instruction of the current round. Assume p is 8, and the preset cache in the current round contains one microinstruction, that is, q = 1. Decode units 1-8 decode instructions 4, 5, 6, 7, 8, 9, 10, and 1, respectively. The number of microinstructions generated by decode units 1-8 is 1, 4, 4, 1, 1, 1, 1, and 1, respectively. After the first accumulation, the accumulated value is 2. Since the accumulated value is less than 8, accumulation continues. After the second accumulation, the accumulated value is 6, and accumulation continues. After the third accumulation, the accumulated value is 10, satisfying the condition of being no less than 8, and accumulation ends. The last instruction processed by the decode unit participating in the accumulation (instruction 6) is used as the ending instruction for the current round. This is equivalent to completing the processing of all microinstructions generated by the decode units whose first microinstruction has a sequence number less than p in the current round. For a non-first decoding unit, the sequence number of the first microinstruction among the generated microinstructions=q+the number of microinstructions generated by all decoding units before the decoding unit+1.

[0041] Figure 2This is a schematic diagram of a re-decoding determination process provided by an embodiment of the present invention. Specifically, in this embodiment of the present invention, the instruction processing device further includes a second selection unit, namely, a BufferSelector. The second selection unit calculates the sequence number of the first microinstruction among the microinstructions generated by each decoding unit. Specifically, the second selection unit receives the number of microinstructions generated by each decoding unit. Starting from 1, the second selection unit first accumulates the number of microinstructions q in a preset buffer to obtain the sequence number of the first microinstruction among the microinstructions generated by the first decoding unit. It then continues to accumulate the number of microinstructions generated by the first decoding unit to obtain the sequence number of the first microinstruction among the microinstructions generated by the second decoding unit. This continues in this manner. If the accumulated value is greater than p, the counting ends. Alternatively, the sequence number of the first microinstruction among the microinstructions generated by all decoding units is directly calculated. The instruction processed by the last decoding unit whose first microinstruction sequence number is not greater than p is used as the ending instruction. In the above example, the sequence numbers of the first microinstructions among the microinstructions generated by each decoding unit are 2, 3, 7, 11, 12, 13, 14, and 15, respectively. Among them, the sequence number of the first microinstruction of the first three decoding units is not greater than p, so the instruction processed by the third decoding unit (instruction 6) is used as the end instruction. For the instructions processed by the decoding unit whose first generated microinstruction has a sequence number not greater than p, the processing is completed in the current round, and there is no need to re-enter the decoding stage in the next round. For the instructions processed by the decoding unit whose first generated microinstruction has a sequence number greater than p, the decoding stage is re-entered in the next round. For the above example, the processing of the first three instructions is completed in the current round, and the remaining 5 instructions re-enter the decoding stage in the next round. It should be noted that the embodiment of the present invention does not limit the algorithm and circuit for how instructions enter the decoding stage before the decoding stage.

[0042] In an embodiment of the present invention, for instructions that do not need to re-enter the decoding stage in the next round, the instruction completes the process from entering the decoding unit to the generated microinstruction entering the renaming stage or the preset cache within the current round, that is, from the instruction entering the decoding unit to the generated microinstruction entering the renaming stage or the preset cache, it only takes one clock cycle to complete. Therefore, this implementation method is more efficient and can improve the performance of the decoding stage.

[0043] Furthermore, if the accumulated value is equal to p when the accumulation operation ends, it indicates that there are no instructions in the current round for which only some microinstructions enter the renaming stage, and the microinstructions corresponding to the end instruction of the current round in the remaining microinstructions in the microinstruction sequence (i.e., the microinstructions in the microinstruction sequence excluding the second target microinstruction) are empty, that is, the microinstructions written to the preset cache in this round are empty. If the accumulated value is greater than p when the accumulation operation ends, it indicates that there are instructions in the current round for which only some microinstructions enter the renaming stage, and there is at least one microinstruction corresponding to the end instruction of the current round among the remaining microinstructions in the microinstruction sequence, that is, at least one microinstruction is written to the preset cache in this round.

[0044] Optionally, the step of reselecting n instructions from the instruction stream as instructions to be decoded in the next round specifically includes: Step 1041: Use the next instruction after the end instruction in the instruction stream as the start instruction of the next round.

[0045] Step 1042: Select n consecutive instructions starting from the start instruction as the instructions to be decoded in the next round.

[0046] Specifically, for each round, up to n consecutive instructions are read from the instruction stream as the instructions to be decoded for that round. Specifically, for the next round after the current round, instruction fetching starts from the instruction following the end instruction of the current round. For example, assuming that the end instruction of the current round is instruction 6, the 8 instructions following instruction 6 in the instruction stream can be obtained as the instructions to be decoded for the next round, and the processing of the next round can be started. In this way, it can be ensured that each round starts fetching instructions from the instruction that has been processed in the previous round, thereby avoiding instruction omissions.

[0047] Optionally, the step of decoding the instruction to be decoded by using n decoding units may specifically include: Step 1011: For any of the decoding units, use the decoding unit to process the instruction input to the decoding unit to obtain a microinstruction corresponding to the instruction.

[0048] An embodiment of the present invention may further include: step S31, taking the number of microinstructions corresponding to the instruction as a first number, and if the first number is not a preset fixed number, determining a fixed number with the smallest difference from the first number as a target number; adding invalid microinstructions to the microinstructions corresponding to the instruction so that the first number reaches the target number.

[0049] Invalid microinstructions refer to decode bubbles, which are bubbles output during the decoding phase and are not valid microinstructions. Specifically, void instructions (NOPs) can be inserted to ensure that the first number reaches a target number. The number of microinstructions corresponding to an instruction (the first number) is the number of microinstructions generated by the decoding unit when processing the instruction. If the number of microinstructions is a preset fixed number, there is no need to increase decode bubbles. If the number of microinstructions is not a preset fixed number, decode bubbles can be added to ensure that the number of microinstructions generated by each decoding unit reaches one of the preset fixed numbers. By constraining the number of microinstructions generated by each decoding unit to a preset fixed number, the input values ​​of the adder circuit implementing the relevant accumulation operation in the hardware circuit are constrained to these fixed numbers, significantly reducing the implementation complexity of the adder circuit implementing the accumulation operation. Furthermore, by determining the fixed number with the smallest difference from the first number as the target number, the number of invalid microinstructions required to be inserted can be minimized, thereby avoiding the frequent occurrence of decode bubbles.

[0050] The preset fixed number can be pre-set based on actual circumstances, and this is not a limitation in the present embodiment. For example, several commonly used numbers can be set as fixed numbers. Thus, for rare instructions where the number of microinstructions generated after processing does not fall within the fixed number, decode bubbles are added to the microinstructions generated for that instruction to achieve a certain commonly used number. For example, the preset fixed number can include 1, 2, 4, or 8, constraining the number of microinstructions ultimately generated by each decoder unit to one of 1, 2, 4, and 8. In this embodiment of the present invention, the instruction processing device may further include a microinstruction selector (a first selection unit). The inputs of the multiple adder circuits included in the first selection unit and the second selection unit are limited to the four values ​​of 1, 2, 4, and 8. For example, eight of the nine 4-bit adder circuits may only have these four input values, while the input values ​​of the remaining adder circuits may cover the number of microinstructions that may be included in the preset cache. This reduces circuit area, hardware circuit area overhead, and timing performance compared to adding circuits that support a wider range of input values, such as inputs of any value from 0 to 8. The first selection unit and the second selection unit can use a shorter number of logic gate levels to implement the selection logic of the microinstruction.

[0051] In an embodiment of the present invention, when an instruction to be decoded is input, the vector configuration information (VTYPE information) corresponding to the instruction is also input synchronously to guide the processing of the vector instruction. The VTYPE information is configured only for one instruction among the instructions to be decoded, and this VTYPE information is used for all subsequent instructions until the VTYPE information is modified. The method for extracting the VTYPE information from the vector configuration instruction and efficiently and correctly propagating it to each instruction in the instruction stream before the instruction stream enters the decoding stage can refer to existing technologies and is not limited in this embodiment of the present invention.

[0052] Figure 3 FIG. 1 is a schematic diagram of the number of microinstructions provided by an embodiment of the present invention. Figure 3 As shown, for a decoding unit, the number of microinstructions generated by the decoding unit is one of 1, 2, 4 or 8 based on the instruction input to the decoding unit and the vector configuration information. Assume that the instruction processed by the decoding unit is: vluxseg7ei8.v, Figure 4 is another schematic diagram related to the number of microinstructions provided by an embodiment of the present invention, such as Figure 4 As shown, 7 microinstructions are generated: microinstruction 0 to microinstruction 6. Therefore, one decode bubble can be used to fill the end of the microinstruction sequence generated by the decode unit, so that the number of microinstructions generated by the decode unit in the current round is 8.

[0053] Taking n as 8, i.e., including 8 decoding units as an example, combined with the instruction sequence .L10 in the assembly code in Table 1 below, how the multi-channel decoding unit performs instruction decoding is explained:

[0054] Table 1 Among them, .L10 indicates the tag of the instruction sequence, and e32, m4, ta, and ma represent vector configuration information. Specifically, e32, m4, ta, and ma are all vector configuration information, corresponding to SEW, LMUL, Vector Tail Agnostic (VTA), and Vector Mask Agnostic (VMA) in VTYPE, respectively. SEW and LMUL are related to instruction splitting, while VTA and VMA are not. VTA is used to indicate how the tail element in the destination vector register is handled, and VMA is used to indicate how masked elements in the destination vector register are handled. In this example, m4 indicates that LMUL used by subsequent instructions is set to 4.

[0055] Assume that instruction 10 in this example always jumps, that is, instructions 1 to 10 are executed cyclically in the instruction stream. The instruction stream can be viewed as: instruction 1, instruction 2, ... instruction 10, instruction 1, instruction 2, ... instruction 10, instruction 1, instruction 2...

[0056] Microinstruction ij represents the jth microinstruction split from the i-th instruction. Figure 5 This is a schematic diagram of a processing process provided by an embodiment of the present invention. Figure 5 As shown, at time T, there are 0 microinstructions in the preset cache, and instructions 1-8 enter the decoding phase. After decoding, instructions 1-3 complete processing in the current round. Instructions 1 and 2 generate a total of 5 microinstructions, all of which enter the renaming phase. Of the 4 microinstructions generated by instruction 3, only the first 3 can enter the renaming phase, and the remaining microinstruction enters the preset cache. Because all microinstructions generated by instruction 4 cannot enter the renaming phase, the preset cache does not receive the microinstructions generated by instruction 4, and instructions 4-8 re-enter the decoding phase in the next round. It should be noted that in this embodiment of the present invention, after the microinstructions in the preset cache are passed to the renaming unit in the current round, the preset cache is cleared, and then the operation of writing the microinstructions not passed in the microinstruction sequence of the current round to the preset cache is executed. Alternatively, a counter can be set for the preset cache to indicate the number of valid microinstructions in the preset cache, and microinstructions exceeding the counter (i.e., microinstructions in the preset cache that have been passed to the renaming unit in the current round) are determined to be invalid microinstructions. In each round, only valid microinstructions in the preset cache are delivered.

[0057] Then, proceed to the next round (T+1 time), Figure 6 This is another processing diagram provided by an embodiment of the present invention. Figure 6 As shown, at time T+1, there is one microinstruction (microinstructions 3 and 4) in the preset cache. Instructions 4-10 and instruction 1 enter the decoding stage. After decoding, instructions 4-6 are processed in the current round (the current round is at time T+1), generating a total of nine microinstructions. The microinstructions corresponding to the one microinstruction in the preset cache, instructions 4, and instruction 5 all enter the renaming stage. The first two microinstructions of instruction 6 enter the renaming stage, and the last two microinstructions enter the preset cache. Instructions 7-10 and instruction 1 re-enter the decoding stage in the next round.

[0058] Then, proceed to the next round (T+2 time), Figure 7 This is another processing diagram provided by an embodiment of the present invention. Figure 7As shown, at time T+2, the preset cache contains two microinstructions (microinstructions 6.3 and 6.4). Instructions 7-10 and instructions 1-4 enter the decoding stage. After decoding, instructions 7-10 and instructions 1-2 are processed within the current round (current round is now T+2), generating a total of nine microinstructions. The two microinstructions in the preset cache, all five microinstructions generated by instructions 7-10 and instruction 1, and the first microinstruction generated by instruction 2 enter the renaming stage. The last three microinstructions generated by instruction 2 enter the preset cache, and the next round begins.

[0059] It should be noted that, in an embodiment of the present invention, it is also possible not to set a preset cache, increase the input width of the renaming unit, and pass all microinstructions in the current round of microinstruction sequences to the renaming unit, so as to improve the decoding throughput. Furthermore, it is also possible to set only some decoding units to have the ability to process instructions that need to be split. Among them, instructions that need to be split refer to instructions that generate at least two microinstructions, and instructions that do not need to be split refer to instructions that only generate one microinstruction. Accordingly, when n instructions are input, the vector instructions in the n instructions are input into the decoding unit that has the ability to process instructions that need to be split. Alternatively, all decoding units are set to have the ability to process instructions that need to be split, so that the input of each decoding unit can be any scalar instruction and vector instruction.

[0060] In the embodiment of the present invention, by using multiple parallel decoding units, the function of decoding multiple instructions at the same time is realized, thereby increasing the decoding throughput of the decoding unit. Moreover, p microinstructions are selected each time, which solves the problem that the decoding throughput of the decoding stage varies with the change of LMUL. Moreover, for an instruction stream that is a mixture of instructions that need to be split and instructions that do not need to be split, n instructions are fed into the decoding unit each time, and the microinstructions generated for one of the instructions can be filled with the microinstructions generated by other instructions to ensure that the microinstructions obtained in the current round can provide sufficient microinstructions for the renaming unit, thereby improving the processing efficiency of the instruction stream, improving the decoding throughput for the instruction stream, and efficiently supporting the decoding splitting of the mixed instruction stream when the decoding output width is large.

[0061] Optionally, in a second implementation, the step of writing the undelivered microinstructions in the microinstruction sequence into the preset cache may include: Step 1034: Determine the first r microinstructions of the remaining microinstructions in the microinstruction sequence as microinstructions to be written; r is the size of the preset cache.

[0062] Step 1035 : Use the instruction corresponding to the last microinstruction in the microinstructions to be written as the target instruction. If the microinstructions to be written include all microinstructions corresponding to the target instruction, write the microinstructions to be written into the preset cache.

[0063] Step 1036: If the microinstructions to be written do not include all the microinstructions corresponding to the target instruction, then write the other microinstructions in the microinstructions to be written except the microinstructions corresponding to the target instruction into the preset cache.

[0064] In this implementation, the BufferSize of the DecodeBuffer is represented by r, which can be greater than the maximum number of microinstructions that can be split from a single instruction, thereby ensuring that the preset cache can store more microinstructions. In this approach, when writing the remaining microinstructions to the DecodeBuffer, while writing as many microinstructions as possible to the DecodeBuffer, the last microinstruction written to the DecodeBuffer is ensured to be the last microinstruction of the instruction.

[0065] Specifically, the first r microinstructions of the remaining microinstructions in the microinstruction sequence can be used as the microinstructions to be written. The instruction corresponding to the last microinstruction in the microinstructions to be written is used as the target instruction. The instruction corresponding to the last microinstruction refers to the instruction that is decoded to obtain the last microinstruction. Based on the constraint that the last microinstruction written to the DecodeBuffer is the last microinstruction of the instruction, if the microinstructions to be written include all microinstructions corresponding to the target instruction, then the last microinstruction in the microinstructions to be written is the last microinstruction of the target instruction. Therefore, the microinstructions to be written can be directly written to the preset cache. Conversely, if the microinstructions to be written do not include all microinstructions corresponding to the target instruction, then the last microinstruction in the microinstructions to be written is not the last microinstruction of the target instruction, and the microinstructions to be written include some microinstructions of the target instruction. Therefore, only the microinstructions in the microinstructions to be written, excluding the microinstructions corresponding to the target instruction, can be written to the preset cache. This avoids writing partial microinstructions split from an instruction, which would cause the instruction to be decoded again in the next round and generate microinstructions that duplicate those in the preset cache, thereby avoiding the problem of wasting processing resources.

[0066] For example, assuming r is 10, corresponding to the round at time T in the above example, the first r of the remaining microinstructions are: microinstructions 3.4, microinstruction 4.1, microinstructions 5.1 to microinstruction 5.4, and microinstructions 6.1 to microinstruction 6.4. Since the first r microinstructions include all microinstructions corresponding to the target instruction (instruction 6), microinstructions 3.4, microinstruction 4.1, microinstructions 5.1 to microinstruction 5.4, and microinstructions 6.1 to microinstruction 6.4 are written to the preset cache. Assuming r is 9, corresponding to the round at time T in the above example, the first r of the remaining microinstructions are: microinstruction 3.4, microinstruction 4.1, microinstruction 5.1 to microinstruction 5.4, and microinstruction 6.1 to microinstruction 6.3. Since the first r microinstructions do not include all microinstructions corresponding to the target instruction (instruction 6), microinstructions 3.4, microinstruction 4.1, and microinstruction 5.1 to microinstruction 5.4 are written to the preset cache.

[0067] Optionally, the step of reselecting n instructions from the instruction stream as instructions to be decoded in the next round may include: Step 1043: Use the instruction corresponding to the last microinstruction written into the preset cache as the end instruction of the current round.

[0068] Step 1044: Use the next instruction after the end instruction in the instruction stream as the start instruction of the next round.

[0069] Step 1045 : Select n consecutive instructions starting from the start instruction as the instructions to be decoded in the next round.

[0070] Corresponding to the second implementation, the instruction corresponding to the last microinstruction written into the preset cache is used as the end instruction of the current round. For example, corresponding to the above example where r is 10, instruction 6 can be used as the end instruction, and accordingly, the n instructions after instruction 6 are selected. Corresponding to the above example where r is 9, instruction 5 can be used as the end instruction, and accordingly, the n instructions after instruction 5 are selected as the instructions to be decoded in the next round, and the processing of the next round is started. In this way, it can be ensured that each round starts fetching instructions from the instructions processed in the previous round, thereby avoiding instruction omissions.

[0071] Optionally, the step of passing the first target microinstruction and the second target microinstruction to the renaming unit includes: Step 1022a: select any one of the first target microinstruction and the second target microinstruction as a first microinstruction, and generate a first selection signal for the first microinstruction based on the order of the first microinstruction in a target sequence; the target sequence includes the first target microinstruction and the microinstruction sequence, and the first target microinstruction is located before the microinstruction sequence in the target sequence; Step 1022b: Execute the first selection signal to select the first microinstruction and pass it to the rename unit.

[0072] In an embodiment of the present invention, a target sequence can be obtained by arranging the microinstructions in a preset cache before the microinstruction sequence of the current round, and arranging the microinstructions output by multiple decoding units in the microinstruction sequence of the current round in a sequential order (for example, arranging them in ascending order of the decoding unit encoding). In an embodiment of the present invention, a first selection unit is provided, and the first selection unit generates a first selection signal for the first microinstruction based on the order of the first microinstruction in the target sequence. By executing the first selection signal, the first microinstruction to be transmitted to the rename unit can be conveniently selected.

[0073] The first selection unit is the microinstruction Selector, and the first selection signal can be a one-hot encoding of the first microinstruction, i.e., a one-hot encoding signal. Specifically, the bit representing the actual source of the first microinstruction in the initial one-hot encoding corresponding to the sequence number of the first microinstruction in the target sequence can be set to 1 to obtain the first selection signal for the first microinstruction. That is, the selection signal represented by the initial one-hot encoding after the setting serves as the first selection signal for the first microinstruction. A bit in the initial one-hot encoding corresponding to the sequence number of the first microinstruction in the target sequence represents a source corresponding to the microinstruction with that sequence number. The initial one-hot encoding can default to all 0s. The sequence number of the microinstruction in the target sequence indicates the microinstruction's nth microinstruction in the target sequence, i.e., the order of the microinstruction in the target sequence. For example, the sequence number of the xth microinstruction in the target sequence is x. Specifically, due to the above two rules and the rule that each decoding unit splits out a fixed number of microinstructions, the possible sources of each microinstruction in the target sequence are fixed. The source of the microinstruction is related to the sequence number of the microinstruction. Taking p=8 as an example, the first target microinstruction and the second target microinstruction that need to be passed to the renaming unit in the current round are the first 8 microinstructions in the target sequence.

[0074] Based on the three rules of splitting each decoder into 1, 2, 4, and 8 microinstructions, prioritizing the microinstructions in the preset cache before the current round's microinstruction sequence, and sequentially arranging the microinstructions output by multiple decoders in the current round's microinstruction sequence, we can derive the source of each bit in the initial one-hot encoding of the eight microinstructions passed to the rename unit, i.e., the first through eighth microinstructions. Assuming the preset cache size is 7, with numbers 1, 2, ..., and 7 representing the first, second, ..., and seventh microinstructions in the preset cache, respectively, a decoder unit has eight ports: port 1 through port 8, each of which can output one microinstruction. The yth microinstruction generated by the decoder unit is generated by the yth port of the decoder unit. Figure 8 This is a schematic diagram of an initial one-hot encoding shown in an embodiment of the present invention, such as Figure 8 As shown, for the first microinstruction that needs to be passed to the rename unit, it may be selected from the first microinstruction in the preset cache and the first microinstruction generated by the first decode unit (corresponding to port 1 of decode unit 1). Therefore, the initial one-hot encoding corresponding to the first microinstruction includes two bits corresponding to number 1 of the preset cache and port 1 of decode unit 1, respectively. For the second microinstruction that needs to be passed to the rename unit, it may be selected from the second microinstruction in the preset cache, the first microinstruction and the second microinstruction generated by the first decode unit (corresponding to ports 1 and 2 of decode unit 1), and the first microinstruction generated by the second decode unit (corresponding to port 1 of decode unit 2). Therefore, the initial one-hot encoding corresponding to the second microinstruction includes four bits corresponding to number 2 of the preset cache, ports 1 and 2 of decode unit 1, and port 1 of decode unit 2, respectively. Among them, port g of decoding unit f represents the g-th port of the f-th decoding unit, and corresponds to outputting the g-th microinstruction generated by the instruction entering the decoding unit.

[0075] Similarly, for the zth microinstruction (z ≤ 7) that needs to be passed to the rename unit, it may be selected from the zth microinstruction in the preset cache, the first microinstruction generated by the first decode unit, the second microinstruction, ..., the zth microinstruction (corresponding to ports 1 to z of decode unit 1), the first microinstruction generated by the second decode unit, ..., the z-1th microinstruction (corresponding to ports 1 to z-1 of decode unit 2), ..., the first microinstruction generated by the zth decode unit (corresponding to port 1 of decode unit z). Therefore, the initial one-hot encoding corresponding to the zth microinstruction includes multiple bits corresponding to the preset cache entry no.z, ports 1 to z of decode unit 1, ports 1 to z-1 of decode unit 2, ..., and port 1 of decode unit z. For the eighth microinstruction that needs to be passed to the rename unit, because the preset cache only has seven entries, the eighth microinstruction does not need to be selected from the preset cache. The eighth microinstruction may be selected from a total of 36 ports of the eight decode units.

[0076] Corresponding to the time T in the above example, the first selection signal generated by the first selection unit may include: 01 0001 0000010 … 000000000000000001000000000000000000 In an embodiment of the present invention, a one-hot encoding can be used as a selection signal, combined with an AND-OR combination circuit in the first selection unit to implement selection. For the w-th microinstruction in the target sequence, the initial one-hot encoding of the microinstruction can represent an alternative microinstruction sequence for the microinstruction. Among them, the microinstructions from the source represented by all bits in the initial one-hot encoding of the microinstruction constitute the alternative microinstruction sequence. Exemplarily, for the second microinstruction, the alternative microinstruction sequence of the second microinstruction includes: the second microinstruction in the preset cache (in this example, the preset cache does not include the second microinstruction for illustration), the microinstruction output by port 1 of decoding unit 1: microinstruction 1.1, the microinstruction output by port 2 of decoding unit 1: microinstruction 1.2, and the microinstruction output by port 1 of decoding unit 2: microinstruction 2.1. Figure 9 This is a selection diagram provided by an embodiment of the present invention, such as Figure 9 As shown, for the second microinstruction, the candidate microinstruction sequence of the second microinstruction and the first selection signal of the second microinstruction ( Figure 9 0001 is used as the input of the selection circuit of the second microinstruction of the target sequence. For this example, the output of the selection circuit of the second microinstruction is microinstruction 2.1.

[0077] It is understandable that when the hth microinstruction of the target sequence needs to be selected, the candidate microinstruction sequence for the hth microinstruction and the selection signal of the hth microinstruction are used as inputs to the selection circuit for the hth microinstruction of the target sequence, and the output of the selection circuit for the hth microinstruction is the hth microinstruction. The selection signal may be the first selection signal, the second selection signal, or the third selection signal in the embodiment of the present invention.

[0078] Using one-hot encoding as the selection signal enables a two-stage AND-OR combinational circuit to select the microinstructions to be passed to the rename unit from the target sequence. Using one-hot encoding as the selection signal, combined with the AND-OR combinational circuit for selection, enables a selection circuit with the shortest critical path, achieving optimal timing.

[0079] Optionally, the step of writing the microinstructions corresponding to the end instruction of the current round among the remaining microinstructions in the microinstruction sequence into the preset cache includes: Step 1033a: Take any microinstruction among the remaining microinstructions corresponding to the end instruction of the current round as the second microinstruction, and generate a second selection signal for the second microinstruction based on the order of the second microinstruction in the target sequence by a second selection unit; the target sequence includes the first target microinstruction and the microinstruction sequence, and the first target microinstruction in the target sequence is located before the microinstruction sequence.

[0080] Step 1033b: Execute the second selection signal to select the second microinstruction and write it into the preset cache.

[0081] The second selection unit is a BufferSelector, and the second selection signal can be a one-hot encoding of the second microinstruction. Specifically, the bit representing the actual source of the second microinstruction in the initial one-hot encoding corresponding to the sequence number of the second microinstruction in the target sequence can be set to 1 to obtain the second selection signal of the second microinstruction. That is, the selection signal represented by the initial one-hot encoding after setting serves as the second selection signal of the second microinstruction. In this case, one bit in the initial one-hot encoding corresponding to the sequence number of the second microinstruction in the target sequence represents a source corresponding to the microinstruction with that sequence number. The initial one-hot encoding corresponding to each sequence number can be pre-set, and the value of each initial one-hot encoding can be defaulted to all 0s. For example, assuming that the microinstructions corresponding to the end instruction of the current round among the remaining microinstructions include microinstructions 6.3 and 6.4, and microinstructions 6.3 and 6.4 are the 9th and 10th microinstructions in the target sequence, then selection signals for the 9th and 10th microinstructions can be generated, respectively, to obtain the second selection signal for the 9th microinstruction and the second selection signal for the 10th microinstruction. In the embodiment of the present invention, the one-hot encoding of the second microinstruction can be used as the selection signal, combined with the AND-OR combination circuit in the second selection unit to achieve selection.

[0082] It should be noted that, for any microinstruction that needs to be written into the preset cache as the third microinstruction in the second implementation, the same method can be adopted, and the second selection unit sets the bit representing the actual source of the third microinstruction in the initial one-hot encoding corresponding to the serial number of the third microinstruction in the target sequence to 1, thereby obtaining the third selection signal of the third microinstruction. That is, the selection signal represented by the initial one-hot encoding after setting is used as the third selection signal of the third microinstruction. The third selection signal is executed to select the third microinstruction and write it into the preset cache. The first selection signal, the second selection signal and the third selection signal in the embodiment of the present invention are all selections, and the first selection signal, the second selection signal and the third selection signal respectively represent the selection signals of the first microinstruction, the second microinstruction and the third microinstruction.

[0083] In an embodiment of the present invention, a second selection unit is set up, and the second selection unit generates a second selection signal for the second microinstruction based on the order of the second microinstruction in the target sequence. By executing the second selection signal, the second microinstruction that needs to be written into the preset cache can be conveniently selected.

[0084] Figure 10 This is a schematic diagram of an instruction processing shown in an embodiment of the present invention. Figure 10As shown, the instructions to be decoded and their vector configuration information are input into multiple decoding units, and the microinstructions in the preset cache and the microinstructions output by the multiple decoding units form a target sequence. The first selection unit can select the first microinstruction from the target sequence to be passed to the rename unit, and the second selection unit can select the second microinstruction from the target sequence to be written into the preset cache.

[0085] It should be noted that in the last round, the number of microinstructions in the target sequence may be less than UOPWidth due to the small number of remaining instructions. In this case, all microinstructions in the target sequence can be selected. That is, the number of microinstructions selected from the target sequence by the first selection unit satisfies the condition of not exceeding UOPWidth.

[0086] In an embodiment of the present invention, for any current round, the number of microinstructions q included in the preset cache and the number of microinstructions decoded by each decoding unit are transmitted to the first selection unit and the second selection unit. The first selection unit and the second selection unit use q and the number of microinstructions decoded by each decoding unit to calculate the sequence number of each microinstruction in the preset cache and the sequence number of the first microinstruction among the microinstructions generated by each decoding unit. Based on the sequence number of the first microinstruction among the microinstructions generated by each decoding unit, the sequence numbers of all microinstructions in the target sequence are determined. The sequence number of the microinstruction is the sequence number of the microinstruction in the target sequence.

[0087] Among them, the method for calculating the sequence number of the first microinstruction in the microinstructions generated by each decoding unit can refer to the above and will not be repeated here. For each microinstruction in the preset cache, the sequence number of the e-th microinstruction is set to e, where e is not greater than q. For any decoding unit, the sequence number of the first microinstruction in the microinstructions generated by the decoding unit is accumulated k times, and the accumulation amount is 1 each time, and the value obtained by each accumulation is used as the sequence number of another microinstruction in the microinstructions generated by the decoding unit. Among them, k is the total number of other microinstructions in the microinstructions generated by the decoding unit, and k is an integer not less than 0. Accordingly, after obtaining the sequence number of each microinstruction, it is convenient to generate a selection signal for the microinstruction based on the sequence number of the microinstruction in the target sequence.

[0088] Figure 11 FIG. 1 is a schematic diagram of a microinstruction transmission provided by an embodiment of the present invention, such as Figure 11 As shown, for the microinstruction generated by the decode unit in the current round, the sequence number of the microinstruction in the target sequence can be calculated. If the sequence number is not greater than the input width of the rename unit, the microinstruction is passed to the rename unit to enter the rename stage.

[0089] Of course, if the sequence number is greater than the input width of the rename unit, the microinstruction is written into a preset cache or discarded so that the microinstruction can be regenerated in the next round.

[0090] In the embodiment of the present invention, a first selection unit and a second selection unit are introduced to select microinstructions from the target sequence to be passed to the rename unit and microinstructions to be written to the preset cache based on these two units. Since the first selection unit selects UopWidth microinstructions by default to pass to the rename unit, the problem of the throughput of the decoding stage varying with the LMUL is avoided to a certain extent, allowing the decoding stage to output the decoding throughput required to support high-performance processors.

[0091] Reference Figure 12 , shows a block diagram of an instruction processing device provided by an embodiment of the present invention, such as Figure 12 As shown, the device may specifically include: The first processing module 201 is configured to select n instructions from the instruction stream as instructions to be decoded in the current round, and decode the instructions to be decoded using n decoding units to obtain a microinstruction sequence; n is an integer not less than 2; A transfer module 202 is configured to transfer microinstructions in a preset cache and microinstructions in the microinstruction sequence to the renaming unit according to the input width of the renaming unit; the preset cache is used to store microinstructions that were not transferred in the previous round; A writing module 203 is configured to write the undelivered microinstructions in the microinstruction sequence into the preset cache; The second processing module 204 is configured to reselect n instructions from the instruction stream as instructions to be decoded in the next round, and return to the step of decoding the instructions to be decoded using n decoding units to continue executing until a stop condition is reached.

[0092] Optionally, the transmission module 202 is specifically configured to: Using the microinstructions in the preset cache as first target microinstructions and using the first p-q microinstructions in the microinstruction sequence as second target microinstructions; The first target microinstruction and the second target microinstruction are passed to the renaming unit; p is the input width, and q is the number of the first target microinstructions.

[0093] Optionally, the writing module 203 is specifically configured to: Starting from a first decoding unit among the n decoding units, sequentially accumulating the number of microinstructions generated by the decoding units for the q; If the accumulated value is not less than p, the instruction processed by the last decoding unit participating in the accumulation is used as the end instruction of the current round; The microinstructions remaining in the microinstruction sequence and corresponding to the end instruction of the current round are written into the preset cache.

[0094] Optionally, the second processing module 204 is specifically configured to: Using the next instruction after the end instruction in the instruction stream as the start instruction of the next round; Starting from the starting instruction, n consecutive instructions are selected as the instructions to be decoded in the next round.

[0095] Optionally, the first processing module 201 is specifically configured to: For any of the decoding units, using the decoding unit to process the instruction input to the decoding unit to obtain a microinstruction corresponding to the instruction; The number of microinstructions corresponding to the instruction is taken as the first number. If the first number is not a preset fixed number, the fixed number with the smallest difference from the first number is determined as the target number; invalid microinstructions are added to the microinstructions corresponding to the instruction so that the first number reaches the target number.

[0096] Optionally, the transmission module 202 is further configured to: any one of the first target microinstruction and the second target microinstruction is used as a first microinstruction, and a first selection unit generates a first selection signal for the first microinstruction based on the order of the first microinstruction in a target sequence; the target sequence includes the first target microinstruction and the microinstruction sequence, and the first target microinstruction is located before the microinstruction sequence in the target sequence; The first selection signal is executed to select the first microinstruction and transmit the first microinstruction to the renaming unit.

[0097] Optionally, the writing module 203 is further configured to: any microinstruction among the remaining microinstructions corresponding to the end instruction of the current round is used as a second microinstruction, and a second selection unit generates a second selection signal for the second microinstruction based on an order of the second microinstruction in a target sequence; the target sequence includes the first target microinstruction and the microinstruction sequence, and the first target microinstruction is located before the microinstruction sequence in the target sequence; The second selection signal is executed to select the second microinstruction and write it into the preset cache.

[0098] Optionally, the transmission module 202 is specifically configured to: Determine the first r microinstructions among the remaining microinstructions in the microinstruction sequence as microinstructions to be written; wherein r is the size of the preset cache; Taking the instruction corresponding to the last microinstruction in the microinstructions to be written as the target instruction, and if the microinstructions to be written include all microinstructions corresponding to the target instruction, writing the microinstructions to be written into the preset cache; If the microinstructions to be written do not include all the microinstructions corresponding to the target instruction, the other microinstructions in the microinstructions to be written except the microinstructions corresponding to the target instruction are written into the preset cache.

[0099] Optionally, the second processing module 204 is specifically configured to: Using the instruction corresponding to the last microinstruction written into the preset cache as the end instruction of the current round; Using the next instruction after the end instruction in the instruction stream as the start instruction of the next round; Starting from the starting instruction, n consecutive instructions are selected as the instructions to be decoded in the next round.

[0100] In summary, in the instruction processing device provided by the embodiment of the present invention, n instructions are selected from the instruction stream as the instructions to be decoded in the current round, and n decoding units are used to decode the instructions to be decoded to obtain a microinstruction sequence; n is an integer not less than 2. According to the input width of the renaming unit, the microinstructions in the preset cache and the microinstructions in the microinstruction sequence are passed to the renaming unit; the preset cache is used to store the microinstructions that were not passed in the previous round. The microinstructions that were not passed in the microinstruction sequence are written to the preset cache. N instructions are reselected from the instruction stream as the instructions to be decoded in the next round, and the step of decoding the instructions to be decoded using n decoding units is returned to continue execution until the stop condition is reached. In this way, each time n instructions are decoded, the number of microinstructions in the microinstruction sequence obtained in the current round can be increased, so that sufficient microinstructions can be passed to the renaming unit, thereby improving the decoding throughput and improving the decoding efficiency.

[0101] And each time the microinstructions are passed to the renaming unit according to the input width of the renaming unit, that is, the input width microinstructions are passed to the renaming unit each time, avoiding the problem of decoding a single instruction, the decoding throughput is not fixed, and the stable decoding throughput cannot be guaranteed. At the same time, by introducing a preset cache, the microinstructions that were not passed in the previous round are stored, and the microinstructions in the preset cache are continued to be passed to the renaming unit in the current round. This makes it possible to pass these microinstructions to the renaming unit in the current round without re-decoding the instructions corresponding to the microinstructions in the preset cache, thereby improving the overall processing efficiency to a certain extent.

[0102] Reference Figure 13 , is a schematic diagram of the structure of an electronic device provided by an embodiment of the present invention. Figure 13 As shown, the electronic device includes: a processor, a memory, a communication interface, and a communication bus. The processor, the memory, and the communication interface communicate with each other via the communication bus. The memory is used to store executable instructions that enable the processor to execute the instruction processing method of the aforementioned embodiment. The executable instructions can constitute a program.

[0103] An embodiment of the present invention provides a readable storage medium having executable instructions stored thereon. When executed by one or more processors, the processors are enabled to execute the instruction processing method of the aforementioned embodiment.

[0104] The various embodiments in this specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the various embodiments can be referenced to each other.

[0105] Those skilled in the art will appreciate that the embodiments of the present invention may be provided as methods, devices, or computer program products. Therefore, the embodiments of the present invention may take the form of a complete hardware embodiment, a complete software embodiment, or an embodiment combining software and hardware. Moreover, the embodiments of the present invention may take the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code. It should be noted that all actions of acquiring signals, information, or data in this application are performed in compliance with the relevant data protection laws and policies of the country of residence and with authorization from the owner of the corresponding device. The embodiments of the present invention are described with reference to the flowcharts and / or block diagrams of the methods, terminal devices (systems), and computer program products according to the embodiments of the present invention. It should be understood that each process and / or box in the flowchart and / or block diagram, as well as the combination of processes and / or boxes in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing terminal device to produce a machine, so that the instructions executed by the processor of the computer or other programmable data processing terminal device generate instructions for implementing the processes in the process. Figure 1 a process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.

[0106] These computer program instructions may also be stored in a computer readable memory capable of directing a computer or other programmable data processing terminal device to operate in a predictable manner, so that the instructions stored in the computer readable memory produce an article of manufacture comprising an instruction device, which implements the process Figure 1 a process or multiple processes and / or boxes Figure 1 The function specified in one or more boxes.

[0107] These computer program instructions can also be loaded onto a computer or other programmable data processing terminal device so that a series of operating steps are executed on the computer or other programmable terminal device to produce a computer-implemented process, thereby providing instructions for executing on the computer or other programmable terminal device to implement the process. Figure 1 a process or multiple processes and / or boxes Figure 1 A step that specifies a function in one or more boxes.

[0108] Although the preferred embodiments of the present invention have been described, those skilled in the art may make additional changes and modifications to these embodiments once they become aware of the basic creative concepts. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications that fall within the scope of the embodiments of the present invention.

[0109] Finally, it should be noted that, in this document, relational terms such as first and second, etc., are used only to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations. Moreover, the terms "comprises," "comprising," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or terminal device that includes a series of elements includes not only those elements, but also other elements not explicitly listed, or elements inherent to such process, method, article, or terminal device. In the absence of further limitations, an element defined by the phrase "comprising a ..." does not exclude the presence of additional identical elements in the process, method, article, or terminal device that includes the element.

[0110] The above is a detailed introduction to an instruction processing method, an instruction processing device, an electronic device and a readable storage medium provided by the present invention. Specific examples are used herein to illustrate the principles and implementation methods of the present invention. The description of the above embodiments is only used to help understand the method of the present invention and its core idea. At the same time, for those skilled in the art, according to the ideas of the present invention, there will be changes in the specific implementation methods and application scopes. In summary, the content of this specification should not be understood as limiting the present invention.

Claims

1. A method for processing an instruction, characterized in that: The method comprises: Selecting n instructions from the instruction stream as instructions to be decoded in the current round, and decoding the instructions to be decoded using n decoding units to obtain a microinstruction sequence; wherein n is an integer not less than 2; delivering microinstructions in a preset cache and microinstructions in the microinstruction sequence to the renaming unit according to an input width of the renaming unit; the preset cache is used to store microinstructions that were not delivered in the previous round; The undelivered microinstructions in the microinstruction sequence are written into the preset cache, and n instructions are reselected from the instruction stream as instructions to be decoded in the next round, and the step of decoding the instructions to be decoded using n decoding units is returned to until a stop condition is reached.

2. The method according to claim 1, characterized in that The step of transferring the microinstructions in the preset cache and the microinstructions in the microinstruction sequence to the rename unit according to the input width of the rename unit includes: Using the microinstructions in the preset cache as first target microinstructions and using the first p-q microinstructions in the microinstruction sequence as second target microinstructions; The first target microinstruction and the second target microinstruction are passed to the renaming unit; p is the input width, and q is the number of the first target microinstructions.

3. The method according to claim 2, characterized in that Writing the undelivered microinstructions in the microinstruction sequence into the preset cache comprises: Starting from a first decoding unit among the n decoding units, sequentially accumulating the number of microinstructions generated by the decoding units for the q; If the accumulated value is not less than p, the instruction processed by the last decoding unit participating in the accumulation is used as the end instruction of the current round; The microinstructions remaining in the microinstruction sequence and corresponding to the end instruction of the current round are written into the preset cache.

4. The method according to claim 3, characterized in that The reselecting n instructions from the instruction stream as instructions to be decoded in the next round includes: Using the next instruction after the end instruction in the instruction stream as the start instruction of the next round; Starting from the starting instruction, n consecutive instructions are selected as the instructions to be decoded in the next round.

5. The method according to claim 1, wherein The step of decoding the instruction to be decoded by using n decoding units includes: For any of the decoding units, using the decoding unit to process the instruction input to the decoding unit to obtain a microinstruction corresponding to the instruction; The method also includes: taking the number of microinstructions corresponding to the instruction as a first number, and if the first number is not a preset fixed number, determining the fixed number with the smallest difference from the first number as the target number; and adding invalid microinstructions to the microinstructions corresponding to the instruction so that the first number reaches the target number.

6. The method according to claim 2, characterized in that The step of passing the first target microinstruction and the second target microinstruction to the renaming unit includes: any one of the first target microinstruction and the second target microinstruction is used as a first microinstruction, and a first selection unit generates a first selection signal for the first microinstruction based on the order of the first microinstruction in a target sequence; the target sequence includes the first target microinstruction and the microinstruction sequence, and the first target microinstruction is located before the microinstruction sequence in the target sequence; The first selection signal is executed to select the first microinstruction and transmit the first microinstruction to the renaming unit.

7. The method according to claim 3, characterized in that Writing the microinstructions corresponding to the end instruction of the current round among the remaining microinstructions in the microinstruction sequence into the preset cache includes: any microinstruction among the remaining microinstructions corresponding to the end instruction of the current round is used as a second microinstruction, and a second selection unit generates a second selection signal for the second microinstruction based on an order of the second microinstruction in a target sequence; the target sequence includes the first target microinstruction and the microinstruction sequence, and the first target microinstruction is located before the microinstruction sequence in the target sequence; The second selection signal is executed to select the second microinstruction and write it into the preset cache.

8. The method according to claim 1, characterized in that Writing the undelivered microinstructions in the microinstruction sequence into the preset cache comprises: Determine the first r microinstructions among the remaining microinstructions in the microinstruction sequence as microinstructions to be written; wherein r is the size of the preset cache; Taking the instruction corresponding to the last microinstruction in the microinstructions to be written as the target instruction, and if the microinstructions to be written include all microinstructions corresponding to the target instruction, writing the microinstructions to be written into the preset cache; If the microinstructions to be written do not include all the microinstructions corresponding to the target instruction, the other microinstructions in the microinstructions to be written except the microinstructions corresponding to the target instruction are written into the preset cache.

9. The method according to claim 8, characterized in that The reselecting n instructions from the instruction stream as instructions to be decoded in the next round includes: Using the instruction corresponding to the last microinstruction written into the preset cache as the end instruction of the current round; Using the next instruction after the end instruction in the instruction stream as the start instruction of the next round; Starting from the starting instruction, n consecutive instructions are selected as the instructions to be decoded in the next round.

10. An instruction processing device, characterized in that: The device comprises: A first processing module is configured to select n instructions from an instruction stream as instructions to be decoded in a current round, and decode the instructions to be decoded using n decoding units to obtain a microinstruction sequence; wherein n is an integer not less than 2; a transfer module, configured to transfer microinstructions in a preset cache and microinstructions in the microinstruction sequence to the renaming unit according to an input width of the renaming unit; the preset cache is used to store microinstructions that were not transferred in the previous round; A writing module, configured to write the undelivered microinstructions in the microinstruction sequence into the preset cache; The second processing module is used to reselect n instructions from the instruction stream as instructions to be decoded in the next round, and return to the step of decoding the instructions to be decoded by using n decoding units until a stop condition is reached.

11. An electronic device, characterized in that: include: A processor, a memory, a communication interface, and a communication bus, wherein the processor, the memory, and the communication interface communicate with each other via the communication bus; The memory is used to store executable instructions, and the executable instructions enable the processor to execute the method according to any one of claims 1 to 9.

12. A readable storage medium, characterized in that: Executable instructions are stored thereon, which, when executed by one or more processors, cause the processors to perform the method according to any one of claims 1 to 9.

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