Full-dynamic index increment type low-delay high-precision analog-to-digital converter

Abstract

The invention relates to a full-dynamic exponential increment type low-delay high-precision analog-to-digital converter, which comprises a loop integrator used for receiving an ith-round input signal, and sequentially performing addition processing and integration processing on the ith-round input signal and a feedback signal calibrated by an (i-1) th round to obtain an ith-round integration signal; the first-order exponential increment error feedback noise shaping SAR quantizer is used for carrying out addition processing and multi-bit quantization on the ith round integral signal and the double (i-1) th round residual signal to obtain an ith round quantization signal; the digital-to-analog conversion module is used for sequentially performing format conversion, mismatch calibration and digital-to-analog conversion on the (i-1) th round of quantized signals in the process of processing the ith round of input signals to obtain feedback signals after the (i-1) th round of calibration; and the digital decimation filter module is used for carrying out digital filtering and down-sampling processing on the ith-round quantized signal to obtain an ith-round Nyquist rate output signal. The system can realize higher significant digits in shorter conversion time.

Description

Technical Field

[0001] The present invention belongs to the technical field of digital-analog hybrid integrated circuits, and in particular relates to a full-dynamic exponential incremental low-delay high-precision analog-to-digital converter. Background Art

[0002] In recent years, with the rapid development of semiconductor and integrated circuit technology, the number of MOS transistors integrated into very large-scale integrated circuits (VLSIs) has reached millions or even billions, greatly improving the processing performance of integrated circuits and rapidly entering the digital age. However, the physical quantities and processes we see and experience in the real world are all continuously changing analog signals. Analog signals have weak interference resistance and are prone to distortion and aliasing during transmission. Therefore, they must be converted into digital signals with high stability and strong interference resistance. The analog-to-digital converter (ADC) is the interface between analog signals and discrete digital signals, and it is also the bridge between the physical world and the electronic information world. In recent years, the Sigma-Delta ADC, with its unique noise shaping and oversampling technologies, has become an ideal choice for low-frequency signal processing scenarios that require high precision and strong interference resistance.

[0003] In ultra-low-frequency signal processing scenarios, such as bioelectric signal acquisition front-ends and precision sensors, the system places stringent demands on the noise suppression and quantization accuracy of analog-to-digital converters. Incremental Sigma-Delta analog-to-digital converters use noise shaping and oversampling techniques to shift quantization noise outside the target frequency band, and achieve a high effective number of bits through digital filtering and downsampling. Furthermore, an additional timed reset operation allows the analog-to-digital converter to overcome the effects of idle tones. Its digital filter structure is simpler, with shorter latency, making it more suitable for sensor interface circuits requiring time-division multiplexing.

[0004] However, for traditional incremental Sigma-Delta analog-to-digital converters, in order to further increase the effective number of bits, one can increase the number of quantizer bits, but this will cause the overhead of the mismatch calibration module circuit to increase exponentially; the second is to increase the oversampling rate, but this will inevitably increase power consumption; in addition, increasing the order of the loop can also increase the effective number of bits, but this will cause loop instability and narrow the signal input range. Summary of the Invention

[0005] In order to solve the above problems existing in the prior art, the present invention provides a full-dynamic exponential incremental low-latency high-precision analog-to-digital converter. The technical problem to be solved by the present invention is achieved through the following technical solutions:

[0006] The present invention provides a full-dynamic exponential incremental low-latency high-precision analog-to-digital converter, comprising: a loop integrator, a first-order exponential incremental error feedback noise shaping SAR quantizer, a digital-to-analog conversion module, and a digital decimation filter module; the loop integrator is used to receive an i-th round input signal, and sequentially perform addition processing on the i-th round input signal and a feedback signal after calibration of the i-1th round, and perform integration processing to obtain an i-th round integrated signal, wherein the i-th round integrated signal includes the i-th round first differential signal V DSM_N and the second differential signal V of the i-th round DSM_P ; i is a positive integer greater than or equal to 1; the first-order exponential incremental error feedback noise shaping SAR quantizer is used to add the i-th round integrated signal and twice the i-1-th round residual signal to obtain the i-th round added signal, and perform multi-bit quantization on the i-th round added signal to obtain the i-th round quantized signal; the i-1-th round residual signal is generated internally by the first-order exponential incremental error feedback noise shaping SAR quantizer in the i-1-th round; the digital-to-analog conversion module is used to perform format conversion, mismatch calibration and digital-to-analog conversion on the i-1-th round quantized signal in sequence during the process of processing the i-th round input signal to obtain the i-1-th round calibrated feedback signal; the digital decimation filter module is used to perform digital filtering on the i-th round quantized signal to obtain the i-1-th round Nyquist rate output signal.

[0007] Compared with the prior art, the present invention has the following beneficial effects:

[0008] The fully dynamic exponential incremental low-latency, high-precision analog-to-digital converter of this embodiment effectively improves the analog-to-digital converter's ability to suppress quantization noise by embedding a first-order exponential incremental error feedback noise-shaping SAR quantizer. Its exponential operating mode accelerates residual accumulation, achieving a higher effective number of bits with a shorter conversion cycle without adding additional hardware overhead. The first-order exponential incremental error feedback noise-shaping SAR quantizer employs a dynamic buffer and capacitor stacking technology to double the accumulation of residual signals. The internal buffer utilizes a dynamic unity-gain buffer based on an inverter, and the loop integrator utilizes a switched-capacitor integrator based on a dynamic floating inverter amplifier. Both are enabled during operation and reset in the non-operating state to eliminate quiescent current, meeting low-power requirements. Furthermore, a periodic global reset operation clears signal information stored in the integrator, quantizer, and filter, allowing operation to begin from a fresh system state. This ensures that the exponential operating mode does not cause system saturation. Furthermore, the digital decimation filter has a simpler structure and lower latency, making the analog-to-digital converter provided by the present invention more suitable for sensor interface circuits requiring time-division multiplexing. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Figure 1This is a structural diagram of a full-dynamic exponential incremental low-latency high-precision analog-to-digital converter provided by the present invention;

[0010] Figure 2 This is a schematic diagram of the system structure of the full-dynamic exponential incremental low-latency high-precision analog-to-digital converter provided by the present invention;

[0011] Figure 3 This is a circuit connection diagram of a first-order exponential incremental error feedback noise shaping SAR quantizer provided by the present invention;

[0012] Figure 4 1 is a schematic diagram of a clock signal of a first-order exponential incremental error feedback noise shaping SAR quantizer provided by an embodiment of the present invention;

[0013] Figure 5 1 is a circuit connection diagram of a DAC submodule provided in an embodiment of the present invention;

[0014] Figure 6 It is a schematic diagram of the system structure of the digital extraction filter module provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0015] The present invention will be further described in detail below with reference to specific examples, but the embodiments of the present invention are not limited thereto.

[0016] In the description of the present invention, the terms "first" and "second" are used for descriptive purposes only and should not be understood to indicate or imply relative importance or implicitly specify the number of the technical features indicated. Therefore, a feature specified as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of the present invention, "plurality" means two or more, unless otherwise specifically defined.

[0017] In the description of this specification, the reference terms "one embodiment", "some embodiments", "example", "specific example", or "some examples" mean that the specific features, structures, materials, or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials, or characteristics described can be combined in any appropriate manner in any one or more embodiments or examples. In addition, those skilled in the art can combine and combine different embodiments or examples described in this specification.

[0018] Although the present invention is described herein in conjunction with various embodiments, in the process of implementing the claimed invention, those skilled in the art can understand and implement other variations of the disclosed embodiments by reviewing the drawings, the disclosure, and the appended claims. In the claims, the word "comprising" does not exclude other components or steps, and "a" or "an" does not exclude multiple situations. A single processor or other unit can implement several functions listed in the claims. Certain measures are recorded in different dependent claims, but this does not mean that these measures cannot be combined to produce good results.

[0019] The full-dynamic exponential incremental low-latency high-precision analog-to-digital converter provided by the present invention will now be described in detail with reference to the accompanying drawings.

[0020] Figure 1 This is a structural diagram of the full dynamic exponential incremental low-delay high-precision analog-to-digital converter provided by the present invention. Figure 1 As shown, it includes: a loop integrator 101, a first-order exponential incremental error feedback noise shaping SAR quantizer 102, a digital-to-analog conversion module 103 and a digital decimation filter module 104; the loop integrator 101 is used to receive the i-th round input signal, and sequentially add the i-th round input signal and the feedback signal after the i-1th round calibration, and perform integration processing to obtain the i-th round integrated signal, which includes the i-th round first differential signal V DSM_N and the second differential signal V of the i-th round DSM_P ; i is a positive integer greater than or equal to 1; a first-order exponential incremental error feedback noise shaping SAR quantizer 102 is used to add the i-th round integrated signal and twice the i-1-th round residual signal to obtain the i-th round added signal, and perform multi-bit quantization on the i-th round added signal to obtain the i-th round quantized signal; the i-1-th round residual signal is generated internally by the first-order exponential incremental error feedback noise shaping SAR quantizer 102 in the i-1-th round; a digital-to-analog conversion module 103 is used to perform format conversion, mismatch calibration, and digital-to-analog conversion on the i-1-th round quantized signal in sequence during the process of processing the i-th round input signal to obtain the i-1-th round calibrated feedback signal; a digital decimation filter module 104 is used to perform digital filtering and downsampling on the i-th round quantized signal to obtain an output signal of the i-th round Nyquist rate.

[0021] Figure 2 This is a schematic diagram of the system structure of the full dynamic exponential incremental low-delay high-precision analog-to-digital converter provided by the present invention. Figure 2 The numbers between the modules refer to the number of coding bits. Figure 2As shown, the loop integrator 101 includes: a first multiplier, a second multiplier, a first adder and a first integrator; wherein the gain of the first multiplier is c1, the gain of the second multiplier is -f1, and the control end of the first integrator is connected to a periodic reset signal; the input end of the first multiplier is connected to the i-th round input signal, and the output end is connected to the first input end of the first adder; the input end of the second multiplier is connected to the output end of the digital-to-analog conversion module 103 to receive the feedback signal after the (i-1)-th round calibration, and the output end is connected to the second input end of the first adder; the output end of the first adder is connected to the input end of the first integrator, and the output end of the first integrator is connected to the input end of the first-order exponential incremental error feedback noise shaping SAR quantizer 102.

[0022] Here, the first integrator is a discrete-time switched capacitor integrator that uses a dynamic floating inverter amplifier based on an inverter. This operational amplifier is only activated during the integration phase and is in a reset state at other times, eliminating static current to reduce power consumption and meet the requirements of the low-power field. The transfer function of the first integrator is: Assume that the input signal of round i is X i , the feedback signal after the i-1th round of calibration is Y i-1 The signal actually received by the first integrator is expressed as (c1*X i -f1*Y i-1 ).

[0023] Figure 3 This is a circuit connection diagram of the first-order exponential incremental error feedback noise shaping SAR quantizer provided by the present invention. Figure 3 As shown, the first-order exponential incremental error feedback noise shaping SAR quantizer 102 includes: an asynchronous clock submodule, a first SAR logic submodule, a second SAR logic submodule, a comparator, a buffer, a P-terminal DAC P Submodule, N-end DAC N Submodule, residual signal storage capacitor C P_o , residual signal storage capacitor C P_e , residual signal storage capacitor C N_o , residual signal storage capacitor C N_e and switch tubes K1-K18; wherein, the first output end of the asynchronous clock submodule is connected to the control end of the first SAR logic submodule, the second output end is connected to the control end of the comparator, and the third output end is connected to the control end of the second SAR logic submodule; the asynchronous clock submodule is used to provide an asynchronous clock signal CLKc to the first SAR logic submodule, the comparator, and the second SAR logic submodule respectively; the output end of the first SAR logic submodule is connected to the P-terminal DAC P The control end of the submodule is connected; the P end DAC PThe first, fourth and seventh input terminals of the submodule are all connected to the output terminal of the loop integrator 101 to receive the first differential signal V DSM_N The second, fifth and eighth input terminals are connected to the i-1th round feedback signal V REFP The third, sixth and ninth input terminals are connected to the i-1th round feedback signal V REFN , P-side DAC P The first to third output terminals of the submodule are connected to one terminal of the switch tube K1 and one terminal of the switch tube K2 respectively; the other terminal of the switch tube K1 is connected to the voltage V CM The other end of the switch tube K2 is connected to one end of the switch tube K3, and the other end of the switch tube K3 is connected to the residual signal storage capacitor C P_o One end of the residual signal storage capacitor C P_o The other end of the switch tube K5 and the other end of the switch tube K6 are connected to the voltage V CM The other end of the switch tube K4 is connected to the positive electrode of the comparator; the output end of the second SAR logic submodule is connected to the N-end DAC N Control terminal connection of submodule; N-terminal DAC N The first, fourth and seventh input terminals of the submodule are all connected to the output terminal of the loop integrator 101 to receive the second differential signal V DSM_P The second, fifth and eighth input terminals are connected to the i-1th round feedback signal V REFP The third, sixth and ninth input terminals are connected to the i-1th round feedback signal V REFN , N-terminal DAC N The first to third output terminals of the submodule are connected to one terminal of the switch tube K10 and one terminal of the switch tube K11 respectively; the other terminal of the switch tube K10 is connected to the voltage V CM The other end of the switch tube K11 is connected to one end of the switch tube K12, and the other end of the switch tube K12 is connected to the residual signal storage capacitor C N_e One end of the residual signal storage capacitor C N_e The other end of the switch tube K14 and the other end of the switch tube K15 are connected to the voltage V CMThe other end of the switch tube K13 is connected to the negative electrode of the comparator; the positive electrode of the comparator is also connected to one end of the switch tube K7, and the other end of the switch tube K7 is connected to the first positive electrode of the buffer; the negative electrode of the comparator is also connected to one end of the switch tube K16, and the other end of the switch tube K16 is connected to the first negative electrode of the buffer; the output end of the comparator is respectively connected to the digital-to-analog conversion module 103, the input end of the asynchronous clock and the input end of the digital extraction filter module 104; the second positive electrode of the buffer is respectively connected to one end of the switch tube K8 and one end of the switch tube K17, and the second negative electrode of the buffer is respectively connected to one end of the switch tube K9 and one end of the switch tube K18. A residual signal storage capacitor C is connected between the switch tubes K8 and K9. P_e A residual signal storage capacitor C is connected between the switch tube K17 and the switch tube K18. N_o .

[0024] The control signals connected to each switch tube may be different, and the functions they play are also different. Specifically, the control terminals of the switch tubes K5, K6, K14, and K15 are all connected to the periodic reset signal to periodically clear the residual signal storage capacitor C. P_o 、C P_e 、C N_o and C N_e The residual signal stored in the ; the control terminals of the switch tubes K1 and K10 are connected to the clock signal CLKs, and the control terminals of the switch tubes K2 and K11 are connected to the clock signal CLK S_B ; Clock signal CLKs and clock signal CLK S_B It is used to control the first-order exponential incremental error feedback noise shaping SAR quantizer 102 to collect the i-th round integration signal; the control terminals of the switch tube K3 and the switch tube K4 are both connected to the ping-pong timing signal CLK o The control terminals of the switch tubes K12 and K13 are both connected to the ping-pong timing signal CLK e The control terminals of the switch tubes K8 and K9 are both connected to the ping-pong timing signal CLK E_e The control terminals of the switch tubes K8 and K9 are both connected to the ping-pong timing signal CLK N_e , Ping-pong timing signal CLK o , CLK e , CLK E_e and CLK N_e Used to control the corresponding switch tube to enable the residual storage capacitor, complete the storage of the residual signal and the accumulation operation with the output signal of the loop integrator 101; the control terminals of the switch tube K7 and the switch tube K6 are both connected to the clock signal CLK BUF , clock signal CLK BUF Used to control the buffer to complete the transmission of the residual signal.

[0025] Here, the switch tube K3, the switch tube K4 and the residual signal storage capacitor C P_o The first P-end residual signal storage submodule is composed of the switch tube K8, the switch tube K9 and the residual signal storage capacitor C P_e The second P-end residual signal storage submodule is used to store the residual signal at the P-end DAC. P The submodule receives the first differential signal V of round i DSM_N When the residual signal storage submodule of the first P terminal provides the i-1th round residual signal, and stores the i-th round residual signal; the switch tube K12, the switch tube K13 and the residual signal storage capacitor C N_e The first N-terminal residual signal storage submodule is composed of the switch tube K17, the switch tube K18 and the residual signal storage capacitor C N_o The second N-end residual signal storage submodule is used to store the residual signal at the N-end DAC. N The submodule receives the first differential signal V of round i DSM_P When the residual signal of the first N-end residual signal storage submodule is provided, the residual signal of the i-1th round is stored.

[0026] Here, the first SAR logic submodule, P-end DAC P The submodule, the first P-end residual signal storage submodule and the second P-end residual signal storage submodule constitute the P-end circuit, the second SAR logic submodule, the N-end DAC N The submodule, the first N-end residual signal storage submodule and the second N-end residual signal storage submodule constitute an N-end circuit.

[0027] It should be noted that when processing the i+1th round input signal, the second P-end residual signal storage submodule is used to store the residual signal at the P-end DAC. P The submodule receives the first differential signal V of round i+1 DSM_N When the first P-end residual signal storage submodule provides the i-th round residual signal, and stores the i+1-th round residual signal; and the second N-end residual signal storage submodule is used to store the i-th round residual signal at the N-end DAC N The submodule receives the first differential signal V of round i+1 DSM_P When the residual signal of the i-th round is provided to the first N-end residual signal storage submodule, the residual signal of the i+1-th round is stored.

[0028] It should be noted that the SAR logic submodule is an existing SAR logic circuit, which will not be described here for the sake of brevity.

[0029] Here, the buffer is a dynamic unity gain buffer based on an inverter. It works only when charging the residual storage capacitor and is reset at other times to reduce power consumption. Its gain depends only on the size ratio of the input tube to the load tube. It has a simple structure and saves hardware overhead. The comparator compares the voltage signals of the two input terminals P and N. C Multi-bit quantization is completed under the control of , converting the analog signal (the input signal of the i-th round) into a 5-bit binary digital code.

[0030] Please continue to refer to Figure 3 , P-side DAC P The submodule includes a P-side switch selection circuit SWITCH P and PC PDAC_SAR Capacitor array, where the P-side switch selection circuit SWITCH P Includes multiple single-pole triple-throw switches; P end C PDAC_SAR The capacitor array includes multiple capacitors; wherein the P-terminal switch selection circuit SWITCH P Multiple single-pole triple-throw switches in parallel, P-end switch selection circuit SWITCH P A single-pole triple-throw switch in the P terminal C PDAC_SAR A capacitor of the capacitor array is connected, and the three throw contacts of each single-pole triple-throw switch are respectively connected to the first differential signal V DSM_N , the i-1th round feedback signal V REFN and the i-1th round feedback signal V REFP , PC end C PDAC_SAR Each capacitor in the capacitor array is connected to one end of the switch tube K1; the N-terminal DAC N The submodule includes the N-terminal switch selection circuit SWITCH N and N-terminal C NDAC_SAR Capacitor array, where the N-terminal switch selection circuit SWITCH N Includes multiple single-pole triple-throw switches; N-terminal C NDAC_SAR The capacitor array includes multiple capacitors; wherein the N-terminal switch selection circuit SWITCH N Multiple single-pole triple-throw switches in parallel, N-end switch selection circuit SWITCH N A single-pole triple-throw switch in the N terminal C NDAC_SAR A capacitor of the capacitor array is connected, and the three throw contacts of each single-pole triple-throw switch are respectively connected to the first differential signal V DSM_P , the i-1th round feedback signal V REFN and the i-1th round feedback signal V REFP , N-terminal C NDAC_SAR Each capacitor of the capacitor array is connected to one end of the switch tube K10.

[0031] It should be noted that, here, the i-1th round feedback signal V REFP It refers to the final result of the P terminal obtained by internal calculation of the first-order exponential incremental error feedback noise shaping SAR quantizer in the i-1th round; the i-1th round feedback signal V REFN This refers to the final N-terminal result calculated internally by the first-order exponential incremental error feedback noise shaping SAR quantizer in the i-1th round. Module 102 outputs the 5-bit binary code after the i-th round of quantization.

[0032] Now combined Figure 4 The specific working process of module 102 is described. Figure 4 Schematic diagram of the clock signal of the first-order exponential incremental error feedback noise shaping SAR quantizer provided by the embodiment of the present invention. Figure 4 As shown, the P-end circuit is in the ping-pong timing signal CLK o / CLK E_o The N-terminal circuit works under the control of the ping-pong timing signal CLK e / CLK E_e Work under control, ping-pong timing signal CLK o / CLK E_o and ping-pong timing signal CLK e / CLK E_e They are executed alternately, not pulled high or low at the same time.

[0033] Specifically, in a conversion cycle, the periodic reset signal RST is first pulled high, the switch tubes K5, K6, K14, and K15 controlled by RST are closed, and the residual signal storage capacitor C P_o 、C P_e 、C N_o with C N_e The two plates of each are connected to V CM , the residual signal information stored in the residual signal storage capacitor is cleared to complete the reset operation; then, the periodic reset signal RST is pulled low, and the clock signal CLK S Pulled high by CLK S The switch tubes K1 and K10 controlled by the controller are closed. Under the control of the asynchronous clock submodule, the P terminal C PDAC_SAR The upper side of the capacitor array is connected to the P-side switch selection circuit SWITCH P Connect to the negative output of the first integrator V DSM_N , the lower side is connected to V through the first switch K1 CM ; Similarly, the N-terminal C NDAC_SAR The lower side of the capacitor array is connected to the N-terminal switch selection circuit SWITCH N Connect to the positive output of the first integrator V DSM_P, complete the sampling operation of the first integrator output; then, the clock signal CLK S_B Pull high, clock signal CLK S Pull low, the sampling process ends. For the P-end circuit, the ping-pong timing signal CLK o Under control, the switch tubes K3 and K4 are closed, and the P terminal C PDAC_SAR Capacitor array and residual signal storage capacitor C P_o series, stacked at the comparator input, C PDAC_SAR The output signal of the first integrator and the residual signal stored on the capacitor array are stored in the capacitor C P_o The double residual signal of the previous cycle stored in the capacitor is added through the capacitor stacking technology, and the added result appears at the positive input terminal of the comparator.

[0034] Similarly, for the N-terminal circuit, the ping-pong timing signal CLK e Under control, the switch tubes K12 and K13 are closed, and the N terminal C NDAC_SAR Capacitor array and residual signal storage capacitor C N_e Series, stacked at the input of the comparator, N end C NDAC_SAR The output signal of the first integrator and the residual signal stored on the capacitor array are stored in the capacitor C N_e The double residual signal of the previous cycle stored in the capacitor stacking technology is added, and the result of the addition appears at the negative input of the comparator; after the addition operation is completed, the comparator is under the control of the asynchronous clock signal CLKc, and the CLK C When falling, the positive and negative input signals are compared; the output digital signal obtained by comparison enables the switch selection circuit SWITCH under the control of the SAR logic module P 、SWITCH N With the corresponding V REFP or V REFN Then, the clock signal CLK BUF Pull high, the switch tubes K7 and K16 are closed, and the quantized residual signals at the P and N ends are transmitted to the positive input and negative input ends of the buffer respectively.

[0035] To understand the output of module 102, Figure 3 The circuit connection of the first-order exponential incremental error feedback noise shaping SAR quantizer can be simplified as follows: Figure 2 The connection of the 102 modules in the Figure 2 The 102 module is only used to illustrate the input of the i-th round integral signal. Figure 3 The processing done in Figure 2As shown, the first-order exponential incremental error feedback noise shaping SAR quantizer can be simplified as follows: a second adder, a third adder, a fourth adder, and a first delay module; wherein the second adder receives the i-th round integrated signal and adds it to the processed residual signal of twice the i-1-th round, and the result of the addition is again added to the quantization noise Q to obtain the i-th round quantized signal, wherein the i-1-th round residual signal is added to the result output by the second adder of the i-2-th round in the i-1-th round through the fourth adder to obtain the signal V RES , then the transfer function is H(z)=2z -1 The residual signal of the first delay module is obtained by processing the doubled residual signal of the i-1th round. Figure 2 Indicated as 2V RES .

[0036] Here, the residual signal is quantized twice by the previous cycle, 2V RES Added to the i-th round integrated signal, an additional first-order exponential noise shaping of the quantization noise is implemented in the 102 module, so as to achieve a second-order linear exponential cascade noise shaping effect together with the first integrator.

[0037] Here, the Z-domain transfer function of the quantization noise Q is D OUT (z)=V IN (z)z -1 +Q(z)(1-z -1 )(1-2z -1 ).

[0038] The first-order exponential incremental error feedback noise shaping SAR quantizer uses dynamic buffer and capacitor stacking technology to double the storage of the residual signal generated by each quantization. In the next cycle, the doubled residual signal is added to the output signal from the first integrator and then quantized. This method does not increase the additional hardware overhead and only uses the first-order noise shaping circuit structure to achieve better quantization noise suppression effect than the traditional third-order linear structure, greatly improving the effective number of bits of the analog-to-digital converter.

[0039] Please continue to refer to Figure 2The digital-to-analog conversion module 103 includes: a binary-to-thermometer code converter submodule (B to TH decoder), a DWA submodule, and a DAC submodule, which are connected in sequence. The input end of the binary-to-thermometer code converter submodule is connected to the output end of the first-order exponential incremental error feedback noise shaping SAR quantizer 102, and the output end of the DAC submodule is connected to the input end of the loop integrator 101 and the second multiplier. The binary-to-thermometer code converter submodule is used to convert the coding type of the i-1th round quantization signal from binary coding to thermometer coding during the processing of the i-th round input signal to obtain the i-1th round coded signal; the DWA submodule is used to perform weighted averaging processing on the i-1th round coded signal to obtain the i-1th round calibration signal; and the DAC submodule is used to perform digital-to-analog conversion on the i-1th round calibration signal to obtain the i-1th round analog signal, so that the i-1th round analog signal is used as the feedback signal after the i-1th round calibration and input into the loop integrator 101 for processing.

[0040] It should be noted that mismatches in capacitor components due to systematic errors during the manufacturing process can reduce the signal-to-noise ratio (SNR) of the analog-to-digital converter (ADC), necessitating calibration. The DWA submodule provided in this embodiment of the present invention uses a round-robin approach to average the input thermometer code. The weighted averaged thermometer code output is then transmitted to the DAC submodule provided in this embodiment of the present invention.

[0041] Figure 5 4 is a structural diagram of a DAC submodule provided in an embodiment of the present invention. Figure 5 (a) is the circuit connection diagram of the DAC submodule. Figure 5 (b) is a schematic diagram of the phase signal Φ1 and the phase signal Φ2, Figure 5 As shown, the DAC submodule includes: a plurality of parallel switched capacitor units; wherein the i-th weighted unit includes: a switch tube D j , switch tube DB j , switch tube Ф1, switch tube Ф2 and feedback capacitor C REF_j ; Among them, the switch tube D j One end is connected to the i-1th round feedback signal V REFP , switch tube DB j One end is connected to the i-1th round feedback signal V REFN , switch tube D j The other end and the switch tube DB j The other end of each is connected to one end of the switch tube Ф2, and the other end of the switch tube Ф2 is connected to one end of the switch tube Ф1 and the feedback capacitor C REF_j One end of the feedback capacitor C REF_jThe other end is connected to an input end of the DAC submodule; j is a positive integer; wherein the control end of the switch tube Ф1 is connected to the phase signal Ф1, and the control end of the switch tube Ф2 is connected to the phase signal Ф2, and the phase signal Ф1 and the phase signal Ф2 appear alternately.

[0042] For example, the value of j is 31. Each module is controlled by the weighted average thermometer code generated by the DWA submodule. When the phase signal φ1 is high, the feedback capacitor in the DAC submodule is connected to V CM , in the reset state; when the phase signal Ф2 is high, in each submodule, the thermometer code D i and its inverse D Bi Control feedback capacitor C REF_i Connect V REFP or V REFN .

[0043] In one possible implementation, the Z-domain transfer function of the signal received by the first integrator in each round of loop integrator 101 can be expressed as: IN (z)-D OUT (z) = -Q(z)(1-z -1 )(1-2z -1 ). That is, the loop filter composed of the first integrator only processes the quantization noise after being shaped.

[0044] Figure 6 Schematic diagram of the system structure of the digital decimation filter module provided by the embodiment of the present invention. Figure 6 As shown, the digital decimation filter module 104 includes: a binary-to-decimal conversion module, a linear exponential cascade integrator, and a downsampler connected in sequence; wherein the input end of the binary-to-decimal conversion module is connected to the output end of the first-order exponential incremental error feedback noise shaping SAR quantizer 102, and the output end of the downsampler is used to output the output signal of the i-th round Nyquist rate; the binary-to-decimal conversion module is used to convert the coding type of the i-th round quantization signal from binary to decimal to obtain the i-th round decimal signal; the linear exponential cascade integrator is used to integrate the i-th round decimal signal to obtain the i-th round filtered signal; and the downsampler is used to downsample the i-th round filtered signal to obtain the i-th round Nyquist rate output signal. The linear exponential cascade integrator includes a second integrator and a third integrator. The input of the second integrator is connected to the input of the binary-to-decimal conversion module, and the output of the second integrator is connected to the input of the third integrator. The output of the third integrator is connected to the input of the downsampler. The control terminals of the second and third integrators are both connected to a periodic reset signal. Here, the second integrator is a linear integrator, and the third integrator is an exponential integrator.

[0045] Specifically, the digital decimation filter module adopts a CoI (Cascade-of-Integrator) filter with lower delay and simpler structure, in which the linear exponential cascade integrator is formed by cascading delay-free discrete-time integrators. The transfer function of the integrator corresponds to the transfer function of the quantization noise of the analog-to-digital converter. In the embodiment of the present invention, the transfer functions of the two integrators (noise shaping networks) are (1-z -1 ) -1 and (1-2z -1 ) -1 The first-order exponential incremental error feedback noise shaping SAR quantizer 102 outputs a 5-bit binary code, which is converted to decimal by the binary-to-decimal conversion module, passed through a linear exponential cascade integrator, and then sampled by a downsampler to obtain a digital code output at the Nyquist rate.

[0046] The full dynamic exponential incremental low-latency high-precision analog-to-digital converter provided by the embodiment of the present invention has a delay from analog input to digital output of only one Nyquist conversion period T N , and its digital extraction filter is composed only of cascaded integrators, with a simpler structure and no settling time. Compared with the traditional Sigma-Delta analog-to-digital converter, it is more suitable for sensor interface circuits that require time-sharing multiplexing.

[0047] It should be noted that the periodic reset signals of the access loop integrator 101, the first-order exponential incremental error feedback noise shaping SAR quantizer 102, the digital-to-analog conversion module 103 and the digital extraction filter module 104 are synchronized. Since the full-dynamic exponential incremental low-latency high-precision analog-to-digital converter provided by the embodiment of the present invention will process twice the residual information each time quantization, it is easy to cause the quantizer to saturate. The periodic reset operation ensures that the quantizer will not be overloaded, thereby maintaining the stability of the loop.

[0048] In summary, the fully dynamic exponential incremental low-latency, high-precision analog-to-digital converter of this embodiment effectively improves the analog-to-digital converter's ability to suppress quantization noise by embedding a first-order exponential incremental error feedback noise-shaping SAR quantizer. Its exponential operating mode accelerates residual accumulation, achieving a higher effective number of bits with a shorter conversion cycle without adding additional hardware overhead. The first-order exponential incremental error feedback noise-shaping SAR quantizer uses a dynamic buffer and capacitor stacking technology to double the accumulation of residual signals. The internal buffer uses a dynamic unity-gain buffer based on an inverter, and the loop integrator uses a switched-capacitor integrator based on a dynamic floating inverter amplifier. Both are enabled during operation and reset in the non-operating state to eliminate static current and meet low power consumption requirements. Furthermore, a periodic global reset operation is provided to clear the signal information stored in the integrator, quantizer, and filter, allowing operation to begin from a fresh system state. This ensures that the exponential operating mode does not cause system saturation. Furthermore, the digital decimation filter structure is simpler and has lower latency, making the analog-to-digital converter provided by the present invention more suitable for sensor interface circuits requiring time-division multiplexing.

[0049] The above is a further detailed description of the present invention in conjunction with specific preferred embodiments, and the specific implementation of the present invention should not be considered to be limited to these descriptions. For those skilled in the art of the present invention, without departing from the concept of the present invention, several simple deductions or substitutions can be made, which should be considered to fall within the scope of protection of the present invention.

Claims

1. A full-dynamic exponential incremental low-latency high-precision analog-to-digital converter, characterized in that: include: A loop integrator (101), a first-order exponential incremental error feedback noise shaping SAR quantizer (102), a digital-to-analog conversion module (103) and a digital decimation filter module (104); The loop integrator (101) is used to receive the i-th round input signal, and sequentially perform addition processing on the i-th round input signal and the feedback signal after calibration of the i-1th round, and perform integration processing to obtain the i-th round integrated signal, wherein the i-th round integrated signal includes the i-th round first differential signal V DSM_N and the second differential signal V of the i-th round DSM_P ; i is a positive integer greater than or equal to 1; The first-order exponential incremental error feedback noise shaping SAR quantizer (102) is used to perform addition processing on the i-th round integrated signal and twice the i-1-th round residual signal to obtain an i-th round added signal, and perform multi-bit quantization on the i-th round added signal to obtain an i-th round quantized signal; the i-1-th round residual signal is generated internally by the first-order exponential incremental error feedback noise shaping SAR quantizer (102) in the i-1-th round; The digital-to-analog conversion module (103) is used to sequentially perform format conversion, mismatch calibration, and digital-to-analog conversion on the (i-1)th round quantization signal during the process of processing the (i-1)th round input signal, to obtain the (i-1)th round calibrated feedback signal; The digital decimation filter module (104) is used to perform digital filtering on the i-th round quantization signal to obtain an output signal of the i-th round Nyquist rate.

2. The full dynamic exponential incremental low-latency high-precision analog-to-digital converter according to claim 1, characterized in that: The loop integrator (101) comprises: a first multiplier, a second multiplier, a first adder and a first integrator; wherein the gain of the first multiplier is c1, the gain of the second multiplier is -f1, and the control terminal of the first integrator is connected to a periodic reset signal; The input end of the first multiplier is connected to the i-th round input signal, and the output end is connected to the first input end of the first adder; the input end of the second multiplier is connected to the output end of the digital-to-analog conversion module (103) to receive the feedback signal after the i-1-th round calibration, and the output end is connected to the second input end of the first adder; the output end of the first adder is connected to the input end of the first integrator, and the output end of the first integrator is connected to the input end of the first-order exponential incremental error feedback noise shaping SAR quantizer (102).

3. The full dynamic exponential incremental low-latency high-precision analog-to-digital converter according to claim 2, characterized in that: The first-order exponential incremental error feedback noise shaping SAR quantizer (102) comprises: an asynchronous clock submodule, a first SAR logic submodule, a second SAR logic submodule, a comparator, a buffer, a P-terminal DAC P Submodule, N-end DAC N Submodule, residual signal storage capacitor C P_o , residual signal storage capacitor C P_e , residual signal storage capacitor C N_o , residual signal storage capacitor C N_e and switch tubes K1-K18; The first output terminal of the asynchronous clock submodule is connected to the control terminal of the first SAR logic submodule, the second output terminal is connected to the control terminal of the comparator, and the third output terminal is connected to the control terminal of the second SAR logic submodule; the asynchronous clock submodule is used to provide an asynchronous clock signal CLKc to the first SAR logic submodule, the comparator, and the second SAR logic submodule respectively; The output end of the first SAR logic submodule is connected to the P-end DAC P The control end of the submodule is connected; the P end DAC P The first, fourth and seventh input terminals of the submodule are all connected to the output terminal of the loop integrator (101) to receive the first differential signal V DSM_N The second, fifth and eighth input terminals are connected to the i-1th round feedback signal V REFP The third, sixth and ninth input terminals are connected to the i-1th round feedback signal V REFN , the P-terminal DAC P The first to third output terminals of the submodule are connected to one terminal of the switch tube K1 and one terminal of the switch tube K2 respectively; the other terminal of the switch tube K1 is connected to the voltage V cm The other end of the switch tube K2 is connected to one end of the switch tube K3, and the other end of the switch tube K3 is connected to the residual signal storage capacitor C P_o and one end of the switch tube K5, the residual signal storage capacitor C P_o The other end of the switch tube K5 and the other end of the switch tube K6 are connected to the voltage V CM , the other end of the switch tube K4 is connected to the positive electrode of the comparator; The output end of the second SAR logic submodule is connected to the N-end DAC N The control end of the submodule is connected; the N-end DAC N The first, fourth and seventh input terminals of the submodule are all connected to the output terminal of the loop integrator (101) to receive the second differential signal V DSM_P The second, fifth and eighth input terminals are connected to the i-1th round feedback signal V REFP The third, sixth and ninth input terminals are connected to the i-1th round feedback signal V REFN , the N-terminal DAC N The first to third output terminals of the submodule are connected to one terminal of the switch tube K10 and one terminal of the switch tube K11 respectively; the other terminal of the switch tube K10 is connected to the voltage V CM The other end of the switch tube K11 is connected to one end of the switch tube K12, and the other end of the switch tube K12 is connected to the residual signal storage capacitor C N_e and one end of the switch tube K14, the residual signal storage capacitor C N_e The other end of the switch tube K14 and the other end of the switch tube K15 are connected to the voltage V CM , the other end of the switch tube K13 is connected to the negative electrode of the comparator; The positive electrode of the comparator is also connected to one end of the switch tube K7, and the other end of the switch tube K7 is connected to the first positive electrode of the buffer; the negative electrode of the comparator is also connected to one end of the switch tube K16, and the other end of the switch tube K16 is connected to the first negative electrode of the buffer; the output end of the comparator is respectively connected to the digital-to-analog conversion module (103), the input end of the asynchronous clock, and the input end of the digital extraction filter module (104); The second positive electrode of the buffer is connected to one end of the switch tube K8 and one end of the switch tube K17 respectively, and the second negative electrode of the buffer is connected to one end of the switch tube K9 and one end of the switch tube K18 respectively. The residual signal storage capacitor C is connected between the switch tube K8 and the switch tube K9. P_e The residual signal storage capacitor C is connected between the switch tube K17 and the switch tube K18. N_o .

4. The full dynamic exponential incremental low-latency high-precision analog-to-digital converter according to claim 3, characterized in that: The control terminals of the switch tubes K5, K6, K14 and K15 are all connected to a periodic reset signal to periodically clear the residual signal storage capacitor C. P_o 、C P_e 、C N_o and C N_e The residual signal stored in ; The control terminals of the switch tubes K1 and K10 are both connected to the clock signal CLKs, and the control terminals of the switch tubes K2 and K11 are both connected to the clock signal CLK S_B ; The clock signal CLKs and the clock signal CLK S_B used for controlling the first-order exponential incremental error feedback noise shaping SAR quantizer (102) to collect the i-th round integrated signal; The control terminals of the switch tubes K3 and K4 are both connected to the ping-pong timing signal CLK o The control terminals of the switch tube K12 and the switch tube K13 are both connected to the ping-pong timing signal CLK e The control terminals of the switch tube K8 and the switch tube K9 are both connected to the ping-pong timing signal CLK E_e The control terminals of the switch tube K8 and the switch tube K9 are both connected to the ping-pong timing signal CLK N_e , the ping-pong timing signal CLK o , CLK e , CLK E_e and CLK N_e Used to control the corresponding switch tubes to alternately complete the storage of the residual signal and the accumulation operation with the output signal of the loop integrator (101); The control terminals of the switch tubes K7 and K6 are both connected to the clock signal CLK BUF , the clock signal CLK BUF Used to control the buffer to complete the transmission of the residual signal.

5. The full dynamic exponential incremental low-latency high-precision analog-to-digital converter according to claim 3, characterized in that: The switch tube K3, the switch tube K4 and the residual signal storage capacitor C P_o The first P-end residual signal storage submodule is formed, wherein the switch tube K8, the switch tube K9 and the residual signal storage capacitor C P_e The second P-end residual signal storage submodule is formed; wherein the second P-end residual signal storage submodule is used to store the residual signal at the P-end DAC. P The submodule receives the first differential signal V of the i-th round DSM_N , providing the i-1th round residual signal to the first P-end residual signal storage submodule, and storing the i-th round residual signal; The switch tube K12, the switch tube K13 and the residual signal storage capacitor C N_e The first N-terminal residual signal storage submodule is formed, wherein the switch tube K17, the switch tube K18 and the residual signal storage capacitor C N_o The second N-terminal residual signal storage submodule is formed; wherein the second N-terminal residual signal storage submodule is used to store the residual signal at the N-terminal DAC. N The submodule receives the first differential signal V of the i-th round DSM_P When the residual signal of the first N-end residual signal storage submodule is provided, the residual signal of the i-1th round is provided, and the residual signal of the i-th round is stored.

6. The full dynamic exponential incremental low-latency high-precision analog-to-digital converter according to claim 3, characterized in that: The P-terminal DAC P The submodule includes a P-side switch selection circuit SWITCH P and PC PDAC_SAR Capacitor array, wherein the P-terminal switch selection circuit SWITCH P Includes multiple single-pole triple-throw switches; the P terminal C PDAC_SAR The capacitor array includes a plurality of capacitors; Wherein, the P-terminal switch selection circuit SWITCH P The multiple single-pole triple-throw switches are connected in parallel, and the P-end switch selection circuit SWITCH P A single-pole triple-throw switch with the P terminal C PDAC_SAR A capacitor of the capacitor array is connected, and the three throw contacts of each single-pole triple-throw switch are respectively connected to the first differential signal V DSM_N , the i-1th round feedback signal V REFN and the i-1th round feedback signal V REFP , the P end C PDAC_SAR Each capacitor of the capacitor array is connected to one end of the switch tube K1; The N-terminal DAC N The submodule includes the N-terminal switch selection circuit SWITCH N and N-terminal C NDAC_SAR Capacitor array, wherein the N-terminal switch selection circuit SWITCH N Includes multiple single-pole triple-throw switches; the N-terminal C NDAC_SAR The capacitor array includes a plurality of capacitors; Wherein, the N-terminal switch selection circuit SWITCH N The multiple single-pole triple-throw switches are connected in parallel, and the N-end switch selection circuit SWITCH N A single-pole triple-throw switch with the N terminal C NDAC_SAR A capacitor of the capacitor array is connected, and the three throw contacts of each single-pole triple-throw switch are respectively connected to the first differential signal V DSM_P , the i-1th round feedback signal V REFN and the i-1th round feedback signal V REFP , the N-terminal C NDAC_SAR Each capacitor of the capacitor array is connected to one end of the switch tube K10.

7. The full-dynamic exponential incremental low-latency high-precision analog-to-digital converter according to claim 3, characterized in that: The digital-to-analog conversion module (103) comprises: a binary-to-thermometer code converter submodule, a DWA submodule, and a DAC submodule connected in sequence; the input end of the binary-to-thermometer code converter submodule is connected to the output end of the first-order exponential incremental error feedback noise shaping SAR quantizer (102), and the output end of the DAC submodule is connected to the input end of the loop integrator (101) and the second multiplier; The binary-thermometer code converter submodule is configured to convert the coding type of the (i-1)th round quantization signal from binary coding to thermometer coding during processing of the (i-1)th round input signal, thereby obtaining the (i-1)th round coded signal; The DWA submodule is configured to perform weighted averaging on the (i-1)th round coded signal to obtain an (i-1)th round calibration signal; The DAC submodule is used to perform digital-to-analog conversion on the i-1th round calibration signal to obtain the i-1th round analog signal, thereby using the i-1th round analog signal as a feedback signal after the i-1th round calibration to be input into the loop integrator (101) for processing.

8. The full dynamic exponential incremental low-latency high-precision analog-to-digital converter according to claim 7, characterized in that: The DAC submodule includes: a plurality of parallel weighted units; wherein the i-th weighted unit includes: a switch tube D j , switch tube DB j , switch tube Ф1, switch tube Ф2 and feedback capacitor C REF_j ; Among them, the switch tube D j One end of the input is connected to the i-1th round feedback signal V REFP , the switch tube DB j One end of the input is connected to the i-1th round feedback signal V REFN , the switch tube D j The other end and the switch tube DB j The other end of each is connected to one end of the switch tube Φ2, and the other end of the switch tube Φ2 is connected to one end of the switch tube Φ1 and the feedback capacitor C REF_j One end of the feedback capacitor C REF_j The other end of is connected to an input end of the DAC submodule; j is a positive integer; The control end of the switch tube Φ1 is connected to the phase signal Φ1, and the control end of the switch tube Φ2 is connected to the phase signal Φ2. The phase signal Φ1 and the phase signal Φ2 appear alternately.

9. The full dynamic exponential incremental low-latency high-precision analog-to-digital converter according to claim 1, characterized in that: The digital decimation filter module (104) comprises: a binary-to-decimal conversion module, a linear exponential cascade integrator and a downsampler connected in sequence; The input end of the binary-to-decimal conversion module is connected to the output end of the first-order exponential incremental error feedback noise shaping SAR quantizer (102), and the output end of the downsampler is used to output an output signal of the i-th round Nyquist rate; The binary-to-decimal conversion module is configured to convert the encoding type of the i-th round quantization signal from binary to decimal to obtain the i-th round decimal signal; The linear exponential cascade integrator is used to perform integration processing on the i-th round decimal signal to obtain the i-th round filtered signal; The downsampler is used to downsample the i-th round filtered signal to obtain the i-th round Nyquist rate output signal.

10. The full dynamic exponential incremental low-latency high-precision analog-to-digital converter according to claim 9, characterized in that: The linear exponential cascade integrator includes a second integrator and a third integrator. The input end of the second integrator is connected to the input end of the binary-to-decimal conversion module, and the output end is connected to the input end of the third integrator. The output end of the third integrator is connected to the input end of the downsampler. The control ends of the second integrator and the third integrator are both connected to the periodic reset signal.

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