Inverted silver mirror light emitting diode chip and preparation method thereof

Abstract

The invention discloses an inverted silver mirror light-emitting diode chip and a preparation method thereof, and relates to the technical field of semiconductors. The inverted silver mirror light-emitting diode chip comprises a substrate, an epitaxial layer, a current expansion layer, a Bragg reflection layer, a metal reflection layer, a first insulating layer, a P-type metal conductive layer and an N-type metal conductive layer, the epitaxial layer comprises an N-type semiconductor layer, an active light-emitting layer and a P-type semiconductor layer; the Bragg reflection layer is provided with a Bragg reflection layer P-type through hole, the first insulating layer is provided with a first insulating layer P-type through hole, and the included angle beta between the hole wall of the first insulating layer P-type through hole and the horizontal plane is smaller than the included angle alpha between the hole wall of the Bragg reflection layer P-type through hole and the horizontal plane; the distance L between the projection edge of the P-type through hole of the first insulating layer and the projection edge of the P-type through hole of the Bragg reflection layer is 5 [mu] m-12 [mu] m. According to the invention, the structure of the flip silver mirror light-emitting diode chip is improved, so that the capability of the flip silver mirror light-emitting diode chip for resisting large current can be improved.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, in particular to a flip-chip silver mirror light-emitting diode chip and a preparation method thereof. Background Art

[0002] In the field of semiconductor lighting technology, flip-chip silver mirror LED chips have attracted considerable attention due to their unique structural design and performance advantages. Their backside emission optimizes the light output path and improves light extraction efficiency. Their excellent heat dissipation effectively reduces chip operating temperature, ensuring stable device operation. Their excellent weldability, high thrust, and high reliability ensure excellent adaptability and stability during assembly and long-term use in various electronic devices, leading to their widespread application in numerous fields.

[0003] However, with the continued development and improvement of LED chip technology, flip-chip silver mirror LED chips are gradually being used in applications with higher power and current requirements, such as automotive and stage lighting. In high-power, high-current operating environments, chips face even more stringent electrical performance tests. Effectively improving the ability of flip-chip silver mirror LED chips to withstand high currents has become a key technical issue that needs to be addressed, and it is also the core challenge in promoting the further expansion of flip-chip silver mirror LED chips in more demanding applications. Summary of the Invention

[0004] The technical problem to be solved by the present invention is to provide a flip-chip silver mirror light-emitting diode chip, which can improve the ability of the flip-chip silver mirror light-emitting diode chip to withstand high current.

[0005] The technical problem to be solved by the present invention is also to provide a method for preparing a flip-chip silver mirror light-emitting diode chip, which is used to prepare the above-mentioned flip-chip silver mirror light-emitting diode chip and improve the ability of the flip-chip silver mirror light-emitting diode chip to withstand high current.

[0006] In order to solve the above technical problems, the present invention provides a flip-chip silver mirror light-emitting diode chip, comprising a substrate, an epitaxial layer, a Bragg reflection layer, a metal reflection layer, a first insulating layer, a P-type metal conductive layer and an N-type metal conductive layer;

[0007] The epitaxial layer includes an N-type semiconductor layer, an active light-emitting layer and a P-type semiconductor layer sequentially stacked on the substrate;

[0008] The Bragg reflective layer is stacked on the P-type semiconductor layer, and the Bragg reflective layer is provided with a Bragg reflective layer P-type through hole; the metal reflective layer covers the surface of the Bragg reflective layer, and the metal reflective layer is electrically connected to the current spreading layer through the Bragg reflective layer P-type through hole;

[0009] The first insulating layer is stacked on the metal reflective layer, and the first insulating layer is provided with a first insulating layer P-type through hole, and one end of the first insulating layer P-type through hole extends to the metal reflective layer;

[0010] The P-type metal conductive layer and the N-type metal conductive layer are spatially separated from each other, the P-type metal conductive layer is stacked on the first insulating layer, and the P-type metal conductive layer is electrically connected to the metal reflective layer through the P-type through-hole of the first insulating layer, and the N-type metal conductive layer is electrically connected to the N-type semiconductor layer;

[0011] The angle β between the hole wall of the P-type through hole in the first insulating layer and the horizontal plane is smaller than the angle α between the hole wall of the P-type through hole in the Bragg reflector layer and the horizontal plane;

[0012] A distance L between a projected edge of the P-type through hole in the first insulating layer and a projected edge of the P-type through hole in the Bragg reflector layer is 5 μm to 12 μm.

[0013] As an improvement of the above technical solution, a distance L between a projected edge of the P-type through hole in the first insulating layer and a projected edge of the P-type through hole in the Bragg reflector layer is 5 μm to 8 μm.

[0014] As an improvement of the above technical solution, the difference between the angle β between the hole wall of the P-type through hole in the first insulating layer and the horizontal plane and the angle α between the hole wall of the P-type through hole in the Bragg reflection layer and the horizontal plane is ≤20°.

[0015] As an improvement of the above technical solution, the angle β between the hole wall of the P-type through hole in the first insulating layer and the horizontal plane is 15° to 20°.

[0016] As an improvement of the above technical solution, the angle α between the hole wall of the P-type through hole in the Bragg reflector layer and the horizontal plane is 25° to 40°.

[0017] As an improvement of the above technical solution, the flip-chip silver mirror light-emitting diode chip further includes a current expansion layer and a current blocking layer;

[0018] The N-type semiconductor layer is stacked on the surface of the substrate, the N-type semiconductor layer includes a first N-type semiconductor portion and a second N-type semiconductor portion connected to each other, the P-type semiconductor layer and the active light-emitting layer are sequentially stacked on the first N-type semiconductor portion, and the current spreading layer covers the surface of the P-type semiconductor layer, so that the current spreading layer and the P-type semiconductor layer are electrically connected;

[0019] The current blocking layer covers the surface of the current spreading layer and the second N-type semiconductor portion, and the Bragg reflection layer covers the surface of the current blocking layer;

[0020] The current blocking layer is provided with a current blocking layer P-type through hole, one end of the current blocking layer P-type through hole is connected to the Bragg reflection layer P-type through hole, and the other end extends to the current spreading layer;

[0021] The metal reflective layer is located above the current spreading layer. A protrusion is provided on a side of the metal reflective layer close to the substrate. The protrusion sequentially fills the P-type through-holes of the Bragg reflective layer and the P-type through-holes of the current blocking layer. An end of the protrusion contacts the current spreading layer, thereby electrically connecting the metal reflective layer and the current spreading layer.

[0022] As an improvement to the above technical solution, the Bragg reflector layer includes a first Bragg reflector portion and a second Bragg reflector portion connected to each other, the first Bragg reflector portion and the second Bragg reflector portion respectively covering the surface of the current blocking layer, and the first Bragg reflector portion is located above the P-type semiconductor layer, and the second Bragg reflector portion is located above the second N-type semiconductor portion; the first Bragg reflector portion is provided with a P-type through-hole of the Bragg reflector layer; the second Bragg reflector portion is provided with an N-type through-hole of the Bragg reflector layer, and one end of the N-type through-hole of the Bragg reflector layer extends to the current blocking layer;

[0023] The first insulating layer includes a first insulating layer portion A and a first insulating layer portion B connected to each other, the first insulating layer portion A is stacked on the metal reflective layer, and the first insulating layer portion B is stacked on the second Bragg reflector; the first insulating layer P-type through hole is located in the first insulating layer portion A, and the first insulating layer portion B is provided with a first insulating layer N-type through hole, and the first insulating layer N-type through hole is located inside the N-type through hole of the Bragg reflector;

[0024] The current blocking layer is further provided with a current blocking layer N-type through hole, one end of the current blocking layer N-type through hole is connected to the first insulating layer N-type through hole, and the other end extends to the second N-type semiconductor portion;

[0025] The P-type metal conductive layer and the N-type metal conductive layer are spatially separated from each other. The P-type metal conductive layer covers the surface of the first insulating layer portion A, and the N-type metal conductive layer covers the surface of the first insulating layer portion B and sequentially fills the first insulating layer N-type through holes and the current blocking layer N-type through holes until they contact the second N-type semiconductor portion.

[0026] As an improvement to the above technical solution, the flip-chip silver mirror light-emitting diode chip further includes a second insulating layer, which covers the surface of the P-type metal conductive layer, the N-type metal conductive layer, and the exposed first insulating layer. The second insulating layer is provided with a second insulating layer P-type through-hole and a second insulating layer N-type through-hole, one end of the second insulating layer P-type through-hole extends to the P-type metal conductive layer, and one end of the second insulating layer N-type through-hole extends to the N-type metal conductive layer.

[0027] Correspondingly, the present invention also provides a method for preparing a flip-chip silver mirror light-emitting diode chip, which is used to prepare the above-mentioned flip-chip silver mirror light-emitting diode chip, comprising the following steps:

[0028] (1) providing a substrate, and sequentially depositing an N-type semiconductor layer, an active light-emitting layer, and a P-type semiconductor layer on the substrate to obtain an epitaxial layer;

[0029] (2) removing the P-type semiconductor layer and the corresponding active light-emitting layer in a designated area to expose a portion of the N-type semiconductor layer, where the exposed N-type semiconductor layer is the second N-type semiconductor portion;

[0030] (3) depositing indium tin oxide on the surface of the P-type semiconductor layer to form a current spreading layer on the surface of the P-type semiconductor layer;

[0031] (4) depositing SiO on the surface of the P-type semiconductor layer, the current spreading layer, and the second N-type semiconductor portion to form a current blocking layer;

[0032] (5) sequentially depositing a stack of TiO and SiO layers on the surface of the current blocking layer to form a Bragg reflection layer;

[0033] (6) opening a Bragg reflector layer P-type through hole and a Bragg reflector layer N-type through hole at a designated position of the Bragg reflector layer;

[0034] (7) opening a current blocking layer P-type through hole and a current blocking layer N-type through hole at a designated position of the current blocking layer;

[0035] (8) growing a metal reflective layer above a designated position of the Bragg reflective layer, wherein the metal reflective layer fills the P-type through-holes of the Bragg reflective layer and the P-type through-holes of the current blocking layer;

[0036] (9) depositing SiO on the metal reflective layer to form a first insulating layer; opening a first insulating layer P-type through hole and a first insulating layer N-type through hole at a designated position of the first insulating layer;

[0037] (10) A P-type metal conductive layer and an N-type metal conductive layer are formed on designated positions of the first insulating layer.

[0038] As an improvement to the above technical solution, in step (6), the method of opening a Bragg reflector layer P-type through hole and a Bragg reflector layer N-type through hole at a designated position of the Bragg reflector layer includes the following steps:

[0039] Coating a third photoresist on the surface of the Bragg reflector layer, removing the third photoresist at a designated position on the Bragg reflector layer, and then removing the exposed Bragg reflector layer to form a P-type through hole and an N-type through hole in the Bragg reflector layer, exposing the current blocking layer below the P-type through hole and the N-type through hole in the Bragg reflector layer, and then removing the third photoresist; the thickness of the third photoresist is 1.5 μm to 2 μm;

[0040] In step (9), the method for forming a first insulating layer P-type through hole and a first insulating layer N-type through hole at a designated position of the first insulating layer includes the following steps: coating a sixth photoresist on the surface of the first insulating layer, removing the sixth photoresist at the designated position to expose a portion of the first insulating layer, then removing the exposed first insulating layer using a second BOE etching solution to form a first insulating layer P-type through hole and a first insulating layer N-type through hole, and removing the sixth photoresist;

[0041] The second BOE etching solution comprises components of hydrofluoric acid, ammonium fluoride and water. The volume ratio of ammonium fluoride to hydrofluoric acid in the second BOE etching solution is 15:1 to 20:1.

[0042] Implementation of the present invention has the following beneficial effects: by controlling the angle β between the hole wall of the P-type through hole in the first insulating layer and the horizontal plane to be smaller than the angle α between the hole wall of the P-type through hole in the Bragg reflector layer and the horizontal plane, and controlling the distance L between the projected edge of the P-type through hole in the first insulating layer on the horizontal plane and the projected edge of the P-type through hole in the Bragg reflector layer on the horizontal plane to be 5 μm to 12 μm, the present invention can significantly improve the ability of the flip-chip silver mirror light-emitting diode chip to withstand high currents, thereby effectively extending the service life of the flip-chip silver mirror light-emitting diode chip under high current working conditions, so that the chip of the present invention can be used in scenes with high power and current requirements, such as car lights and stage lights. BRIEF DESCRIPTION OF THE DRAWINGS

[0043] Figure 1 1 is a schematic structural diagram of a flip-chip silver mirror light-emitting diode chip in Example 1 of the present invention;

[0044] Figure 2 is a partially enlarged schematic diagram of the flip-chip silver mirror light-emitting diode chip of Example 1 of the present invention;

[0045] Figure 3 yes Figure 2 A partial enlarged schematic diagram;

[0046] Wherein: substrate 10, epitaxial layer 11, current spreading layer 12, current blocking layer 13, Bragg reflector 14, metal reflector 15, first insulating layer 16, P-type metal conductive layer 171, N-type metal conductive layer 172, second insulating layer 18, N-type semiconductor layer 111, active light emitting layer 112, P-type semiconductor layer 113, first N-type semiconductor portion 1111, second N-type semiconductor portion 1112, current blocking layer P-type via 131, current blocking layer N-type via 132, protrusion 151, first Bragg reflector 141, second Bragg reflector 142, Bragg reflector P-type via 1411, Bragg reflector N-type via 1421, first insulating layer P-type via 1611, first insulating layer N-type via 1621, second insulating layer P-type via 181, second insulating layer N-type via 182. DETAILED DESCRIPTION

[0047] To make the objectives, technical solutions, and advantages of the present invention more apparent, the present invention will be described in further detail below with reference to the accompanying drawings. The present invention can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided to provide a more thorough and comprehensive understanding of the disclosure of the present invention.

[0048] If no specific techniques or conditions are specified in the examples, the techniques or conditions described in the literature in this field or the product instructions were used. Raw materials used without manufacturer specified are all commercially available conventional products.

[0049] like Figure 1 and Figure 2 As shown, this embodiment discloses a flip-chip silver mirror light-emitting diode chip, including a substrate 10, an epitaxial layer 11, a current spreading layer 12, a Bragg reflection layer 14, a metal reflection layer 15, a first insulating layer 16, a P-type metal conductive layer 171 and an N-type metal conductive layer 172; the epitaxial layer 11 includes an N-type semiconductor layer 111, an active light-emitting layer 112 and a P-type semiconductor layer 113;

[0050] The N-type semiconductor layer 111 is stacked on the surface of the substrate 10. The N-type semiconductor layer 111 includes a first N-type semiconductor portion 1111 and a second N-type semiconductor portion 1112 connected to each other. The P-type semiconductor layer 113 and the active light-emitting layer 112 are stacked on the first N-type semiconductor portion 1111 from top to bottom. The current spreading layer 12 covers the surface of the P-type semiconductor layer 113, so that the current spreading layer 12 and the P-type semiconductor layer 113 are electrically connected.

[0051] The Bragg reflective layer 14 is stacked above the P-type semiconductor layer 113 and the second N-type semiconductor portion 1112 . The Bragg reflective layer 14 is provided with a Bragg reflective layer P-type through hole 1411 that penetrates the Bragg reflective layer 14 from top to bottom.

[0052] The metal reflective layer 15 covers the surface of the Bragg reflective layer 14 and fills the P-type through-hole 1411 of the Bragg reflective layer. The metal reflective layer 15 is electrically connected to the current spreading layer 12. The provision of the Bragg reflective layer 14 on the surface of the metal reflective layer 14 can improve the luminous efficiency of the chip through the synergistic effect of the optical interference principle and material properties, thereby optimizing the optical performance of the chip.

[0053] The first insulating layer 16 is stacked above the metal reflective layer 15 and the second N-type semiconductor portion 1112 . The first insulating layer 16 is provided with a first insulating layer P-type through hole 1611 . One end of the first insulating layer P-type through hole 1611 extends to the metal reflective layer 15 .

[0054] The P-type metal conductive layer 171 and the N-type metal conductive layer 172 are spatially separated from each other. The P-type metal conductive layer 171 is stacked on the first insulating layer 16 and fills the P-type through hole 1611 of the first insulating layer, so that the P-type metal conductive layer 171 and the metal reflective layer 15 are electrically connected. The N-type metal conductive layer 172 is stacked on the first insulating layer 16 and electrically connected to the second N-type semiconductor portion 1112.

[0055] The angle β between the hole wall of the P-type through hole 1611 in the first insulating layer and the horizontal plane is smaller than the angle α between the hole wall of the P-type through hole 1411 in the Bragg reflector layer and the horizontal plane;

[0056] A distance L between a projected edge of the first insulating layer P-type through hole 1611 on a horizontal plane and a projected edge of the Bragg reflector layer P-type through hole 1411 on a horizontal plane is 5 μm to 12 μm. Specifically, the distance L between the projected edge of the first insulating layer P-type through hole 1611 on a horizontal plane and the projected edge of the Bragg reflector layer P-type through hole 1411 on a horizontal plane is illustratively 5 μm, 5.5 μm, 6 μm, 6.5 μm, 7 μm, 7.5 μm, 8 μm, 9 μm, 10 μm, 11 μm, or 12 μm, but is not limited thereto.

[0057] It is worth noting that, by providing a first insulating layer P-type through hole 1611 in the first insulating layer 16, the P-type metal conductive layer 171 is electrically connected to the metal reflective layer 15 located below the first insulating layer 16, and by providing a Bragg reflective layer P-type through hole 1411 in the Bragg reflective layer 14, the metal reflective layer 15 is electrically connected to the P-type semiconductor layer 113 located below the Bragg reflective layer 14. By controlling the angle β between the wall of the first insulating layer P-type through hole 1611 and the horizontal plane to be smaller than the angle α between the wall of the Bragg reflector layer P-type through hole 1411 and the horizontal plane, and controlling the distance L between the projected edge of the first insulating layer P-type through hole 1611 on a plane and the projected edge of the Bragg reflector layer P-type through hole 1411 on a horizontal plane to be 5μm to 12μm, the present invention can significantly improve the high current resistance capability of the flip-chip silver mirror LED chip, thereby effectively extending the service life of the flip-chip silver mirror LED chip under high current conditions, making the chip of the present invention suitable for use in applications with high power and current requirements, such as automotive lights and stage lights. If the angle β between the wall of the first insulating layer P-type through hole 1611 and the horizontal plane is greater than or equal to the angle α between the wall of the Bragg reflector layer P-type through hole 1411 and the horizontal plane, the chip's high current resistance capability will be significantly reduced. If the distance L between the projected edge of the P-type through hole 1611 of the first insulating layer on the horizontal plane and the projected edge of the P-type through hole 141 of the Bragg reflector layer on the horizontal plane is less than 5 μm, the chip's ability to withstand large currents will be greatly reduced; if L is greater than 12 μm, the improvement of the chip's ability to withstand large currents will be limited, and when L is greater than 12 μm, the chip's operating voltage will increase significantly.

[0058] More preferably, the distance L between the projected edge of the P-type through hole 1611 of the first insulating layer on the horizontal plane and the projected edge of the P-type through hole 1411 of the Bragg reflector layer on the horizontal plane is 5μm to 8μm. By further limiting the distance L to 5μm to 8μm, L within this numerical range can effectively improve the ability of the flip-chip silver mirror light-emitting diode chip to withstand high currents, and the greater the distance L within this range, the better the chip's ability to withstand high currents. In addition, when L is 5μm to 8μm, the operating voltage of the chip is relatively low; when L is greater than 8μm and less than or equal to 12μm, the operating voltage of the chip will increase, which is likely to affect other performance of the chip, such as increasing the chip's power consumption and reducing the chip's stability.

[0059] In one embodiment, the difference between the angle β between the wall of the P-type through hole 1611 in the first insulating layer and the horizontal plane and the angle α between the wall of the P-type through hole 1411 in the Bragg reflector layer and the horizontal plane is ≤ 20°. By limiting the difference between the angle β and the angle α to ≤ 20°, the flip-chip silver mirror LED chip can be ensured to have excellent high current resistance. If the difference between the angle β and the angle α is greater than 20°, the chip's high current resistance capability will be significantly reduced.

[0060] Specifically, the difference between the angle β between the hole wall of the first insulating layer P-type through hole 1611 and the horizontal plane and the angle α between the hole wall of the Bragg reflection layer P-type through hole 1411 and the horizontal plane is exemplarily 5°, 8°, 10°, 12°, 15°, 18° or 20°, but is not limited thereto.

[0061] In one embodiment, the angle β between the hole wall of the first insulating layer P-type through hole 1611 and the horizontal plane is 15° to 20°, and the angle α between the hole wall of the Bragg reflector layer P-type through hole 1411 and the horizontal plane is 25° to 40°. By further controlling the angle β to 15° to 20° and the angle α to 25° to 40°, the ability of the flip-chip silver mirror LED chip to withstand high currents can be further improved.

[0062] Specifically, the angle β between the hole wall of the P-type through hole 1611 of the first insulating layer and the horizontal plane is exemplarily 15°, 16°, 17°, 18°, 19° or 20°, and the angle α between the hole wall of the P-type through hole 1411 of the Bragg reflection layer and the horizontal plane is 25°, 26°, 27°, 28°, 29°, 30°, 31°, 32°, 33°, 34°, 35°, 36°, 37°, 38°, 39° or 40°, but is not limited thereto. It is only necessary to control the angle α-angle β≤20°.

[0063] In one embodiment, the flip-chip silver mirror light-emitting diode chip further includes a current blocking layer 13, the current blocking layer 13 covers the surface of the current spreading layer 12 and the second N-type semiconductor portion 1112, and the Bragg reflection layer 14 covers the surface of the current blocking layer 13;

[0064] The current blocking layer 13 is provided with a current blocking layer P-type through hole 131, one end of the current blocking layer P-type through hole 131 is connected to the Bragg reflection layer P-type through hole 1411, and the other end extends to the current spreading layer 12, so that the current spreading layer 12 is partially exposed;

[0065] A protrusion 151 is provided on the side of the metal reflective layer 15 close to the substrate 10. The protrusion 151 sequentially fills the Bragg reflective layer P-type through-hole 1411 and the current blocking layer P-type through-hole 131, and the end of the protrusion contacts the current spreading layer 12, so that the metal reflective layer 15 and the current spreading layer 12 are electrically connected.

[0066] In one embodiment, the Bragg reflector 14 includes a first Bragg reflector portion 141 and a second Bragg reflector portion 142 connected to each other. The first Bragg reflector portion 141 and the second Bragg reflector portion 142 respectively cover the surface of the current blocking layer 13, and the first Bragg reflector portion 141 is located above the P-type semiconductor layer 113, and the second Bragg reflector portion 142 is located above the second N-type semiconductor portion 1112. The first Bragg reflector portion 141 is provided with a Bragg reflector layer P-type through hole 1411; the second Bragg reflector portion 142 is provided with a Bragg reflector layer N-type through hole 1421, and one end of the Bragg reflector layer N-type through hole 1421 extends to the current blocking layer 13.

[0067] The first insulating layer 16 includes a first insulating layer A portion 161 and a first insulating layer B portion 162 connected to each other. The first insulating layer A portion 161 is stacked above the metal reflective layer 15, and the first insulating layer B portion 162 is stacked above the second Bragg reflector 142. The first insulating layer P-type through hole 1611 is located in the first insulating layer A portion 161. The first insulating layer B portion 162 is provided with a first insulating layer N-type through hole 1621. The first insulating layer N-type through hole 1621 is located inside the Bragg reflector N-type through hole 1421.

[0068] The current blocking layer 13 is further provided with a current blocking layer N-type through hole 132 , one end of the current blocking layer N-type through hole 132 is connected to the first insulating layer N-type through hole 1621 , and the other end extends to the second N-type semiconductor portion 1112 ;

[0069] The P-type metal conductive layer 171 and the N-type metal conductive layer 172 are spatially separated from each other so that there is no direct physical contact between the two. The P-type metal conductive layer 171 covers the surface of the first insulating layer A portion 161 and fills the first insulating layer P-type through hole 1611, so that the P-type metal conductive layer 171 and the metal reflective layer 15 are electrically connected. The N-type metal conductive layer 172 covers the surface of the first insulating layer B portion 162 and sequentially fills the first insulating layer N-type through hole 1621 and the current blocking layer N-type through hole 132, so that the N-type metal conductive layer 172 and the second N-type semiconductor portion 1112 are electrically connected.

[0070] In one embodiment, the flip-chip silver mirror light-emitting diode chip further includes a second insulating layer 18, which covers the surface of the P-type metal conductive layer 171, the N-type metal conductive layer 172, and the exposed first insulating layer 16. The second insulating layer 18 is provided with a second insulating layer P-type through-hole 181 and a second insulating layer N-type through-hole 182. One end of the second insulating layer P-type through-hole 181 extends to the P-type metal conductive layer 171, so that part of the P-type metal conductive layer 171 is exposed, and one end of the second insulating layer N-type through-hole 182 extends to the N-type metal conductive layer 172, so that part of the N-type metal conductive layer 172 is exposed.

[0071] Specifically, the second insulating layer P-type through-hole 181 only exposes a specific area of ​​the P-type metal conductive layer 171, allowing the upper metal or conductive structure (such as interconnect wiring, electrodes) to form an exclusive electrical connection therewith, thereby avoiding a short circuit with the N-type metal conductive layer 172. Similarly, the second insulating layer N-type through-hole 182 only exposes a specific area of ​​the N-type metal conductive layer 172, ensuring that the upper structure is only conductive with the N-type metal conductive layer 172. The second insulating layer 18 covers the non-through-hole areas of the P-type metal conductive layer 171 and the N-type metal conductive layer 172, as well as the exposed surface of the first insulating layer 16, forming a sealed barrier to prevent excessive metal from coming into contact with air and water vapor and causing oxidation or corrosion, thereby extending the life of the device.

[0072] Specifically, the second insulating layer 18 and the first insulating layer 16 cooperate to separate the P-type metal conductive layer 171 and the N-type metal conductive layer 172 from each other in space without direct physical contact, thereby realizing circuit connection within the chip and preventing short circuits between layers.

[0073] Correspondingly, this embodiment further discloses a method for preparing a flip-chip silver mirror light-emitting diode chip, which is used to prepare the above-mentioned flip-chip silver mirror light-emitting diode chip, comprising the following steps:

[0074] (1) providing a substrate 10, and sequentially depositing an N-type semiconductor layer 111, an active light-emitting layer 112, and a P-type semiconductor layer 113 on the substrate 10 by an MOCVD process to obtain an epitaxial layer 11; preferably, the substrate 10 may be a GaN substrate, an Al2O3 substrate, or a Si substrate;

[0075] (2) removing a portion of the P-type semiconductor layer 113 and the corresponding active light-emitting layer 112 to expose a portion of the N-type semiconductor layer 111, where the exposed N-type semiconductor layer 111 is the second N-type semiconductor portion 1112; in some embodiments, coating a first photoresist on the surface of the P-type semiconductor layer 113, and then removing a portion of the first photoresist on the P-type semiconductor layer 113 by an exposure and development process to expose a portion of the P-type semiconductor layer 113; removing the exposed P-type semiconductor layer 113 and the corresponding active light-emitting layer 112 by an inductively coupled plasma etching process to expose a portion of the N-type semiconductor layer 111, where the exposed portion of the N-type semiconductor layer 111 is the second N-type semiconductor portion 1112, and then removing the first photoresist;

[0076] (3) Depositing indium tin oxide on the surface of the P-type semiconductor layer 113 to form a current spreading layer 12 on the surface of the P-type semiconductor layer 113; in some embodiments, depositing indium tin oxide on the surface of the P-type semiconductor layer 113 and the second N-type semiconductor portion 1112 using a magnetron sputtering process; then coating the surface of the indium tin oxide with a second photoresist, and then removing a portion of the second photoresist by exposure and development to expose a portion of the indium tin oxide; then removing the exposed indium tin oxide using an indium tin oxide etching solution, and then removing the second photoresist, so that the current spreading layer 12 is formed on the surface of the P-type semiconductor layer 113;

[0077] (4) SiO2 is deposited on the surface of the P-type semiconductor layer 113, the current spreading layer 12 and the second N-type semiconductor portion 1112 using a PECVD process to form a current blocking layer 13. The thickness of the current blocking layer 13 is greater than 5000 Å;

[0078] (5) using an electron beam evaporation process to sequentially deposit 2 to 10 groups of TiO2 and SiO2 stacks on the surface of the current blocking layer 13 to form a Bragg reflection layer 14;

[0079] (6) a Bragg reflector layer P-type through hole 1411 and a Bragg reflector layer N-type through hole 1421 are formed at designated positions of the Bragg reflector layer 14; in some embodiments, a third photoresist is coated on the surface of the Bragg reflector layer 14, and the third photoresist on a portion of the Bragg reflector layer 14 is removed by exposure and development, and then the exposed Bragg reflector layer 14 is removed by an inductively coupled plasma etching process to form the Bragg reflector layer P-type through hole 1411 and the Bragg reflector layer N-type through hole 1421, exposing the current blocking layer 13 below the Bragg reflector layer P-type through hole 1411 and the Bragg reflector layer N-type through hole 1421, and then the third photoresist is removed;

[0080] (7) a current blocking layer P-type through hole 131 and a current blocking layer N-type through hole 132 are formed at designated positions of the current blocking layer 13; in some embodiments, a fourth photoresist is coated on the surfaces of the Bragg reflective layer 14, the Bragg reflective layer P-type through hole 1411, and the Bragg reflective layer N-type through hole 1421; a portion of the fourth photoresist within the Bragg reflective layer P-type through hole 1411 and the Bragg reflective layer N-type through hole 1421 is removed by exposure and development, exposing the current blocking layer 13 below the Bragg reflective layer P-type through hole 1411 and the Bragg reflective layer N-type through hole 142; the exposed current blocking layer 13 is removed by a first BOE etching solution, forming the current blocking layer P-type through hole 131 and the current blocking layer N-type through hole 132, respectively, and then the fourth photoresist is removed;

[0081] (8) growing a metal reflective layer 15 above a designated position of the Bragg reflective layer 14, and the metal reflective layer 15 fills the Bragg reflective layer P-type through hole 1411 and the current blocking layer P-type through hole 131; in some embodiments, first coating the Bragg reflective layer 14, the Bragg reflective layer P-type through hole 1411, the Bragg reflective layer N-type through hole 1421, the current blocking layer P-type through hole 131, the current blocking layer N-type through hole 132, and the exposed portion of the current blocking layer 13 with a fifth photoresist; removing a portion of the fifth photoresist by exposure and development; then sequentially evaporating Ag / Ni / Ti / Ni / Ti / Ni / Ti / Ni / Ti metals by electron beam evaporation to form the metal reflective layer 15 (i.e., the metal reflective layer 15 is a Ag / Ni / Ti / Ni / Ti / Ni / Ti / Ni / Ti metal stack); then removing the metal above the fifth photoresist and removing the fifth photoresist by a blue film stripping process;

[0082] (9) SiO2 is deposited on the metal reflective layer 15 using a second PECVD process to form a first insulating layer 16; a first insulating layer P-type through hole 1161 and a first insulating layer N-type through hole 1621 are opened at designated positions of the first insulating layer 16; in some embodiments, a sixth photoresist is first coated on the surface of the first insulating layer 16, and a portion of the sixth photoresist is removed by exposure and development to expose a portion of the first insulating layer 16, and then a second BOE etching solution is used to remove the exposed first insulating layer 16 to form the first insulating layer P-type through hole 1161 and the first insulating layer N-type through hole 1621, and the sixth photoresist is removed;

[0083] (10) forming a P-type metal conductive layer 171 and an N-type metal conductive layer 172 at designated positions of the first insulating layer 16; in some embodiments, coating a seventh photoresist on the surface of the first insulating layer 16, the first insulating layer P-type through hole 1161, and the first insulating layer N-type through hole 1621, and then removing a portion of the seventh photoresist by exposure and development; sequentially evaporating Al / Ti / Al / Ti / Al / Ti / Ni / Au / Ti metals by electron beam evaporation to form a P-type metal conductive layer 171 and an N-type metal conductive layer 172 (i.e., the P-type metal conductive layer 171 and the N-type metal conductive layer 172 are both Al / Ti / Al / Ti / Al / Ti / Ni / Au / Ti metal stacks), and then removing the metal on the seventh photoresist by a blue film stripping process, and then removing the seventh photoresist;

[0084] (11) SiO2 is deposited as the second insulating layer 18 on the surface of the P-type metal conductive layer 171, the N-type metal conductive layer 172 and the surface of the first insulating layer 16 not covered by the P-type metal conductive layer 171 and the N-type metal conductive layer 172 by using a PECVD process; an eighth photoresist is coated on the surface of the second insulating layer 18, and then a portion of the eighth photoresist is removed by exposure and development to expose a portion of the second insulating layer 18, and then a third BOE etching solution is used to remove the exposed second insulating layer, and then the eighth photoresist is removed to form a second insulating layer P-type through hole 181 and a second insulating layer N-type through hole 182.

[0085] In one embodiment, in step (6), the method of opening a Bragg reflector layer P-type through hole 1411 and a Bragg reflector layer N-type through hole 1421 at a designated position of the Bragg reflector layer 14 comprises the following steps:

[0086] A third photoresist is coated on the surface of the Bragg reflector layer 14, and the third photoresist at a designated position on the Bragg reflector layer 14 is removed by exposure and development. Then, the exposed Bragg reflector layer 14 is removed by an inductively coupled plasma etching process to form a Bragg reflector layer P-type through hole 1411 and a Bragg reflector layer N-type through hole 1421, exposing the current blocking layer 13 below the Bragg reflector layer P-type through hole 1411 and the Bragg reflector layer N-type through hole 1421, and then removing the third photoresist.

[0087] The thickness of the third photoresist is 1.5 μm to 2 μm; the angle α between the hole wall of the Bragg reflector layer P-type through hole 1411 and the horizontal plane depends on the thickness of the third photoresist. By controlling the thickness of the third photoresist to 1.5 μm to 2 μm, the angle α between the hole wall of the Bragg reflector layer P-type through hole 1411 and the horizontal plane can be controlled to be 25° to 40°.

[0088] In step (9), the method for forming the first insulating layer P-type through hole 1161 and the first insulating layer N-type through hole 1621 at the designated position of the first insulating layer 16 includes the following steps: coating a sixth photoresist on the surface of the first insulating layer 16, removing the sixth photoresist at the designated position by exposure and development to expose a portion of the first insulating layer 16, then removing the exposed first insulating layer 16 by a second BOE etching solution to form the first insulating layer P-type through hole 1161 and the first insulating layer N-type through hole 1621, and removing the sixth photoresist;

[0089] The second BOE etching solution comprises hydrofluoric acid, ammonium fluoride, and water. The volume ratio of ammonium fluoride to hydrofluoric acid in the second BOE etching solution is 15:1 to 20:1. The angle β between the hole wall of the first insulating layer P-type through hole 1611 and the horizontal plane depends on the volume ratio of ammonium fluoride to hydrofluoric acid in the second BOE etching solution. By controlling the volume ratio of ammonium fluoride to hydrofluoric acid to be 15:1 to 20:1, the angle β between the hole wall of the first insulating layer P-type through hole 1611 and the horizontal plane can be controlled to be 15° to 20°, thereby ensuring that the resulting flip-chip silver mirror light-emitting diode chip has excellent high-current resistance.

[0090] The technical solution of the present invention is further described below through examples and comparative examples.

[0091] Example 1

[0092] This embodiment discloses a flip-chip silver mirror light-emitting diode chip, comprising a substrate 10, an epitaxial layer 11, a current spreading layer 12, a current blocking layer 13, a Bragg reflector 14, a metal reflector 15, a first insulating layer 16, a P-type metal conductive layer 171, an N-type metal conductive layer 172, and a second insulating layer 18; the epitaxial layer 11 comprises an N-type semiconductor layer 111, an active light-emitting layer 112, and a P-type semiconductor layer 113;

[0093] The current blocking layer 13 is provided with a current blocking layer P-type through hole 131 and a current blocking layer N-type through hole 132 , and the Bragg reflection layer 14 is provided with a Bragg reflection layer P-type through hole 1411 and a Bragg reflection layer N-type through hole 1421 ;

[0094] The first insulating layer 16 is provided with a first insulating layer P-type through hole 1611 and a first insulating layer N-type through hole 1621;

[0095] In this embodiment, the angle β between the hole wall of the P-type through hole 1611 in the first insulating layer and the horizontal plane is 15°, and the angle α between the hole wall of the P-type through hole 1411 in the Bragg reflector layer and the horizontal plane is 25°.

[0096] A distance L between a projected edge of the first insulating layer P-type through hole 1611 on a horizontal plane and a projected edge of the Bragg reflector layer P-type through hole 1411 on a horizontal plane is 5 μm.

[0097] The method for preparing the flip-chip silver mirror light-emitting diode chip of this embodiment includes the following steps:

[0098] (1) providing a substrate 10, and sequentially depositing an N-type semiconductor layer 111, an active light-emitting layer 112, and a P-type semiconductor layer 113 on the substrate 10 by an MOCVD process to obtain an epitaxial layer 11; the substrate 10 is a GaN substrate;

[0099] (2) coating a first photoresist on the surface of the P-type semiconductor layer 113, then removing a portion of the first photoresist on the P-type semiconductor layer 113 by an exposure and development process, exposing a portion of the P-type semiconductor layer 113; removing the exposed P-type semiconductor layer 113 and the corresponding active light-emitting layer 112 by an inductively coupled plasma etching process, exposing a portion of the N-type semiconductor layer 111, the exposed portion of the N-type semiconductor layer 111 being the second N-type semiconductor portion 1112, and then removing the first photoresist;

[0100] (3) Depositing indium tin oxide on the surface of the P-type semiconductor layer 113 and the second N-type semiconductor portion 1112 using a magnetron sputtering process; then coating the surface of the indium tin oxide with a second photoresist, and then removing a portion of the second photoresist by exposure and development to expose a portion of the indium tin oxide; then removing the exposed indium tin oxide using an indium tin oxide etching solution, and then removing the second photoresist, thereby forming a current spreading layer 12 on the surface of the P-type semiconductor layer 113;

[0101] (4) SiO2 is deposited on the surface of the P-type semiconductor layer 113, the current spreading layer 12 and the second N-type semiconductor portion 1112 using a PECVD process to form a current blocking layer 13. The thickness of the current blocking layer 13 is 5500 Å;

[0102] (5) using an electron beam evaporation process to sequentially deposit five groups of TiO2 and SiO2 stacks on the surface of the current blocking layer 13 to form a Bragg reflection layer 14;

[0103] (6) coating a third photoresist on the surface of the Bragg reflector layer 14, removing a portion of the third photoresist on the Bragg reflector layer 14 by exposure and development, and then removing the exposed Bragg reflector layer 14 by an inductively coupled plasma etching process to form a Bragg reflector layer P-type through hole 1411 and a Bragg reflector layer N-type through hole 1421, exposing the current blocking layer 13 below the Bragg reflector layer P-type through hole 1411 and the Bragg reflector layer N-type through hole 1421, and then removing the third photoresist; wherein, in this embodiment, the thickness of the third photoresist is 1.5 μm;

[0104] (7) coating a fourth photoresist on the surface of the Bragg reflective layer 14, the Bragg reflective layer P-type through hole 1411, and the Bragg reflective layer N-type through hole 1421; removing a portion of the fourth photoresist inside the Bragg reflective layer P-type through hole 1411 and the Bragg reflective layer N-type through hole 1421 by exposure and development, exposing the current blocking layer 13 below the Bragg reflective layer P-type through hole 1411 and the Bragg reflective layer N-type through hole 1421; removing the exposed current blocking layer 13 by a first BOE etching solution, forming a current blocking layer P-type through hole 131 and a current blocking layer N-type through hole 132, respectively, and then removing the fourth photoresist;

[0105] (8) coating a fifth photoresist on the Bragg reflective layer 14, the Bragg reflective layer P-type through hole 1411, the Bragg reflective layer N-type through hole 1421, the current blocking layer P-type through hole 131, the current blocking layer N-type through hole 132, and the exposed portion of the current blocking layer 13; removing a portion of the fifth photoresist by exposure and development; then sequentially evaporating Ag / Ni / Ti / Ni / Ti / Ni / Ti / Ni / Ti metals by electron beam evaporation to form a metal reflective layer 15 (i.e., the metal reflective layer 15 is a Ag / Ni / Ti / Ni / Ti / Ni / Ti / Ni / Ti metal stack); then removing the metal located above the fifth photoresist and removing the fifth photoresist by a blue film stripping process;

[0106] (9) SiO2 is deposited on the metal reflective layer 15 by a second PECVD process to form a first insulating layer 16; a sixth photoresist is coated on the surface of the first insulating layer 16, and a portion of the sixth photoresist is removed by exposure and development to expose a portion of the first insulating layer 16, and then a second BOE etching solution is used to remove the exposed first insulating layer 16 to form a first insulating layer P-type through hole 1161 and a first insulating layer N-type through hole 1621, and the sixth photoresist is removed; wherein the second BOE etching solution comprises hydrofluoric acid, ammonium fluoride and water, and in this embodiment, the volume ratio of ammonium fluoride to hydrofluoric acid in the second BOE etching solution is 15:1;

[0107] (10) coating a seventh photoresist on the surface of the first insulating layer 16, the first insulating layer P-type through hole 1161 and the first insulating layer N-type through hole 1621, and then removing part of the seventh photoresist by exposure and development; sequentially evaporating Al / Ti / Al / Ti / Al / Ti / Ni / Au / Ti metals by electron beam evaporation process to form a P-type metal conductive layer 171 and an N-type metal conductive layer 172 (i.e., the P-type metal conductive layer 171 and the N-type metal conductive layer 172 are both Al / Ti / Al / Ti / Al / Ti / Ni / Au / Ti metal stacks), and then removing the metal on the seventh photoresist by a blue film stripping process, and then removing the seventh photoresist;

[0108] (11) SiO2 is deposited as the second insulating layer 18 on the surface of the P-type metal conductive layer 171, the N-type metal conductive layer 172 and the surface of the first insulating layer 16 not covered by the P-type metal conductive layer 171 and the N-type metal conductive layer 172 by using a PECVD process; an eighth photoresist is coated on the surface of the second insulating layer 18, and then a portion of the eighth photoresist is removed by exposure and development to expose a portion of the second insulating layer 18, and then a third BOE etching solution is used to remove the exposed second insulating layer, and then the eighth photoresist is removed to form a second insulating layer P-type through hole 181 and a second insulating layer N-type through hole 182.

[0109] Example 2

[0110] This embodiment discloses a flip-chip silver mirror light-emitting diode chip. The structure and preparation method of the flip-chip silver mirror light-emitting diode chip of this embodiment are basically the same as those of Example 1, except that: in the flip-chip silver mirror light-emitting diode chip of Example 2, the angle β between the hole wall of the P-type through hole 1611 of the first insulating layer and the horizontal plane is 20°, and the angle α between the hole wall of the P-type through hole 1411 of the Bragg reflection layer and the horizontal plane is 40°; in step (6), the thickness of the third photoresist is 2 μm; and in step (9), the volume ratio of ammonium fluoride to hydrofluoric acid in the second BOE etching solution is 20:1.

[0111] Example 3

[0112] This embodiment discloses a flip-chip silver mirror light-emitting diode chip. The structure and preparation method of the flip-chip silver mirror light-emitting diode chip of this embodiment are basically the same as those of Example 1, except that: in the flip-chip silver mirror light-emitting diode chip of Example 3, the angle β between the hole wall of the first insulating layer P-type through hole 1611 and the horizontal plane is 20°, and the angle α between the hole wall of the Bragg reflector layer P-type through hole 1411 and the horizontal plane is 40°; in step (6), the thickness of the third photoresist is 2 μm; in step (9), the volume ratio of ammonium fluoride to hydrofluoric acid in the second BOE etching solution is 20:1; and the distance L between the projected edge of the first insulating layer P-type through hole 1611 on the horizontal plane and the projected edge of the Bragg reflector layer P-type through hole 1411 on the horizontal plane is 6.5 μm.

[0113] Example 4

[0114] This embodiment discloses a flip-chip silver mirror light-emitting diode chip. The structure and preparation method of the flip-chip silver mirror light-emitting diode chip of this embodiment are basically the same as those of Example 1, except that: in the flip-chip silver mirror light-emitting diode chip of Example 3, the angle β between the hole wall of the first insulating layer P-type through hole 1611 and the horizontal plane is 20°, and the angle α between the hole wall of the Bragg reflector layer P-type through hole 1411 and the horizontal plane is 40°; in step (6), the thickness of the third photoresist is 2 μm; in step (9), the volume ratio of ammonium fluoride to hydrofluoric acid in the second BOE etching solution is 20:1; and the distance L between the projected edge of the first insulating layer P-type through hole 1611 on the horizontal plane and the projected edge of the Bragg reflector layer P-type through hole 1411 on the horizontal plane is 8 μm.

[0115] Example 5

[0116] This embodiment discloses a flip-chip silver mirror light-emitting diode chip. The structure and preparation method of the flip-chip silver mirror light-emitting diode chip of this embodiment are basically the same as those of Example 1, except that: in the flip-chip silver mirror light-emitting diode chip of Example 3, the angle β between the hole wall of the first insulating layer P-type through hole 1611 and the horizontal plane is 20°, and the angle α between the hole wall of the Bragg reflector layer P-type through hole 1411 and the horizontal plane is 40°; in step (6), the thickness of the third photoresist is 2 μm; in step (9), the volume ratio of ammonium fluoride to hydrofluoric acid in the second BOE etching solution is 20:1; and the distance L between the projected edge of the first insulating layer P-type through hole 1611 on the horizontal plane and the projected edge of the Bragg reflector layer P-type through hole 1411 on the horizontal plane is 12 μm.

[0117] Comparative Example 1

[0118] This comparative example discloses a flip-chip silver mirror light-emitting diode chip. The structure and preparation method of the flip-chip silver mirror light-emitting diode chip of this comparative example are basically the same as those of Example 1, except that: in the flip-chip silver mirror light-emitting diode chip of Comparative Example 1, the angle β between the hole wall of the P-type through hole of the first insulating layer and the horizontal plane is 65°, and the angle α between the hole wall of the P-type through hole of the Bragg reflector layer and the horizontal plane is 20°; in step (6), the thickness of the third photoresist is 4 μm; in step (9), the volume ratio of ammonium fluoride to hydrofluoric acid in the second BOE etching solution is 13:1; and the distance L between the projected edge of the P-type through hole of the first insulating layer on the horizontal plane and the projected edge of the P-type through hole of the Bragg reflector layer on the horizontal plane is 0 μm.

[0119] Specifically, the flip-chip silver mirror LED chips produced in Examples 1 to 5 and Comparative Example 1 were subjected to a long-term, high-current aging test at room temperature (25°C). The high current was three times the operating current. Before aging, the chip brightness was measured and recorded as the initial brightness. During the aging process, the chip brightness was measured every 72 hours as the real-time brightness. When the ratio of the real-time brightness to the initial brightness was less than 90%, the chip was deemed failed, and the time of chip failure was recorded. The chip size used in the test was 1200μm×1200μm, and the operating current was 700mA, meaning the high aging current was 2100mA. The test results are shown in Table 1 below:

[0120] Table 1 Performance test results

[0121]

[0122] From the test results in Table 1, it can be seen that in Examples 1 to 5, by controlling the distance L between the projected edge of the first insulating layer P-type through hole 1611 on the horizontal plane and the projected edge of the Bragg reflector layer P-type through hole 1411 on the horizontal plane to be 5 μm to 12 μm, and controlling the angle β between the hole wall of the first insulating layer P-type through hole 1611 and the horizontal plane to be smaller than the angle α between the hole wall of the Bragg reflector layer P-type through hole 1411 and the horizontal plane, the service life of the chip at a high current of 2100 mA can be significantly extended. At a high current of 2100 mA, the chip can operate continuously for more than 1700 hours. Therefore, it can be seen that the flip-chip silver mirror light-emitting diode chips of Examples 1 to 5 have excellent high current resistance capabilities.

[0123] The above description is merely a preferred embodiment of the present invention and does not constitute any form of limitation to the present invention. Although the present invention has been disclosed as above in terms of a preferred embodiment, it is not intended to limit the present invention. Any person skilled in the art may, without departing from the scope of the technical solution of the present invention, make some changes or modifications to equivalent embodiments using the technical contents suggested above. However, any simple modifications, equivalent changes and modifications made to the above embodiments based on the technical essence of the present invention without departing from the content of the technical solution of the present invention shall still fall within the scope of the solution of the present invention.

Claims

1. A flip-chip silver mirror light-emitting diode chip, characterized in that: It includes a substrate, an epitaxial layer, a Bragg reflection layer, a metal reflection layer, a first insulating layer, a P-type metal conductive layer and an N-type metal conductive layer; The epitaxial layer includes an N-type semiconductor layer, an active light-emitting layer and a P-type semiconductor layer sequentially stacked on the substrate. The Bragg reflective layer is stacked on the P-type semiconductor layer, and the Bragg reflective layer is provided with a Bragg reflective layer P-type through hole; the metal reflective layer covers the surface of the Bragg reflective layer, and the metal reflective layer is electrically connected to the P-type semiconductor layer through the Bragg reflective layer P-type through hole; The first insulating layer is stacked on the metal reflective layer, and the first insulating layer is provided with a first insulating layer P-type through hole, and one end of the first insulating layer P-type through hole extends to the metal reflective layer; The P-type metal conductive layer is stacked on the first insulating layer, and the P-type metal conductive layer is electrically connected to the metal reflective layer through the P-type through-hole of the first insulating layer, and the N-type metal conductive layer is electrically connected to the N-type semiconductor layer; The angle β between the hole wall of the P-type through hole in the first insulating layer and the horizontal plane is smaller than the angle α between the hole wall of the P-type through hole in the Bragg reflector layer and the horizontal plane; A distance L between a projected edge of the P-type through hole in the first insulating layer and a projected edge of the P-type through hole in the Bragg reflective layer is 5 μm to 12 μm.

2. The flip-chip silver mirror light-emitting diode chip according to claim 1, characterized in that: A distance L between a projected edge of the P-type through hole in the first insulating layer and a projected edge of the P-type through hole in the Bragg reflector layer is 5 μm to 8 μm.

3. The flip-chip silver mirror light-emitting diode chip according to claim 1, characterized in that: The difference between the angle β between the hole wall of the P-type through hole in the first insulating layer and the horizontal plane and the angle α between the hole wall of the P-type through hole in the Bragg reflector layer and the horizontal plane is ≤20°.

4. The flip-chip silver mirror light-emitting diode chip according to claim 1, 2 or 3, characterized in that: The angle β between the hole wall of the P-type through hole in the first insulating layer and the horizontal plane is 15° to 20°.

5. The flip-chip silver mirror light-emitting diode chip according to claim 4, characterized in that: The angle α between the hole wall of the P-type through hole in the Bragg reflector layer and the horizontal plane is 25° to 40°.

6. The flip-chip silver mirror light-emitting diode chip according to claim 1, characterized in that: The flip-chip silver mirror light-emitting diode chip further includes a current spreading layer and a current blocking layer; The N-type semiconductor layer is stacked on the surface of the substrate, the N-type semiconductor layer includes a first N-type semiconductor portion and a second N-type semiconductor portion connected to each other, the P-type semiconductor layer and the active light-emitting layer are sequentially stacked on the first N-type semiconductor portion, and the current spreading layer covers the surface of the P-type semiconductor layer, so that the current spreading layer and the P-type semiconductor layer are electrically connected; The current blocking layer covers the surface of the current spreading layer and the second N-type semiconductor portion, and the Bragg reflection layer covers the surface of the current blocking layer; The current blocking layer is provided with a current blocking layer P-type through hole, one end of the current blocking layer P-type through hole is connected to the Bragg reflection layer P-type through hole, and the other end extends to the current spreading layer; The metal reflective layer is located above the current spreading layer. A protrusion is provided on a side of the metal reflective layer close to the substrate. The protrusion sequentially fills the P-type through-holes of the Bragg reflective layer and the P-type through-holes of the current blocking layer. An end of the protrusion contacts the current spreading layer, so that the metal reflective layer and the current spreading layer are electrically connected.

7. The flip-chip silver mirror light-emitting diode chip according to claim 6, characterized in that: The Bragg reflector layer includes a first Bragg reflector portion and a second Bragg reflector portion connected to each other, wherein the first Bragg reflector portion and the second Bragg reflector portion respectively cover a surface of the current blocking layer, and the first Bragg reflector portion is located above the P-type semiconductor layer, and the second Bragg reflector portion is located above the second N-type semiconductor portion; the first Bragg reflector portion is provided with a Bragg reflector layer P-type through hole; the second Bragg reflector portion is provided with a Bragg reflector layer N-type through hole, and one end of the Bragg reflector layer N-type through hole extends to the current blocking layer; The first insulating layer includes a first insulating layer portion A and a first insulating layer portion B connected to each other, the first insulating layer portion A is stacked on the metal reflective layer, and the first insulating layer portion B is stacked on the second Bragg reflector; the first insulating layer P-type through hole is located in the first insulating layer portion A, and the first insulating layer portion B is provided with a first insulating layer N-type through hole, and the first insulating layer N-type through hole is located inside the N-type through hole of the Bragg reflector; The current blocking layer is further provided with a current blocking layer N-type through hole, one end of the current blocking layer N-type through hole is connected to the first insulating layer N-type through hole, and the other end extends to the second N-type semiconductor portion; The P-type metal conductive layer and the N-type metal conductive layer are spatially separated from each other. The P-type metal conductive layer covers the surface of the first insulating layer portion A, and the N-type metal conductive layer covers the surface of the first insulating layer portion B and sequentially fills the first insulating layer N-type through holes and the current blocking layer N-type through holes until they contact the second N-type semiconductor portion.

8. The flip-chip silver mirror light-emitting diode chip according to claim 7, characterized in that: The flip-chip silver mirror light-emitting diode chip also includes a second insulating layer, which covers the P-type metal conductive layer, the N-type metal conductive layer and the surface of the exposed first insulating layer. The second insulating layer is provided with a second insulating layer P-type through-hole and a second insulating layer N-type through-hole, one end of the second insulating layer P-type through-hole extends to the P-type metal conductive layer, and one end of the second insulating layer N-type through-hole extends to the N-type metal conductive layer.

9. A method for preparing a flip-chip silver mirror light-emitting diode chip, characterized in that: The method for preparing the flip-chip silver mirror light-emitting diode chip according to any one of claims 1 to 8 comprises the following steps: (1) providing a substrate, and sequentially depositing an N-type semiconductor layer, an active light-emitting layer, and a P-type semiconductor layer on the substrate to obtain an epitaxial layer; (2) removing the P-type semiconductor layer and the corresponding active light-emitting layer in a designated area to expose a portion of the N-type semiconductor layer, where the exposed N-type semiconductor layer is the second N-type semiconductor portion; (3) depositing indium tin oxide on the surface of the P-type semiconductor layer to form a current spreading layer on the surface of the P-type semiconductor layer; (4) depositing SiO on the surface of the P-type semiconductor layer, the current spreading layer, and the second N-type semiconductor portion to form a current blocking layer; (5) sequentially depositing a stack of TiO and SiO layers on the surface of the current blocking layer to form a Bragg reflection layer; (6) opening a Bragg reflector layer P-type through hole and a Bragg reflector layer N-type through hole at a designated position of the Bragg reflector layer; (7) opening a current blocking layer P-type through hole and a current blocking layer N-type through hole at a designated position of the current blocking layer; (8) growing a metal reflective layer above a designated position of the Bragg reflective layer, wherein the metal reflective layer fills the P-type through-holes of the Bragg reflective layer and the P-type through-holes of the current blocking layer; (9) depositing SiO on the metal reflective layer to form a first insulating layer; opening a first insulating layer P-type through hole and a first insulating layer N-type through hole at a designated position of the first insulating layer; (10) A P-type metal conductive layer and an N-type metal conductive layer are formed on designated positions of the first insulating layer.

10. The method for preparing a flip-chip silver mirror light-emitting diode chip according to claim 9, characterized in that: In step (6), the method of opening a Bragg reflector layer P-type through hole and a Bragg reflector layer N-type through hole at a designated position of the Bragg reflector layer comprises the following steps: Coating a third photoresist on the surface of the Bragg reflector layer, removing the third photoresist at a designated position on the Bragg reflector layer, and then removing the exposed Bragg reflector layer to form a P-type through hole and an N-type through hole in the Bragg reflector layer, exposing the current blocking layer below the P-type through hole and the N-type through hole in the Bragg reflector layer, and then removing the third photoresist; the thickness of the third photoresist is 1.5 μm to 2 μm; In step (9), the method for forming a first insulating layer P-type through hole and a first insulating layer N-type through hole at a designated position of the first insulating layer includes the following steps: coating a sixth photoresist on the surface of the first insulating layer, removing the sixth photoresist at the designated position to expose a portion of the first insulating layer, then removing the exposed first insulating layer using a second BOE etching solution to form a first insulating layer P-type through hole and a first insulating layer N-type through hole, and removing the sixth photoresist; The second BOE etching solution comprises components of hydrofluoric acid, ammonium fluoride and water. The volume ratio of ammonium fluoride to hydrofluoric acid in the second BOE etching solution is 15:1 to 20:1.

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