Management method and device of memory device

Abstract

The invention discloses a memory device management method and device, and relates to the field of computers.The method comprises the steps that field data of N bytes are extracted from serial existence detection data of a server memory device, and the bytes comprise key fields such as manufacturer numbers, production place information, production years, production weeks and serial numbers; and the target sequence identifier is generated according to the preset rule combination, and the identifier completely reflects physical factory information such as a manufacturer, a production place, time and a unique serial number of the memory device, so that the purpose of unifying memory sequence identifier display is achieved, and the technical effect that complete memory information can be accurately checked in real time without physically disassembling a server is achieved. The operation and maintenance efficiency of the server is improved, the hardware management cost is reduced, and the reliability and applicability of the system are enhanced.

Description

Technical Field

[0001] The present application relates to the field of computers, and in particular to a method and apparatus for managing memory devices. Background Art

[0002] In the server world, memory devices like DDR5 are core components, and their unique serial identifiers are crucial for device management and tracking. Traditional serial identifiers use 8 bits, while physical memory uses 18-bit identifiers when shipped from the factory. The formats and contents of the two are inconsistent. This discrepancy results in discrepancies between the displayed serial identifiers and the actual physical identifiers when querying them via standard commands in the server operating system or viewing them in the baseboard management controller interface. Users must shut down and physically disassemble the server to obtain complete serial information, increasing operational and maintenance costs and time, and reducing server management efficiency. Summary of the Invention

[0003] The present application provides a method and apparatus for managing a memory device, so as to at least solve the technical problems of high management cost and low efficiency of memory devices in related technologies.

[0004] The present application provides a method for managing a memory device, comprising: extracting N bytes of field data from serial presence detection data corresponding to the memory device, wherein the memory device represents a memory device in an in-place state configured for a server, and the N bytes represent the i-th byte to the j-th byte of the pre-set serial presence detection data, where i, j, and N are all positive integers; combining the N bytes of field data to generate a target sequence identifier, wherein the target sequence identifier is used to identify relevant information of the memory device; and displaying the target sequence identifier.

[0005] The present application also provides a memory device management device, including: an extraction module, used to extract N bytes of field data from serial presence detection data corresponding to the memory device, wherein the memory device represents a memory device in an in-place state configured for a server, and the N bytes represent the i-th byte to the j-th byte of the pre-set serial presence detection data, where i, j, and N are all positive integers; a combination module, used to combine the N bytes of field data to generate a target sequence identifier, wherein the target sequence identifier is used to identify relevant information of the memory device; and a display module, used to display the target sequence identifier.

[0006] In an exemplary embodiment, the device is used to extract N bytes of field data from the serial presence detection data corresponding to the memory device in the following manner: during the startup phase of the server, detecting whether the memory slot of the server is installed with the memory device; when it is detected that the memory slot is installed with the memory device, extracting N bytes of field data from the serial presence detection data corresponding to the memory device.

[0007] In an exemplary embodiment, the apparatus is used to extract N bytes of field data from serial presence detection data corresponding to a memory device in the following manner: during the startup phase of the server, polling the central processing unit number, memory channel number, and memory slot number of the server to determine whether the memory device is in place; when it is detected that the memory device associated with the current slot is in place, extracting N bytes of field data from the serial presence detection data corresponding to the memory device; when it is detected that the memory device associated with the current slot is not in place, skipping the current slot and continuing to poll the slot next to the current slot.

[0008] In an exemplary embodiment, the apparatus is configured to extract N bytes of field data from serial presence detection data corresponding to a memory device in the following manner: obtaining the field data corresponding to the i-th byte to the i+1-th byte from the serial presence detection data through a two-wire serial bus protocol; and assembling the field data corresponding to the i-th byte to the i+1-th byte into double-byte data, wherein the double-byte data is used to indicate a manufacturer identification of the memory device.

[0009] In an exemplary embodiment, the apparatus is configured to extract N bytes of field data from serial presence detection data corresponding to a memory device in at least one of the following ways: obtaining field data corresponding to the i+2th byte from the serial presence detection data through a two-wire serial bus protocol, wherein the i+2th byte is used to indicate the production location of the memory device; obtaining field data corresponding to the i+3th byte from the serial presence detection data through the two-wire serial bus protocol, wherein the i+3th byte is used to indicate the production date of the memory device; obtaining field data corresponding to the i+4th byte from the serial presence detection data through the two-wire serial bus protocol, wherein the i+4th byte is used to indicate the number of production cycles of the memory device.

[0010] In an exemplary embodiment, the apparatus is configured to extract N bytes of field data from serial presence detection data corresponding to a memory device in the following manner: obtaining field data corresponding to bytes i+5 to j from the serial presence detection data via a two-wire serial bus protocol using a batch read method, wherein bytes i+5 to j are used to indicate a traditional serial number of the memory device.

[0011] In an exemplary embodiment, the device is used to combine the N bytes of field data to generate a target sequence identifier in the following manner: sequentially splicing the N bytes of field data according to byte positions to generate the target sequence identifier that meets a preset character length; and updating the target sequence identifier to the storage structure of the memory device through a system management basic input and output system protocol.

[0012] In an exemplary embodiment, the device is used to display the target sequence identifier in at least one of the following ways: in response to a target command in the operating system of the server, displaying the target sequence identifier in the operating system; sending the target sequence identifier to a baseboard management controller via an intelligent platform management interface protocol, and displaying the target sequence identifier on the baseboard management controller.

[0013] In an exemplary embodiment, the apparatus is further configured to: during the startup phase of the server, poll the central processing unit number, memory channel number, and memory slot number of the server to determine whether the memory device is in place; when it is detected that the memory device associated with the current slot is not in place, skip the current slot and continue to poll the slot next to the current slot; when it is detected that the memory device associated with the current slot is in place, obtain field data corresponding to the i-th byte to the j-th byte from the serial presence detection data through a two-wire serial bus protocol, wherein the field data corresponding to the i-th byte to the i+1-th byte is used to indicate the manufacturer identification of the memory device, the i+2-th byte is used to indicate the production place of the memory device, and the i+3-th byte is used to indicate the production place of the memory device. Used to indicate the production date of the memory device, the i+4th byte is used to indicate the production cycle number of the memory device, and the i+5th byte to the jth byte are used to indicate the traditional serial number of the memory device; the field data corresponding to the i-th byte to the j-th byte are sequentially spliced ​​according to the byte position to generate the target sequence identifier that meets the preset character length; the target sequence identifier is updated to the storage structure of the memory device through the system management basic input and output system protocol; in response to the target command in the operating system of the server, the target sequence identifier is displayed in the operating system; the target sequence identifier is sent to the baseboard management controller through the intelligent platform management interface protocol, and the target sequence identifier is displayed on the baseboard management controller.

[0014] The present application also provides an electronic device, comprising: a memory for storing a computer program; and a processor for implementing the steps of any of the above-mentioned memory device management methods when executing the computer program.

[0015] The present application also provides a computer-readable storage medium, in which a computer program is stored. When the computer program is executed by a processor, the steps of any of the above-mentioned memory device management methods are implemented.

[0016] The present application also provides a computer program product, including a computer program, which implements the steps of any of the above-mentioned memory device management methods when executed by a processor.

[0017] Through the embodiment of the present application, N bytes of field data are extracted from the serial presence detection data of the server memory device, where the memory device is a memory in an in-place state. These bytes include key fields such as manufacturer ID, production location information, production year, production week and serial number, and are combined according to preset rules to generate a target sequence identifier. The identifier fully reflects the physical factory information of the memory device such as manufacturer, origin, time and unique serial number, achieving the purpose of unified memory sequence identifier display and eliminating the inconsistency problem between the traditional 8-bit identifier and the physical 18-bit identifier, thereby achieving the technical effect of real-time and accurate viewing of complete memory information without physically disassembling the server, improving server operation and maintenance efficiency, reducing hardware management costs, enhancing system reliability and applicability, and being suitable for multi-architecture server environments. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] In order to more clearly illustrate the embodiments of the present application, the following is a brief introduction to the drawings required for use in the embodiments. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0019] Figure 1 A schematic diagram of an application framework of a memory device management method provided in an embodiment of the present application;

[0020] Figure 2 A flowchart of a method for managing a memory device provided in an embodiment of the present application;

[0021] Figure 3 A flowchart of another memory device management method provided in an embodiment of the present application;

[0022] Figure 4 A flowchart of another memory device management method provided in an embodiment of the present application;

[0023] Figure 5 A schematic diagram of the structure of a memory device management apparatus provided in an embodiment of the present application. DETAILED DESCRIPTION

[0024] The following will be combined with the accompanying drawings in the embodiments of this application to clearly and completely describe the technical solutions in the embodiments of this application. Obviously, the embodiments described are only part of the embodiments of this application, not all of them. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of this application.

[0025] It should be noted that, in the description of this application, the terms "comprises," "includes," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or device comprising a series of elements includes not only those elements, but also other elements not explicitly listed, or elements inherent to such process, method, article, or device. The terms "first," "second," etc., in this application are used to distinguish similar objects, and are not used to describe a particular order or sequence.

[0026] In order to enable those skilled in the art to better understand the present application, the present application is further described in detail below with reference to the accompanying drawings and specific implementation methods.

[0027] Abbreviations and key terms are defined below:

[0028] BIOS: Basic Input Output System.

[0029] CPU: Central Processing Unit, referred to as CPU.

[0030] IPMI: Intelligent Platform Management Interface.

[0031] BMC: Baseboard Management Controller.

[0032] I2C: Inter-Integrated Circuit, two-wire serial bus.

[0033] PEI stage: Pre-EFI Initialization, is an important stage in the UEFI (Unified Extensible Firmware Interface) startup process.

[0034] DXE: Driver Execution Environment, is another important stage in the UEFI (Unified Extensible Firmware Interface) startup process.

[0035] DDR5: DDR5 is a computer memory specification.

[0036] SN: Serial Number.

[0037] SMBIOS: System Management BIOS, system management BIOS.

[0038] Type17: Type 17.

[0039] In conjunction with the specific application environment architecture or specific hardware architecture on which the execution of the memory device management method depends, the specific application environment architecture or specific hardware architecture is described herein.

[0040] like Figure 1 As shown, according to Figure 1 The dual-core server architecture shown, the application framework of the embodiment of the present application can be implemented based on the server motherboard hardware system. Figure 1 The physical connections between the CPU (Central Processing Unit), memory channels, DIMMs (Dual In-line Memory Modules), and their SPD (Serial Presence Detect) chips are clearly shown in the framework. This framework supports the execution of the complete technical process:

[0041] S1, data extraction phase. During the server startup process, the BIOS (Basic Input Output System) performs a memory device status check to confirm the attached Figure 1 The memory devices in physical slots DIMM0 through DIMM3 are shown as being actively connected. Based on the preset byte range parameters (for example, i=512, j=520, and N=9), the BIOS accesses the SPD chip via the I2C (Inter-Integrated Circuit) protocol to read the data in bytes 512 to 520 of the specified memory device. This area stores the original information such as the memory vendor ID, manufacturing location, date, and serial number according to JEDEC (Joint Electron Device Engineering Council) standards.

[0042] S2, the identification generation phase. The BIOS will extract the 9-byte raw data and perform format parsing and combination conversion. Specifically: the manufacturer ID field (2-byte ASCII code), production region code (1-byte BCD code), manufacturing year and month (4-byte BCD code) and serial number (2-byte hexadecimal number) are combined in a fixed order to generate an 18-bit target sequence identification. This identification fully retains the factory information of the physical memory, as shown in the attached Figure 1 The SPD chip marked below the DIMM module carries key data.

[0043] S3, identification display stage. The target sequence identification is distributed through a two-level path: first, the BIOS updates the memory device information library based on the SMBIOS (System Management BIOS) protocol and writes the identification into the Type17 structure; at the same time, it transmits data to the BMC (Baseboard Management Controller) through the IPMI (Intelligent Platform Management Interface) protocol. The end user can view it in two ways: execute the dmidecode command in the operating system command line to parse the SMBIOS data, or query the memory properties in the BMC Web interface. Figure 1 As shown in the figure, BIOS communicates with BMC through interfaces such as LPC (Low Pin Count) / SPI (Serial Peripheral Interface) to ensure a smooth display path.

[0044] The embodiment of the present application provides a method for managing a memory device, and combines the execution process of the method for managing a memory device, such as Figure 2 As shown, a detailed description of the memory device management method is given.

[0045] S202, extracting N bytes of field data from the serial presence detection data corresponding to the memory device, where the memory device represents a memory device configured for the server and in an in-place state, and the N bytes represent bytes i to j of the preset serial presence detection data, where i, j, and N are all positive integers;

[0046] S204, combining the N bytes of field data to generate a target sequence identifier, wherein the target sequence identifier is used to identify relevant information of the memory device;

[0047] S206, displaying the target sequence identifier.

[0048] Optionally, in an embodiment of the present application, the above-mentioned memory device may include but is not limited to a memory module that is physically installed in the server and can be detected by the system as being in a working state. It is a core component used for data storage and processing during the operation of the server. Its in-place state means that the memory module has been correctly installed in the memory slot and can be recognized by system components such as BIOS. In the management scenario of memory devices, the in-place state of the memory device is a prerequisite for subsequent information extraction and management. Only by confirming that the memory is in place can its related data be further obtained to achieve effective management. Including but not limited to DDR5 memory modules produced by manufacturers installed in the server, these memory modules will be identified as in place by BIOS by detecting the CPU bit number, memory channel number and memory slot number when the server is powered on, thereby providing memory resource support for the system.

[0049] Optionally, in an embodiment of the present application, the above-mentioned serial presence detection data may include but is not limited to a data set stored in the SPD chip of the memory device, which is used to record detailed parameters and information of the memory device. The content includes memory manufacturer information, production parameters, serial number-related data, etc. Different types of memory (such as DDR3, DDR5) have different serial presence detection data lengths. The length of this data for DDR5 is 1024 bytes. In the management scenario of memory devices, serial presence detection data is a key source for obtaining memory device identification information. By reading specific fields in this data, accurate identification and management of memory devices can be achieved. Including but not limited to the manufacturer ID information, production country information, production date information and default SN data stored in 512 bytes to 520 bytes in the SPD data of DDR5 memory, these data provide the basis for generating a unique identifier for the memory device.

[0050] Optionally, in an embodiment of the present application, the above-mentioned N bytes of field data may include but are not limited to continuous byte segments selected from the serial presence detection data for generating a unique identifier for the memory device. These byte segments correspond to different attribute information of the memory device according to preset rules, and the value of N is determined by the range of attribute information that needs to be covered. In the management scenario of the memory device, the specific N bytes are selected because they together constitute an information set that can fully reflect the identity of the memory device. By extracting these bytes, it can be ensured that the generated identifier contains sufficient distinguishing information. Including but not limited to 9 bytes of data from 512 bytes to 520 bytes in the SPD data of DDR5 memory, of which 512-513 bytes correspond to the manufacturer ID, 514 bytes corresponds to the place of production, 515-516 bytes correspond to the production time, and 517-520 bytes correspond to the traditional SN information. These bytes together constitute the field data required to generate the 18-bit identifier.

[0051] Optionally, in an embodiment of the present application, the target sequence identifier may include, but is not limited to, a string generated by combining N bytes of field data to uniquely identify a memory device. The identifier contains relevant information such as the manufacturer, production location, production date, and serial number of the memory device, and can fully reflect the identity characteristics of the memory device. In the memory device management scenario, the target sequence identifier is the core basis for distinguishing different memory devices. This identifier can be used to track, maintain, and manage memory devices. It includes, but is not limited to, an 18-bit string generated by combining 512-520 bytes of DDR5 memory SPD data, of which the first 4 digits are the manufacturer's DID information, 5-6 digits are the production location information (such as "50" represents China), 7-10 digits are the production time (year and week), and 11-18 digits are traditional SN related information. This identifier is consistent with the physical silk screen identifier of the memory and can be used to accurately identify the memory device.

[0052] By way of example, the above-mentioned S202 can be understood as, during the server startup process, after the BIOS confirms that a memory device is in place by detecting the CPU bit number, memory channel number, and memory slot number during the DXE phase, accessing the memory device's SPD chip via the I2C bus and reading a predetermined number of consecutive N bytes of data, from bytes i to j, from the serial presence detection data stored therein. For example, for a DDR5 memory device in place in a server, after confirming its presence, the BIOS will read the nine bytes of data, from bytes 512 to 520, from the memory's SPD data. These bytes correspond to the manufacturer ID, production location, production time, and traditional SN information, respectively, providing raw data for the subsequent generation of the target sequence identifier.

[0053] Exemplarily, S204 can be understood as combining the N bytes of field data extracted from the serial presence detect data according to the composition rules of the memory device identification information to form a complete string of information that can identify the relevant information of the memory device. For example, for the 9 bytes of data from bytes 512 to 520 extracted from the DDR5 memory SPD data, characters 1-4 are combined to represent the manufacturer's DID information (composed of bytes 512-513), characters 5-6 are the production location information (generated from byte 514), characters 7-10 are the production time (composed of bytes 515-516, where 7-8 are the year and 9-10 are the week number), and characters 11-18 are the traditional SN information (composed of bytes 517-520). This ultimately generates an 18-bit target serial identifier that fully contains relevant information such as the manufacturer, production location, production time, and serial number of the memory device.

[0054] Exemplarily, S206 can be understood as presenting the generated target sequence identifier to the user in an appropriate manner, allowing the user to conveniently obtain and view the identification information of the memory device. For example, the BIOS updates the generated 18-bit target sequence identifier to the Type 17 structure of the memory via the SMBIOS protocol. After the server enters the operating system, the user can view the identifier in the system by executing the dmidecode –t17 command. Simultaneously, the BIOS transmits the identifier to the BMC via the IPMI protocol. The BMC then updates the identifier to the asset information management interface. The user can also view the identifier through the BMC's web interface, thereby enabling convenient access to the memory device's identification information without disassembling the server.

[0055] It should be noted that when extracting N bytes of field data from the serial presence detection data corresponding to the memory device, the memory device can be of different generations, such as DDR4, DDR5, etc., and is not limited to DDR5. The value of N can be set according to actual needs. For example, 10 bytes may be extracted for some memory and 8 bytes may be extracted for others. The relevant information of the target sequence identifier can also be expanded. In addition to manufacturer and production information, it can also include memory capacity, speed, etc. The method of combining field data can also be diverse. It can be spliced ​​in byte order or the order can be adjusted according to preset rules. In addition to operating system commands and BMC interface, the display method can also be pushed through remote management software. This application does not make specific restrictions on this.

[0056] Through the embodiments of the present application, accurate consistency between the target sequence identifier and the physical identifier of the memory device can be achieved, ensuring that the identification information viewed by the user through commands under the system or in the BMC management interface is exactly the same as the physical silk-screen identifier of the memory, avoiding the problem of inconsistent identification in traditional methods; detailed identification information of the memory device can be obtained without physically disassembling the server, reducing the operational complexity during server operation and maintenance, saving time in viewing and confirming memory information, and improving management efficiency; this solution is applicable to any server architecture that supports DDR5 memory, has wide applicability and scalability, can effectively reduce the operation and maintenance costs of the server, while ensuring the accuracy and reliability of memory device management, and providing strong support for the efficient management of server memory devices.

[0057] As an optional solution, extract N bytes of field data from the serial presence detection data corresponding to the memory device, including:

[0058] During the server startup phase, check whether the server's memory slots are equipped with memory devices.

[0059] When it is detected that a memory device is installed in the memory slot, N bytes of field data are extracted from the serial presence detection data corresponding to the memory device.

[0060] Optionally, in an embodiment of the present application, the startup phase of the server may include, but is not limited to, the entire process from when the server is powered on to when it successfully enters the operating system. This phase includes the initialization process of the BIOS (Basic Input Output System), of which the DXE phase (Driver Execution Environment) is a key link. In the memory device management scenario, this phase will complete the detection, identification, and reading of related data of the memory device, laying the foundation for subsequent memory information processing and management. This includes, but is not limited to, after the server is powered on, the BIOS performs a self-test, sequentially going through the PEI phase (Pre-EFI Initialization) and the DXE phase. In the DXE phase, the BIOS will detect the memory slots, memory device status, etc., which is an important part of the server startup phase and ensures that the memory device can be correctly identified and managed by the system.

[0061] Optionally, in embodiments of the present application, the memory slots described above may include, but are not limited to, interface locations on a server motherboard for physically installing memory devices. Each slot has a unique number that distinguishes different memory installation locations. In memory device management scenarios, the slot number can be used to accurately locate the memory device, facilitating system detection of memory presence and subsequent information tracking and management. These include, but are not limited to, slots labeled DIMM0, DIMM1, and DIMM2 on the server motherboard. Each slot corresponds to a specific memory channel. The BIOS determines whether a memory device is installed by identifying these slot numbers, which is the basis for locating devices in memory management.

[0062] For example, during the server startup phase, the aforementioned detection of whether a memory device is installed in a server's memory slot can be understood as follows: after the server is powered on and begins booting, when the BIOS reaches the DXE phase, it will check each memory slot on the server motherboard one by one, detecting whether a memory device is installed in that slot by detecting the physical connection signal and electrical feedback from the memory device. For example, during server startup, the BIOS will sequentially send detection signals to slots such as DIMM0 and DIMM1. If a memory device is installed in a slot, a corresponding response signal will be returned, and the BIOS will then determine that a memory device is installed in that slot.

[0063] For example, when a memory device is detected in a memory slot, the extraction of N bytes of field data from the serial presence detection data corresponding to the memory device can be understood as follows: when the BIOS confirms that a memory device is installed in a memory slot through detection, it will immediately establish communication with the SPD chip of the memory device via a two-wire serial bus protocol, and then read the pre-set N bytes of field data from all data stored in the SPD. This data contains the key identification information of the memory. For example, after detecting that DDR5 memory is installed in the DIMM0 slot, the BIOS reads the 9 bytes of data from bytes 512 to 520 in the memory SPD via the I2C protocol. This data will be used to generate the unique identifier of the memory.

[0064] It should be noted that when detecting whether a memory device is installed in a memory slot during the server startup phase, the startup phase may include different sub-phases such as the PEI phase and the DXE phase, and is not limited to the DXE phase; the detection method may be through electrical signal detection, slot sensor feedback, etc., and different servers may adopt different detection mechanisms; the types of memory devices may also be diverse, including RDIMM, UDIMM, SODIMM, etc. Regardless of the type, as long as it is installed in the slot, it can be detected, and this application does not make specific limitations on this.

[0065] Through the embodiments of the present application, slots with memory devices installed are targetedly detected and data is extracted during the server startup phase, thereby avoiding invalid processing of slots without memory and improving the efficiency of data extraction.

[0066] As an optional solution, extract N bytes of field data from the serial presence detection data corresponding to the memory device, including:

[0067] During the server startup phase, the server's central processing unit number, memory channel number, and memory slot number are polled to determine whether the memory device is in place;

[0068] When it is detected that the memory device associated with the current slot is in place, N bytes of field data are extracted from the serial presence detection data corresponding to the memory device;

[0069] When it is detected that the memory device associated with the current slot is not in place, the current slot is skipped and the next slot after the current slot is polled.

[0070] Optionally, in an embodiment of the present application, the aforementioned central processing unit bit number may include, but is not limited to, numbers used to identify multiple central processing units (CPUs) in a server. In a server with a multi-CPU architecture, different CPUs manage different memory channels and slots. In memory device management scenarios, the central processing unit bit number can be used to determine the CPU to which the memory device belongs, assisting in detecting the memory in-bit status and extracting information. This includes, but is not limited to, numbers such as CPU0 and CPU1 in the server, each corresponding to a physical CPU. When detecting memory, the BIOS will use this bit number to determine the CPU region where the memory is located, ensuring accurate identification of the memory location.

[0071] Optionally, in an embodiment of the present application, the memory channel number may include, but is not limited to, the number of the data transmission channel between the CPU and the memory device in the server. Each CPU is typically equipped with multiple memory channels for parallel data transmission to improve memory bandwidth. In a memory device management scenario, the memory channel number, combined with the central processing unit number and the memory slot number, can uniquely determine the installation location of the memory device and assist in completing memory presence detection. This includes, but is not limited to, the C0, C1, C2, and C3 channels under CPU0. Each channel connects to multiple memory slots. The BIOS identifies the transmission channel to which the memory device belongs through the channel number, which is an important parameter for locating the memory device.

[0072] For example, during the server startup phase, the polling of the server's central processing unit (CPU) number, memory channel number, and memory slot number to determine whether a memory device is present can be understood as the following: during the DXE phase of server startup, the BIOS will sequentially check each CPU number (e.g., CPU0, CPU1), each CPU's memory channel number (e.g., C0, C1), and each channel's memory slot number (e.g., DIMM0, DIMM1), in a specific order. Using the combination of these three, the BIOS determines whether a memory device is present in the corresponding location. For example, the BIOS first checks the DIMM0 slot of CPU0's C0 channel, then checks the DIMM1 slot of CPU0's C0 channel, polling all possible combinations in order to fully determine whether the memory device is present in each location.

[0073] For example, the extraction of N bytes of field data from the serial presence detection data corresponding to the memory device upon detecting the presence of the memory device associated with the current slot can be understood as follows: when the BIOS confirms the presence of a memory device at a specific location by polling the combination of the central processing unit number, memory channel number, and memory slot number, it initiates a data reading process, accesses the SPD chip of the memory device via a two-wire serial bus protocol, and extracts the preset N bytes of field data from it. This data serves as the basis for generating a memory identifier. For example, when polling indicates that a memory device is present in the DIMM0 slot of the C1 channel of CPU0, the BIOS reads the field data from bytes 512 to 520 of the memory SPD via the I2C protocol, preparing for the subsequent generation of the identifier.

[0074] For example, the above-mentioned process of skipping the current slot and continuing to poll the slot immediately following the current slot upon detecting that the memory device associated with the current slot is not present can be understood as follows: during the polling process, if the BIOS finds that a memory device is not present at a location identified by the combination of the CPU number, memory channel number, and memory slot number, it will immediately terminate the polling at that location and proceed to the next location (i.e., the next slot) to ensure the continuity and efficiency of the polling process. For example, if the BIOS detects that there is no memory device in slot DIMM1 of channel C2 of CPU1, the BIOS will not stop there but will immediately begin testing slot DIMM2 of channel C2 of CPU1 to avoid wasting time.

[0075] It should be noted that when polling the server's central processing unit position number, memory channel number and memory slot number, the polling order can be diversified. You can poll all channels and slots of CPU0 first, then poll CPU1, or you can poll according to channel priority; the judgment criteria for determining whether the memory is in place can also be different, such as by detecting the response signal strength of the memory, multiple consecutive detection confirmations, etc.; for servers with multiple CPU architectures, the CPU position number can be identified in the form of numbers, letters or a combination, and the naming rules of the memory channel number and slot number may also vary from manufacturer to manufacturer, and this application does not make specific restrictions on this.

[0076] Through the embodiments of the present application, the memory in-place status is determined by polling the central processing unit bit number, memory channel number and slot number, ensuring comprehensive detection of all slots, accurately identifying the in-place memory to extract data, and improving polling efficiency by skipping empty bits.

[0077] As an optional solution, extract N bytes of field data from the serial presence detection data corresponding to the memory device, including:

[0078] Obtaining field data corresponding to bytes i to i+1 from the serial presence detection data through a two-wire serial bus protocol;

[0079] The field data corresponding to the i-th byte to the i+1-th byte are assembled into double-byte data, wherein the double-byte data is used to indicate the manufacturer identification of the memory device.

[0080] Optionally, in embodiments of the present application, the two-wire serial bus protocol may include, but is not limited to, the I2C (Inter-Integrated Circuit) protocol, a serial bus protocol used for short-distance communication that implements data transmission between devices via two signal lines. In memory device management scenarios, this protocol is used by the BIOS to communicate with the SPD (Serial Presence Detect) chip of a memory device to read the memory information stored therein. This includes, but is not limited to, the BIOS sending a read instruction to the SPD chip of the memory via the I2C bus to obtain data such as manufacturer information and production parameters stored in the SPD. This is a key communication method for extracting memory identification information.

[0081] Optionally, in an embodiment of the present application, the above-mentioned manufacturer identification may include but is not limited to specific data used to distinguish the memory device manufacturer, which is usually composed of specific bytes in the SPD data. Different manufacturers have unique identification codes. In memory device management scenarios, the manufacturer identification can help users identify the production source of the memory, facilitating device traceability and compatibility management. This includes but is not limited to the double-byte data formed by the combination of bytes 512 and 513 in the DDR5 memory SPD data. This data corresponds to the manufacturer's unique identification and is an important indicator of the memory manufacturer's identity.

[0082] Exemplarily, the aforementioned acquisition of the field data corresponding to bytes i through i+1 from the serial presence detect data via a two-wire serial bus protocol can be understood as the BIOS establishing a communication connection with the memory device's SPD chip using the I2C protocol and then sending a read instruction to the SPD chip, specifying to read the contents of bytes i and i+1. Upon receiving the instruction, the SPD chip returns these two bytes of data to the BIOS. These two bytes of data together contain relevant information about the memory manufacturer. For example, when i is 512, the BIOS reads bytes 512 and 513 of the SPD data via the I2C protocol. These two bytes of field data form the basis of the manufacturer identification.

[0083] Exemplarily, the above-mentioned assembly of the field data corresponding to bytes i through i+1 into double-byte data, where the double-byte data is used to indicate the manufacturer identification of the memory device, can be understood as the BIOS combining the field data of bytes i and i+1 read from the SPD data in a preset order (e.g., byte i first, then byte i+1) to form a double-byte data. This double-byte data can uniquely correspond to the manufacturer of the memory device, thereby clarifying the production source of the memory. For example, the double-byte data formed by combining the field data of bytes 512 and 513 in the DDR5 memory SPD corresponds to the identification of a certain manufacturer, i.e., the manufacturer identification of the memory.

[0084] It should be noted that when obtaining the i-th byte to the i+1-th byte through the two-wire serial bus protocol, the communication rate of the protocol can be adjusted according to the memory type. For example, a higher rate is used in some scenarios to improve reading efficiency, and a lower rate is used in some scenarios to ensure stability; the encoding rules of the manufacturer's identification can be diverse, which can be pure digital encoding or a combination of numbers and letters. The encoding length is not limited to two bytes, such as three bytes; the byte range is not fixed. For the memory of different manufacturers, the bytes corresponding to the manufacturer's identification may be the 510th-511th bytes, or the 514th-515th bytes. This application does not make specific limitations on this.

[0085] Through the embodiment of the present application, the two-byte data of the manufacturer identification is obtained and assembled with the help of the two-wire serial bus protocol, providing an accurate manufacturer information basis for the target sequence identification and ensuring the traceability of the identification.

[0086] As an optional solution, extracting N bytes of field data from the serial presence detection data corresponding to the memory device includes at least one of the following:

[0087] Obtaining field data corresponding to the (i+2)th byte from the serial presence detection data using a two-wire serial bus protocol, wherein the (i+2)th byte is used to indicate a manufacturing location of the memory device;

[0088] Obtaining field data corresponding to the (i+3)th byte from the serial presence detection data using a two-wire serial bus protocol, wherein the (i+3)th byte is used to indicate a production date of the memory device;

[0089] Field data corresponding to the i+4th byte is obtained from the serial presence detection data through a two-wire serial bus protocol, wherein the i+4th byte is used to indicate the number of production cycles of the memory device.

[0090] Optionally, in embodiments of the present application, the aforementioned production location may include, but is not limited to, information about the memory device's production location. This information is typically stored in a specific byte of the SPD data in a specifically encoded format. In memory device management scenarios, this production location information can be used to trace the memory's production region, assisting with supply chain management and quality control. This includes, but is not limited to, byte 514 of the SPD data, which can be used to clearly identify the memory's production location, providing more dimensional information for memory management.

[0091] Exemplarily, the above-mentioned acquisition of the field data corresponding to the i+2th byte from the serial presence detect data via a two-wire serial bus protocol, where the i+2th byte is used to indicate the manufacturing location of the memory device, can be understood as the BIOS communicating with the memory's SPD chip via the I2C protocol, sending a command to read the i+2th byte, and the SPD chip returning the data in that byte to the BIOS. The data in that byte is in a specific encoding format, with each encoding corresponding to a specific country or region of manufacture, thereby identifying the memory's manufacturing location. For example, when i is 512, i+2 is 514, and the field data in byte 514 of the SPD data is read. If this data is a specific value, it indicates that the memory was manufactured in a certain country.

[0092] Optionally, in embodiments of the present application, the aforementioned production date may include, but is not limited to, information identifying the year of production of the memory device, stored in a specific byte of the SPD data. In memory device management scenarios, the production date, combined with the number of production cycles, can determine the production time of the memory, facilitating device lifecycle management and fault tracing. This includes, but is not limited to, the data in byte 515 of the SPD data. The value of this byte corresponds to the year of memory production and is an important component of memory production time information, helping users understand the production year of the memory.

[0093] Exemplarily, the above-described acquisition of the field data corresponding to the i+3th byte from the serial presence detect data via the two-wire serial bus protocol, where the i+3th byte indicates the manufacturing date of the memory device, can be understood as the BIOS sending a command to the memory's SPD chip via the I2C protocol to read the i+3th byte. The SPD chip responds to the command and returns the data in that byte. This data represents the year of the memory device's manufacture and is important information for tracing the memory's manufacturing date. For example, if i is 512, i+3 is 515. The value corresponding to the field data in byte 515 of the SPD data indicates the manufacturing year of the memory device, such as year xx.

[0094] Optionally, in an embodiment of the present application, the aforementioned production cycle number may include, but is not limited to, information identifying the week in which the memory device was produced, stored in a specific byte of the SPD data. In memory device management scenarios, the production cycle number, combined with the production date, can be accurately tracked down to the specific week of memory production, providing a more detailed time basis for device traceability and quality analysis. This includes, but is not limited to, byte 516 of the SPD data, which corresponds to the week of the year in which the memory device was produced, such as week 10, week 25, etc., making the memory production time more specific.

[0095] Exemplarily, the above-mentioned acquisition of the field data corresponding to the i+4th byte from the serial presence detect data via the two-wire serial bus protocol, where the i+4th byte is used to indicate the production cycle number of the memory device, can be understood as the BIOS interacting with the memory's SPD chip via the I2C protocol, sending a command to read the i+4th byte, and the SPD chip returning the data in that byte. This data corresponds to the week of the memory device's production year, used to accurately identify the production time. For example, if i is 512, i+4 is 516. If the data in the 516th byte of the SPD data is 10, it means that the memory device was produced in the 10th week of that year.

[0096] It should be noted that when extracting the production location, production date, and production cycle bytes, the encoding method of the production location may include digital coding (such as 01 represents area A, 02 represents area B), letter coding (such as AB represents area C), or mixed coding; the granularity of the production date can be more detailed, and in addition to the year, it can also include the month and even the day, and the corresponding bytes may require multiple, such as the i+3th byte represents the year, and the i+4th byte represents the month; the expression method of the production cycle number can also be different, which can be either the number of weeks or the number of days. The coding range can be adjusted according to the actual production cycle, and this application does not make specific restrictions on this.

[0097] Through the embodiments of the present application, the production place, production date and production cycle number are extracted, which enriches the information dimension of the target sequence identifier and facilitates tracing the production background of the memory.

[0098] As an optional solution, extract N bytes of field data from the serial presence detection data corresponding to the memory device, including:

[0099] Field data corresponding to bytes i+5 to j are obtained from serial presence detection data using a batch read method through a two-wire serial bus protocol, where bytes i+5 to j are used to indicate a traditional serial number of a memory device.

[0100] Optionally, in embodiments of the present application, the aforementioned traditional serial number may include, but is not limited to, the serial number information of the memory device at the time of shipment, typically as 8-bit characters, stored in a specific byte segment of the SPD data. In memory device management scenarios, the traditional serial number is part of the memory individual identifier and, when combined with other information, forms a complete unique memory identifier used to distinguish different memory devices. This includes, but is not limited to, data from bytes 517 to 520 in the DDR5 memory SPD data, obtained by reading 2 bytes twice to form an 8-bit traditional serial number, which is an important identifier of the memory individual.

[0101] Exemplarily, the aforementioned batch read method for obtaining the field data corresponding to bytes i+5 through j from the serial presence detect data via a two-wire serial bus protocol can be understood as the BIOS sending a 2-byte read instruction each time it communicates with the memory's SPD chip via the I2C protocol, reading all data from bytes i+5 through j in multiple passes. The combined information formed by these bytes is the traditional serial number of the memory device, used to identify individual memory devices. For example, if i is 512 and j is 520, i+5 is 517. The BIOS then reads bytes 517-518 and 519-520 in two passes. These combined data form an 8-bit traditional serial number used to distinguish different memory devices.

[0102] It should be noted that when using batch reading to obtain the i+5th byte to the jth byte, the size of the batch reading can be flexibly set, such as reading 3 bytes or 4 bytes each time, etc., and is not necessarily limited to 2 bytes; the length of the traditional serial number can be adjusted according to manufacturer requirements, such as 6 bits, 10 bits, etc., and the corresponding byte range will also change accordingly, such as the i+5th to i+8th bytes (4 bytes corresponding to an 8-bit serial number), the i+5th to i+9th bytes (5 bytes corresponding to a 10-bit serial number); the verification mechanism during the reading process can also be diverse, such as adding check bits, repeated reading and comparison, etc., and this application does not make specific limitations on this.

[0103] Through the embodiments of the present application, a batch reading method is adopted to obtain the traditional serial number, thereby ensuring the integrity and accuracy of the serial number part in the identification.

[0104] As an optional solution, N bytes of field data are combined to generate a target sequence identifier, including:

[0105] Concatenate the N bytes of field data in sequence according to the byte position to generate a target sequence identifier that meets the preset character length;

[0106] The target sequence identifier is updated to the storage structure of the memory device through the system management basic input and output system protocol.

[0107] Optionally, in an embodiment of the present application, the above-mentioned system management basic input and output system protocol may include but is not limited to a standard protocol for standardizing the storage and access of server hardware information, namely SMBIOS (System Management BIOS), which defines the description format and interface of system hardware components, so that the operating system and management tools can obtain unified hardware information. In the management scenario of memory devices, this protocol is an important carrier for transmitting memory identification information. Through it, the target serial identifier of the memory can be stored in the system in a standardized manner to ensure that different tools and interfaces can read it accurately. Including but not limited to the Type17 structure defined in the SMBIOS protocol, it is specifically used to store detailed information of memory devices, such as serial number, manufacturer, capacity, etc. After the BIOS generates the 18-bit identifier of the memory, it will write the identifier into the corresponding field of the Type17 structure in accordance with the specification of the protocol for access by the system and management tools. The above-mentioned preset character length can be a specified length, such as 18 bits.

[0108] Optionally, in an embodiment of the present application, the above-mentioned storage structure may include but is not limited to a data structure defined in the SMBIOS protocol for storing specific hardware information. The storage structure for memory devices is Type 17, which contains multiple fields corresponding to the serial number, manufacturer, type, capacity and other information of the memory. In the management scenario of memory devices, the structure is a storage container for memory identification information to ensure that the identification information is correctly identified and read by the system. Including but not limited to the field for storing the serial number (SN) in the Type 17 structure, when the BIOS generates an 18-bit target serial identifier, the identifier will be written into the field, so that when querying through system commands or management tools, the accurate memory identifier can be obtained from the structure.

[0109] Exemplarily, the aforementioned concatenation of N bytes of field data in sequence according to byte position to generate a target sequence identifier that meets a preset character length can be understood as sequentially combining the N bytes (e.g., 9 bytes) extracted from the SPD data in their original order in the SPD, converting each byte into a corresponding character, and ultimately forming a string of a preset length (e.g., 18 bits) that contains complete information such as the memory manufacturer, production location, production date, and serial number. For example, bytes 512-520 extracted from the DDR5 memory SPD, a total of 9 bytes, are concatenated in the order of bytes 512-513 (manufacturer ID), 514 (production location), 515-516 (production date), and 517-520 (traditional serial number), with each byte converted into 2 characters, ultimately forming an 18-bit target sequence identifier that is completely consistent with the memory's SN.

[0110] For example, updating the target sequence identifier to the memory device's storage structure via the System Management Basic Input / Output System (SMBIOS) protocol can be understood as the BIOS writing the generated target sequence identifier to the corresponding field of the memory device's storage structure (i.e., Type 17) as defined by the SMBIOS protocol, in accordance with the protocol specifications. This allows the identifier to be stored in a standardized manner by the system for subsequent querying. For example, after generating the 18-bit memory identifier, the BIOS locates the "Serial Number" field of the Type 17 structure in the SMBIOS and writes the 18-bit identifier to that field, ensuring that the operating system and management tools can read the identifier when querying it through the SMBIOS interface.

[0111] It should be noted that when N bytes of field data are sequentially spliced ​​together to generate a target sequence identifier, the splicing order can be adjusted according to the importance of the information, such as displaying the production time first and then the manufacturer information, rather than a fixed manufacturer in front; the preset character length can be set according to the actual scenario, such as 20 bits, 16 bits, etc., as long as it can uniquely identify the memory; the storage structure is not limited to SMBIOS Type17, but can also be other custom structures, as long as it can be recognized by the system and management tools. This application does not make specific limitations on this.

[0112] Through the embodiments of the present application, field data is spliced ​​in sequence and updated to a storage structure through the system management basic input and output system protocol, ensuring that the target sequence identifier format is standardized and can be correctly recognized by the system.

[0113] As an optional solution, displaying the target sequence identifier includes at least one of the following:

[0114] In response to a target command in an operating system of the server, displaying a target sequence identifier in the operating system;

[0115] The target sequence identifier is sent to the baseboard management controller through the intelligent platform management interface protocol, and the target sequence identifier is displayed on the baseboard management controller.

[0116] Optionally, in an embodiment of the present application, the target command in the operating system of the above-mentioned server may include but is not limited to a specific instruction in the operating system for querying SMBIOS information, through which the hardware information stored in the SMBIOS structure, especially the detailed identification of the memory device, can be extracted from the system. In the memory device management scenario, this command provides users with a convenient way to obtain memory identification directly in the operating system without relying on additional tools or physical operations. Including but not limited to the "dmidecode-t17" command in the Linux operating system, after the user executes this command in the terminal of the operating system, the system will parse the information of the Type17 structure in the SMBIOS, which includes the 18-bit memory target sequence identifier written by the BIOS for the user to view.

[0117] Optionally, in an embodiment of the present application, the above-mentioned intelligent platform management interface protocol may include but is not limited to a standardized protocol for server hardware management, namely IPMI (Intelligent Platform Management Interface), which defines the communication specifications between hardware components such as BIOS and baseboard management controller (BMC), and supports functions such as hardware status monitoring and information transmission. In the management scenario of memory devices, this protocol is the key channel for BIOS to transmit memory identification information to BMC, ensuring that BMC can obtain and display the target sequence identifier of the memory in a timely manner. Including but not limited to BIOS encapsulating the generated 18-bit memory identifier into a specific data packet through the message format of the IPMI protocol and sending it to the BMC. After receiving the data packet, the BMC parses the data packet according to the protocol specification, extracts the memory identifier and stores it.

[0118] Optionally, in an embodiment of the present application, the baseboard management controller may include but is not limited to a dedicated hardware component in the server, namely, a BMC (Baseboard Management Controller), which runs independently of the server's CPU and operating system, is responsible for monitoring and managing the server's hardware status, such as temperature, voltage, hardware identification, etc., and provides a management interface for users through a web interface or dedicated tools. In the management scenario of memory devices, the controller is an important carrier for displaying memory target sequence identification. After receiving the identification information transmitted by the BIOS, it will display it in its own management interface for users to view remotely. Including but not limited to the BMC's asset information management interface, after receiving the 18-bit memory identification sent by the BIOS through the IPMI protocol, the identification will be displayed in the memory information area of ​​the interface. Users can access the BMC interface through a browser to view it without logging into the operating system.

[0119] Exemplarily, the above-mentioned display of the target serial identifier in the operating system in response to the target command in the server's operating system can be understood as when a user executes a specific query command in the server's operating system, the system will parse the structure storing memory information in the SMBIOS, extract the target serial identifier, and display it in text form in the terminal or interface for direct viewing by the user. For example, if a user enters the "dmidecode –t17" command in a terminal of the Linux operating system, the system will access the Type17 structure of the SMBIOS, read the 18-bit memory identifier stored therein, and display "SerialNumber: XXXX50XXXXXXXXX" (where XXXX represents specific characters) in the terminal, which is consistent with the physical identifier of the memory.

[0120] For example, the aforementioned sending of the target sequence identifier to the baseboard management controller via the Intelligent Platform Management Interface protocol and the display of the target sequence identifier on the baseboard management controller can be understood as consistent with the aforementioned description, namely, the memory identifier is transmitted between the BIOS and the BMC via the IPMI protocol, and the BMC displays it upon receipt. For example, during server startup, the BIOS generates the memory identifier and immediately sends it to the BMC via the IPMI protocol. The BMC then associates and stores this identifier with the memory slot information. When a user views "Slot 0 Memory Information," the 18-bit identifier is displayed simultaneously, establishing a correspondence between the identifier and the physical location.

[0121] It should be noted that when displaying the target sequence identifier, the target command in the server operating system may vary depending on the type of operating system, such as querying through special tool commands in Windows systems and querying through different parameters of dmidecode in Linux systems; the display method of the baseboard management controller can also be diverse, in addition to the web interface, it can also be through the BMC's command line interface, local display screen, etc.; in addition, the target sequence identifier can also be sent to the management personnel through email notification, SMS push, etc., and this application does not make specific restrictions on this.

[0122] Through the embodiments of the present application, the operating system commands and the baseboard management controller display logo allow users to conveniently view it in the system or management interface without disassembling the server, thereby reducing the complexity of operation and maintenance.

[0123] As an optional solution, the above method further includes:

[0124] During the server startup phase, the server's central processing unit number, memory channel number, and memory slot number are polled to determine whether the memory device is in place;

[0125] When it is detected that the memory device associated with the current slot is not in place, the current slot is skipped and the next slot after the current slot is polled.

[0126] When it is detected that the memory device associated with the current slot is present, field data corresponding to bytes i to j are obtained from the serial presence detection data through a two-wire serial bus protocol, wherein the field data corresponding to bytes i to (i+1) are used to indicate a manufacturer identifier of the memory device, the (i+2) byte is used to indicate a production location of the memory device, the (i+3) byte is used to indicate a production date of the memory device, the (i+4) byte is used to indicate a number of production cycles of the memory device, and the (i+5) to (j) byte are used to indicate a traditional serial number of the memory device;

[0127] Concatenate the field data corresponding to the i-th byte to the j-th byte in sequence according to the byte position to generate a target sequence identifier that meets the preset character length;

[0128] Updating the target sequence identifier to the storage structure of the memory device through the system management basic input and output system protocol;

[0129] In response to a target command in an operating system of the server, displaying a target sequence identifier in the operating system;

[0130] The target sequence identifier is sent to the baseboard management controller through the intelligent platform management interface protocol, and the target sequence identifier is displayed on the baseboard management controller.

[0131] In an exemplary embodiment, the memory management process during the startup phase of a server equipped with DDR5 memory is taken as an example, including but not limited to the following process:

[0132] During the server startup phase, S1 polls the server's CPU number, memory channel number, and memory slot number to determine if the memory device is present. The polling order can be flexibly adjusted: CPU number (e.g., CPU0, CPU1, or labeled A, B) → memory channel number (e.g., C0, C1, or CH0, CH1) → memory slot number (e.g., DIMM0, DIMM1, or SLOT0, SLOT1), or memory channel number → CPU number → memory slot number. Memory presence is determined by combining multiple factors, such as the SPD chip's response signal and the memory power supply status, to avoid misjudgment based on a single signal.

[0133] In step S2, if the memory device associated with the current slot is detected to be absent, the current slot is skipped and the next slot is polled. This includes, but is not limited to, an unresponsive SPD chip, repeated read failures, and abnormal memory power supply. Polling of the next slot can proceed sequentially, sequentially, to adjacent slots within the same channel, or across channels to poll other slots under the same CPU, depending on the server hardware layout.

[0134] S3, when the memory device associated with the current slot is detected to be present, obtains the field data corresponding to bytes i through j from the serial presence detection data via the two-wire serial bus protocol. Bytes i through i+1 indicate the manufacturer identifier, which may be a manufacturer-specific code or a universal identifier; byte i+2 indicates the location of manufacture, which may be a combination of letters or numbers corresponding to different regions; byte i+3 indicates the date of manufacture, which may include the year or a year-month combination; byte i+4 indicates the number of production cycles, which may be weeks or days; and bytes i+5 through j indicate a traditional serial number, the length of which can be adjusted based on manufacturer requirements. The transmission rate of the two-wire serial bus protocol can be dynamically adjusted based on server load, reducing the rate during high loads to ensure data stability.

[0135] S4: Concatenate the field data corresponding to bytes i through j sequentially according to byte position to generate a target sequence identifier that meets the preset character length. This concatenation can be performed strictly in byte order, or the positions of some fields can be adjusted based on information importance, such as prepending the production time field. The preset character length can be set based on the dimensions of the information contained, and can be a fixed length covering the basic information or dynamically increased with expanded information.

[0136] S5: Update the target sequence identifier to the storage structure of the memory device through the system management basic input and output system protocol. The storage structure can be of Type 17 type defined by the protocol. A verification mechanism can be added during the update process to ensure that the data is written accurately before completing the update to avoid structural information anomalies.

[0137] S6. In response to a target command in the server's operating system, the target sequence identifier is displayed in the operating system. The target command can be a query instruction provided by the system or a command of a dedicated management tool developed by the manufacturer. The display format can include a terminal text list, table, etc., to facilitate users to quickly locate the required information.

[0138] S7: The target sequence identifier is sent to the baseboard management controller via the intelligent platform management interface protocol, and the target sequence identifier is displayed on the baseboard management controller. The sending process can be synchronized in real time or pushed on a scheduled basis. The baseboard management controller can display the target sequence identifier on a web management page or a local display panel, allowing users to view the target sequence identifier remotely or locally.

[0139] Through the embodiments of the present application, the on-site detection, information extraction, identification generation and multi-channel display of memory devices can be automatically completed during the server startup phase, and the physical identification of the memory device and the system and management end identification can be accurately unified. Users can easily obtain complete memory identification information without disassembling the server, which greatly reduces the operational complexity of memory management, improves management efficiency and accuracy, and is adaptable to a variety of server architectures and DDR5 memory types, with strong practicality and scalability.

[0140] The following is a further explanation of this application with reference to specific examples:

[0141] In the server world, servers of any architecture require several basic components, such as a CPU, memory, BIOS chip, BMC chip, RAID card, storage hard drives, and network interface cards. These are the core components of a server. Traditional servers install the operating system by mounting an operating system image over the network, using a storage device, or a virtual optical drive. In some server systems, however, customers deploy a real-time operating system over the network and install it directly into the memory address space, ensuring normal system operation without the need for storage media. This solution requires a system installation each time, but offers significant cost advantages. Regardless of server architecture, system memory, specifically DDR memory devices, is required. Some early devices used DDR3 memory, while DDR5 is currently the mainstream. Regardless of manufacturer, memory devices require a unique SN, or memory identification number. Traditional memory device SNs are 8-bit values ​​that do not identify the manufacturer or production date, and are different in size from the manufacturer's factory identification SN.

[0142] like Figure 3 As shown, the detailed implementation steps of this embodiment are as follows:

[0143] S1: The server starts up. During the DXE phase of server startup, the BIOS determines whether the memory is in place based on the server's CPU bit number, memory channel number, and memory slot number. If not, the BIOS skips and proceeds to the next memory slot information check. If the memory is in place, the BIOS prepares to read the memory SPD information.

[0144] S2: When the memory is in place, the BIOS reads the 512-byte and 513-byte data of the SPD of the DDR5 memory through the I2C bus. The 512-byte and 513-byte data constitute the DDR5 memory manufacturer ID information.

[0145] S3, after reading the DDR5 memory manufacturer ID, read the 514 bytes of the DDR5 memory SPD data to obtain the memory production country information;

[0146] S4, continue to read 515 bytes of the DDR5 memory SPD data to obtain the production date information, i.e., the year, and read 516 bytes of the DDR5 SPD data to obtain the production week, etc., which are combined into the production time information;

[0147] S5, finally read the default SN data of DDR5, that is, 517 bytes to 520 bytes of SPD data, reading 2 bytes of data at a time for a total of 2 times;

[0148] S6, the data obtained from 512 bytes to 520 bytes of SPD is progressively combined into 18 characters in length, i.e. 9 bytes, and updated to the SN data structure in Type 17 of the memory through the SMBIOS protocol. At the same time, this SN data is transmitted to the BMC end through the IPMI protocol;

[0149] The above steps can accurately obtain and transmit the 18-bit SN data of the memory, which is convenient for customers to view in real time under the system or through the BMC. It ensures the consistency of the 18-bit information of the server's physical DDR5 memory and prevents memory data errors. The interaction process between the server, BIOS and BMC is as follows: Figure 4 shown.

[0150] This application relates to a method for generating a DDR5 memory identification code. To solve the problem that the identification SN information of DD5 memory at the factory is inconsistent with the traditional SN information, the BIOS reads the CPU bit number, memory channel number, and memory slot number through I2C in the DXE stage to confirm whether the memory is in place. If not, the next memory slot will continue to be polled until the memory polling is completed. If in place, the BIOS reads the SPD data of the DDR5 memory through I2C and reads it in sequence, starting from byte 512 to byte 520 of the SPD, and obtains the memory manufacturer ID information, memory channel number, and memory slot number according to the format of the DDR5 memory identification SN. The production address information, memory production year, memory production cycle number and 8-bit traditional SN data are combined to form 18-bit data, which is updated to the Type17 information of the DDR5 memory through the SMBIOS protocol. At the same time, the BIOS is transmitted to the BMC end through the IPMI protocol. The BMC end obtains the 18-bit SN data of the DDR5 and updates it to the asset information management interface of the BMC. At the same time, after the server starts and enters the operating system, the SN information of each memory can be viewed through commands under the system without disassembling the machine. This embodiment can solve the technical problem of not being able to view the 18-bit SN value of the DDR5 memory identifier.

[0151] This application is convenient, fast and accurate. It solves the technical problem that DDR5's 18-bit memory cannot be accurately viewed. It is not affected by the CPU architecture and can be applied to servers with any architecture that supports DDR5 memory. It has extremely high practicality and applicability. At the same time, it has extremely high scalability and replicability, reducing the server's operation and maintenance costs and increasing the efficiency of viewing the server's DDR5 memory configuration information.

[0152] Through the description of the above implementation methods, those skilled in the art can clearly understand that the method according to the above embodiment can be implemented by means of software plus the necessary general hardware platform, and of course it can also be implemented by hardware, but in many cases the former is a better implementation method.

[0153] The embodiment of the present application also provides a memory device management device, such as Figure 5 As shown, the device includes:

[0154] An extraction module 502 is configured to extract N bytes of field data from the serial presence detection data corresponding to the memory device, where the memory device represents a memory device configured for the server and in an in-place state, and the N bytes represent bytes i to j of the preset serial presence detection data, where i, j, and N are all positive integers;

[0155] A combining module 504 is configured to combine N bytes of field data to generate a target sequence identifier, wherein the target sequence identifier is used to identify relevant information of a memory device;

[0156] The display module 506 is configured to display the target sequence identifier.

[0157] As an optional solution, the apparatus is used to extract N bytes of field data from the serial presence detection data corresponding to the memory device in the following manner:

[0158] During the server startup phase, check whether the server's memory slots are equipped with memory devices.

[0159] When it is detected that a memory device is installed in the memory slot, N bytes of field data are extracted from the serial presence detection data corresponding to the memory device.

[0160] As an optional solution, the apparatus is used to extract N bytes of field data from the serial presence detection data corresponding to the memory device in the following manner:

[0161] During the server startup phase, the server's central processing unit number, memory channel number, and memory slot number are polled to determine whether the memory device is in place;

[0162] When it is detected that the memory device associated with the current slot is in place, N bytes of field data are extracted from the serial presence detection data corresponding to the memory device;

[0163] When it is detected that the memory device associated with the current slot is not in place, the current slot is skipped and the next slot after the current slot is polled.

[0164] As an optional solution, the apparatus is used to extract N bytes of field data from the serial presence detection data corresponding to the memory device in the following manner:

[0165] Obtaining field data corresponding to bytes i to i+1 from the serial presence detection data through a two-wire serial bus protocol;

[0166] The field data corresponding to the i-th byte to the i+1-th byte are assembled into double-byte data, wherein the double-byte data is used to indicate the manufacturer identification of the memory device.

[0167] As an optional solution, the apparatus is configured to extract N bytes of field data from the serial presence detect data corresponding to the memory device by at least one of the following methods:

[0168] Obtaining field data corresponding to the (i+2)th byte from the serial presence detection data using a two-wire serial bus protocol, wherein the (i+2)th byte is used to indicate a manufacturing location of the memory device;

[0169] Obtaining field data corresponding to the (i+3)th byte from the serial presence detection data using a two-wire serial bus protocol, wherein the (i+3)th byte is used to indicate a production date of the memory device;

[0170] Field data corresponding to the i+4th byte is obtained from the serial presence detection data through a two-wire serial bus protocol, wherein the i+4th byte is used to indicate the number of production cycles of the memory device.

[0171] As an optional solution, the apparatus is used to extract N bytes of field data from the serial presence detection data corresponding to the memory device in the following manner:

[0172] Field data corresponding to bytes i+5 to j are obtained from serial presence detection data using a batch read method through a two-wire serial bus protocol, where bytes i+5 to j are used to indicate a traditional serial number of a memory device.

[0173] As an optional solution, the above device is used to generate a target sequence identifier by combining N bytes of field data in the following manner:

[0174] Concatenate the N bytes of field data in sequence according to the byte position to generate a target sequence identifier that meets the preset character length;

[0175] The target sequence identifier is updated to the storage structure of the memory device through the system management basic input and output system protocol.

[0176] As an optional solution, the above device is used to display the target sequence identifier in at least one of the following ways:

[0177] In response to a target command in an operating system of the server, displaying a target sequence identifier in the operating system;

[0178] The target sequence identifier is sent to the baseboard management controller through the intelligent platform management interface protocol, and the target sequence identifier is displayed on the baseboard management controller.

[0179] As an optional solution, the above device is also used for:

[0180] During the server startup phase, the server's central processing unit number, memory channel number, and memory slot number are polled to determine whether the memory device is in place;

[0181] When it is detected that the memory device associated with the current slot is not in place, the current slot is skipped and the next slot after the current slot is polled.

[0182] When it is detected that the memory device associated with the current slot is present, field data corresponding to bytes i to j are obtained from the serial presence detection data through a two-wire serial bus protocol, wherein the field data corresponding to bytes i to (i+1) are used to indicate a manufacturer identifier of the memory device, the (i+2) byte is used to indicate a production location of the memory device, the (i+3) byte is used to indicate a production date of the memory device, the (i+4) byte is used to indicate a number of production cycles of the memory device, and the (i+5) to (j) byte are used to indicate a traditional serial number of the memory device;

[0183] Concatenate the field data corresponding to the i-th byte to the j-th byte in sequence according to the byte position to generate a target sequence identifier that meets the preset character length;

[0184] Updating the target sequence identifier to the storage structure of the memory device through the system management basic input and output system protocol;

[0185] In response to a target command in an operating system of the server, displaying a target sequence identifier in the operating system;

[0186] The target sequence identifier is sent to the baseboard management controller through the intelligent platform management interface protocol, and the target sequence identifier is displayed on the baseboard management controller.

[0187] It should be noted that, for the description of the features in the embodiment corresponding to the apparatus for managing a memory device, reference can be made to the relevant description of the embodiment corresponding to the method for managing a memory device, which will not be repeated here.

[0188] An embodiment of the present application further provides an electronic device, comprising a memory and a processor, wherein the memory stores a computer program, and the processor is configured to run the computer program to execute the steps of any of the above-mentioned memory device management method embodiments.

[0189] An embodiment of the present application further provides a computer-readable storage medium, in which a computer program is stored, wherein the computer program is configured to execute the steps of any of the above-mentioned memory device management method embodiments when running.

[0190] In an exemplary embodiment, the computer-readable storage medium may include, but is not limited to, various media that can store computer programs, such as a USB flash drive, a read-only memory (ROM), a random access memory (RAM), a mobile hard disk, a magnetic disk, or an optical disk.

[0191] An embodiment of the present application further provides a computer program product, which includes a computer program. When the computer program is executed by a processor, the steps of any of the above-mentioned memory device management method embodiments are implemented.

[0192] An embodiment of the present application also provides another computer program product, including a non-volatile computer-readable storage medium, the non-volatile computer-readable storage medium storing a computer program, and when the computer program is executed by a processor, implementing the steps of any of the above-mentioned memory device management method embodiments.

[0193] Professionals may further appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of the two. In order to clearly illustrate the interchangeability of hardware and software, the above description has generally described the components and steps of each example according to their functions. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professionals and technicians may use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0194] The above is a detailed introduction to a memory device management method and apparatus provided by the present application. This article uses specific examples to illustrate the principles and implementation methods of the present application. The description of the above embodiments is only applicable to help understand the method and core ideas of the present application. It should be pointed out that for ordinary technicians in this technical field, without departing from the principles of the present application, several improvements and modifications can be made to the present application, and these improvements and modifications also fall within the scope of protection of the claims of the present application.

Claims

1. A method for managing a memory device, characterized in that: include: Extracting N bytes of field data from serial presence detection data corresponding to a memory device, wherein the memory device represents a memory device configured for the server and in an in-place state, and the N bytes represent the i-th byte to the j-th byte of the preset serial presence detection data, where i, j, and N are all positive integers; Combining the N bytes of field data to generate a target sequence identifier, wherein the target sequence identifier is used to identify relevant information of the memory device; The target sequence identifier is displayed.

2. The memory device management method according to claim 1, wherein: The step of extracting N bytes of field data from the serial presence detection data corresponding to the memory device includes: During the startup phase of the server, detecting whether the memory device is installed in the memory slot of the server; When it is detected that the memory slot is installed with the memory device, N bytes of field data are extracted from the serial presence detection data corresponding to the memory device.

3. The memory device management method according to claim 2, wherein: The step of extracting N bytes of field data from the serial presence detection data corresponding to the memory device includes: During the startup phase of the server, polling the central processing unit number, memory channel number, and memory slot number of the server to determine whether the memory device is in place; When it is detected that the memory device associated with the current slot is in place, extracting N bytes of field data from the serial presence detection data corresponding to the memory device; When it is detected that the memory device associated with the current slot is not in place, the current slot is skipped and the next slot of the current slot is continuously polled.

4. The memory device management method according to claim 1, wherein: The step of extracting N bytes of field data from the serial presence detection data corresponding to the memory device includes: Obtaining field data corresponding to the i-th byte to the i+1-th byte from the serial presence detection data through a two-wire serial bus protocol; The field data corresponding to the i-th byte to the i+1-th byte are assembled into double-byte data, wherein the double-byte data is used to indicate the manufacturer identification of the memory device.

5. The memory device management method according to claim 1, wherein: Extracting N bytes of field data from the serial presence detection data corresponding to the memory device includes at least one of the following: Obtaining field data corresponding to the (i+2)th byte from the serial presence detection data using a two-wire serial bus protocol, wherein the (i+2)th byte is used to indicate a production location of the memory device; Obtaining field data corresponding to the (i+3)th byte from the serial presence detection data using the two-wire serial bus protocol, wherein the (i+3)th byte is used to indicate a production date of the memory device; The field data corresponding to the (i+4)th byte is obtained from the serial presence detection data through the two-wire serial bus protocol, wherein the (i+4)th byte is used to indicate the number of production cycles of the memory device.

6. The memory device management method according to claim 1, wherein: The step of extracting N bytes of field data from the serial presence detection data corresponding to the memory device includes: Field data corresponding to bytes i+5 to j are obtained from the serial presence detection data using a batch read method through a two-wire serial bus protocol, wherein bytes i+5 to j are used to indicate a traditional serial number of the memory device.

7. The memory device management method according to any one of claims 1 to 6, characterized in that: The combining the N bytes of field data to generate a target sequence identifier includes: Sequentially concatenate the N bytes of field data according to byte positions to generate the target sequence identifier that meets a preset character length; The target sequence identifier is updated to the storage structure of the memory device through a system management basic input and output system protocol.

8. The memory device management method according to claim 1, wherein: The displaying of the target sequence identifier includes at least one of the following: In response to a target command in an operating system of the server, displaying the target sequence identifier in the operating system; The target sequence identifier is sent to a baseboard management controller through an intelligent platform management interface protocol, and the target sequence identifier is displayed on the baseboard management controller.

9. The memory device management method according to claim 1, wherein: The method further comprises: During the startup phase of the server, polling the central processing unit number, memory channel number, and memory slot number of the server to determine whether the memory device is in place; When it is detected that the memory device associated with the current slot is not in place, skip the current slot and continue to poll the slot next to the current slot; When it is detected that the memory device associated with the current slot is present, obtaining field data corresponding to the i-th byte to the j-th byte from the serial presence detection data through a two-wire serial bus protocol, wherein the field data corresponding to the i-th byte to the i+1-th byte is used to indicate a manufacturer identifier of the memory device, the i+2-th byte is used to indicate a production location of the memory device, the i+3-th byte is used to indicate a production date of the memory device, the i+4-th byte is used to indicate a number of production cycles of the memory device, and the i+5-th byte to the j-th byte are used to indicate a traditional serial number of the memory device; Sequentially concatenate the field data corresponding to the i-th byte to the j-th byte according to byte positions to generate the target sequence identifier that meets a preset character length; Updating the target sequence identifier to the storage structure of the memory device through a system management basic input and output system protocol; In response to a target command in an operating system of the server, displaying the target sequence identifier in the operating system; The target sequence identifier is sent to a baseboard management controller through an intelligent platform management interface protocol, and the target sequence identifier is displayed on the baseboard management controller.

10. An electronic device, characterized in that: include: memory for storing computer programs; A processor, configured to implement the steps of the memory device management method according to any one of claims 1 to 9 when executing the computer program.

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