Signal identification method and system, electronic equipment and storage medium

Abstract

The invention discloses a signal identification method and system, electronic equipment and a storage medium. The method comprises the following steps: acquiring an original electroencephalogram signal of a test object; performing feature extraction on the original electroencephalogram signals, and constructing an initial feature matrix of the original electroencephalogram signals; reconstructing the initial feature matrix based on module parameters of a plurality of target hardware modules in the signal recognition device to obtain a target feature matrix, the target feature matrix satisfying processing conditions of the plurality of target hardware modules, and the data dimension of the target feature matrix being greater than the data dimension of the initial feature matrix; the target feature matrix is input into a signal recognition device, the original electroencephalogram signals are recognized through the signal recognition device, a signal recognition result is obtained, and the signal recognition result is used for representing the behavior intention of the test object. The technical problem that the operation speed of electroencephalogram signal recognition is low in the prior art is solved.

Description

Technical Field

[0001] The present invention relates to the field of brain-computer interface, and in particular to a signal recognition method and system, electronic equipment, and storage medium. Background Art

[0002] Brain-Computer Interface (BCI) technology is an emerging form of human-computer interaction that allows wearable or implantable devices to interpret user intent directly from brain signals, enabling communication with external devices without the need for traditional physical movements. In recent years, BCI technology has demonstrated tremendous potential in areas such as medical rehabilitation, augmented reality, virtual reality, and smart homes. It is considered a crucial component of cutting-edge technology, particularly for assisting people with disabilities, treating neurological disorders, and enhancing the human-computer interaction experience.

[0003] Steady-State Visual Evoked Potential (SSVEP) is a common EEG control method in brain-computer interfaces. It is based on the synchronized EEG signals generated when the user looks at a light source flickering at a specific frequency. Nowadays, the recognition and decoding of SSVEP signals has become a key link in connecting the brain and the computer. However, the current SSVEP recognition method has low computing speed and efficiency.

[0004] To address the above-mentioned problems, no effective solutions have been proposed so far. Summary of the Invention

[0005] The embodiments of the present invention provide a signal recognition method and system, an electronic device, and a storage medium to at least solve the technical problem of low computing speed for recognizing EEG signals in related technologies.

[0006] According to one aspect of an embodiment of the present invention, a signal recognition method is provided, including: obtaining an original EEG signal of a test subject; performing feature extraction on the original EEG signal to construct an initial feature matrix of the original EEG signal; reconstructing the initial feature matrix based on module parameters of multiple target hardware modules in a signal recognition device to obtain a target feature matrix, wherein the target feature matrix meets the processing conditions of the multiple target hardware modules and the data dimension of the target feature matrix is ​​greater than the data dimension of the initial feature matrix; inputting the target feature matrix into a signal recognition device, and using the signal recognition device to recognize the original EEG signal to obtain a signal recognition result, wherein the signal recognition result is used to characterize the behavioral intention of the test subject.

[0007] Furthermore, the signal recognition device is a device configured based on a signal recognition model, and the method also includes: parsing the signal recognition model to determine the signal recognition parameters of multiple signal recognition modules contained in the signal recognition model, and the execution logic between different signal recognition modules; configuring multiple initial hardware modules based on the signal recognition parameters of multiple signal recognition modules to obtain multiple target hardware modules; writing the initial operation logic between multiple target hardware modules based on the execution logic to obtain target operation logic; and constructing a signal recognition device based on the target operation logic and multiple target hardware modules.

[0008] Furthermore, the signal identification parameters include at least: the processing weight corresponding to the signal identification module, the initial hardware module includes at least: the initial storage module, and the target hardware module includes at least: the target storage module; the multiple initial hardware modules are configured based on the signal identification parameters of multiple signal identification modules to obtain multiple target hardware modules, including: obtaining the data coding and application order corresponding to the processing weight; determining the storage coding corresponding to the processing weight based on the data coding, wherein the storage coding is used to represent the data corresponding to the processing weight when the processing weight is stored in the target storage module; performing data conversion on the storage coding to obtain the weight matrix corresponding to the processing weight; storing the weight matrix to the initial storage module based on the application order to obtain the target storage module.

[0009] Furthermore, after constructing the signal recognition device based on the target operation logic and multiple target hardware modules, the method also includes: inputting the test EEG signal into the signal recognition model based on the test device to obtain the model recognition results output by different signal recognition modules in the signal recognition model, and inputting the test EEG signal into the signal recognition device to obtain the hardware processing results output by different target hardware modules in the signal recognition device; verifying the hardware processing result based on the model recognition result to obtain a signal verification result, wherein the signal verification result is used to characterize whether the execution logic between different signal recognition modules matches the target operation logic between different target hardware modules; in response to the signal verification result being that the execution logic matches the target operation logic, determining that the signal recognition device is successfully constructed.

[0010] Furthermore, the method also includes: in response to the signal verification result that the execution logic does not match the target operation logic, based on the signal verification result, determining the erroneous hardware module from the target hardware module, wherein the operation logic of the erroneous hardware module is different from the execution logic of the corresponding signal identification module; based on the model identification result and signal identification parameters corresponding to the erroneous hardware module, adjusting the module parameters of the erroneous hardware module to obtain a new hardware module, wherein the target operation logic of the new hardware module matches the execution logic of the corresponding signal identification module; updating the signal identification device based on the new hardware module, and determining that the signal identification device is successfully constructed.

[0011] Furthermore, the test device satisfies at least one of the following conditions: the data format of the test data output by the test device is a preset format, and the test data includes a test EEG signal; the application scenario of the test data output by the test device includes a preset scenario, wherein the preset scenario includes a scenario for obtaining the original EEG signal; the delay of the test device outputting the test data is less than a preset threshold; the test device has a resending function, wherein the resending function is used to characterize the resending of the test data in the event of a failure in sending the test data.

[0012] Furthermore, feature extraction is performed on the original EEG signal to construct an initial feature matrix of the original EEG signal, including: preprocessing the original EEG signal to obtain a preprocessed signal; extracting features from the preprocessed signal to obtain signal features of the processed signal; and constructing an initial feature matrix based on eigenvalues ​​of the signal features.

[0013] According to another aspect of an embodiment of the present invention, a signal recognition system is also provided, including: a signal acquisition device for acquiring the original EEG signal of a test subject; a feature processing device, connected to the signal acquisition device, for performing feature extraction on the acquired original EEG signal, constructing an initial feature matrix of the original EEG signal, and reconstructing the initial feature matrix based on the module parameters of multiple target hardware modules in the signal recognition device to obtain a target feature matrix, wherein the target feature matrix meets the processing conditions of multiple target hardware modules, the data dimension of the target feature matrix is ​​greater than the data dimension of the initial feature matrix, and the module parameters are obtained by editing the signal recognition parameters of the signal recognition model; a signal recognition device, connected to the feature processing device, for recognizing the original EEG signal based on the target feature matrix, obtaining a signal recognition result, and returning the signal recognition result to the feature processing device, wherein the signal recognition result is used to characterize the behavioral intention of the test subject; a result display device, connected to the feature processing device, for outputting the signal recognition result.

[0014] Furthermore, the signal identification device includes: a physical layer interface chip, connected to the feature processing device, for receiving a first data signal sent by the feature processing device, or sending a second data signal to the feature processing device, wherein the first data signal includes a signal corresponding to the target feature matrix and a signal corresponding to the signal identification result; a serial interface core, connected to the physical layer interface chip, for converting the data format of the first data signal received by the physical layer interface chip to obtain a third data signal, or converting the data format of the fourth data signal output by the media access control interface to obtain a second data signal; a media access control interface, connected to the physical layer interface chip through the serial interface core, for encapsulating the third data signal to obtain a fifth data signal, or parsing the sixth data signal to obtain a fourth data signal; a signal identification module, connected to the media access control interface, for performing signal identification on the fifth data signal, obtaining a signal identification result, and constructing a sixth data signal based on the signal identification result.

[0015] Furthermore, the physical layer interface chip includes: a media access control interface, used to communicate with the media access control interface based on a preset interface standard; a signal transceiver, connected to the media access control interface, used to receive a first data signal output by the media access control interface based on a low-voltage differential signal transmission technology, or to send a second data signal to the media access control interface based on a low-voltage differential signal transmission technology; an encoding and decoding circuit, connected to the signal transceiver, used to decode the received data signal and encode the sent data signal; a clock data recovery device, connected to the signal transceiver, used to ensure the synchronous transmission of the first data signal or the second data signal.

[0016] Furthermore, the feature processing device is further configured to broadcast an address resolution protocol request; and the signal identification device is further configured to, in response to receiving the address resolution protocol request, send a media access control address of the signal identification device to the feature processing device based on the address resolution protocol request.

[0017] Furthermore, the signal identification device is connected to the feature processing device via a user datagram protocol.

[0018] According to another aspect of an embodiment of the present invention, an electronic device is provided, including: a memory storing an executable program; and a processor for running the program, wherein the program executes the methods of various embodiments of the present invention when running.

[0019] According to another aspect of an embodiment of the present invention, a computer-readable storage medium is provided. The computer-readable storage medium includes a stored executable program, wherein when the executable program is running, the device where the computer-readable storage medium is located is controlled to execute the methods in various embodiments of the present invention.

[0020] According to another aspect of an embodiment of the present invention, a computer program product is provided, including a computer program. When the computer program is executed by a processor, the method in each embodiment of the present invention is implemented.

[0021] According to another aspect of an embodiment of the present invention, a computer program product is provided, including a non-volatile computer-readable storage medium, wherein the non-volatile computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the method in each embodiment of the present invention is implemented.

[0022] According to another aspect of the embodiments of the present invention, a computer program is provided. When the computer program is executed by a processor, the methods in various embodiments of the present invention are implemented.

[0023] In an embodiment of the present invention, the original EEG signal of the test subject is obtained; the original EEG signal is subjected to feature extraction to construct an initial feature matrix of the original EEG signal; the initial feature matrix is ​​reconstructed based on the module parameters of multiple target hardware modules in the signal recognition device to obtain a target feature matrix; the target feature matrix is ​​input into the signal recognition device, and the original EEG signal is recognized by the signal recognition device to obtain a signal recognition result. The original EEG signal is constructed into an initial feature matrix through feature extraction. The above feature extraction process can filter out feature information with high correlation with EEG signal recognition from the original EEG signal, while ignoring feature information with low correlation with EEG signal recognition, thereby eliminating interference from irrelevant data and reducing the complexity of directly processing the original EEG signal. Subsequently, the above initial feature matrix is ​​reconstructed according to the module parameters of the target hardware module to obtain the target feature matrix to meet the processing conditions of the target hardware module, so that hardware resources can be effectively utilized. Finally, since the above-mentioned signal recognition device has lower communication delay and stronger in-memory computing and parallel computing capabilities compared to traditional software systems, it can greatly improve the computing speed and efficiency in the EEG signal recognition process, and the above-mentioned target feature matrix can better fit the processing conditions of the target hardware module in the signal recognition device. Therefore, based on the signal recognition device, hardware acceleration can be used to quickly process the data in the target feature matrix to obtain signal recognition results, thereby achieving the purpose of eliminating the software computing bottleneck in the EEG signal recognition process, thereby achieving the technical effect of improving the recognition speed of EEG signals, and then solving the technical problem of low computing speed for EEG signal recognition in related technologies. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] The drawings described herein are used to provide a further understanding of the present invention and constitute a part of this application. The exemplary embodiments of the present invention and their descriptions are used to explain the present invention and do not constitute an improper limitation of the present invention. In the drawings:

[0025] Figure 1 is a flow chart of a signal recognition method according to an embodiment of the present invention;

[0026] Figure 2 is a flowchart of an optional preprocessing and feature extraction according to an embodiment of the present invention;

[0027] Figure 3 This is an optional flow chart of converting floating-point numbers to binary fixed-point numbers according to an embodiment of the present invention;

[0028] Figure 4 is a flow chart of an optional method for recognizing and classifying EEG signals according to an embodiment of the present invention;

[0029] Figure 5 is a schematic diagram of a signal recognition system according to an embodiment of the present invention;

[0030] Figure 6 is a schematic diagram of an optional FPGA-based SSVEP EEG recognition system according to an embodiment of the present invention;

[0031] Figure 7 is a detailed schematic diagram of an optional EEG signal recognition and classification process according to an embodiment of the present invention;

[0032] Figure 8 is a schematic diagram of an optional communication process according to an embodiment of the present invention;

[0033] Figure 9 It is a schematic diagram of an optional UDP protocol content according to an embodiment of the present invention. DETAILED DESCRIPTION

[0034] In order to enable those skilled in the art to better understand the solutions of the present invention, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the embodiments described are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts should fall within the scope of protection of the present invention.

[0035] It should be noted that the terms "first", "second", etc. in the description and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that the numbers used in this way can be interchanged where appropriate, so that the embodiments of the present invention described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions. For example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0036] According to an embodiment of the present invention, an embodiment of a signal recognition method is provided. It should be noted that the steps shown in the flowchart of the accompanying drawings can be executed in a computer system such as a set of computer-executable instructions, and although a logical order is shown in the flowchart, in some cases, the steps shown or described can be executed in an order different from that shown here.

[0037] Figure 1 is a flow chart of a signal recognition method according to an embodiment of the present invention. Figure 1 As shown, the method includes the following steps:

[0038] Step S102: obtaining the original EEG signal of the test subject.

[0039] The above-mentioned test subject can be a person or animal that can provide EEG signals. The above-mentioned test subject can perform tasks related to EEG signal acquisition to generate different types of EEG activities, thereby facilitating the acquisition of the above-mentioned original EEG signals. For example, the above-mentioned test subject can perform concentration, imaginative movement or other cognitive activities, but is not limited to this.

[0040] The above-mentioned raw EEG signal can be an unprocessed EEG activity signal obtained directly from the scalp of the above-mentioned test subject. The above-mentioned raw EEG signal reflects the changes in the electrical signals of the neurons in the brain of the test subject. The signal can be captured by an EEG acquisition device placed on the surface of the test subject's scalp, or provided by the test subject itself, which is not limited here. The above-mentioned raw EEG signal can contain all the original information of the test subject's brain activity, such as brain waves of various frequencies and event-related potentials of the test subject, but is not limited to this. It should be noted that since the electric field generated by brain activity is relatively weak, the above-mentioned raw EEG signal may be mixed with a large amount of noise. For example, the above-mentioned noise may include noise from muscle activity, heartbeat, environmental electromagnetic interference, and poor electrode contact, but is not limited to this.

[0041] In an optional embodiment, in order to more accurately collect the original EEG signals of the above-mentioned test subject, the test subject can be asked to wear an EEG cap. The electrodes on the above-mentioned EEG cap can cover the area where the test subject's brain is located so as to capture the SSVEP signal. After the above-mentioned test subject wears the EEG cap, the collection of original EEG signals can be started. At this time, the staff can guide the test subject to perform tasks related to SSVEP signal collection, such as observing visual stimuli. During this process, the EEG cap can record the test subject's EEG activity and transmit it to a preset recognition system (hereinafter referred to as the recognition system), so that the recognition system can more accurately obtain the test subject's original EEG signals.

[0042] In another optional embodiment, the above-mentioned test subject can collect the original EEG signals in advance, and encrypt the collected original EEG signals and send them to the background server of the recognition system. The recognition system can extract the received encrypted data from the above-mentioned background server, and decrypt and verify the format of the data. Once the data format of the decrypted original EEG signal meets the requirements of the recognition system, the recognition system can directly store the signal locally to facilitate subsequent recognition and classification work.

[0043] In another optional embodiment, in order to improve the convenience of acquisition and the comfort of the test subject, the recognition system can also use a flexible EEG patch to collect the original EEG signal of the test subject. The flexible EEG patch is different from the traditional rigid EEG acquisition device and can fit the scalp better, reduce motion artifacts, and provide higher signal sensitivity. Specifically, the staff can select several target positions on the head of the test subject in advance and stick the flexible EEG patch on the above target positions without having the test subject wear a heavy EEG acquisition device. When the test subject performs the EEG acquisition task, the flexible EEG patch can collect the original EEG signal of the test subject in real time and send it to the recognition system through wired or wireless transmission, thereby ensuring the authenticity and integrity of the collected original EEG signal and improving the comfort of the test subject during the acquisition process.

[0044] It should be noted that the above-mentioned raw EEG signal collection and recognition process complies with relevant laws, regulations and ethical principles. During the above process, the privacy of the test subjects will be effectively protected.

[0045] Step S104: extract features from the original EEG signal and construct an initial feature matrix of the original EEG signal.

[0046] The initial feature matrix can be a mathematical structure composed of multiple eigenvectors, which is used to summarize and present the characteristic information of the raw EEG signal. Each eigenvector in the feature matrix can summarize an attribute or pattern of the raw EEG signal. For example, the rows of the feature matrix can correspond to different raw EEG signal segments, and the columns of the feature matrix can represent different feature types or signal channels, but are not limited to these.

[0047] In an optional embodiment, considering that the above-mentioned raw EEG signals are usually mixed with various physiological and environmental noises, the feature extraction process can help the recognition system extract signal components related to the brain cognitive activities or stimulus responses performed by the test subject, thereby removing the noise in the raw EEG signals, concentrating useful information, and thus improving the accuracy of subsequent raw EEG signal recognition. In the specific implementation process, in order to further improve the accuracy of the above-mentioned initial feature matrix, the recognition system can also pre-denoise the above-mentioned original EEG signal to eliminate various noise interferences in the original EEG signal, and then perform feature extraction. The goal of the above-mentioned feature extraction is to extract feature information that can better represent and distinguish the above-mentioned original EEG signal from the original EEG signal after noise reduction. Considering that the time domain features are sensitive to the instantaneous changes of the original EEG signal, it is helpful to identify and classify EEG activity patterns, and time domain analysis does not require complex calculations and is suitable for scenarios with limited computing resources. Therefore, the recognition system can divide the above-mentioned original EEG signal into multiple signal windows. For each signal window, the recognition system can calculate the time domain statistical features corresponding to the window, such as mean, variance, root mean square value, zero crossing rate, slope angle and kurtosis, etc. Subsequently, the recognition system can assemble all the extracted time domain feature vectors into an initial feature matrix in time order or electrode order. Each row can correspond to the feature vector of a signal window, and each column can represent different types of time domain features.

[0048] In another optional embodiment, considering that the frequency domain characteristics are directly related to the stimulation frequency of the brain-computer interface, it is beneficial to improve the accuracy of SSVEP recognition, and the spectrum analysis results are highly visible, which helps the recognition system to intuitively understand the signal components. Therefore, the recognition system can also pre-set a target frequency and apply Fast Fourier Transform (FFT) or Power Spectral Density (PSD) estimation to each of the above signal windows to obtain the spectrum of the signal corresponding to the window. Subsequently, the recognition system can extract the amplitude or power of the above target frequency as a feature, and arrange the frequency domain feature vectors in time or electrode order to form the above initial feature matrix, where each row can correspond to the frequency domain feature of a signal window.

[0049] In another optional embodiment, considering that time-frequency domain feature extraction combines signal information in the time dimension and the frequency dimension, it is suitable for identifying non-stationary signals, and the rich time-frequency information helps to improve the classification performance of the recognition system for different EEG patterns. Therefore, the recognition system can also apply short-time Fourier transform (STFT), continuous wavelet transform (CWT) or Hilbert-Huang transform (HHT) to each of the above signal windows to delete the generated time-frequency spectrum and extract features from the time-frequency spectrum, such as local energy, instantaneous rate of change of frequency, or spectrum changes within a specified time interval. Subsequently, the recognition system can convert the frequency domain features of each time point of the time-frequency spectrum into feature vectors, and concatenate the feature vectors of all time points in chronological order into an initial feature matrix, wherein each row of the matrix can represent a feature vector of a time point, and each column can represent a feature at a fixed frequency or frequency interval.

[0050] Step S106, reconstructing the initial feature matrix based on the module parameters of multiple target hardware modules in the signal recognition device to obtain a target feature matrix, wherein the target feature matrix meets the processing conditions of the multiple target hardware modules, and the data dimension of the target feature matrix is ​​greater than the data dimension of the initial feature matrix.

[0051] The above-mentioned signal recognition device can be a device for decoding EEG signals and converting the signals into a form that can be understood and interpreted by a computer. For example, the above-mentioned signal recognition device can be an FPGA (Field-Programmable Gate Array) chip, a DSP (Digital Signal Processor) processor or a GPU (Graphics Processing Unit), etc., but is not limited to this. The above-mentioned module parameters can be the rules, configurations or specifications that the target hardware module needs to follow when performing signal processing tasks, such as sampling rate, data width, processing delay, memory limitations, etc., but are not limited to this. The above-mentioned target feature matrix can be a feature matrix that is made by preprocessing, converting or expanding the above-mentioned initial feature matrix so that the above-mentioned initial feature matrix meets the processing conditions of the above-mentioned target hardware module. The above-mentioned data dimension can be the number and structure of features in the feature matrix.

[0052] In an optional embodiment, considering that different target hardware modules in the above-mentioned signal recognition device may have different data types, bit widths, memory capacity and computing speed limitations, in order to maximize the performance and effectiveness of the target hardware modules, the recognition system can adjust the above-mentioned feature matrix based on the module parameters of the above-mentioned target hardware modules so that the matrix meets the processing conditions of the current target hardware modules. Specifically, the recognition system can analyze the data type preferences, computing resource limitations and processing requirements of each target hardware module. Then, based on the results obtained from the above-mentioned analysis process, the recognition system can adjust the initial feature matrix. For example, the recognition system can add and delete features, convert data types (such as from floating point numbers to fixed point numbers), design parallel processing structures, and reorganize and package features on the initial feature matrix. In order to more fully describe the signal characteristics of the EEG signal and make the above-mentioned signal characteristics match the computing power of the target hardware, the recognition system can also increase the dimension of the initial feature matrix after the above-mentioned adjustment to obtain the above-mentioned target feature matrix. For example, the recognition system can reconstruct a feature matrix with larger data dimensions and more information by introducing additional frequency domain features, time-frequency features or high-order cross-correlation features as the above-mentioned target feature matrix. Through the above steps, not only can the signal recognition device be ensured to efficiently process and recognize complex EEG signals, but it can also fully utilize the unique advantages of various target hardware modules to improve the effect of EEG signal processing. The target feature matrix finally generated not only meets the processing conditions of the target hardware module, but also has richer data dimensions than the initial feature matrix, which also promotes the improvement of signal recognition performance and speed.

[0053] Step S108: input the target feature matrix into a signal recognition device, and use the signal recognition device to recognize the original EEG signal to obtain a signal recognition result, wherein the signal recognition result is used to characterize the behavioral intention of the test subject.

[0054] The above-mentioned signal recognition result may refer to the classification or decision output generated by the above-mentioned signal recognition device after analyzing the target feature matrix, which is used to decode and interpret the behavioral intention or state expressed by the test subject through its brain activity.

[0055] In an optional embodiment, the recognition system can input the constructed target feature matrix into the above-mentioned signal recognition device, which can include a pre-trained machine learning or deep learning model. The above-mentioned model can identify the behavioral intentions behind different brain activity patterns. After receiving the feature matrix, the signal recognition device can use the trained model to analyze the features, and by comparing the features with the multiple behavioral intention patterns stored in the model, determine the most matching intention category and output the signal recognition result. This result is based on the accurate translation of the brain signal and can directly indicate the current behavioral intention of the test subject.

[0056] In another optional embodiment, to increase recognition speed, the recognition system may pre-store a series of feature templates of known behavioral intentions in the signal recognition device and utilize a DSP processor to recognize the raw EEG signals. Specifically, when the signal recognition device is required to recognize the raw EEG signals, the recognition system may input the target feature matrix into the signal recognition device. The DSP processor in the device then executes a template matching algorithm to search for a template that matches the input features. Based on this, the system infers the test subject's behavioral intentions, thereby obtaining the signal recognition result.

[0057] In an embodiment of the present invention, the original EEG signal of the test subject is obtained; the original EEG signal is subjected to feature extraction to construct an initial feature matrix of the original EEG signal; the initial feature matrix is ​​reconstructed based on the module parameters of multiple target hardware modules in the signal recognition device to obtain a target feature matrix; the target feature matrix is ​​input into the signal recognition device, and the original EEG signal is recognized by the signal recognition device to obtain a signal recognition result. The original EEG signal is constructed into an initial feature matrix through feature extraction. The above feature extraction process can filter out feature information with high correlation with EEG signal recognition from the original EEG signal, while ignoring feature information with low correlation with EEG signal recognition, thereby eliminating interference from irrelevant data and reducing the complexity of directly processing the original EEG signal. Subsequently, the above initial feature matrix is ​​reconstructed according to the module parameters of the target hardware module to obtain the target feature matrix to meet the processing conditions of the target hardware module, so that hardware resources can be effectively utilized. Finally, since the above-mentioned signal recognition device has lower communication delay and stronger in-memory computing and parallel computing capabilities compared to traditional software systems, it can greatly improve the computing speed and efficiency in the EEG signal recognition process, and the above-mentioned target feature matrix can better fit the processing conditions of the target hardware module in the signal recognition device. Therefore, based on the signal recognition device, hardware acceleration is used to quickly process the data in the target feature matrix to obtain signal recognition results, thereby achieving the purpose of eliminating the software computing bottleneck in the EEG signal recognition process, thereby achieving the technical effect of improving the recognition speed of EEG signals, and then solving the technical problem of low computing speed for EEG signal recognition in related technologies.

[0058] Furthermore, the signal recognition device is a device configured based on a signal recognition model, and the method also includes: parsing the signal recognition model to determine the signal recognition parameters of multiple signal recognition modules contained in the signal recognition model, and the execution logic between different signal recognition modules; configuring multiple initial hardware modules based on the signal recognition parameters of multiple signal recognition modules to obtain multiple target hardware modules; writing the initial operation logic between multiple target hardware modules based on the execution logic to obtain target operation logic; and constructing a signal recognition device based on the target operation logic and multiple target hardware modules.

[0059] The signal recognition model can be an algorithmic framework for processing and recognizing EEG signals, typically composed of a series of mathematical models and machine learning models, used to extract key features from complex raw signals and then classify or predict the signals. For example, the signal recognition model can be, but is not limited to, a frequency band convolutional autoencoder with cross-correlation network (FBCACNN).

[0060] The signal recognition module may be part of the signal recognition model, with each module responsible for a fixed task in the signal processing or recognition process. For example, in the FBCACNN framework, the signal recognition module may include at least one or more of the following: a convolutional layer, a pooling layer, a fully connected layer, an activation layer, etc., but is not limited thereto. The fixed tasks may include at least one or more of the following: feature extraction, convolution operation, activation function calculation, etc., but are not limited thereto.

[0061] The signal recognition parameters may refer to configuration information and trained parameters required by the signal recognition module during operation. For example, the signal recognition parameters may include, but are not limited to, at least one or more of the following: filter coefficients, convolution kernel size, learning rate, weights, and biases. The signal recognition parameters may be determined based on the characteristics of the SSVEP signal and the training results of the signal recognition model.

[0062] The initial operation logic may be the operation process and rules of the signal recognition model before being adjusted for different target hardware modules. The target operation logic may be the operation process and rules after the signal recognition model is transplanted to different target hardware modules. The target operation logic may be reconfigured for different target hardware modules to fully adapt to the parallel computing capabilities, memory access modes, and data transmission characteristics of different hardware modules.

[0063] In an optional embodiment, considering that the signal recognition model is often composed of a multi-layer neural network or other complex machine learning algorithms, and contains multiple signal recognition modules, the purpose of the above-mentioned model analysis is to understand the structure and working principle of the model and determine the recognition parameters of each module, which is the prerequisite for subsequent hardware configuration and logic writing. Specifically, the recognition system can deeply analyze the signal recognition model and clarify the different signal recognition modules contained in the model structure. For example, the above-mentioned signal recognition model can be decomposed into a convolution module, a pooling module, an activation module, and a fully connected module, etc. Subsequently, the recognition system can determine the signal recognition parameters of each of the above-mentioned signal recognition modules, such as the size of the convolution kernel, the weight value, etc. After determining the above-mentioned signal recognition parameters, the recognition system can sort out the execution logic between different signal recognition modules, that is, define how the above-mentioned signal recognition modules collaborate, how EEG signals are transmitted between different modules, and the triggering mechanism of the control signal, so as to ensure that the different signal recognition modules can work together and operate efficiently when the signal recognition model is running. After completing the determination of the above-mentioned signal recognition parameters and execution logic, the recognition system can select and configure the appropriate initial hardware modules based on the signal recognition parameters, and perform precise hardware resource configuration according to the task characteristics and required parameters of each module, for example, determining the size of the weight storage area, the depth of the input signal buffer, the number of computing units, etc., thereby obtaining the above-mentioned multiple target hardware modules. Subsequently, the recognition system can, based on the above-mentioned execution logic, write and implement the circuit logic of each target hardware module through a hardware description language such as Verilog or VHDL (VHSIC Hardware Description Language, very large-scale integrated circuit hardware description language) to obtain the above-mentioned target operation logic. Finally, the recognition system can integrate the configured target hardware modules and the written target operation logic into a signal recognition device, thereby constructing the above-mentioned signal recognition device.

[0064] Furthermore, the signal identification parameters include at least: the processing weight corresponding to the signal identification module, the initial hardware module includes at least: the initial storage module, and the target hardware module includes at least: the target storage module; the multiple initial hardware modules are configured based on the signal identification parameters of multiple signal identification modules to obtain multiple target hardware modules, including: obtaining the data coding and application order corresponding to the processing weight; determining the storage coding corresponding to the processing weight based on the data coding, wherein the storage coding is used to represent the data corresponding to the processing weight when the processing weight is stored in the target storage module; performing data conversion on the storage coding to obtain the weight matrix corresponding to the processing weight; storing the weight matrix to the initial storage module based on the application order to obtain the target storage module.

[0065] The processing weights mentioned above can be parameters used for convolution operations, calculations in fully connected layers, and other modules in the signal recognition model. The data encoding mentioned above can be the digital representation of the signal recognition parameters when stored and processed in the hardware. For example, because hardware platforms such as memristors in FPGAs have requirements for the bit width and format of data, the processing weights need to be converted from the floating-point format in the software to a hardware-compatible data encoding format, that is, fixed-point format. The application order mentioned above can be the time series of operations of each signal recognition module during the execution of the signal recognition model, which determines when and how the processing weights are used. The storage encoding mentioned above can be the conversion of the data encoding of the processing weights into the format for storage in the target storage module, which takes into account the characteristics of hardware storage, such as address mapping, memory organization, and data alignment, but is not limited to this. The weight matrix mentioned above can be a matrix representation of the processing weights arranged in the order of application.

[0066] In an optional embodiment, considering that the above-mentioned signal recognition model has advantages in flexibility, it may encounter problems such as slow computing speed, high power consumption and large delay when processing large-scale data sets, especially in demanding application scenarios such as real-time signal recognition and brain-computer interface. Therefore, by hardwareizing some or all of the functions of the above-mentioned signal recognition model, the computing efficiency can be significantly improved, the delay can be reduced, and the power consumption can be reduced, thereby achieving higher recognition accuracy and faster response speed. Specifically, the recognition system can first analyze the signal recognition model and identify the weight matrix of each layer in the model and its application order in the calculation process of the model. Then, the recognition system can parse the data encoding corresponding to the processing weights in the signal recognition model. At the same time, the recognition system can also clarify the application order of the above-mentioned processing weights when the model is running according to the calculation logic of the signal recognition model. After obtaining the above-mentioned data encoding and application order, the recognition system can determine the storage encoding based on the data encoding format of the processing weights, that is, determine how to effectively store the processing weights in the target storage module. It should be noted that the determination of the above-mentioned storage code not only needs to consider the data type of the data corresponding to the above-mentioned processing weights, but also needs to be combined with the characteristics of the storage medium, such as storage speed, addressing mode and capacity, to adjust the data representation of the processing weights. After determining the above-mentioned storage code, the recognition system can use programming tools or scripts to convert the storage code data to obtain the weight matrix corresponding to the processing weights, so as to reduce storage requirements and improve hardware computing efficiency. Subsequently, the recognition system can use the hardware description language to write code according to the application order of the weight matrix, and store the weight matrix according to the storage code in the target storage module. This step requires precise control to ensure that the data corresponding to the processing weights can be correctly loaded and read in the hardware.

[0067] Furthermore, after constructing the signal recognition device based on the target operation logic and multiple target hardware modules, the method also includes: inputting the test EEG signal into the signal recognition model based on the test device to obtain the model recognition results output by different signal recognition modules in the signal recognition model, and inputting the test EEG signal into the signal recognition device to obtain the hardware processing results output by different target hardware modules in the signal recognition device; verifying the hardware processing result based on the model recognition result to obtain a signal verification result, wherein the signal verification result is used to characterize whether the execution logic between different signal recognition modules matches the target operation logic between different target hardware modules; in response to the signal verification result being that the execution logic matches the target operation logic, determining that the signal recognition device is successfully constructed.

[0068] The above-mentioned test EEG signals may refer to sample data used to verify the accuracy of the signal recognition model and its hardware implementation. These signals come from real EEG acquisition. For example, the above-mentioned test EEG signals may be SSVEP signals collected by an OpenBCI (Open Brain Computer Interface) EEG cap, but are not limited to this. The above-mentioned test EEG signals may cover all types and ranges that the model is expected to process to comprehensively evaluate the performance and consistency of the device. The above-mentioned model recognition results may be the classification or recognition results output by the above-mentioned signal recognition model after receiving the test EEG signals. The above-mentioned model recognition results reflect the analysis and judgment results of the signal recognition model on the test EEG signals and are the benchmark for evaluating the performance of the hardware device. The above-mentioned hardware processing results may be the output results generated by the above-mentioned signal recognition device after receiving the same test EEG signal, which are used to verify the accuracy of the hardware processing. The above-mentioned signal verification results may be an indicator used to judge the consistency between the recognition results of the above-mentioned signal recognition model and the hardware processing results. It evaluates whether the hardware device has accurately performed the signal recognition task by comparing the outputs of the signal recognition model and the hardware processing.

[0069] In an optional embodiment, the recognition system can pre-deploy a set of test scripts to construct the above-mentioned test device. The script can not only simulate the data format sending and receiving of real data, and the test data range covers all real data samples, but also ensure low latency in data transmission, and has the ability to handle packet loss problems in the event of transmission failure or retransmission timeout. Subsequently, the recognition system can input the collected test EEG signal into the signal recognition model in the software environment based on the above-mentioned test script. Each different signal recognition module in the model will output the model recognition result corresponding to the current module. Similarly, the recognition system can also input the same test EEG signal into the signal recognition device. Each target hardware module in the device can execute the function of the corresponding recognition module and output its own hardware processing result. After completing the above processing, the recognition system can collect the model recognition results of the software model and the hardware processing results output by the target hardware module of the hardware device, and match the software simulation results with the actual hardware output results one by one, and compare in detail whether the execution logic between different signal recognition modules matches the target operation logic between different target hardware modules, so as to obtain the signal verification result. If the above signal verification result shows that the execution logic of all signal recognition modules is highly consistent with the target operation logic of the target hardware module, without obvious errors or abnormalities, then the recognition system can determine that the above signal recognition device is successfully constructed, which means that the function of the software model has been accurately transplanted to the hardware, and the signal recognition device can perform signal recognition tasks at the speed and efficiency of hardware to achieve the expected recognition performance.

[0070] For example, the recognition system can deploy the neural network structure and parameters on the PC side to the FPGA side and perform verification. Specifically, before inputting the test EEG signal into the FPGA, it is necessary to ensure that the format of the test EEG signal is consistent with the requirements of the FPGA. Therefore, the recognition system can first quantize the test EEG signal so that the test EEG signal is read in a fixed-point format. The above-mentioned fixed-point format can be pre-specified by the recognition system, such as 16-bit quantization, including the integer part and the fractional part bit width. After the test EEG signal is read into the FPGA, the recognition system can also perform a series of verifications to ensure that the test EEG signal has not been erroneous during transmission or conversion. Further considering that the parameters such as weights and biases of the neural network are usually stored in COE files (Coefficient Files), the recognition system also needs to write the parameters such as weights and biases from the COE file to the memory of the FPGA and verify the accuracy of the writing process. In order to ensure that the neural network model reconstructed in the FPGA can perform calculations correctly, the recognition system can verify the calculation results of the network layer by layer. Specifically, on the PC, the recognition system can use the same neural network structure and parameters to perform calculations and generate the expected output results. The recognition system can then send this input data to the FPGA via a communication interface (such as Ethernet). The FPGA performs the same calculations and sends the results back to the PC. Finally, the recognition system can compare the two results on the PC and FPGA to ensure that they are consistent or the difference is within an acceptable range, thereby verifying that the neural network model in the FPGA is correctly reconstructed and performs calculations.

[0071] Furthermore, the method also includes: in response to the signal verification result that the execution logic does not match the target operation logic, based on the signal verification result, determining the erroneous hardware module from the target hardware module, wherein the operation logic of the erroneous hardware module is different from the execution logic of the corresponding signal identification module; based on the model identification result and signal identification parameters corresponding to the erroneous hardware module, adjusting the module parameters of the erroneous hardware module to obtain a new hardware module, wherein the target operation logic of the new hardware module matches the execution logic of the corresponding signal identification module; updating the signal identification device based on the new hardware module, and determining that the signal identification device is successfully constructed.

[0072] The erroneous hardware module may be a hardware component in the signal recognition device that fails to accurately reproduce the corresponding signal recognition model execution logic.

[0073] In an optional embodiment, if the above-mentioned signal verification results show that the execution logic of all signal identification modules is inconsistent with the target operation logic of the target hardware module, the identification system can carefully review the output of each target hardware module and the expected output of the signal identification model based on the above-mentioned signal verification results to find the differences. By comparing the intermediate results of the software model and the actual output of the hardware device, the identification system can locate the erroneous hardware module whose operation logic is different from the execution logic of the corresponding signal identification module. Once the erroneous hardware module is determined, the identification system can analyze the reasons for the inconsistency between the module operation logic and the execution logic of the corresponding signal identification module, and adjust the module parameters of the erroneous hardware module to obtain a new hardware module whose target operation logic matches the execution logic of the corresponding signal identification module. Subsequently, the identification system can replace the original erroneous hardware module with the new hardware module, and again perform signal verification based on the software model and the updated hardware device, and compare the matching degree of the model identification result with the hardware processing result. If the output of the new hardware module is consistent with the predicted result of the software model, it indicates that the target operation logic has matched the execution logic and the hardware adjustment has been successful.

[0074] Furthermore, the test device satisfies at least one of the following conditions: the data format of the test data output by the test device is a preset format, and the test data includes a test EEG signal; the application scenario of the test data output by the test device includes a preset scenario, wherein the preset scenario includes a scenario for obtaining the original EEG signal; the delay of the test device outputting the test data is less than a preset threshold; the test device has a resending function, wherein the resending function is used to characterize the resending of the test data in the event of a failure in sending the test data.

[0075] The preset format can be a predefined method for organizing and presenting data, and is a standard format followed by the test device when outputting data. The preset scenario can refer to the application scenario in which the test device outputs test data, and can match the signal recognition model and the expected usage environment of the hardware device.

[0076] In an optional embodiment, the recognition system can predetermine a standard data format for transmitting test EEG signals. For example, the recognition system can predefine detailed information such as the sampling rate, duration, number of channels, and quantization level of the signal. The above-mentioned preset format should strictly match the input requirements of the signal recognition model to ensure that the data can be correctly interpreted and processed. Furthermore, the recognition system can also define preset test scenarios, especially those that can cover the target applications of the signal recognition device, such as different types of raw EEG signal acquisition scenarios. The above-mentioned test device can simulate the acquisition of real data in these scenarios, thereby providing representative test cases to fully verify the recognition capabilities of the signal recognition device. In addition, when designing the test device, the recognition system can ensure that the time from signal acquisition to data transmission to the signal recognition device is less than a preset threshold by adjusting the data processing process, adopting a high-speed transmission protocol, and reducing the processing level. Finally, the identification system can also add error detection and retransmission functions to the test device through protocol design, such as the timeout retransmission mechanism of UDP (User Datagram Protocol) or additional error correction coding. When the data packet is not confirmed to be received by the signal identification device, the test device can automatically trigger the retransmission of the data, ensuring that data transmission can be completed even under unstable network conditions.

[0077] Furthermore, feature extraction is performed on the original EEG signal to construct an initial feature matrix of the original EEG signal, including: preprocessing the original EEG signal to obtain a preprocessed signal; extracting features from the preprocessed signal to obtain signal features of the processed signal; and constructing an initial feature matrix based on eigenvalues ​​of the signal features.

[0078] The preprocessed signal may refer to an EEG signal that has undergone a series of preprocessing operations, such as filtering, baseline drift removal, and segmentation. The signal features may be discriminative and representative information extracted from the preprocessed signal, and the signal features may be used for training a signal recognition model, or for recognition or classification tasks.

[0079] In an optional embodiment, considering that the original EEG signal usually carries various noises and interferences, including but not limited to muscle activity, eye movement, heartbeat and environmental electromagnetic interference, the recognition system can preprocess the above-mentioned original EEG signal to improve the purity and signal-to-noise ratio of the original EEG signal, thereby providing high-quality signal data for subsequent analysis. Specifically, the recognition system can apply a bandpass filter to remove interference from irrelevant frequency bands, retain the frequency components related to SSVEP, and remove the slowly changing trend in the signal through high-pass filtering or moving average method to reduce the impact of baseline drift. In addition, the recognition system can also perform time window truncation on the signal based on the characteristics of the SSVEP signal and extract a fixed-length signal sequence to facilitate feature extraction. After the above-mentioned preprocessing steps, the recognition system can convert the above-mentioned original EEG signal into a preprocessed signal. After obtaining the above-mentioned preprocessed signal, in order to convert the complex, high-dimensional preprocessed signal into a more compact, low-dimensional feature representation to reduce the amount of calculation and improve the efficiency of subsequent processing and recognition accuracy, the recognition system can respectively calculate the time domain features, frequency domain features and time-frequency features of the preprocessed signal to obtain the signal features of the preprocessed signal. After feature extraction is completed, the recognition system can organize the extracted eigenvalues ​​into a matrix, namely the initial feature matrix, thereby organizing the extracted eigenvalues ​​into a form that can be easily processed by the signal recognition model to improve computing efficiency.

[0080] For ease of understanding, Figure 2 is a flow chart of an optional preprocessing and feature extraction according to an embodiment of the present invention, such as Figure 2 As shown, the raw EEG signal is first segmented to obtain a 7-second window of raw EEG signals. Subsequently, steps such as scaling, outlier removal, and baseline drift removal are performed sequentially to ensure that the processed signal meets the requirements of subsequent processes. The signal is then subjected to a 6-48 Hz bandpass filter and a power frequency notch filter to remove low-frequency noise, high-frequency noise, and grid frequency interference. The filtered signal can be truncated to a data window. The window size is typically selected based on the signal characteristics and subsequent processing requirements. The data from each window can be used for subsequent feature extraction. After data window truncation, the floating-point data format in the data must be converted to a fixed-point format to meet the computing requirements of the hardware and improve computational speed and efficiency. The converted data can be divided into two parts for use: one part can be used for online classification, i.e., real-time feature extraction and classification based on the converted data; the other part can be used for offline data recording, i.e., recording the original dataset based on the converted data. A feature dataset is then generated from this original dataset, and this feature dataset is used to train the classification model.

[0081] It should be noted that the specific values ​​of the above-mentioned window signal length, bandpass filter frequency, etc. are only for illustrative purposes. The staff can set them according to actual needs and are not limited here.

[0082] Figure 3 This is a flow chart of converting an optional floating point number to a binary fixed point number according to an embodiment of the present invention. Figure 3 As shown, first you need to determine the sign bit of the floating-point number, that is, whether the floating-point number is negative, and record the sign bit for subsequent representation. Then, you can formulate the integer part width (Integer Length, IL) and the decimal part width (Decimal Length, DL) of the fixed-point number. For example, in a 32-bit fixed-point number, you can allocate 7 bits to the integer part, 24 bits to the decimal part, and retain 1 bit as the sign bit. Then, the floating-point number can be divided into an integer part and a decimal part. After the division is completed, the integer part and the decimal part of the floating-point number can be taken separately. Next, the integer part and the decimal part can be truncated within a preset range. Specifically, for the integer part, you can use the rounding-down method, that is, directly truncate the integer part of the floating-point number, and then limit the integer part to the range of the integer part of the fixed-point number. The range can be -2 3 to 2 3 -1, if it exceeds this range, the larger or smaller value is taken. For the decimal part, you can use the rounding method, that is, multiply the decimal part of the floating point number by 2 4 , then round the calculated value to the nearest integer and limit the value to the range of the decimal part of the fixed-point number, that is, 0 to 2 4 -1, and if it exceeds this range, the larger or smaller value is taken. After completing the above conversion, the integer part and the fractional part can be combined into a 32-bit binary number. That is, the processed integer and fractional parts are combined into a single 32-bit binary number, where the integer part needs to be shifted left by DL bits to make room for the fractional part, and then added to the binary representation of the fractional part. Finally, the specified bit width can be combined with the sign bit. If the floating-point number is positive, the sign bit is set to 0, and if the floating-point number is negative, the sign bit is set to 1.

[0083] Optionally, the recognition system can also convert the floating point number represented by the high bit width into an integer with a low bit width by using a neural network quantization method. Specifically, the recognition system can first set the maximum value x of the floating point number. max and the minimum value x min, and set the range to be quantized. For example, under asymmetric quantization, the above range can be [0, 255]. The recognition system can then calculate the scaling factor and translation factor. The scaling factor can be used to map the range of floating-point numbers to the quantized integer range. The translation factor can be used to adjust the quantized value to ensure that the value falls within the specified integer range. The specific calculation process of the scaling factor and translation factor can be shown as follows:

[0084]

[0085]

[0086] Where s represents the scaling factor, z represents the translation factor, and round represents the rounding operation. After calculating the above scaling factors and zero point values, the recognition system can perform quantitative calculations based on the following formula:

[0087]

[0088] x quan =clamp(0,N levels -1,x int );

[0089] Where x int Represents the quantized integer value, x represents the original floating point number, x quan Represents the final quantized value, N levels Indicates the quantization level, for example, in 8-bit quantization, N levels The value of can be 256. Clamp represents a truncation operation, which is used to limit any value to a specified range. The interpretation of other symbols in the formula is consistent with the previous formula and will not be repeated here. The specific calculation process of the above truncation operation can be shown as follows:

[0090]

[0091] In the formula, the specified interval is [a, b], and the interpretation of other symbols in the formula is consistent with the previous formula and will not be repeated here. The recognition system can also perform inverse quantization calculation based on the following formula:

[0092] x float =(x quan -z)*s.

[0093] Where x float represents the floating-point value obtained through inverse quantization. The interpretations of other symbols in the formula are consistent with those in the previous formula and are not repeated here. This neural network quantization operation can reduce the storage requirements and computational complexity during signal recognition, improving recognition efficiency while minimizing the need for accuracy and performance.

[0094] It should be noted that all specific values ​​such as the number of digits of the fixed-point number, the range of the integer part, the range of the decimal part, etc. are only for illustrative purposes. Staff can set them according to actual needs and are not limited here.

[0095] For ease of understanding, Figure 4 is a flow chart of an optional method for recognizing and classifying EEG signals according to an embodiment of the present invention, such as Figure 4 As shown, EEG signals are first collected and transmitted. The collected SSVEP signals can then undergo data preprocessing and feature extraction. This preprocessing includes, but is not limited to, signal amplification, baseline drift removal, and filtering to remove noise and enhance signal quality. Multiple features can be extracted from the preprocessed signals, such as time-domain features, frequency-domain features, and time-frequency features, which form the basis for SSVEP signal recognition. After preprocessing and feature extraction, the extracted features are input into a memristor array-level convolutional computation model. This model leverages the in-memory computing properties of memristors to perform post-processing for SSVEP signal recognition and classification, significantly reducing data transmission latency and power consumption while improving decoding speed. Finally, the classification results are transmitted back to the host system and displayed on a demonstration interface. The system also provides feedback, such as through a triangle prompt or screen flashing, to help users understand whether their actions have been correctly recognized by the system, forming a closed-loop interactive process, enabling host system display and feedback.

[0096] According to an embodiment of the present invention, an embodiment of a signal recognition system is provided. It should be noted that the system can be used to execute the above-mentioned signal recognition method. Figure 5 is a schematic diagram of a signal recognition system according to an embodiment of the present invention. Figure 5 As shown, the system includes: a signal acquisition device 502, which is used to acquire the original EEG signal of the test subject; a feature processing device 504, which is connected to the signal acquisition device 502, and is used to extract features from the acquired original EEG signal, construct an initial feature matrix of the original EEG signal, and reconstruct the initial feature matrix based on the module parameters of multiple target hardware modules in the signal recognition device 506 to obtain a target feature matrix, wherein the target feature matrix meets the processing conditions of multiple target hardware modules, the data dimension of the target feature matrix is ​​greater than the data dimension of the initial feature matrix, and the module parameters are obtained by editing the signal recognition parameters of the signal recognition model; the signal recognition device 506, which is connected to the feature processing device 504, and is used to recognize the original EEG signal based on the target feature matrix, obtain a signal recognition result, and return the signal recognition result to the feature processing device 504, wherein the signal recognition result is used to characterize the behavioral intention of the test subject; a result display device 508, which is connected to the feature processing device 504, and is used to output the signal recognition result.

[0097] The signal acquisition device can be a device for collecting EEG signals from the test subject. For example, the signal acquisition device can be an EEG cap, a flexible EEG patch, etc., but is not limited to such. The feature processing device can be a device for preprocessing and extracting features from the raw EEG signals. For example, the feature processing device can be a device containing host computer software, but is not limited to such. Such a device can be located between the signal acquisition device and the signal recognition device. The feature processing device can convert the raw EEG signals into a data format that can be analyzed by a computer and construct an initial feature matrix. The signal recognition device can be a device for receiving a target feature matrix and identifying or classifying the raw EEG signals based on a built-in signal recognition model. Such a device can be implemented based on a memristor chip embedded in an FPGA. The result display device can be a device for receiving and interpreting the signal recognition results transmitted by the signal recognition device. For example, the result display device can be a display, liquid crystal display, etc., but is not limited to such.

[0098] In an optional embodiment, the signal recognition system can select a signal acquisition device to collect the raw EEG signals of the test subject. For example, the signal recognition system can select an OpenBCI EEG cap, and use the electrodes on the EEG cap to contact the scalp of the test subject to collect the raw EEG signals. After collecting the raw EEG signals, the signal recognition system can use a feature processing device connected to the signal acquisition device to extract features from the collected raw EEG signals, parse out eigenvalues ​​including time domain, frequency domain, and time-frequency domain features from the raw EEG signals, and organize the extracted eigenvalues ​​into a matrix format according to samples and feature types, with each row representing a eigenvector of a signal time window and each column corresponding to a specific feature. Subsequently, the feature processing device can reconstruct the initial feature matrix to meet the input requirements of the hardware module. The reconstructed matrix, that is, the target feature matrix, can have a higher data dimension, allowing for more complex signal pattern recognition. After completing the reconstruction of the target feature matrix, the signal recognition device can complete the recognition process of the original EEG signal based on the target feature matrix through parallel computing of the hardware modules, thereby obtaining a signal recognition result. The signal recognition result includes the behavioral intention of the test subject. Subsequently, the signal recognition device can return the result to the feature processing device. The result display device can receive the signal recognition result returned by the signal recognition device and perform necessary post-processing (such as decoding and visualization) on the result, intuitively displaying the behavioral intention of the test subject through a graphical user interface.

[0099] For ease of understanding, Figure 6 FIG is a schematic diagram of an optional FPGA-based SSVEP EEG recognition system according to an embodiment of the present invention, Figure 6As shown, after the EEG cap collects the raw EEG signals of the test subject, it can be sent to the PC (Personal Computer) host via Bluetooth transmission. The PC host receives the raw EEG signals from the EEG cap and is responsible for the preliminary processing of the raw EEG signals. In addition, the PC host can also exchange data with the FPGA via the UDP protocol to ensure the continuity and coordination of signal processing. The FPGA receives the pre-processed signals from the PC host and uses an internally designed neural network model for in-depth processing, including convolution operations, feature analysis, etc., to identify and classify SSVEP signals. After completing the recognition and classification, the FPGA can return the recognition and classification results to the PC host, and the PC host can output the recognition and classification results to the display via the HDMI (High Definition Multimedia Interface) radio frequency line.

[0100] Furthermore, the signal identification device includes: a physical layer interface chip, connected to the feature processing device, for receiving a first data signal sent by the feature processing device, or sending a second data signal to the feature processing device, wherein the first data signal includes a signal corresponding to the target feature matrix and a signal corresponding to the signal identification result; a serial interface core, connected to the physical layer interface chip, for converting the data format of the first data signal received by the physical layer interface chip to obtain a third data signal, or converting the data format of the fourth data signal output by the media access control interface to obtain a second data signal; a media access control interface, connected to the physical layer interface chip through the serial interface core, for encapsulating the third data signal to obtain a fifth data signal, or parsing the sixth data signal to obtain a fourth data signal; a signal identification module, connected to the media access control interface, for performing signal identification on the fifth data signal, obtaining a signal identification result, and constructing a sixth data signal based on the signal identification result.

[0101] The physical layer interface chip may be a physical communication interface chip for connecting the hardware of the signal recognition device with other systems. For example, the physical layer interface chip may be an Ethernet PHY (Physical Layer) chip, but is not limited thereto.

[0102] The first data signal may be a signal sent by the feature processing device to the signal recognition device. The first data signal may include a signal corresponding to the target feature matrix and a signal corresponding to the signal recognition result. The first data signal must conform to the data format accepted by the physical layer interface chip to ensure that the signal recognition device can correctly read and process the feature data.

[0103] The second data signal may be a signal sent back to the feature processing device after the signal recognition device completes the recognition, and the second data signal may include a signal recognition result.

[0104] The serial interface core may be a device for converting signals from serial to parallel or from parallel to serial. The serial interface core may convert a first data signal received from the physical layer interface chip into a third data signal.

[0105] The third data signal may be a data signal that the serial interface converts the format of the first data signal and is then ready for processing by the media access control interface. The format of the third data signal must match the input format of the media access control interface to facilitate higher-level data encapsulation or parsing.

[0106] The media access control interface may be an interface for encapsulating or parsing data signals at the network layer. The media access control interface may encapsulate the third data signal into a fifth data signal for easy reading by the signal recognition module, and parse the sixth data signal into a fourth data signal.

[0107] The fourth data signal may be a signal identification result signal encapsulated by the media access control interface, and the fourth data signal may include information after signal identification is completed.

[0108] The fifth data signal may be the target characteristic matrix signal encapsulated by the media access control interface. The fifth data signal may be encapsulated and possibly have a network protocol header added, and then enter the signal recognition module for recognition processing.

[0109] The sixth data signal may be a packaged signal including a signal recognition result constructed by the signal recognition module after the signal recognition module completes the recognition of the fifth data signal.

[0110] In an optional embodiment, the physical layer interface chip can be responsible for establishing a physical connection with the feature processing device to enable bidirectional transmission of data signals. Specifically, when receiving a signal corresponding to a target feature matrix (a first data signal) from the feature processing device, the physical layer interface chip can decode it and provide it to subsequent components for processing. Similarly, the physical layer interface chip can also encode a signal corresponding to the signal recognition result (a second data signal) and send it back to the feature processing device, forming a closed loop of signal processing. The serial interface core can be closely connected to the physical layer interface chip, and its task is to perform format conversion on data signals. Specifically, when the physical layer interface chip receives the first data signal, the serial interface core can convert the first data signal from serial format to parallel format (a third data signal) to facilitate processing by subsequent components. After signal recognition is completed, the serial interface core can receive a fourth data signal from the media access control interface and convert the fourth data signal back to serial format (a second data signal) to facilitate transmission through the physical layer interface chip. The above-mentioned media access control interface is located between the serial interface core and the signal identification module. The media access control interface is responsible for the encapsulation and parsing of data packets. In the specific encapsulation process, the media access control interface can package the third data signal received from the serial interface core and add the necessary header information and check data to generate a fifth data signal suitable for network transmission. Subsequently, the media access control interface can send the above-mentioned fifth data signal to the signal identification module. After the signal identification module completes signal identification and generates a signal identification result, the media access control interface can receive the signal identification result (sixth data signal), parse the result, remove the header information, and obtain the above-mentioned fourth data signal. The above-mentioned fourth data signal can be format-converted by the serial interface core. The above-mentioned signal identification module can use a pre-trained model to perform signal identification based on the target feature matrix in the fifth data signal to obtain a signal identification result. The above-mentioned signal identification result can then be used to construct a sixth data signal, that is, information containing user behavior intentions. The media access control interface can encapsulate the sixth data signal. The encapsulated sixth data signal can be returned to the physical layer interface chip through the serial interface core and finally delivered to the feature processing device.

[0111] Furthermore, the physical layer interface chip includes: a media access control interface, used to communicate with the media access control interface based on a preset interface standard; a signal transceiver, connected to the media access control interface, used to receive a first data signal output by the media access control interface based on a low-voltage differential signal transmission technology, or to send a second data signal to the media access control interface based on a low-voltage differential signal transmission technology; an encoding and decoding circuit, connected to the signal transceiver, used to decode the received data signal and encode the sent data signal; a clock data recovery device, connected to the signal transceiver, used to ensure the synchronous transmission of the first data signal or the second data signal.

[0112] The above-mentioned preset interface standard may be a specific physical layer standard used in a communication link. For example, the above-mentioned preset interface standard may be GMII (Gigabit Media Independent Interface), SGMII (Serial Gigabit Media Independent Interface) or RGMII (Reduced Gigabit Media Independent Interface), but is not limited thereto. The above-mentioned preset interface standard defines the speed, encoding method, signal level, timing protocol, etc. of signal transmission to ensure physical layer compatibility and communication efficiency between different devices. The above-mentioned signal transceiver may be a bridge between a physical layer interface chip and an external communication medium. The above-mentioned signal transceiver may receive or send data signals based on low voltage differential signaling (LVDS) transmission technology. The above-mentioned encoding and decoding circuit may be a circuit for encoding a data signal to be transmitted for LVDS transmission and decoding a received LVDS signal. The above-mentioned clock data recovery device may be a device for analyzing a received data signal and extracting an accurate clock signal therefrom to ensure correct decoding of the data and synchronization of system operation.

[0113] In an optional embodiment, the above-mentioned media access control interface can serve as a bridge between the physical layer and higher-level protocols. The media access control interface can communicate with the media access control interface based on preset interface standards such as GMII, SGMII, RGMII, etc., to achieve coordination between the encapsulation and parsing of data packets, ensure the integrity of data packets and correctly control the timing of sending and receiving data on the physical media. The above-mentioned signal transceiver is closely connected to the media access control interface. The signal transceiver can be responsible for converting parallel data into serial data, or converting serial data into parallel data. In this context, the signal transceiver can receive the first data signal from the media access control interface based on LVDS technology, and can convert the first data signal into a high-speed serial signal for transmission. Similarly, when it is necessary to send a second data signal to the media access control interface, the signal transceiver can convert the serial signal back into parallel data to ensure that data can be smoothly exchanged between different components within the system. Furthermore, when a data signal is received from a signal transceiver, a decoding circuit can convert the serial data into its original digital signal format. Conversely, when the data needs to be transmitted via LVDS, an encoding circuit can convert the digital signal into a format suitable for LVDS transmission, thereby increasing the signal's DC balance and improving its anti-interference capabilities. Between the signal transceiver and the encoding / decoding circuit, a clock data recovery device can recover the clock signal in the received data. Specifically, the clock data recovery device can extract a synchronous clock signal from the high-speed serial data stream, thereby ensuring that the receiving end can correctly synchronize and decode the data. For the transmitted data signal, the clock data recovery device can generate a stable transmit clock, ensuring synchronous transmission of data on the LVDS link and avoiding data distortion and bit errors.

[0114] Furthermore, the feature processing device is further configured to broadcast an address resolution protocol request; and the signal identification device is further configured to, in response to receiving the address resolution protocol request, send a media access control address of the signal identification device to the feature processing device based on the address resolution protocol request.

[0115] In an optional embodiment, the feature processing device needs to establish communication with the signal identification device and other devices. In order to know the actual network location of the signal identification device, that is, the media access control address of the signal identification device, the feature processing device can broadcast a broadcast address resolution protocol request (Address Resolution Protocol, abbreviated as ARP). This request contains the IP (Internet Protocol) address of the feature processing device itself and the IP address of the target device it wants to resolve. The signal identification device can monitor the address resolution protocol requests on the network. When it receives an address resolution protocol request directed to itself, it will read the target IP address in the request and confirm that the request is sent to itself. Based on this, the signal identification device can construct a response packet corresponding to the above-mentioned address resolution protocol request. The response packet includes its own media access control address and IP address, and indicates the correspondence between the above-mentioned media access control address and IP address. After completing the construction of the above-mentioned response packet, the signal recognition device will not directly send the response packet back to the feature processing device, but will send the response packet to the host computer where the upper computer software is located through the network. The upper computer software monitors the response on the network. Once the response packet of the signal recognition device is received, it can parse the media access control address of the signal recognition device and establish a network communication link between the feature processing device and the signal recognition device. This mechanism ensures that even in a dynamic network environment, the various devices in the signal recognition system can quickly and accurately identify each other, thereby promoting efficient data transmission and the smooth progress of the EEG signal recognition process. The use of the address resolution protocol simplifies the process of establishing communication between the various devices in the signal recognition system, avoids lengthy address resolution before each communication, and contributes to the real-time performance and reliability of the signal recognition system.

[0116] For ease of understanding, the communication process in this embodiment is described by taking PC and VCU108 development board as an example. Specifically, the above-mentioned VCU108 development board can be configured with an LVDS-based SGMII interface Ethernet PHY chip. The above-mentioned PHY chip can adopt 88E1111 chip, which supports RGMII, GMII, SGMII and other interfaces to connect with the MAC layer. On the above-mentioned development board, an LVDS-based SGMII interface can be adopted between the PHY chip and the FPGA. When the PC is connected to the above-mentioned development board, this design implements the ping function, that is, sends an Echo request (message in ICMP) of the Internet Control Message Protocol (ICMP) to the development board, and confirms the connection by observing the response of the development board. In this process, the ARP protocol plays an important role. The specific steps are as follows:

[0117] Step S601: The PC sends an ARP request to the development board, requesting the MAC address (Media Access Control Address) of the development board. This step is to obtain the MAC address of the development board to ensure normal communication;

[0118] Step S602: After receiving the ARP request, the development board will respond with an ARP response packet containing the development board's MAC address and return the packet to the PC. This process ensures that the PC obtains the correct MAC address of the development board.

[0119] Step S603: In the connection confirmation phase, the PC sends an ICMP Echo request to the development board by implementing the ping function. If the development board can respond to the request normally, it means that the connection is normal, and it also proves that the ARP protocol is running effectively.

[0120] Step S604: After the connection is established, the PC will receive an ARP packet returned by the development board. This packet may include information such as the MAC address of the development board, thereby verifying that the connection between the PC and the FPGA is normal.

[0121] Furthermore, the signal identification device is connected to the feature processing device via a user datagram protocol.

[0122] In an optional embodiment, the signal recognition device can first create a UDP Socket (User Datagram Protocol Socket), which is equivalent to opening up an endpoint in the network environment that can receive and send UDP datagrams. Similarly, the feature processing device can also create a corresponding UDP Socket, ready to receive data sent by the signal recognition device. In the feature processing device, the feature data (such as the target feature matrix) formed after the original EEG signal is preprocessed and feature extracted needs to be encapsulated into a UDP datagram. This usually includes adding UDP headers before and after the data, including information such as the source port, destination port, length and checksum, to ensure the correct routing and integrity check of the data in the network. The feature processing device sends the encapsulated UDP datagram to the signal recognition device, and the signal recognition device listens to the specified UDP port. Once the datagram is received, the signal recognition device can parse the UDP header and extract the actual feature data for subsequent signal recognition process.

[0123] For ease of understanding, Figure 7 FIG. 1 is a detailed schematic diagram of an optional EEG signal recognition and classification process according to an embodiment of the present invention. Figure 7As shown, first, the test subject can wear an EEG cap to acquire raw EEG signals. These raw EEG signals can then undergo data preprocessing, which can include potential amplitude conversion, baseline offset removal, bandpass filtering, and floating-point to fixed-point conversion. After data preprocessing, the raw EEG signals can be further analyzed for features, specifically time-domain, frequency-domain, and time-frequency features. The preprocessed and analyzed signal features are then fed into an FPGA for computation. The FPGA utilizes its built-in hardware accelerator, such as a memristor-based convolutional computation model, to rapidly analyze and process these features. After initial processing on the FPGA, these signal features are fed into a CNN network for more refined recognition and classification of the SSVEP signals, and the results are then transmitted to the FPGA. The FPGA can then transmit the generated classification results to a display to match the interface display function. Triangular prompts or visual feedback on the display can indicate whether the test subject's selection was correctly identified by the signal recognition system.

[0124] Figure 8 is a schematic diagram of an optional communication process according to an embodiment of the present invention, such as Figure 8 As shown, the PC first converts the feature matrix (3, 28, 24) into its two's complement by converting binary fixed-point numbers to its two's complement. After specifying the data dimension, the data is sent to the FPGA in three packets. The FPGA then decodes three UDP protocol packets. Specifically, the FPGA decodes each packet and stores the data into a newly created empty matrix (3, 28, 24) by concatenating two bytes of data. The FPGA then inputs the feature matrix into a 16-bit quantized CNN network written in Veri Log. This network performs classification based on SSVEP features and outputs a 28-dimensional two's complement matrix, which is sent to the PC. Specifically, the FPGA writes the above two's complement matrix into a UDP protocol packet and sends it to the PC. The PC receives one packet and decodes the data to restore the (28, 1) matrix.

[0125] It should be noted that all specific values ​​such as the above-mentioned characteristic matrix, the number of UDP protocol packets, the dimension of the complement matrix, etc. are only for illustrative purposes. Staff can set them according to actual needs and are not limited here.

[0126] Specifically, Figure 9 Schematic diagram of an optional UDP protocol content according to an embodiment of the present invention, such as Figure 9As shown, the UDP protocol content includes source port, destination port, packet length, checksum and data content. Among them, the source port represents the sender of UDP data, the destination port represents the receiver of UDP sending, the packet length represents the total length of the sent UDP datagram, including the length of the header and data part, the checksum is a field used to detect data errors during transmission, and the data content represents the actual data part of the UDP datagram, which includes the actual data from the sender to the receiver. The construction and use process of the UDP programming server can be shown as follows:

[0127] Step S9011, use the socket() function to create a socket;

[0128] Step S9012 (optional): Use the setsockopt() function to set the properties of the socket.

[0129] Step S9013, use the bind() function to bind the IP address, port and other information to the above socket;

[0130] Step S9014, using the recvfrom() function to receive data in a loop;

[0131] Step S9015, close the network connection.

[0132] Among them, the socket() function is used to create a socket, the setsockopt() function is used to set socket properties and adjust the behavior of the socket, the bind() function is used to bind the socket to a specific IP address and port number to receive or send data, and the recvfrom() function is used to receive data packets from the client and obtain the client address and port that sent the data. Correspondingly, the client construction and use process of UDP programming can be as follows:

[0133] Step S9021, using the socket() function to create a socket;

[0134] Step S9022 (optional): Use the setsockopt() function to set the properties of the socket.

[0135] Step S9023 (optional): Use the bind() function to bind the IP address, port and other information to the socket.

[0136] Step S9024, setting the other party's IP address, port and other attributes;

[0137] Step S9025, use the sendto() function to send data;

[0138] Step S9026, close the network connection.

[0139] Among them, the sendto() function represents a function used to send a data packet from the current socket to a specified address. The interpretations of other functions in steps S9021 to S9026 are consistent with the aforementioned steps and will not be repeated here.

[0140] An embodiment of the present application further provides an electronic device, comprising: a memory storing an executable program; and a processor for running the program, wherein the program executes the methods of various embodiments of the present invention when running.

[0141] An embodiment of the present application further provides a computer-readable storage medium, which includes a stored executable program, wherein when the executable program is running, the device where the computer-readable storage medium is located is controlled to execute the methods in various embodiments of the present invention.

[0142] An embodiment of the present application further provides a computer program product, including a computer program, which implements the methods in various embodiments of the present invention when executed by a processor.

[0143] An embodiment of the present application further provides a computer program product, including a non-volatile computer-readable storage medium, wherein the non-volatile computer-readable storage medium is used to store a computer program, and when the computer program is executed by a processor, the method in each embodiment of the present invention is implemented.

[0144] The embodiments of the present application further provide a computer program, which implements the methods in the above-mentioned embodiments of the present invention when executed by a processor.

[0145] In the above embodiments of the present invention, the description of each embodiment has its own focus. For parts that are not described in detail in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

[0146] In the several embodiments provided in this application, it should be understood that the disclosed technical content can be implemented in other ways. Among them, the device embodiments described above are only exemplary. For example, the division of the units can be a logical function division. In actual implementation, there may be other division methods, such as multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some interfaces, indirect coupling or communication connection of units or modules, which can be electrical or other forms.

[0147] The units described as separate components may or may not be physically separate, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed across multiple units. Some or all of the units may be selected according to actual needs to achieve the purpose of the present embodiment.

[0148] In addition, the functional units in the various embodiments of the present invention may be integrated into a single processing unit, each unit may exist physically separately, or two or more units may be integrated into a single unit. The aforementioned integrated units may be implemented in the form of hardware or software functional units.

[0149] If the integrated unit is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present invention, or the part that contributes to the prior art, or all or part of the technical solution can be embodied in the form of a software product. The computer software product is stored in a storage medium and includes several instructions for enabling a computer device (which can be a personal computer, server or network device, etc.) to perform all or part of the steps of the method described in each embodiment of the present invention. The aforementioned storage medium includes: U disk, read-only memory (ROM, Read-Only Memory), random access memory (RAM, Random Access Memory), mobile hard disk, magnetic disk or optical disk, etc. Various media that can store program codes.

[0150] The above is only a preferred embodiment of the present invention. It should be pointed out that for ordinary technicians in this technical field, several improvements and modifications can be made without departing from the principles of the present invention. These improvements and modifications should also be regarded as the scope of protection of the present invention.

Claims

1. A signal recognition method, characterized in that: include: Obtaining the original EEG signals of the test subject; Extracting features from the original EEG signal to construct an initial feature matrix of the original EEG signal; Reconstructing the initial feature matrix based on module parameters of multiple target hardware modules in the signal recognition device to obtain a target feature matrix, wherein the target feature matrix satisfies processing conditions of the multiple target hardware modules and has a data dimension greater than a data dimension of the initial feature matrix; The target feature matrix is ​​input into the signal recognition device, and the original EEG signal is recognized by the signal recognition device to obtain a signal recognition result, wherein the signal recognition result is used to characterize the behavioral intention of the test subject.

2. The method according to claim 1, characterized in that The signal recognition device is a device configured based on a signal recognition model, and the method further includes: Analyzing the signal recognition model to determine signal recognition parameters of multiple signal recognition modules included in the signal recognition model and execution logic between different signal recognition modules; Configuring a plurality of initial hardware modules based on the signal recognition parameters of the plurality of signal recognition modules to obtain the plurality of target hardware modules; Compiling initial operation logic between the plurality of target hardware modules based on the execution logic to obtain target operation logic; The signal recognition device is constructed based on the target operation logic and the multiple target hardware modules.

3. The method according to claim 2, characterized in that The signal identification parameters include at least a processing weight corresponding to the signal identification module, the initial hardware module includes at least an initial storage module, and the target hardware module includes at least a target storage module; configuring the multiple initial hardware modules based on the signal identification parameters of the multiple signal identification modules to obtain the multiple target hardware modules includes: Obtaining data encoding and application order corresponding to the processing weights; determining a storage code corresponding to the processing weight based on the data code, wherein the storage code is used to represent data corresponding to the processing weight when the processing weight is stored in the target storage module; Performing data conversion on the stored code to obtain a weight matrix corresponding to the processing weight; The weight matrix is ​​stored in the initial storage module based on the application order to obtain the target storage module.

4. The method according to claim 2, characterized in that After constructing the signal recognition device based on the target operation logic and the plurality of target hardware modules, the method further includes: Inputting a test EEG signal into the signal recognition model based on the test device to obtain model recognition results output by different signal recognition modules in the signal recognition model, and inputting the test EEG signal into the signal recognition device to obtain hardware processing results output by different target hardware modules in the signal recognition device; Verifying the hardware processing result based on the model recognition result to obtain a signal verification result, wherein the signal verification result is used to indicate whether the execution logic between different signal recognition modules matches the target operation logic between different target hardware modules; In response to the signal verification result being that the execution logic matches the target operation logic, it is determined that the signal recognition device is constructed successfully.

5. The method according to claim 4, characterized in that The method further comprises: In response to the signal verification result indicating that the execution logic does not match the target operation logic, determining an erroneous hardware module from the target hardware modules based on the signal verification result, wherein the operation logic of the erroneous hardware module is different from the execution logic of the corresponding signal identification module; Adjusting module parameters of the faulty hardware module based on the model recognition result and signal recognition parameters corresponding to the faulty hardware module to obtain a new hardware module, wherein the target operation logic of the new hardware module matches the execution logic of the corresponding signal recognition module; The signal recognition device is updated based on the new hardware module, and it is determined that the signal recognition device is successfully constructed.

6. The method according to claim 4, characterized in that The testing device satisfies at least one of the following conditions: The data format of the test data output by the testing device is a preset format, and the test data includes the test EEG signal; The application scenario of the test data output by the test device includes a preset scenario, wherein the preset scenario includes a scenario for obtaining the original EEG signal; The time delay of the test device outputting the test data is less than a preset threshold; The test device has a resending function, wherein the resending function is used to represent resending the test data when sending the test data fails.

7. A signal recognition system, characterized in that: include: A signal acquisition device for acquiring raw EEG signals from the test subject; a feature processing device, connected to the signal acquisition device, for extracting features from the collected raw EEG signals, constructing an initial feature matrix of the raw EEG signals, and reconstructing the initial feature matrix based on module parameters of multiple target hardware modules in the signal recognition device to obtain a target feature matrix, wherein the target feature matrix satisfies processing conditions of the multiple target hardware modules, the data dimension of the target feature matrix is ​​greater than the data dimension of the initial feature matrix, and the module parameters are obtained by editing the signal recognition parameters of the signal recognition model; The signal recognition device is connected to the feature processing device and is used to recognize the original EEG signal based on the target feature matrix, obtain a signal recognition result, and return the signal recognition result to the feature processing device, wherein the signal recognition result is used to characterize the behavioral intention of the test subject; A result display device is connected to the feature processing device and is used to output the signal recognition result.

8. The system according to claim 7, characterized in that The signal recognition device comprises: a physical layer interface chip connected to the feature processing device and configured to receive a first data signal sent by the feature processing device, or to send a second data signal to the feature processing device, wherein the first data signal includes a signal corresponding to the target feature matrix and a signal corresponding to the signal recognition result; a serial interface core connected to the physical layer interface chip and configured to convert the data format of a first data signal received by the physical layer interface chip to obtain a third data signal, or to convert the data format of a fourth data signal output by a media access control interface to obtain the second data signal; The media access control interface is connected to the physical layer interface chip through the serial interface core, and is used to encapsulate the third data signal to obtain the fifth data signal, or to parse the sixth data signal to obtain the fourth data signal; A signal identification module is connected to the media access control interface, and is configured to perform signal identification on the fifth data signal, obtain the signal identification result, and construct the sixth data signal based on the signal identification result.

9. The system according to claim 8, characterized in that The physical layer interface chip includes: a media access control interface, configured to communicate with the media access control interface based on a preset interface standard; a signal transceiver connected to the media access control interface, and configured to receive the first data signal output by the media access control interface based on a low voltage differential signaling transmission technology, or to send the second data signal to the media access control interface based on the low voltage differential signaling transmission technology; An encoding and decoding circuit, connected to the signal transceiver, for decoding received data signals and encoding transmitted data signals; A clock data recovery device is connected to the signal transceiver and is used to ensure synchronous transmission of the first data signal or the second data signal.

10. The system according to claim 7, wherein: The feature processing device is further configured to broadcast an address resolution protocol request; and the signal identification device is further configured to, in response to receiving the address resolution protocol request, send a media access control address of the signal identification device to the feature processing device based on the address resolution protocol request.

11. The system according to claim 7, wherein: The signal identification device is connected to the feature processing device via the User Datagram Protocol.

12. An electronic device, characterized in that: include: a memory storing an executable program; A processor, configured to run the program, wherein the program executes the method according to any one of claims 1 to 6 when running.

13. A computer-readable storage medium, characterized in that The computer-readable storage medium includes a stored executable program, wherein when the executable program is run, the device where the storage medium is located is controlled to execute the method according to any one of claims 1 to 6.

14. A computer program product, characterized in that The invention comprises a computer program which, when executed by a processor, implements the method according to any one of claims 1 to 6.

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