Wafer-level multi-chip metal wiring method and wafer

Abstract

The invention relates to the technical field of integrated circuit manufacturing, in particular to a wafer-level multi-chip metal wiring method and a wafer. Metal wires are arranged in a layered mode, and preset intervals are set for isolation; jumper connection between the metal wires of different metal layers is achieved through the through holes at the intersections of the scribing grooves, high-density signal transmission is achieved through the multiple layers of metal wires, and the situation that two adjacent metal wires are short-circuited together due to cutting extrusion during scribing can be prevented through cross-layer jumpers and interval isolation arrangement of the metal wires. By means of the layered metal wiring structure and spaced wiring, efficient data burning of thousands of chips on the wafer is achieved, stray capacitance and short circuit risks are remarkably reduced, meanwhile, the wafer utilization rate and burning efficiency are improved, the number and grouping mode of the chip arrays can be flexibly adjusted according to requirements, and the method is suitable for large-scale popularization and application. And the manufacturing requirements of chips with different scales are met.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuit manufacturing, and in particular to a metal wiring method for wafer-level multi-chips and a wafer. Background Art

[0002] In the integrated circuit manufacturing process, chip data programming is a critical step. Traditional chip data programming methods can only program one or dozens of chips at a time. For example, programming is performed one chip at a time on a specific fixture, multiple chips are connected to a onewire transmission line for data programming, and multiple chips can be programmed at once using protocols such as the Serial Peripheral Interface (SPI). If efficiency is to be further improved and costs reduced, the aforementioned programming methods cannot meet the requirements. These methods have limited drive capabilities and can typically only support the simultaneous programming of a small number of chips, at most dozens or even hundreds.

[0003] To meet the requirement of programming thousands of chips at the wafer level at once, traditional methods require cutting and packaging the chips before programming. This programming method requires programming one chip using a fixture and then mechanically replacing it with the next, which is inefficient and costly. Furthermore, soldering the chips to a printed circuit board (PCB) after packaging introduces significant parasitic capacitance, further limiting the drive capability of the data programming interface.

[0004] In view of this, overcoming the defects of the prior art is an urgent problem to be solved in this technical field. Summary of the Invention

[0005] The technical problem to be solved by the present invention is how to solve the problem of low efficiency in burning chip data in the prior art.

[0006] The present invention adopts the following technical solutions: In a first aspect, a wafer-level multi-chip metal wiring method is provided, comprising: Setting metal traces in the wafer scribe lines; arranging the metal traces in layers and isolating them at predetermined intervals; At the intersection of the scribe lines, jumper connections between metal traces on different metal layers are achieved through through-holes; The interface chip and the corresponding metal wiring transmit the programming data from the data programming module to each programming chip on the wafer. After receiving the corresponding programming data, each programming chip completes its own programming through the preset communication protocol.

[0007] Preferably, the method further comprises: The chip array is divided into a plurality of areas, and at least one interface chip is arranged at the edge of each area. The programming chip in each area is connected to the at least one interface chip via a data return line.

[0008] Preferably, a first metal layer, a second metal layer, a third metal layer, and a fourth metal layer are sequentially arranged in the scribe lines of the wafer; wherein the first metal layer is used to carry power lines, ground lines, and data lines; The second metal layer is used to realize jumper connection of different metal layers at the intersection of the scribe lines; The third metal layer is used for laying data return lines and control signal lines; The fourth metal layer is used for laying out the power line of the programming chip.

[0009] Preferably, a through-hole layer is provided between the third metal layer and the fourth metal layer to achieve isolation of the metal layers in the longitudinal direction.

[0010] Preferably, adjacent metal traces alternately use different metal layers in the horizontal and vertical directions and are isolated by a preset spacing, and the lateral spacing between adjacent metal traces is not less than 0.5 μm; The longitudinal spacing between different metal layers is set according to preset process parameters, wherein the longitudinal spacing between the first metal layer and the second metal layer is not less than 3 μm.

[0011] Preferably, the method further comprises: Divide the chip array on the wafer into multiple areas, each area corresponds to a set of data return lines; Each set of data return lines is driven by a buffer in the programming chip. Only one buffer is allowed to output data at the same time, and the buffers in the other programming chips remain in a high-impedance state to avoid bus conflicts.

[0012] Preferably, the method further comprises: In the incomplete block at the edge of the wafer, the data return line of the programming chip at the edge is connected to the nearest interface chip through the metal traces in the scribe line; Redundant metal lines are added to the edge area of ​​the scribe line to compensate for the wiring loss caused by incomplete blocks, ensuring that all burned chips can be connected to the interface chip through at least one path.

[0013] Preferably, the method further comprises: A plurality of pads are provided at the interface chip, wherein the pads are respectively connected to the power line, the ground line and the data line in the scribe groove; The probe is electrically connected to the pad through the probe machine to realize data burning of the chip on the wafer.

[0014] Preferably, the method further comprises: The width and thickness of the metal traces are dynamically set according to the current density and signal integrity requirements, wherein: the width of the power line is greater than or equal to 5μm, and the thickness is greater than or equal to 3μm; the width of the data line is greater than or equal to 2μm, and the thickness is greater than or equal to 0.2μm; the width of the clock line and the control signal line is greater than or equal to 1μm, and the thickness is greater than or equal to 0.2μm.

[0015] In a second aspect, a wafer for multi-chip programming is provided, wherein the layout of metal traces is achieved by the metal wiring method as described in the first aspect; The wafer includes at least one interface chip, a plurality of burning chips and metal traces, and the metal traces are arranged in the scribe lines of the wafer; The interface chip is connected to different programming chips respectively through the metal wiring; The interface chip is used to be connected to the output end of the data burning module to receive the burning data sent by the data burning module; The interface chip is used to transmit the programming data to the programming chip through the metal wiring; The programming chip is used to complete chip programming according to a preset communication protocol and the programming data.

[0016] Compared with the prior art, the present invention has the following beneficial effects: On the one hand, the present invention arranges metal traces in the wafer scribe grooves, and transmits the programming data from the data programming module to each programming chip on the wafer through the interface chip and the corresponding metal traces. After receiving the corresponding programming data, each programming chip completes its own programming through a preset communication protocol. By arranging the metal traces in the wafer scribe grooves and then performing chip programming, the parasitic capacitance is much lower than the capacitance soldered on the PCB board after packaging, thereby improving the reliability of signal transmission.

[0017] On the other hand, the present invention arranges the metal traces in layers and sets preset spacing for isolation; jumper connections between metal traces of different metal layers are achieved through through holes at the intersection of the dicing grooves, and multi-layer metal traces achieve high-density signal transmission. By setting cross-layer jumpers and spacing isolation for the metal traces, two adjacent metal traces can be prevented from short-circuiting due to cutting and extrusion during dicing.

[0018] In summary, the present invention achieves efficient data burning of thousands of chips on a wafer through a layered metal wiring structure and spaced wiring. This method significantly reduces parasitic capacitance and short-circuit risks, while improving wafer utilization and burning efficiency. The number and grouping of chip arrays can be flexibly adjusted according to demand, and is suitable for chip manufacturing needs of different scales. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0020] Figure 1 This is a flow chart of a wafer-level multi-chip metal wiring method provided by an embodiment of the present invention; Figure 2 This is a schematic diagram of an interface chip provided by an embodiment of the present invention; Figure 3 This is a schematic diagram of a chip array and layered metal wiring provided by an embodiment of the present invention; Figure 4 This is a schematic diagram of a mesh layout structure of an RX metal line provided by an embodiment of the present invention; Figure 5 1 is a schematic diagram of a mesh layout structure of a VDD metal line provided by an embodiment of the present invention; Figure 6 This is a schematic diagram of a mesh layout structure of a tx0 metal line provided by an embodiment of the present invention; Figure 7 This is a schematic diagram of a mesh layout structure of a tx1 metal line provided by an embodiment of the present invention; Figure 8 This is a schematic diagram of a mesh layout structure of a tx2 metal line provided by an embodiment of the present invention; Figure 9 This is a schematic diagram of a mesh layout structure of a tx3 metal line provided by an embodiment of the present invention; Figure 10 This is a schematic diagram of a cross-sectional structure of a metal wire close to the longitudinal axis of an interface chip provided by an embodiment of the present invention; Figure 11 1 is a schematic diagram of a cross-sectional structure of a metal wire along a longitudinal axis provided by an embodiment of the present invention; Figure 12 This is a schematic diagram of a cross-sectional structure of a metal wire along a horizontal axis provided by an embodiment of the present invention; Figure 13 This is a schematic structural diagram of a wafer for multi-chip programming provided by an embodiment of the present invention; Figure 14 This is a schematic structural diagram of a metal routing of a chip on a wafer provided by an embodiment of the present invention; Figure 15 This is a schematic structural diagram of an interface chip provided by an embodiment of the present invention; Figure 16 This is a schematic structural diagram of a programming chip provided by an embodiment of the present invention; Figure 17 The present invention provides a flow chart of a wafer-level multi-chip data burning method. DETAILED DESCRIPTION

[0021] In order to make the purpose, technical solutions and advantages of the present invention more clearly understood, the present invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not intended to limit the present invention.

[0022] Unless the context requires otherwise, throughout the specification and claims, the term "including" is to be interpreted as meaning open inclusion, that is, "including, but not limited to". In the description of the specification, the terms "one embodiment", "some embodiments", "exemplary embodiments", "example", "specific example" or "some examples" and the like are intended to indicate that the specific features, structures, materials or characteristics associated with the embodiment or example are included in at least one embodiment or example of the present disclosure. The schematic representation of the above terms does not necessarily refer to the same embodiment or example. In addition, the specific features, structures, materials or characteristics may be included in any one or more embodiments or examples in any appropriate manner, that is, although they may be carried in the embodiments or examples of the above terms due to reasons such as the order and position of appearance, it is not limited to that they can be carried in combination by one embodiment or example.

[0023] In the description of the present invention, the terms "first" and "second" are used for descriptive purposes only, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, the features defined as "first" and "second" may explicitly or implicitly include one or more of the features. In the description of the embodiments of the present disclosure, unless otherwise specified, "multiple" means two or more. In addition, for example, the description may also use the method of adding "A" and "B" at the end to describe the same type of nouns as two independent individuals. In this case, the corresponding features defined as "A" and "B" are only used to distinguish the description purposes of the same type of individuals, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated.

[0024] When describing some embodiments, the expressions “coupled”, “coupled” and “connected” and their derivatives may be used. For example, when describing some embodiments, the term “connected” may be used to indicate that two or more components are in direct physical or electrical contact with each other. For another example, when describing some embodiments, the term “coupled” may be used to indicate that two or more components are in direct physical or electrical contact. However, the term “connected” or “coupled” may also mean that two or more components are not in direct contact with each other, but still cooperate or interact with each other, such as “optical coupling”, “wireless connection”, etc. The embodiments disclosed herein are not necessarily limited to the contents of the present invention.

[0025] In addition, the technical features involved in the various embodiments of the present invention described below can be combined with each other as long as they do not conflict with each other.

[0026] Example 1: In order to solve the problems of the prior art, this embodiment proposes a wafer-level multi-chip metal wiring method. In one embodiment, Figure 1 Shown, including: Step 101: Setting metal traces in the scribe lines of the wafer; arranging the metal traces in layers and setting preset spacing for isolation.

[0027] The metal traces may include power lines (VPP, VCC, and VDD), ground lines (VSS), data lines (rx and tx), a clock line (clk), a clock select signal (clk_sel), and a power-on reset signal (rstn). clk, clk_sel, and rstn can be retained based on actual needs. The width and thickness of the metal traces can be dynamically adjusted based on current density and signal integrity requirements. Power lines must be 5μm or wider and 3μm or thicker; data lines must be 2μm or wider and 0.2μm or thicker; and clock and control signal lines must be 1μm or wider and 0.2μm or thicker.

[0028] Step 102: Implement jumper connections between metal traces on different metal layers through through-holes at the intersections of the scribe lines.

[0029] In one embodiment, a first metal layer, a second metal layer, a third metal layer, and a fourth metal layer are sequentially arranged in the wafer's scribe lines. The first metal layer carries power lines, ground lines, and data lines; the second metal layer enables jumper connections between different metal layers at the intersections of the scribe lines; the third metal layer routes data return lines and control signal lines; and the fourth metal layer routes power lines for programming chips. In one embodiment, a via layer is provided between the third and fourth metal layers to vertically isolate the metal layers. The via layer acts as a through hole, vertically isolating the metal layers one at a time.

[0030] In one embodiment, adjacent metal traces use different metal layers alternately in the horizontal and vertical directions and are isolated by a preset spacing, and the lateral spacing between adjacent metal traces is not less than 0.5 μm; the vertical spacing between different metal layers is set according to preset process parameters, wherein the vertical spacing between the first metal layer and the second metal layer is not less than 3 μm.

[0031] Step 103: The interface chip and corresponding metal traces transmit the programming data from the data programming module to each programming chip on the wafer. After receiving the corresponding programming data, each programming chip completes its own programming through a preset communication protocol.

[0032] Among them, multiple groups of pads are set at the interface chip, and the pads are respectively connected to the power line, ground line and data line in the dicing groove; the probe is electrically connected to the pad through the probe machine to realize data burning of the chip on the wafer.

[0033] The data programming module sends the programming data to the interface chip, which then transmits the programming data to the target programming chip through the interface chip and corresponding metal traces. All programming chips receive the programming data and write it into their internal storage units according to the preset communication protocol, completing the programming of each programming chip. The preset communication protocol can be the OneWire protocol.

[0034] It is worth noting that in this embodiment, because the programming chip has a built-in one-time programming memory, programming data requires a high-voltage power supply VPP of 5V or above. Whether this power supply is needed or other power supplies are added should be determined according to actual needs. After dicing is completed, VPP is powered by an internal low-voltage difference linear regulator; VCC powers the programming interface, and VDD powers the programming chip. When VCC is not powered, the programming interface data lines and backup clock signal lines (rx, tx0, tx1, tx2, tx3, clk, clk_sel, rstn) are invalid, which does not affect the normal operation of the chip. The same is true after dicing is completed. The layout of the metal layer needs to ensure that VCC, VPP and VDD will not be short-circuited.

[0035] On the one hand, this embodiment arranges metal traces in the wafer's scribe grooves, and the interface chip and the corresponding metal traces transmit the programming data from the data programming module to each programming chip on the wafer. After receiving the corresponding programming data, each programming chip completes its own programming through a preset communication protocol. By arranging metal traces in the wafer scribe grooves and then performing chip programming, the parasitic capacitance is much lower than the capacitance soldered on the PCB board after packaging, thereby improving the reliability of signal transmission.

[0036] On the other hand, this embodiment arranges the metal traces in layers and sets a preset spacing for isolation; at the intersection of the dicing grooves, jumper connections between metal traces of different metal layers are achieved through through holes, and multi-layer metal traces achieve high-density signal transmission. By setting cross-layer jumpers and spacing isolation for the metal traces, two adjacent metal traces can be prevented from short-circuiting due to cutting and extrusion during dicing.

[0037] In summary, this embodiment achieves efficient data burning of thousands of chips on a wafer through a layered metal wiring structure and spaced wiring. This method significantly reduces parasitic capacitance and short circuit risks, while improving wafer utilization and burning efficiency. The number and grouping of chip arrays can be flexibly adjusted according to demand, and is suitable for chip manufacturing needs of different scales.

[0038] If only a single interface chip is set on the wafer, the distance between the burning chip at the edge and the single interface chip is far (possibly several centimeters), and the resistance and capacitance effects of the metal routing are significant, resulting in signal attenuation, timing delay, and increased burning failure rate. The chip layout at the edge of the irregular wafer is scattered, and it is difficult for a global single interface chip to cover all edge chips through a unified routing network. Some corner chips may not be burned normally. During global unified burning, all burning chips need to wait for the same interface chip to process data in sequence. Especially for edge chips, the waiting time accounts for a higher proportion. In order to burn the burning chip at the edge of an irregular wafer, in one embodiment, the wafer-level multi-chip metal wiring method also includes: dividing the chip array into multiple areas, and setting at least one interface chip at the edge of each area, and the burning chip in each area is connected to at least one interface chip through a data return line.

[0039] In one embodiment, the chip array on the wafer is divided into multiple areas, each area corresponds to a group of data return lines; each group of data return lines is driven by the buffer in the burning chip, and only one buffer is allowed to output data at the same time, and the buffers in the other burning chips remain in a high impedance state to avoid bus conflicts. Figure 2 and Figure 3 As shown, each of the four areas has an interface chip (P0, P1, P2 and P3), and the rest are programming chips.

[0040] By deploying interface chips close to the edge of the wafer, signal quality can be significantly improved. Each interface chip can independently receive instructions related to data programming, significantly increasing processing efficiency across the entire wafer. Furthermore, interface chips at the wafer edge can be flexibly assigned to corresponding zones based on the wafer's actual contours, avoiding wiring challenges caused by irregular wafer shapes.

[0041] In order to further solve the above wiring problem, in one embodiment, referring to Figure 3 In the incomplete blocks at the edge of the wafer, the data return lines of the programming chips at the edge are connected to the nearest interface chip via metal traces in the scribe lines. The chips on the wafer can be divided into four areas, with the chips at the four corners of each area set as interface chips, and the remaining chips as programming chips. Each interface chip is responsible for programming the programming chips in its corresponding area and serves as a data interface for communication with the data programming module. The four corner interface chips simplify the layout of the metal traces, and their placement at the edge facilitates connection to the data programming module, significantly reducing the complexity of the metal trace layout.

[0042] Due to the incompleteness of the wafer edge blocks caused by the cut contour, some scribe lines are truncated, preventing the traditional metal routing network from forming a complete path. The scattered chip layout in the edge area and the narrow scribe line width lead to insufficient metal routing or excessive spacing, which can easily lead to signal blind spots. To address this issue, in one embodiment, redundant metal lines are added to the scribe lines in the edge area to compensate for the missing wiring caused by the incomplete blocks, ensuring that all programmed chips can connect to the interface chip through at least one path.

[0043] Specifically, redundant horizontal and vertical traces are added to the edge of the scribe grooves to ensure that at least two paths exist between any two points: a primary path and a backup path. Redundant traces with the same topology are set up on different metal layers, and inter-layer interconnection is achieved through vias. Some of the redundant traces are dedicated to power backup, while others are used for signal transmission, preventing single-point failures from affecting the overall power supply. The interface chip detects the resistance value of each path and automatically selects the optimal path (the one with the lowest resistance and the strongest signal) for data transmission. If the primary path fails, the system switches from the primary path to the backup path within a preset time (e.g., 10ns) to ensure uninterrupted communication.

[0044] In one embodiment, independent voltage monitoring units can be set on both the main path and the backup path of the power line, and the voltage detection results of the voltage detection unit can be obtained in real time. The voltage fluctuations of the main power path and the backup power path can be compared in real time based on the voltage detection results. When the voltage drop of the main power path exceeds the threshold, it automatically switches to the backup path. The same applies in reverse. In one embodiment, a micro resistor sensor (such as a piezoresistive sensor based on CMOS technology) can be integrated into each metal trace to measure the resistance value in real time. The sensor accuracy must reach ±0.1Ω to distinguish the subtle differences between different paths. A path evaluation unit is built into the interface chip, which periodically (such as every 100ms) sends detection pulses to each path, calculates the signal quality based on the echo signal strength and phase, and comprehensively evaluates the quality of the path based on the resistance value, and selects the appropriate path for data or voltage transmission.

[0045] Example 2: To further illustrate the wafer-level multi-chip metal routing method in Example 1, this embodiment provides a specific example. Taking a block of a wafer containing 1024 chips as an example, the metal routing includes VPP, VCC, VDD, VSS, clk_sel, rstn, clk, rx, tx0, tx1, tx2, and tx3.

[0046] In one embodiment, referring to Figure 2 The diagram below shows the interface chip interface, with the inner rectangle representing the pad. The four interface chips P0, P1, P2, and P3 are all connected to the VPP, VCC, VDD, VSS, clk_sel, rstn, clk, rx, tx0, tx1, tx2, and tx3 lines in the scribe lines. The programming chips in the four chip regions C0, C1, C2, and C3, in addition to connecting to VPP, VCC, VDD, VSS, clk_sel, rstn, clk, and rx, only need to connect the data return line tx corresponding to each programming chip in each region to a corresponding one of tx0, tx1, tx2, or tx3. Therefore, with the exception of tx, all metal lines with the same name in all chips in the array are connected together. With this layout, the probe machine only needs to operate any one of P0, P1, P2, or P3 to complete data programming for all 1020 chips in the array.

[0047] Reference Figure 3This is a schematic diagram of the chip array and layered metal wiring. Metal traces are arranged in the chip array's scribe grooves, including three power lines (VPP, VCC, and VDD), one ground line (VSS), five data lines (rx, tx0, tx1, tx2, tx3), a clock line (clk), a clock select signal line (clk_sel), and a power-on reset signal line (rstn). The function of each metal line is not described in detail here. In one embodiment, 1024 chips are integrated into a single block of a wafer to form a chip array (there are multiple metal lines in the scribe grooves, and the width of the scribe grooves is not in a fixed ratio to the width and length of the chips). The chips at the four corners of the chip array are set as interface chips (P0, P1, P2, and P3). The remaining 1020 chips are programming chips. C0, C1, C2, and C3 represent programming chips located in four different areas. They can be the same or different models (but the chip size must remain consistent). Each area has 255 programming chips. The specific number can be expanded or reduced according to demand to expand or reduce the array size.

[0048] In one embodiment, referring to Figure 3 In order to distinguish different metal lines, color drawings are used for illustration. Among them, blue metal lines represent metal traces of the first metal layer, green metal lines represent metal traces of the second metal layer, orange metal lines represent metal traces of the third metal layer, and black metal lines represent metal traces of the fourth metal layer. The via layer is not shown in the figure.

[0049] In one embodiment, Figure 4 The figure shows the mesh layout of the data line rx. Figure 5 This is the mesh layout of the power line VDD. Because except for the data lines tx (including tx0, tx1, tx2 and tx3), all the metal lines with the same name in the chip are connected together. Therefore, except for the metal layer, the metal line layout of the two (rx and VDD) is the same. Figure 4 and Figure 5 It can also represent the layout of other metal lines besides tx0, tx1, tx2 and tx3. Figure 4 and Figure 5 As you can see, the metal wires are routed every other row (or column), totaling 16 both horizontally and vertically. The intersections are connected by punched holes. This wiring method ensures that even though each metal wire is not very thick, the combined width is substantial and evenly distributed, fully meeting the current density requirements.

[0050] In one embodiment, Figure 6The figure shows the mesh layout of data line tx0, with four interface chips located in four corners. It can be seen that in the C0 area, the metal wires of data line tx0 are wired in the first metal layer with one row (or one column) between them, with a total of eight wires in both directions. The first and eighth wires (counted from left to right) are punched at the boundary between C0 and C1 (i.e., dotted line X) and jumpered to the third metal layer. The third metal layer is then extended to the C1 area, so that the first metal wire of data line tx0 can be connected to the interface chips P0 and P1 in the C0 and C1 areas respectively. Figure 6 On the horizontal axis, 6 metal wires are arranged on the second metal layer, passing through the C2 and C3 areas respectively, and connected to the 8th metal wire through the holes in the C0 and C1 areas. The metal wires arranged on the third metal layer on the scribe grooves near the interface chips in the C2 and C3 areas are connected to the 6 metal wire through holes on the horizontal axis, and can be connected to the interface chips P2 and P3 in the C2 and C3 areas respectively. The layout of tx1, tx2 and tx3 is similar, as shown below. Figure 7 、 Figure 8 、 Figure 9 As shown in the figure, the four data return lines (tx0, tx1, tx2, and tx3) are connected (or selectively connected) to one or more of the four interface chips. This array can be scaled to meet specific needs. For example, if a 4096-chip array is used, the tx bus can be expanded to 16. Additional signal lines can also be added to the scribe lines as needed, provided the necessary conditions are met. In short, this creates a mutual avoidance feature between the tx0-tx3 data lines.

[0051] In one embodiment, Figure 10 The figure shows a cross-sectional view of the metal line in the vertical axis of the interface chip scribe groove in the data line tx0 area. In this example, the metal line width is 2um, the thickness of the first metal layer is 3um, and the thickness of other metal lines is 0.2um. The height of the metal line in the cross-sectional view represents the different levels of the metal line. Figure 10 From top to bottom, the diagram shows the first metal layer (blue), the second metal layer (green), the third metal layer (orange), the via layer (cyan), and the fourth metal layer (black). The dashed boxes represent the metal lines of the second metal layer and the via layer, which are only used sparingly at intersections.

[0052] In one embodiment, the distance between the first metal layer and the second metal layer in the vertical direction is 3 μm, the distance between the second metal layer and the third metal layer in the vertical direction is 0.2 μm, the distance between the third metal layer and the via layer in the vertical direction is 0.2 μm, and the distance between the via layer and the fourth metal layer in the vertical direction is 0.2 μm. In the longitudinal axis close to the interface chip, as shown in FIG. Figure 3As shown by the middle arrow and dashed box, after the data line tx0 in area C0 reaches the junction of areas C0 and C1, it needs to jump horizontally to the second metal layer and then vertically to the third metal layer before being routed into area C1. This means that a metal line spacing must be left between the data line tx1 and the data line rx. Therefore, the spacing between the data lines tx1 and rx is 3µm, and all other horizontal spacings are 0.5µm.

[0053] In one embodiment, Figure 11 Shown are cross-sectional views of other longitudinal scribe line metal lines, such as Figure 12 The figure shows a cross-sectional view of the metal lines in the horizontal scribe groove. The cross-sectional views of the two figures are the same. They are based on the metal lines in the scribe groove close to the interface chip, and the data lines tx1, tx2 and tx3 are removed, while the others remain unchanged. Therefore, in the same scribe groove, except for the second metal layer and the through-hole layer, the horizontal distance between two metal lines of the same layer is 5.5um, the horizontal distance between two adjacent metal lines is 0.5um, the vertical distance between the first metal layer and the third metal layer is 3.4um, and the vertical distance between the third metal layer and the fourth metal layer is 0.6um. This method of using multi-layer metal spacing for wiring increases the distance between adjacent metal lines in space to prevent two adjacent metal lines from short-circuiting due to cutting and squeezing during scribe.

[0054] Example 3: This embodiment will propose a wafer for multi-chip programming. The wafer-level multi-chip metal wiring method proposed in Example 1 can be applied to the wafer. In one embodiment, Figure 13 As shown, the wafer includes at least one interface chip, multiple burning chips and metal traces, and the metal traces are arranged in the dicing grooves of the wafer; the interface chip is connected to different burning chips respectively through the metal traces; the interface chip is used to connect to the output end of the data burning module to receive the burning data sent by the data burning module; the interface chip is used to transmit the burning data to the burning chip through the metal traces; the burning chip is used to complete chip burning according to a preset communication protocol and the burning data.

[0055] It is worth noting that the black dots at the intersections of the metal lines indicate electrical connections, while the other places without black dots indicate no electrical connections between the intersecting metal lines.

[0056] In one embodiment, metal traces are embedded in the scribe lines reserved for wafer dicing, and data path layout is performed using the space not occupied by the chip.

[0057] In one embodiment, the wafer includes multiple blocks, and 1024 chips can be integrated in each block. At least one of the chips can be configured as an interface chip to realize data interaction between the data burning module and the burning chip. In order to facilitate the configuration of the chip, one or four chips in the four corners of the wafer can be configured as interface chips, and the remaining chips are the burning chips that need to be burned. The size of the burning chips remains consistent and all meet the preset communication protocol. The burning chips on the wafer can be chips of the same model or chips of different models. More details will be explained below.

[0058] The programming process for a programming chip includes the following steps: the data programming module sends the programming data to the interface chip, which then transmits the programming data to the programming chip through the interface chip and corresponding metal traces. All programming chips are then able to receive the programming data and write it to their internal storage units according to a preset communication protocol, completing the programming of each programming chip. The preset communication protocol can be the OneWire protocol.

[0059] In this embodiment, metal traces are arranged in the scribe grooves on the wafer, and the interface chip and the corresponding metal traces transmit the programming data from the data programming module to each programming chip on the wafer. After receiving the corresponding programming data, each programming chip completes its own programming through a preset communication protocol. By directly programming the chip data during the wafer manufacturing stage, the inefficiency of the traditional method of performing programming after cutting and packaging the chip is avoided, thereby significantly improving production efficiency. The step of separate programming after packaging is reduced, and at the same time, no additional programming ports are required in the programming chip for programming data, thereby saving chip area and reducing production costs and time costs. At the same time, the number and grouping method of the chip array can be flexibly adjusted according to demand, and is suitable for chip manufacturing needs of different scales.

[0060] In order to place the metal traces in the scribe lines, in one embodiment, referring to Figure 13 The metal routing is arranged in the scribe groove in a horizontal and vertical cross-arrangement, and the level and spacing of the metal routing are adjusted according to the characteristics and quantity of the required metal routing; the metal routings with different functions at the same level in the horizontal and vertical directions, the metal routing in one direction is switched to the metal routing at other levels through punching jumpers at the intersection of the scribe grooves, so as to realize the staggered intersection of the metal routings in the two directions at the intersection; the metal routings with the same function are connected by punching at the intersection of the scribe grooves.

[0061] In one embodiment, metal traces with different functions can be arranged in different metal layers, and metal lines with the same function in the horizontal and vertical directions are connected by punching at the intersection of the scribe grooves; secondly, metal traces with different functions can also be arranged in the same metal layer as long as the distance between them is set appropriately (for example, the spacing is less than a preset value). Metal traces with different functions at the same level in the horizontal and vertical directions, the metal traces in one direction are switched to the metal traces at other levels through punching jumpers at the intersection of the scribe grooves, so that the metal traces in the two directions meet at the intersection in staggered layers and are connected by punching at the intersection.

[0062] Among them, high-layer metal lines are selected as much as possible for the metal lines in the horizontal and vertical directions. At the intersection, different lines need to be switched through punching to achieve staggered intersection to avoid short circuit of metal lines with different functions. At the same time, metal lines with the same function are connected by punching here.

[0063] The metal traces include power lines (VDD and VDD_EXT), a ground line (VSS), a data transmission line (rx), and at least one data return line (tx0, tx1, tx2, and tx3 in this embodiment). The data transmission line is used to transmit the programming data from the data programming module to each of the programming chips. The data return line is used to transmit the programming return data fed back from each programming chip to the interface chip.

[0064] Among them, the horizontal and vertical cross setting means that in the dicing groove area of ​​the wafer, the metal lines are arranged in a manner that crosses each other horizontally (horizontally) and vertically (vertically) and interweaves vertically, forming a "grid-like" wiring structure.

[0065] Among them, horizontal routing refers to the extension along the horizontal direction of the scribe groove (such as the X-axis), and vertical routing refers to the extension along the vertical direction of the scribe groove (such as the Y-axis), which crosses perpendicularly with the horizontal routing. Within the limited scribe groove width, the horizontal and vertical crossings maximize the use of two-dimensional space, significantly improve the wiring density, and avoid the problem of insufficient space caused by all routing being squeezed in the same direction.

[0066] In one embodiment, the horizontal and vertical cross-connected traces are distributed across different metal layers, separated by an insulating layer to achieve functional isolation. Connections between metal layers are achieved through vias (punched holes). At the intersections of the horizontal and vertical traces (i.e., where different metal layers overlap), vias are created through an etching process, connecting the upper and lower metal traces to achieve electrical continuity.

[0067] For example, horizontal traces run horizontally on the M1 layer, while vertical traces run vertically on the M2 layer. Vias connect the traces on the M1 and M2 layers at their intersections, forming corresponding conductive paths. In one embodiment, the via type (through hole, blind via, buried via) and size must be designed based on process precision to ensure reliable connections without compromising the mechanical strength of the scribe lines.

[0068] The specific layout of the metal wiring will be described in detail in the following embodiments.

[0069] In order to ensure that each chip in the edge area of ​​the wafer can be connected to at least one interface chip, and to avoid the problem of being unable to program the regional programming chip when the wafer block is incomplete. In one embodiment, Figure 14 As shown, the chips at the four corners of the wafer are respectively configured as interface chips, and the chips on the wafer are divided into four areas, and each area includes at least one interface chip and multiple burning chips; the metal wiring includes a power line, a ground line, a data transmission line and four data return lines; each interface chip is connected to the data burning module through the metal wiring; the burning chip is connected to any interface chip through the power line, the ground line, the data transmission line and any data return line.

[0070] To avoid having all programming chips connected to the same interface chip, which would complicate wiring on the wafer, this embodiment provides four interface chips on the wafer. Each of the four interface chips is connected to the programming chips in its corresponding area and is responsible for programming data to the programming chips in its corresponding area. In other embodiments, more interface chips can be provided to further simplify wiring on the wafer. However, this embodiment will not provide further details.

[0071] Reference Figure 14 , 1024 chips are integrated into one block of the wafer to form a chip array. The chips at the four corners of the chip array are configured as interface chips (such as Figure 14The remaining 1020 chips (P0, P1, P2, and P3) are the programming chips. C0, C1, C2, and C3 represent the programming chips located in four different areas, each containing 255 programming chips. The specific number can be increased or decreased based on demand. Metal traces are laid in the chip array's scribe lines for power lines (VDD_EXT and VDD), ground lines (VSS), data transmission lines (rx), and data return lines (including tx0, tx1, tx2, and tx3). The four interface chips P0, P1, P2, and P3 are connected to VDD_EXT, VDD, VSS, rx, tx0, tx1, tx2, and tx3 in the scribe lines, respectively. In addition to connecting to VDD_EXT, VDD, VSS, and rx, the programming chips in the four regions C0, C1, C2, and C3 only need to connect their corresponding data return lines (tx) to one of tx0, tx1, tx2, and tx3. That is, the programming chip tx in region C0 connects to tx0, the programming chip tx in region C1 connects to tx1, the programming chip tx in region C2 connects to tx2, and the programming chip tx in region C3 connects to tx3. It is worth noting that black dots at the intersections of metal lines indicate intersections; otherwise, the metal lines do not intersect.

[0072] With this layout, the probe machine only needs to operate any one of the P0, P1, P2 or P3 interface chips to complete the data burning of the 1020 programming chips in the entire chip array. In actual operation, four probes are required to connect the four pads VDD_EXT, VDD, VSS and prog corresponding to the interface chip (see Figure 3 shown).

[0073] In summary, by providing four interface chips, each programming chip at the wafer edge can be connected to at least one interface chip. Even if the wafer edge area is incomplete, it can still be connected to the interface chip through the metal traces in the scribe line, ensuring that every programming chip can be programmed.

[0074] In order to realize data interaction between the data burning module and the burning chip, in one embodiment, Figure 15As shown, the interface chip includes a pull-up resistor R1, an output unit, a pull-down switch (i.e., Q1), at least one pull-down resistor R2, and an input unit; the input end (i.e., prog) of the output unit, the pull-up resistor R1, and one end of the pull-down switch are respectively connected to the output end of the data programming module; the other end of the pull-up resistor R1 is connected to the programming voltage (i.e., VDD_EXT); the other end of the pull-down switch is grounded; the output end (i.e., rx) of the output unit is respectively connected to different programming chips through the metal traces; one end of the pull-down resistor R2 and the input end of the input unit are respectively connected to the programming chip through the metal traces (i.e., tx0~tx3); the other end of the pull-down resistor R2 is grounded; the output end of the input unit is connected to the control end of the pull-down switch.

[0075] In one embodiment, referring to Figure 15 The output unit includes a first trigger (i.e., smit1) and a first buffer (i.e., buffer1) connected in sequence. The input of the first trigger is connected to the output of the data programming module. The output of the first buffer is connected to different programming chips via the metal trace (i.e., tx) to transmit programming data to the programming chip. The input unit includes at least one second trigger (i.e., smit2) and a second buffer (i.e., buffer2) connected in sequence. The input of the second trigger is connected to the programming chip via the metal trace (tx0, tx1, tx2, or tx3) to receive programming return data. The output of the second buffer is connected to the control terminal of the pull-down switch.

[0076] In one embodiment, under the premise of providing four interface chips, the interface chip includes four pull-down resistors R2 and four second triggers, and the interface chip also includes a four-input OR gate (ie, OR).

[0077] The programming data from the data programming module is transmitted from the data receiving end (i.e., prog) of the interface chip through the first trigger and the first buffer to the data transmission line rx. The data transmission line rx transmits the programming data to each programming chip. The programming chips in the four areas C0, C1, C2, and C3 return programming return data via data return lines tx0, tx1, tx2, and tx3, respectively. The programming return data indicates whether the programming chip was successfully programmed.

[0078] In one embodiment, a low level of the programming return data indicates a successful programming; a high level indicates a failed programming. The programming return data may be in the form of a pulse. That is, if programming is successful, a high level is output for a preset time. The preset time may be in the order of microseconds or milliseconds, depending on the programming time of the chip. The purpose is to ensure that the programming return data can provide feedback on successful programming without affecting the programming of the next chip.

[0079] In this embodiment, the four data return lines are respectively connected to the pull-down resistor R2 and then to a second trigger. The second trigger is connected to a 4-input OR gate. After the second trigger increases the driving capability, the on and off of the pull-down switch is controlled.

[0080] That is, the 4-input OR gate is connected to the 4 data return lines respectively. When the programming chip corresponding to the data return line has no programming return data, the second flip-flop maintains a tri-state output, that is, the second flip-flop outputs 0. When the programming chip corresponding to the data return line has programming return data, the second flip-flop outputs the corresponding programming return data.

[0081] When all data return lines do not return programming return data or the returned programming return data is 0, the 4-input OR gate outputs a low level, the pull-down switch is closed, and the level of the prog interface is pulled high by the pull-up resistor R1, allowing programming data to continue to be sent to the programming chip. When the programming return data returned by any data return line is 1, the 4-input OR gate outputs a high level, the pull-down switch is opened, and the level of the prog interface is pulled low, preventing programming data from being sent.

[0082] In one embodiment, each programming chip on the wafer is internally designed with a unique identification sequence. During data programming, all programming chips simultaneously receive commands / data (i.e., programming data) sent by an external device through a prog interface. The programming data carries chip selection information. The programming chip parses the commands / data and compares the chip selection information parsed from the commands / data with the unique identification sequence within the programming chip. A programming chip that successfully identifies a match is used as the target chip and communicates with the data programming module (the TX outputs of all programming chips other than the target chip remain in a tri-state). Information is read from the target chip and data is programmed. By sending and parsing different chip selection information in this way, programming of all programming chips in the entire array is completed in sequence.

[0083] When there is no burning return data transmission on the corresponding data return line, the pull-down resistor R2 can keep the port in a low state. The resistance of the pull-down resistor R2 is determined by the requirements, for example, 50kΩ.

[0084] In one embodiment, Figure 16 As shown, the programming chip includes a pull-down resistor R3, a first logic gate (i.e., buf), and a second logic gate (i.e., AND); the input end of the first logic gate is respectively connected to one end of the pull-down resistor R3 and the programming voltage; the output end of the first logic gate is connected to the internal control circuit of the programming chip; one input end of the second logic gate is connected to the programming voltage, and the other input end of the second logic gate is connected to the output end of the interface chip to receive the programming data through the metal traces.

[0085] In one embodiment, referring to Figure 16 The first logic gate may be a buffer gate, the second logic gate may be an AND gate, and the programming chip further includes a tri-state buffer (ie, en).

[0086] Further references Figure 16 The programming chip also includes a data channel selection module (not shown). tx_ic_en (data return enable signal), tx_ic (data return signal), rx_ic (data receive signal), and prog_en (programming interface valid signal) are connected to the data channel selection module. tx_ic_en and tx_ic are also connected to the two inputs of a tri-state buffer, respectively. The tri-state buffer's output, tx, is connected to one of the corresponding data return lines, tx0, tx1, tx2, and tx3, on the metal traces. Only when tx_ic_en is active (typically high, depending on the specific definition) can data from tx_ic pass through the tri-state buffer and drive the programming return data output. If tx_ic_en is inactive, the tx terminal assumes a high-impedance state.

[0087] Reference Figure 16 One input terminal (rx in the figure) of the AND gate (i.e., the second logic gate) is used to receive the programming data output by the interface chip, and the other input terminal of the AND gate is connected to the programming voltage (i.e., VDD_EXT). The input terminals of the buffer gate (i.e., the first logic gate) are connected to the programming voltage and one end of the pull-down resistor R3, respectively. In one embodiment, when VDD_EXT is connected to an external voltage, the buffer gate outputs prog_en = 1, indicating that the programming chip is enabled to receive signals from the prog terminal of the interface chip. When VDD_EXT is not connected to an external voltage, the buffer gate outputs prog_en = 0, indicating that the programming chip does not receive signals from the prog terminal of the interface chip.

[0088] When the voltage of VDD_EXT is equal to that of VDD, the circuit structure of the programming chip can be directly Figure 16 When designing, if the voltage of VDD_EXT is not equal to that of VDD, it is necessary to Figure 16When programming the chip, VDD_EXT and VDD are both powered, prog_en = 1, and the programming chip receives or returns data according to the preset communication protocol to implement data programming. After the array is programmed, subsequent production processes such as dicing and packaging will be carried out. At this time, only VDD is powered, and VDD_EXT is not. Due to the pull-down resistor R3, prog_en = 0, and the programming chip no longer receives or returns data through the corresponding interface chip.

[0089] In one embodiment, power, ground, and data lines are routed through all scribe lines, arranged both horizontally and vertically. Vias are drilled at the intersections of the scribe lines to reduce parasitic resistance (due to the high current draw from thousands of chips operating simultaneously) and ensure stable and uniform power supply. In this embodiment, eight metal lines are used: VDD_EXT, VDD, VSS, rx, tx0, tx1, tx2, and tx3. Multiple layers of metal are used for routing, spacing adjacent metal lines apart.

[0090] In one embodiment, the scale of this embodiment can be adjusted according to actual needs. For example, if the scale of 4096 chips is adopted, the tx data lines can be expanded to 16. At the same time, other signal lines can be added to the dicing grooves according to needs if the conditions are met. The details will not be explained in detail in this embodiment.

[0091] The specific process of the wafer-level multi-chip metal wiring method is shown in Example 1 and will not be repeated in this embodiment.

[0092] Example 4: In order to further illustrate the wafer for programming multiple chips proposed in Example 3, this embodiment proposes a wafer-level multi-chip data programming method. In one embodiment, Figure 17 As shown, the wafer-level multi-chip data burning method includes: Step 201: The interface chip is connected to the output end of the data burning module to receive the burning data sent by the data burning module.

[0093] The data programming module establishes an electrical connection with an interface chip via a specific physical interface, such as a prober. The interface chip is used to transmit programming data to the programming chip. Metal traces enable data communication between the interface chip and the numerous programming chips without affecting subsequent wafer dicing and packaging. When the interface chip transmits data, the electrical signal is transmitted along the metal traces to each programming chip.

[0094] Step 202: The interface chip transmits the programming data to the programming chip through the metal wiring; the programming chip is used to complete chip programming according to a preset communication protocol and the programming data.

[0095] The preset communication protocol specifies how the programming chip receives, identifies, and processes data. This includes the data format (such as the data frame structure, start bit, data bits, parity bit, stop bit, etc.), transmission rate, timing requirements (when data is sent and when it is received), and error handling mechanisms. After receiving data from the metal traces, the programming chip parses the programming data according to the preset communication protocol.

[0096] Once the programming chip successfully parses the programming data according to the preset communication protocol, it writes the corresponding programming data to a specific internal storage area, such as flash memory or electrically erasable programmable read-only memory. After programming is complete, the relevant circuits within the programming chip configure and initialize the written data, enabling the chip to have the corresponding functions.

[0097] In one embodiment, the wafer-level multi-chip data burning method further includes: During the wafer manufacturing stage, a unique identification sequence (such as a unique ID code) is preset inside each programming chip.

[0098] The data programming module broadcasts commands / data (including chip selection information) to all programming chips on the wafer simultaneously through the shared prog interface.

[0099] All programming chips receive and parse the received commands / data in real time, extract the chip selection information, and compare the chip selection information with their own unique identification sequence.

[0100] The successfully matched programming chip activates the communication function and sends an enable signal to the interface chip through the data return line to notify the interface chip that its own communication function has been activated; the port connected to the data return line of the unmatched programming chip remains in a high-impedance state to avoid bus conflicts.

[0101] The data programming module establishes a point-to-point communication channel with the activated programming chip. After the communication channel is established, the data programming module reads the status information of the activated programming chip (such as the storage area address) through the interface chip, and sends the programming data to execute the data programming operation on the activated programming chip and write the specified data.

[0102] After the activated programming chip completes programming, the programming return data is transmitted through the data return line.

[0103] The data programming module updates the chip selection information in the command / data (pointing to the identification sequence of the next programming chip).

[0104] Repeat the above steps until all the chips on the wafer are programmed.

[0105] The present invention arranges metal traces in the scribe grooves on the wafer, and the interface chip and the corresponding metal traces transmit the burning data from the data burning module to each burning chip on the wafer. After receiving the corresponding burning data, each burning chip completes its own burning through a preset communication protocol. By directly burning data on the chip during the wafer manufacturing stage, the inefficiency of burning the chip after cutting and packaging in the traditional method is avoided, and production efficiency is significantly improved. The step of separate burning after packaging is reduced, and at the same time, there is no need to increase the burning port in the burning chip due to burning data, which saves chip area and reduces production cost and time cost. At the same time, the number and grouping method of the chip array can be flexibly adjusted according to demand, and it is suitable for chip manufacturing needs of different scales.

[0106] Regarding the specific structure of the wafer for multi-chip programming, please refer to Example 3 and will not be repeated in this embodiment.

[0107] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions and improvements made within the spirit and principles of the present invention should be included in the scope of protection of the present invention.

Claims

1. A wafer-level multi-chip metal wiring method, characterized in that: include: Setting metal traces in the wafer scribe lines; arranging the metal traces in layers and isolating them at predetermined intervals; At the intersection of the scribe lines, jumper connections between metal traces on different metal layers are achieved through through-holes; The interface chip and the corresponding metal wiring transmit the programming data from the data programming module to each programming chip on the wafer. After receiving the corresponding programming data, each programming chip completes its own programming through the preset communication protocol.

2. The wafer-level multi-chip metal wiring method according to claim 1, characterized in that: The method further comprises: The chip array is divided into a plurality of areas, and at least one interface chip is arranged at the edge of each area. The programming chip in each area is connected to the at least one interface chip via a data return line.

3. The wafer-level multi-chip metal wiring method according to claim 1, characterized in that: A first metal layer, a second metal layer, a third metal layer, and a fourth metal layer are sequentially arranged in the scribe lines of the wafer; wherein the first metal layer is used to carry power lines, ground lines, and data lines; The second metal layer is used to realize jumper connection of different metal layers at the intersection of the scribe lines; The third metal layer is used for laying data return lines and control signal lines; The fourth metal layer is used for laying out the power line of the programming chip.

4. The wafer-level multi-chip metal wiring method according to claim 3, characterized in that: A through-hole layer is provided between the third metal layer and the fourth metal layer to achieve vertical isolation of the metal layers.

5. The wafer-level multi-chip metal wiring method according to claim 3, characterized in that: Adjacent metal traces use different metal layers alternately in the horizontal and vertical directions and are isolated by a preset spacing. The lateral spacing between adjacent metal traces is not less than 0.5μm. The longitudinal spacing between different metal layers is set according to preset process parameters, wherein the longitudinal spacing between the first metal layer and the second metal layer is not less than 3 μm.

6. The wafer-level multi-chip metal wiring method according to claim 1, characterized in that: The method further comprises: Divide the chip array on the wafer into multiple areas, each area corresponds to a set of data return lines; Each set of data return lines is driven by a buffer in the programming chip. Only one buffer is allowed to output data at the same time, and the buffers in the other programming chips remain in a high-impedance state to avoid bus conflicts.

7. The wafer-level multi-chip metal wiring method according to claim 1, characterized in that: The method further comprises: In the incomplete block at the edge of the wafer, the data return line of the programming chip at the edge is connected to the nearest interface chip through the metal traces in the scribe line; Redundant metal lines are added to the edge area of ​​the scribe line to compensate for the wiring loss caused by incomplete blocks, ensuring that all burned chips can be connected to the interface chip through at least one path.

8. The wafer-level multi-chip metal wiring method according to claim 1, wherein: The method further comprises: A plurality of pads are provided at the interface chip, wherein the pads are respectively connected to the power line, the ground line and the data line in the scribe groove; The probe is electrically connected to the pad through the probe machine to realize data burning of the chip on the wafer.

9. The wafer-level multi-chip metal wiring method according to claim 1, characterized in that: The method further comprises: The width and thickness of the metal traces are dynamically set according to the current density and signal integrity requirements, wherein: the width of the power line is greater than or equal to 5μm, and the thickness is greater than or equal to 3μm; the width of the data line is greater than or equal to 2μm, and the thickness is greater than or equal to 0.2μm; the width of the clock line and the control signal line is greater than or equal to 1μm, and the thickness is greater than or equal to 0.2μm.

10. A wafer for multi-chip programming, characterized in that: Implementing the layout of metal traces by the metal wiring method according to any one of claims 1 to 9; The wafer includes at least one interface chip, a plurality of burning chips and metal traces, and the metal traces are arranged in the scribe lines of the wafer; The interface chip is connected to different programming chips respectively through the metal wiring; The interface chip is used to be connected to the output end of the data burning module to receive the burning data sent by the data burning module; The interface chip is used to transmit the programming data to the programming chip through the metal wiring; The programming chip is used to complete chip programming according to a preset communication protocol and the programming data.

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