Phase locking method suitable for unbalanced power grid condition

Abstract

The invention relates to the technical field of unbalanced power grid voltage phase detection and harmonic suppression, and provides a phase locking method suitable for an unbalanced power grid condition. The objective of the invention is to solve the problems of instability of a phase-locked loop, increase of harmonic content of output current of an inverter and reduction of dynamic response performance caused by unbalanced power grid voltage. According to the main technical scheme, the method comprises the steps that the three-phase voltage Vabc of a point of common coupling PCC is converted into an alpha component and a beta component under a two-phase static coordinate system through a coordinate conversion unit of the three-phase voltage; two mutually orthogonal signals are generated through a second-order generalized integrator SOGI; orthogonal signals output by the SOGI are input into a decoupling network through Park transformation, a positive sequence voltage component and a negative sequence voltage component are separated out, and then smoothing processing is carried out through a first-order low-pass filter; an improved moving average filter is adopted for dynamic correction, and a phase locking angle is generated; the phase locking angle is adjusted through a proportional-integral controller and an integral element 1 / s, and a synchronizing signal is output to control the output current of the grid-connected inverter.

Description

Technical Field

[0001] The present invention relates to the technical fields of unbalanced power grid voltage phase detection and harmonic suppression, and in particular to a phase locking method suitable for unbalanced power grid conditions. Background Art

[0002] As global climate change intensifies, energy structure transformation has become an international consensus, and renewable energy systems have garnered significant attention. Energy storage technology, acting as a stabilizer and regulating valve for energy systems, effectively improves renewable energy absorption capacity by shifting energy supply and demand in time and space. Grid-connected inverters, as key devices connecting distributed generation systems with energy storage systems, have a direct impact on power system stability and power quality through their control performance. The inverter phase-locked loop (PLL), a core component of the grid-connected inverter control system, is responsible for real-time tracking of grid voltage phase and frequency information, providing a reference signal for inverter synchronization control. In actual grid operation, three-phase imbalance in grid voltage is common due to factors such as load imbalance, single-phase load connection, and asymmetric transmission line parameters. This poses a significant challenge to the control of grid-connected inverters. This is due to instability in the phase-locked loop (PLL) during grid faults. Most grid faults result in an asymmetric drop in grid voltage, increasing harmonics at the point of common coupling (PCC), distorting the current waveform, and reducing inverter efficiency.

[0003] To ensure stable operation of grid-connected inverters under unbalanced power grids, the voltage and current on the inverter output side must be synchronized. Researchers have proposed a variety of positive and negative sequence separation algorithms, which are divided into coordinate transformation, filter, delay, and adaptive filtering methods. Delay-based positive and negative sequence separation methods, such as the delayed signal cancellation method (DSC), can eliminate specific frequency components through appropriate delays and linear combinations. However, they have very high requirements for grid stability, and the delay period must also accurately correspond to 1 / 4 of the grid period, making them unsuitable for harsh grid environments. Adaptive filtering-based positive and negative sequence separation methods, such as the dual second-order generalized integrator (DSOGI), process the α-axis and β-axis signals separately, and achieve positive and negative sequence separation through cross-coupling. The separation accuracy is greatly improved and it can also adapt to changes in grid frequency. However, it is necessary to consider the parameter matching of the two channels at the same time, which makes parameter optimization and system debugging more difficult, and there is a large filtering delay. Filter-based positive- and negative-sequence separation techniques, such as the moving average filter (MAF), eliminate harmonic components of specific frequencies by averaging the signal within a time window. This algorithm has a simple structure and easily ensures system stability, but the filter window also introduces delays that affect dynamic performance. Coordinate transformation-based methods, such as the decoupled dual synchronous coordinate system phase-locked loop (DDSRF-PLL), eliminate negative-sequence components in a positive-sequence synchronous coordinate system and positive-sequence components in a negative-sequence synchronous coordinate system, significantly improving separation accuracy. However, this also increases system complexity, and its dynamic response is highly sensitive to voltage phase angle jumps, resulting in large frequency estimation errors. Summary of the Invention

[0004] The purpose of the present invention is to solve the problems of phase-locked loop instability, increased harmonic content in the inverter output current, and decreased dynamic response performance caused by unbalanced three-phase grid voltage. By introducing a hybrid phase-locked structure of a second-order generalized integrator (SOGI) and an improved moving average filter (EMAF), effective separation and dynamic correction of positive and negative sequence voltage components are achieved, thereby improving the inverter's phase tracking accuracy, frequency recovery speed, and power dynamic response capability under unbalanced grid conditions, reducing harmonic distortion, and enhancing system stability.

[0005] In order to achieve the purpose of the invention, the technical solutions adopted are as follows:

[0006] The present invention provides a phase locking method suitable for use in an unbalanced power grid, comprising the following steps:

[0007] Step 1: Use the three-phase voltage coordinate transformation unit to transform the three-phase voltage V abc Convert to α and β components in a two-phase stationary coordinate system;

[0008] Step 2: Process the α and β components through the second-order generalized integrator SOGI to generate two mutually orthogonal signals u'α , u' β ;

[0009] Step 3: Convert the quadrature signal u' output by SOGI α , u' β The positive sequence voltage component is separated by inputting it into the decoupling network through Park transformation. and negative sequence voltage component

[0010] Step 4: Use a first-order low-pass filter to filter the separated positive sequence and negative sequence components Perform smoothing and extract the DC component to obtain the positive sequence DC component and negative sequence DC component And return these DC components to the decoupling network in step 3 as input;

[0011] Step 5: Use the improved moving average filter (EMAF) to decouple the q-axis positive sequence voltage obtained from the network The signal is dynamically corrected to generate a phase-locked angle, which is then adjusted through a proportional-integral controller and an integral link 1 / s to output a synchronization signal to control the output current of the grid-connected inverter.

[0012] In the above scheme, in step 1, the three-phase voltage V abc Connect the Clarke transform unit and transform the signal from the three-phase stationary coordinate system to the two-phase stationary coordinate system through Clarke transform to obtain the α component and β component. The matrix of Clarke transform is expressed as:

[0013]

[0014] U a Indicates the voltage of phase A, U b Indicates the B phase voltage, U c Indicates the C phase voltage, u α represents the transformed α-axis component, u β represents the transformed β-axis component.

[0015] In the above scheme, in step 2, the voltage component u in the two-phase stationary coordinate system is α and u β The input is to the second-order generalized integrator SOGI, which generates two pairs of mutually orthogonal signals through the following transfer function:

[0016]

[0017] u' α =G(s)u' α

[0018] uβ =G(s)u β

[0019] Where s represents the complex frequency variable, k represents the SOGI attenuation coefficient, ω′ represents the SOGI center angular frequency, and s represents the complex frequency variable.

[0020] In the above scheme, in step 3, the quadrature signal u output by the second-order generalized integrator (SOGI) is converted to α ,u β The Park transformation is input to the decoupling network to eliminate the coupling between the positive sequence voltage component and the negative sequence voltage component. and The decoupling network is decoupled by the following matrix operation:

[0021]

[0022] where u d+ and u q+ Indicates u α and u β The d-axis voltage and q-axis voltage are obtained after the angular velocity is ω Park transformation, u d- and u q- Indicates u' α and u' β The d-axis voltage and q-axis voltage obtained after the angular velocity is -ω Park transformation are: represents the d-axis component of the positive sequence voltage, represents the q-axis component of the positive sequence voltage, represents the d-axis component of the negative sequence voltage, represents the q-axis component of the negative sequence voltage, ω represents the grid angular frequency, t represents time, express The d-axis positive sequence voltage after passing through the first-order low-pass filter is: express The q-axis positive sequence voltage after passing through the first-order low-pass filter, express The d-axis negative sequence voltage after passing through the first-order low-pass filter is: express The q-axis negative sequence voltage after passing through the first-order low-pass filter.

[0023] In the above scheme, in step 4,

[0024] The positive sequence voltage component of the decoupling network output and negative sequence voltage component Input them into the first-order low-pass filter (LPF) respectively, attenuate the fluctuation component through the following transfer function, extract the DC component, and obtain the positive sequence DC component and negative sequence DC component

[0025]

[0026] s represents a complex frequency variable, ω f represents the low-pass filter cutoff angular frequency, ω represents the grid angular frequency, and k represents the filter coefficient ratio.

[0027] In the above scheme, in step 5,

[0028] The q-axis positive sequence voltage obtained by the decoupling network The input is sent to the improved moving average filter (EMAF), and dynamic correction is achieved through the following transfer function to generate the phase-locked angle. The phase-locked angle is adjusted through the proportional-integral controller and the integral link 1 / s. The phase-locked loop adjustment transfer function is:

[0029]

[0030] k p represents the proportional gain, k i represents the integral gain, μ represents the attenuation factor, T W represents the EMAF filter window time constant, θ pll is the phase-locked angle output by the improved sliding average filter.

[0031] In the above scheme, Obtained by the following steps:

[0032] Step a: Build a basic model based on the transfer function of the traditional moving average filter MAF:

[0033] By averaging the input signal within a time window, the transfer function of the traditional moving average filter MAF is:

[0034]

[0035] Step b: Introduce a correction link to optimize dynamic performance and design the correction link G d (s), its transfer function is:

[0036]

[0037] Step 3: Derivation of the transfer function of the improved moving average filter EMAF combined with the correction link

[0038] Combine the traditional MAF with the correction link G d (s) are connected in series to obtain the transfer function of the improved moving average filter EMAF:

[0039] G EMAF (s)=GMAF (s)·G d (s)

[0040] Substituting the expressions in step a and step b, we can get the following after simplification:

[0041]

[0042] Further, the exponential term is converted to Converted to rational function form, it is finally simplified to:

[0043]

[0044] G MAF (s) represents the transfer function of the moving average filter MAF, G d (s) Transfer function of the correction link, T W Indicates the EMAF filter window time constant, G EMAF (s) represents the transfer function of the improved moving average filter, k p represents the proportional gain, k i represents the integral gain, μ represents the attenuation factor, 0<μ<1.

[0045] This invention integrates a hybrid phase-locked structure of a second-order generalized integrator (SOGI) and an improved moving average filter (EMAF), combined with coordinate transformation, decoupling network, and low-pass filtering technology, to effectively solve the problems of phase-locked loop instability caused by three-phase grid voltage imbalance, increased harmonic content in inverter output current, reduced active power output by the inverter, and decreased dynamic response performance. The following effects are analyzed in detail based on the synergistic effect of the technical features:

[0046] The present invention introduces a second-order generalized integrator (SOGI) in step 2 to process the α and β components to generate orthogonal signals. After Park transformation, it is combined with the decoupling network in step 3 to solve the technical problem of phase-locked instability caused by the coupling of positive and negative sequence components when the grid voltage is unbalanced, thereby achieving the effect of improving separation accuracy and enhancing system stability. The specific logical analysis is as follows:

[0047] SOGI acts as a bandpass filter (transfer function ), through its orthogonal signal generation capability, it filters out noise interference outside the grid fundamental frequency and provides a pure input signal for the decoupling network.

[0048] The decoupling network (matrix operation eliminates coupling terms) relies on the orthogonal signal output by SOGI and the stability of the phase angle of the phase-locked loop to accurately separate the positive and negative sequence components after the Park transformation. and The pre-processing of SOGI reduces the residual harmonics during the decoupling process. The decoupling network avoids the mixing of negative sequence components into positive sequence voltage and the mixing of positive sequence voltage into negative sequence voltage, thereby suppressing the phase-locking angle deviation.

[0049] The two work together: SOGI improves the signal-to-noise ratio, and the decoupling network achieves efficient separation based on high-quality input, jointly reducing the frequency fluctuation range and ensuring stable operation of the phase-locked loop under grid distortion conditions.

[0050] 2. The present invention uses a first-order low-pass filter (LPF) to extract the DC component in step 4, and combines it with the improved moving average filter (EMAF) for dynamic correction in step 5. This solves the dynamic response lag and frequency mutation instability problems caused by filtering delay in traditional phase-locked methods, achieving the effect of accelerating frequency recovery speed and power tracking capability. The specific logical analysis is as follows:

[0051] LPF (Transfer Function ) smoothes the positive and negative sequence components of the decoupling output, extracts the DC component, and provides feedback for the decoupling network to attenuate the fluctuation component, forming a closed-loop stability support.

[0052] EMAF optimizes the window delay problem of the traditional sliding average filter through the correction link. The signal is dynamically corrected to generate a phase-locked angle, which is then adjusted by a proportional-integral controller and an integral link to achieve fast phase tracking.

[0053] The two work synergistically: the LPF ensures a stable DC input to the decoupling network, reducing system oscillations. The EMAF, leveraging the LPF's stable output and the decoupling network's harmonic suppression, accelerates the phase-lock angle response through low-latency correction. This combination prevents power overshoot and harmonic amplification during sudden grid voltage changes (such as low voltage ride-through), improving the inverter's efficiency and dynamic tracking capabilities.

[0054] 3. Through the synergistic effect of the overall technical process (steps 1 to 5), this invention solves the technical problems of insufficient phase-locking accuracy, weak harmonic suppression, and poor system robustness in unbalanced power grids, achieving the effects of comprehensively improving phase tracking accuracy, reducing harmonic distortion, and enhancing steady-state and dynamic performance. The specific logical analysis is as follows:

[0055] The Clarke transform in step 1 provides the basic coordinate system for subsequent processing, the SOGI preprocessing in step 2 enhances the anti-interference capability, the decoupling network in step 3 achieves high-precision positive and negative sequence separation, the LPF closed-loop feedback in step 4 maintains component stability, and the EMAF-PLL in step 5 optimizes the dynamic response.

[0056] Collaboration among various links: SOGI’s output directly optimizes the decoupling network input to reduce separation error; the DC component of the LPF is fed back to the decoupling network (step 3) to form a real-time correction loop; EMAF is based on the decoupling The signal is combined with PI control to achieve rapid phase locking. Under grid asymmetry conditions (such as single-phase faults), this process suppresses current harmonics through step-by-step signal optimization, ensuring inverter output synchronization, thereby reducing overall harmonic distortion and improving power quality.

[0057] In summary, the present invention significantly improves the stability, response speed and harmonic suppression capability of the phase-locked loop in harsh power grid environments through hierarchical coordination and closed-loop design of technical features without relying on numerical optimization. BRIEF DESCRIPTION OF THE DRAWINGS

[0058] Figure 1 Flow chart of the method of the present invention;

[0059] Figure 2 It is a traditional decoupled dual synchronous frame phase-locked loop (DDSRF);

[0060] Figure 3 This is a structural diagram of the hybrid decoupled dual synchronous coordinate system phase-locked loop provided by the present invention;

[0061] Figure 4 This is a structural diagram of the second-order generalized integrator (SOGI) provided by the present invention;

[0062] Figure 5 This is a diagram of the decoupling network structure provided by the present invention;

[0063] Figure 6 This is a structural diagram of the improved sliding average filter phase-locked loop provided by the present invention;

[0064] Figure 7 The double sequence PQ control chart provided by the present invention;

[0065] Figure 8 Bode diagrams of different dynamic coefficients of the second-order generalized integrator (SOGI) provided by the present invention;

[0066] Figure 9 This is the light-load three-phase symmetrical low-voltage ride-through frequency diagram provided by the present invention;

[0067] Figure 10 The light-load three-phase symmetrical low voltage ride-through power tracking diagram provided by the present invention;

[0068] Figure 11 The heavy-load three-phase symmetrical low-voltage ride-through frequency diagram provided by the present invention;

[0069] Figure 12 The heavy-load three-phase symmetrical low voltage ride-through power tracking diagram provided by the present invention;

[0070] Figure 13 The light-load two-phase asymmetric low-voltage ride-through frequency diagram provided by the present invention;

[0071] Figure 14 The light-load two-phase asymmetric low voltage ride-through power tracking diagram provided by the present invention;

[0072] Figure 15 The heavy-load two-phase asymmetric low-voltage ride-through frequency diagram provided by the present invention;

[0073] Figure 16 The heavy-load two-phase asymmetric low voltage ride-through power tracking diagram provided by the present invention; DETAILED DESCRIPTION

[0074] To make the objectives, technical solutions, and advantages of the embodiments of the present invention more clear, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts shall fall within the scope of protection of the present invention.

[0075] The present invention discloses a phase-locking method suitable for use in unbalanced power grids, relating to the field of grid-connected power electronic converters. This method is used to address the voltage imbalance in the three-phase grid caused by the random and uneven connection of a large number of new energy devices, such as photovoltaics, energy storage, wind power, and charging stations, to different phases of a three-phase system, or by certain large single-phase loads, such as single-phase railway traction loads. This can cause the inverter, the connection hub between the new energy devices and the grid, to operate in an unstable state, increasing the harmonic content of the grid current and further aggravating the distortion of the grid voltage and current. This significantly reduces the utilization rate of new energy, can damage grid equipment, and even cause the entire grid system to collapse.

[0076] Traditional synchronous phase-locked loops (SRF-PLLs) can only phase-lock three-phase balanced systems. Voltage can be decomposed into positive-sequence voltage, negative-sequence voltage, and zero-sequence voltage using the symmetrical component method. However, in a balanced three-phase system, there is no negative-sequence component, and the inverter does not have a zero-sequence current loop, so the zero-sequence component will not affect the inverter. When the grid voltage is unbalanced, the negative-sequence component decomposed into the voltage is non-zero. While the SRF-PLL can only phase-lock the positive-sequence voltage alone, the presence of the negative-sequence voltage component can cause the phase-locked loop to become unstable and the inverter to become uncontrollable. In recent years, the decoupled dual synchronous phase-locked loop (DDSRF-PLL) has been proposed. This separates the positive-sequence voltage from the negative-sequence voltage and then phase-locks the positive-sequence voltage alone. This significantly improves the separation accuracy, but also increases the system complexity and significantly reduces the system's dynamic performance.

[0077] In summary, research on phase-locked loop (PLL) technology for grid-connected inverters integrating renewable energy is of great significance. Based on this, a hybrid phase-locked loop (HPL) was proposed. Its purpose is to balance the inverter's output current, reduce harmonic content in grid voltage and current, and reduce energy metering errors. Furthermore, it improves the dynamic recovery speed of the grid frequency and the dynamic tracking capability of the grid-connected inverter's output power, enabling the inverter to operate stably and efficiently in unbalanced grids.

[0078] The present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0079] A phase-locked method suitable for unbalanced power grid conditions consists of a three-phase voltage coordinate transformation unit, SOGI, a decoupling network, a first-order low-pass filter, an improved moving average filter (EMAF), a proportional integral controller, and an integral link 1 / s. The three-phase voltage V at the point of common coupling (PCC) is abc Connected to the input of the Clarke transform, the signal is first converted from the three-phase stationary coordinate system to the two-phase stationary coordinate system.

[0080] like Figure 2 The traditional decoupled dual synchronous frame phase-locked loop has a low-pass filter delay, and the decoupling network also needs to use the filtered value for calculation, which greatly reduces the speed of separating the positive and negative sequence voltages and the speed of the phase-locked loop phase-locked loop. In addition, the phase-locked loop used is also the most basic synchronous frame phase-locked loop. Once the DDSRF positive and negative sequence decomposition is not complete, the negative sequence voltage is also coupled in the positive sequence voltage, which will cause the phase-locked loop to fail to lock. If the phase is wrong, the result after the dq conversion will be an AC quantity, which cannot be controlled, causing the inverter to work in an unstable state.

[0081] Traditional decoupled dual synchronous coordinate system phase-locked loop phase-locked principle

[0082]

[0083] Where U + is the positive sequence voltage amplitude, U - is the negative sequence voltage amplitude, U 0 is the zero-sequence voltage amplitude. Since the inverter does not have a zero-sequence path, the zero-sequence voltage component can be ignored. is the initial phase angle of the positive sequence voltage, is the initial phase angle of negative sequence voltage, is the initial phase angle of zero-sequence voltage.

[0084] Transfer the abc coordinate system to the αβ coordinate system through Clarke transformation

[0085]

[0086] Where: u αβ represents the voltage vector sum in the αβ coordinate system, Indicates the amplitude is U + , the positive sequence voltage component with angular velocity ω rotating counterclockwise, Indicates the amplitude is U - , the angular velocity is the negative sequence voltage component with clockwise rotation.

[0087] From formula (3), it can be concluded that under the unbalanced condition of the three-phase grid voltage, the voltage vector in the αβ coordinate system can be decomposed into a positive sequence voltage component with an amplitude of the positive sequence voltage and an angular velocity of +ω rotating counterclockwise and a negative sequence voltage component with an amplitude of the negative sequence voltage and an angular velocity of -ω rotating clockwise. The positive and negative sequence voltage signals coupled after dq transformation can be expressed by formulas (4), (5), and (7)

[0088]

[0089] in It represents the representation of the positive sequence voltage component in the dq coordinate system, It represents the negative sequence voltage component in the dq coordinate system, It represents the representation of the positive sequence voltage component in the α-β coordinate system, It represents the negative sequence voltage component in the α-β coordinate system,

[0090]

[0091]

[0092] where u d+ and u q+ represents the d-axis voltage and q-axis voltage obtained after the angular velocity is ω Park transformation, u d- and u q- represents the d-axis voltage and q-axis voltage obtained after the angular velocity is -ω Park transformation. represents the d-axis component of the positive sequence voltage, represents the q-axis component of the positive sequence voltage, represents the d-axis component of the negative sequence voltage, represents the q-axis component of the negative sequence voltage, ω represents the grid angular frequency, t represents time, express The d-axis positive sequence voltage after passing through the first-order low-pass filter is: express The q-axis positive sequence voltage after passing through the first-order low-pass filter, express The d-axis negative sequence voltage after passing through the first-order low-pass filter is: express The q-axis negative sequence voltage after passing through the first-order low-pass filter.

[0093] pass Figure 5 The decoupling network shown can eliminate the negative sequence double frequency AC component in the positive sequence voltage and the positive sequence double frequency AC component in the negative sequence voltage, and obtain the positive sequence DC component and the negative sequence DC component. The negative sequence DC component is used as the input of the SRF-PLL phase-locked loop, and the phase-locked angle required for the Park transformation is obtained through the PI controller and the integral link. The positive sequence DC component and the negative sequence DC component continue to pass through the low-pass filter to attenuate the fluctuating components and return them to the decoupling network for calculation. Finally, the positive sequence DC component and the negative sequence DC component are attenuated by Figure 7 The control structure obtains the modulation wave of the inverter.

[0094] This embodiment and Figure 2 The difference is:

[0095] like Figure 4 As shown in the figure, a second-order generalized integrator (SOGI) is added to the front stage of the DDSRF-PLL. ω is the resonant frequency of the SOGI, and k is the attenuation coefficient of the SOGI. Although its bandwidth and gain are affected not only by the attenuation coefficient k but also by the resonant frequency ω', the SOGI, as the front stage of the DDSRF phase-locked loop, only needs to enhance the harmonic suppression capability and response speed. The positive and negative sequence separation steps are calculated and decomposed by the decoupling network of the DDSRF. Figure 8 Bode plots of the filter for different k values ​​are shown. Comparing the filtering effect and phase steady-state characteristics, smaller k values ​​improve harmonic suppression but also slow down the response. k = 1.414 provides better filtering performance than k = 3, and better phase steady-state performance than k = 0.3. Taking all these factors into consideration, the attenuation coefficient k is set to 1.414, while the resonant frequency is generally set to the grid frequency of 50 Hz.

[0096] like Figure 6 As shown in the figure, a sliding average filter (MAF) is introduced into the SRF-PLL and improved. MAF can obtain good phase-locked performance under distorted power grid. However, MAF needs to average the signal within a long window period, and the dynamic response speed is greatly weakened. To solve this problem, a correction link G is introduced. d An improved moving average filter (EMAF-PLL) is obtained, and the transfer function is as follows:

[0097]

[0098] Where μ is the attenuation factor, 0<μ<1;

[0099]

[0100] The transfer function of EMAF in the z domain is:

[0101]

[0102] N represents the sampling order of EMAF:

[0103]

[0104] Where T s is the sampling period of the control system, T s =0.1Ms. The window length of EMAF is half of the power frequency period; that is, T w =0.01s. At this time, EMAF can consider filtering the even harmonic components in the grid voltage signal in the synchronous reference frame, which corresponds to the odd harmonic components in the EMAF-PLL input voltage signal.

[0105] The transfer function of EMAF is approximated by the second-order Padé approximation to obtain the transfer function of GMAF:

[0106]

[0107] The transfer function of the EMAF-PLL is:

[0108]

[0109] According to the stability and dynamic response performance of the PLL, the attenuation coefficient α is selected as 0.25. The transfer function of the EMAF-PLL conforms to the typical type II system tuning form. The transfer function of the EMAF-PLL is tuned using the typical type II system parameters to enhance the anti-interference ability of the phase-locked loop and reduce the overshoot problem caused by the double integration. p =0.45, k i =2.

[0110] At this point, the design of the phase-locked method under unbalanced power grid conditions is completed.

[0111] To verify the performance of the phase-locked loop proposed in this invention, a MATLAB / Simulink platform was used to build an energy storage load circuit, and grid connection was achieved through an inverter and a three-phase LCL filter circuit. Based on this main circuit, the following tests were conducted: heavy-load three-phase symmetrical low-voltage ride-through, light-load three-phase symmetrical low-voltage ride-through, heavy-load two-phase asymmetrical low-voltage ride-through, and light-load two-phase asymmetrical low-voltage ride-through. The active power generated by the heavy load was 0.9 pu, and the active power generated by the light load was 0.2 pu. In the three-phase symmetrical low-voltage ride-through, the voltage of the three phases A, B, and C decreased by 0.5 pu at 0.5 s, and the three-phase voltages returned to balance after 1 s. In the two-phase asymmetrical low-voltage ride-through, the voltage of the two phases A and B decreased by 0.5 pu at 0.5 s, the voltage of the phase C remained unchanged, and the two-phase voltages returned to balance after 1 s.

[0112] from Figure 9 The DDSRF phase-locked loop (PLL) experiences significant frequency fluctuations during low-voltage ride-through and is prone to instability when operating under harsh grid conditions. The MAF phase-locked loop (PLL) performs better than the DDSRF phase-locked loop (PLL). However, the frequency fluctuations of the hybrid PLL are much smaller than those of the DDSRF and MAF phase-locked loops, and its recovery response speed is also faster than the comparison algorithms. Figure 10 The power tracking speed of the hybrid PLL is initially slower than that of the DDSRF PLL and MAF PLL, but when the voltage drops to 0.5 pu, the power reduction rate of the hybrid PLL exceeds that of the comparison algorithm. When the voltage increases within 1 s, the power increase rate of the hybrid PLL is also much faster than that of the comparison algorithm.

[0113] Figure 11 The frequency fluctuation range of the hybrid PLL is smaller than that of the comparison algorithm, but the recovery speed during the two traversal periods is slower than that of the comparison algorithm. Figure 12 The power of the comparison algorithm overshoots during ride-through, especially when the voltage recovers at 1 second. The power of the comparison algorithm reaches 1.4 pu, and the current at this time exceeds twice the rated current, which can easily harm the components of the grid-connected system and require excessive resources for component maintenance. However, the hybrid PLL does not overshoot during low-voltage ride-through, and the overshoot during voltage recovery is much smaller than that of the comparison algorithm.

[0114] Figure 13 The frequency fluctuation range of the hybrid PLL is smaller than that of the comparison algorithm, and the frequency dynamic recovery speed is faster than that of the comparison algorithm.

[0115] Figure 14 The tracking speed of the hybrid PLL is faster than that of the comparison algorithm.

[0116] Figure 15 The frequency fluctuation range of the hybrid PLL is smaller than that of the comparison algorithm, and the frequency dynamic recovery speed is improved compared with the three-phase weighed load low voltage ride-through, and the speed is faster than the comparison algorithm, which proves the superiority of the frequency dynamic characteristics of the hybrid PLL in dealing with unbalanced grid voltage. Figure 16 The comparison algorithm showed overshoot during low voltage ride-through and voltage recovery.

[0117] pass Figures 9-16 It can be seen from the comparison that the phase-locked loop proposed in the present invention has excellent characteristics in both steady-state characteristics and dynamic tracking capabilities. It can quickly and accurately achieve the phase-locked function when the grid voltage undergoes symmetrical low voltage ride-through and asymmetrical low voltage ride-through, and is fully suitable for grid-connected synchronization applications under unbalanced power grids.

[0118] The present invention has the following effects:

[0119] (1) The pre-stage SOGI filter provided by the present invention pre-processes the collected voltage signal on the basis of the DDSRF phase-locked loop, and removes the redundant noise signals outside the grid frequency without losing accuracy, making the frequency dynamics significantly smoother and the fluctuation range much smaller, thereby increasing the stability of the phase-locked loop.

[0120] (2) The EMAF-PLL provided by the present invention adds a correction link on the basis of the ordinary MAF-PLL, which solves the disadvantage of MAF-PLL being unstable when the grid frequency suddenly changes. In addition, the second-order Padé approximation is used to solve the system delay problem caused by the increase in the filter window introduced by MAF-PLL, thereby accelerating the response speed of the system.

[0121] The hybrid decoupled dual synchronous coordinate system phase-locked loop proposed in this invention enhances the stability of frequency locking and phase locking on the basis of the traditional phase-locked loop, reduces the error, and effectively improves the dynamic characteristics and steady-state performance of the grid-connected system.

[0122] To sum up, the above is only a specific embodiment of the present invention, but the scope of protection of the present invention is not limited to this. Any changes or replacements that can be easily thought of by technicians in this technical field within the technical scope disclosed by the present invention should be covered by the scope of protection of the present invention.

Claims

1. A phase-locking method suitable for use in unbalanced power grid conditions, characterized by: The following steps are involved: Step 1: Use the three-phase voltage coordinate transformation unit to transform the three-phase voltage V abc Convert to α and β components in a two-phase stationary coordinate system; Step 2: Process the α and β components through the second-order generalized integrator SOGI to generate two mutually orthogonal signals u′ α , u′ β ; Step 3: Transform the quadrature signal u′ output by SOGI α , u′ β The positive sequence voltage component is separated by inputting it into the decoupling network through Park transformation. and negative sequence voltage component Step 4: Use a first-order low-pass filter to filter the separated positive sequence and negative sequence components Perform smoothing and extract the DC component to obtain the positive sequence DC component and negative sequence DC component And return these DC components to the decoupling network in step 3 as input; Step 5: Use the improved moving average filter (EMAF) to decouple the q-axis positive sequence voltage obtained from the network The signal is dynamically corrected to generate a phase-locked angle, which is then adjusted through a proportional-integral controller and an integral link 1 / s to output a synchronization signal to control the output current of the grid-connected inverter.

2. The method according to claim 1, characterized in that In step 1, the three-phase voltage V at the point of common coupling (PCC) abc Connect the Clarke transform unit and transform the signal from the three-phase stationary coordinate system to the two-phase stationary coordinate system through Clarke transform to obtain the α component and β component. The matrix of Clarke transform is expressed as: U a Indicates the voltage of phase A, U b Indicates the B phase voltage, U c Indicates the C phase voltage, u α represents the transformed α-axis component, u β represents the β-axis component after transformation.

3. The method according to claim 1, characterized in that In step 2, the voltage component u in the two-phase stationary coordinate system is α and u β The input is to the second-order generalized integrator SOGI, which generates two pairs of mutually orthogonal signals through the following transfer function: u′ α =G(s)u α u′ β =G(s)u β Where s represents the complex frequency variable, k represents the SOGI attenuation coefficient, ω′ represents the SOGI center angular frequency, and s represents the complex frequency variable.

4. The method according to claim 1, wherein In step 3, the quadrature signal u′ output by the second-order generalized integrator (SOGI) is converted to α , u′ β The Park transformation is input to the decoupling network to eliminate the coupling between the positive sequence voltage component and the negative sequence voltage component. and The decoupling network is decoupled by the following matrix operation: where u d+ and u q+ represents u′ α and u′ β The d-axis voltage and q-axis voltage are obtained after the angular velocity is ω Park transformation, u d- and u q- represents u′ α and u′ β The d-axis voltage and q-axis voltage obtained after the angular velocity is -ω Park transformation are: represents the d-axis component of the positive sequence voltage, represents the q-axis component of the positive sequence voltage, represents the d-axis component of the negative sequence voltage, represents the q-axis component of the negative sequence voltage, ω represents the grid angular frequency, t represents time, express The d-axis positive sequence voltage after passing through the first-order low-pass filter is: express The q-axis positive sequence voltage after passing through the first-order low-pass filter, express The d-axis negative sequence voltage after passing through the first-order low-pass filter is: express The q-axis negative sequence voltage after passing through the first-order low-pass filter.

5. The method according to claim 1, wherein In step 4, The positive sequence voltage component of the decoupling network output and negative sequence voltage component Input them into the first-order low-pass filter (LPF) respectively, attenuate the fluctuation component through the following transfer function, extract the DC component, and obtain the positive sequence DC component and negative sequence DC component s represents a complex frequency variable, ω f represents the low-pass filter cutoff angular frequency, ω represents the grid angular frequency, and k′ represents the filter coefficient ratio.

6. The method according to claim 1, characterized in that In step 5, The q-axis positive sequence voltage obtained by the decoupling network The input is sent to the improved moving average filter (EMAF), and dynamic correction is achieved through the following transfer function to generate the phase-locked angle. The phase-locked angle is adjusted through the proportional-integral controller and the integral link 1 / s. The phase-locked loop adjustment transfer function is: k p represents the proportional gain, k i represents the integral gain, μ represents the attenuation factor, T W represents the EMAF filter window time constant, θ pll is the phase-locked angle output by the improved sliding average filter.

7. The method according to claim 6, characterized in that Obtained by the following steps: Step a: Build a basic model based on the transfer function of the traditional moving average filter MAF: By averaging the input signal within a time window, the transfer function of the traditional moving average filter MAF is: Step b: Introduce a correction link to optimize dynamic performance and design the correction link G d (s), its transfer function is: Step 3: Derivation of the transfer function of the improved moving average filter EMAF combined with the correction link Combine the traditional MAF with the correction link G d (s) are connected in series to obtain the transfer function of the improved moving average filter EMAF: G EMAF (s)=G MAF (s)·G d (s) Substituting the expressions in step a and step b, we can get the following after simplification: Further, the exponential term is converted to Converted to rational function form, it is finally simplified to: G MAF (s) represents the transfer function of the moving average filter MAF, G d (s) Transfer function of the correction link, T W Indicates the EMAF filter window time constant, G EMAF (s) represents the transfer function of the improved moving average filter, k p represents the proportional gain, k i represents the integral gain, μ represents the attenuation factor, 0<μ<1.

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