MoS2-based thin film transistor MOSFET structure and preparation method thereof

Abstract

The invention discloses a MoS2-based thin film transistor MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) structure and a preparation method thereof, and belongs to the technical field of semiconductors. Comprising a drain electrode, a semiconductor epitaxial layer, a source electrode and a grid electrode; by arranging the lightly doped N layer in the middle of the N drift layer and cooperating with the design of the arc-shaped side-symmetric P-layers on the two sides, the electric field distribution in the device is effectively optimized, the lightly doped N layer widens a depletion region between a channel and a drain electrode and weakens the permeation of a drain electrode electric field to the channel, and the arc-shaped side-symmetric P-layers and the N substrate layer are in direct contact to form a transverse field limiting ring, so that the device performance is improved. And electric field concentration is further dispersed, the induced barrier lowering effect and the hot carrier effect of the drain electrode are reduced, and the control capability of the grid electrode on the channel is enhanced, so that the problems of subthreshold swing increase, threshold voltage drift and the like are inhibited, and the switching controllability of the device is improved.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a MoS2-based thin film transistor (MOSFET) structure and a preparation method thereof. Background Art

[0002] Since its inception, the Metal Oxide Semiconductor Field-Effect Transistor (MOSFET) has played an irreplaceable core role in numerous electronic fields, including integrated circuits, due to its unique advantages. Early advances in the field, such as growing a thin, high-quality thermally oxidized SiO2 layer on the silicon surface to effectively neutralize surface states, laid the key foundation for the birth of the MOSFET. Since then, with the continuous evolution of technology, MOSFET has been widely used in various circuits, from simple drive circuits to complex power rectifiers and inverters, becoming the cornerstone of modern electronic systems. The prior art (Announcement No.: CN119947193A) discloses a Schottky thin-film transistor structure based on a polycrystalline indium oxide active layer and a preparation method thereof. The technology includes a substrate, a gate electrode, a gate dielectric layer, an active layer, a barrier layer, an ohmic contact electrode, and a Schottky contact electrode stacked in sequence. The active layer covers the gate dielectric layer and is polycrystalline indium oxide grown by metal organic chemical vapor deposition, and has an optical band gap greater than 3.1 eV. The barrier layer completely covers the active layer and is made of a high-bandgap insulating material with a thickness of ≤5 nm. The active layer of this technology uses polycrystalline indium oxide, which increases the saturation current of the Schottky thin-film transistor. The use of a high-bandgap insulating material with a thickness of no more than 5 nm as the barrier layer reduces the off-state current of the indium oxide Schottky transistor. However, as integrated circuits develop towards higher integration and faster computing speeds, the characteristic dimensions of MOSFETs continue to shrink in order to achieve higher device density and faster switching speeds. However, when the device size enters the nanoscale range, the short channel effect becomes increasingly significant, resulting in an intensification of the drain-induced barrier lowering effect and the hot carrier effect. The short channel effect weakens the gate's effective control over the channel, resulting in an increase in the subthreshold swing, a decrease in the threshold voltage, and difficulty in precise control, which in turn significantly increases the device's leakage current. This not only significantly increases power consumption, but also seriously affects the device's switching speed and reliability, greatly limiting further improvements in integrated circuit performance. Summary of the Invention

[0003] Purpose of the invention: The purpose of the present invention is to provide a solution to the problems raised in the background technology.

[0004] Technical solution: A MoS2-based thin-film transistor MOSFET structure and its preparation method, comprising a plurality of mutually parallel MOS cells, wherein a single MOS cell comprises a drain, a semiconductor epitaxial layer, a source, and a gate; the semiconductor epitaxial layer comprises an N substrate layer, an N drift layer, a P+ layer, an N well layer, and a P well layer; a lightly doped N layer is provided in the middle of the N drift layer of a single MOS cell; A laterally symmetric P-layer is provided inside a single MOS cell and on the left and right sides of the N drift layer. The cross-sectional profiles of the two laterally symmetric P-layers are both arc-shaped, and the bottom ends of the two laterally symmetric P-layers are in contact with the upper surface of the N substrate layer.

[0005] Furthermore, a semicircular P-layer is formed inside the lightly doped N layer by ion implantation, and the bottom end of the semicircular P-layer contacts the upper surface of the N substrate layer.

[0006] Furthermore, a heavily doped N layer is formed inside the lightly doped N layer and outside the semicircular P-layer by ion implantation. The cross-sectional profile of the heavily doped N layer is semicircular, and the inner side of the heavily doped N layer contacts the outer side of the semicircular P-layer.

[0007] Furthermore, a semi-elliptical P-layer is formed on the top of the heavily doped N layer by ion implantation.

[0008] Furthermore, the N substrate layer is made of rigid glass.

[0009] Furthermore, trapezoidal heavily doped N-type half layers are formed on the left and right sides of the lightly doped N layer and outside the heavily doped N layer by ion implantation.

[0010] Furthermore, a Y-shaped heavily doped N-type half layer is formed inside the lightly doped N layer by ion implantation, and the bottom end of the Y-shaped heavily doped N-type half layer contacts the upper surface of the N substrate layer.

[0011] Furthermore, triangular heavily doped N-type half layers are formed on the left and right sides of the lightly doped N layer by ion implantation, and the bottom ends of the two triangular heavily doped N-type half layers are in contact with the upper surface of the N substrate layer.

[0012] A method for preparing a MoS2-based thin-film transistor (MOSFET) structure, comprising: S1. Select the N substrate layer made of rigid glass, ultrasonically clean it with acetone, ethanol, and deionized water in sequence to remove surface organic matter and impurity particles, then dry it in an oven, and then treat it with oxygen plasma to improve its surface activity; S2. Depositing the N drift layer on the N substrate layer using low-pressure chemical vapor deposition (LPCVD) technology, with a mixture of silane and phosphine as the reaction gas, and performing high-temperature annealing in a nitrogen atmosphere after the deposition is completed to eliminate lattice defects generated during the deposition process; S3. Forming a rectangular mask pattern of the lightly doped N layer in the middle region of the N drift layer using a photolithography technique, then using an ion implantation process to implant nitrogen ions into the rectangular mask pattern region to form the lightly doped N layer. After the implantation is completed, removing the photoresist, then defining an arc-shaped region of the laterally symmetric P-layer using a new photolithography mask, implanting boron ions, and forming an arc-shaped cross-section of the laterally symmetric P-layer using a thermal diffusion process, ensuring that its bottom end contacts the upper surface of the N substrate layer. After the implantation is completed, placing the layer in an annealing furnace to repair lattice damage. S4. Define a semicircular region 1 inside the lightly doped N layer by photolithography, then use an ion implantation process to implant boron ions into the semicircular region 1 to form the semicircular P-layer, ensuring that its bottom end is in contact with the upper surface of the N substrate layer; then define a semicircular region 2 outside the semicircular P-layer by photolithography, and implant phosphorus ions into the semicircular region 2 to form the heavily doped N layer, ensuring that its inner side is in close contact with the outer side of the semicircular P-layer; after the implantation is completed, place the device in an annealing furnace to repair lattice damage; S5. Defining a semi-elliptical region on top of the heavily doped N layer by a photolithography process, implanting boron ions into the semi-elliptical region by an ion implantation process to form the semi-elliptical P-layer, and performing annealing to activate the implanted impurity ions. S6, then defining trapezoidal regions on the left and right sides of the lightly doped N-type layer by photolithography, and implanting phosphorus ions into the trapezoidal regions by ion implantation to form the trapezoidal heavily doped N-type half-layer, followed by annealing to further activate impurities and repair lattice damage; S7, using a combination of photolithography and ion implantation to sequentially implant corresponding impurities in designated areas to form the P+ layer, the N-well layer, and the P-well layer, wherein boron ions are implanted in the P+ layer, phosphorus ions are implanted in the N-well layer, and boron ions are implanted in the P-well layer. After the implantation is completed, annealing is performed to activate the impurities and repair lattice damage; S8. Finally, by photolithography or sputtering process, metal layers are sequentially deposited and patterned to form ohmic contacts and Schottky contacts of the drain, the source, and the gate.

[0013] Beneficial effects: 1. The present invention effectively optimizes the electric field distribution inside the device by disposing a lightly doped N layer in the middle of the N drift layer and combining it with the design of arc-shaped symmetrical P-layers on both sides. The lightly doped N layer widens the depletion region between the channel and the drain, weakening the penetration of the drain electric field into the channel. The arc-shaped symmetrical P-layer directly contacts the N substrate layer to form a lateral field confinement ring, further dispersing the electric field concentration, reducing the drain-induced barrier lowering effect and hot carrier effect, and enhancing the gate's control over the channel, thereby suppressing problems such as increased subthreshold swing and threshold voltage drift, and improving the device's switching controllability. 2. A complementary doping structure is formed by a semicircular P-layer within the lightly doped N-layer, a heavily doped N-layer, and a semi-elliptical P-layer on top. The gradient barrier design strengthens the constraint on carrier transport. The semicircular P-layer contacts the N substrate layer to form a longitudinal PN junction, expanding the space charge region to suppress leakage current. The heavily doped N-layer provides a low-resistance conductive channel to reduce current transmission loss. The semi-elliptical P-layer regulates the electric field on the top of the heavily doped N-layer to avoid abnormal carrier aggregation. The synergistic effect of the three significantly reduces device leakage current, reduces power consumption, and improves switching speed. 3. The present invention provides stable mechanical support for the device through a rigid glass N-type substrate layer, reducing stress-induced defects commonly seen in flexible substrates. Combined with the symmetrical design of the trapezoidal heavily doped N-type half-layer, the carrier transport path within the nanochannel is more uniform, avoiding thermal failure caused by localized excessive current. Furthermore, the Y-shaped, triangular, and other heavily doped N-type half-layers further optimize carrier transport efficiency through multi-path conduction design and natural doping gradients, enhancing the consistency of the device's electrical performance. 4. The preparation process of the present invention adopts a combination of photolithography and ion implantation to achieve precise doping and patterning of each functional layer. Combined with multi-step annealing treatment, it effectively repairs lattice damage and activates impurities, ensuring the stability and reliability of the device structure. The synergistic effect of the overall structure and process enables the device to maintain excellent electrical properties at the nanoscale, breaking through the bottleneck of traditional MOSFET in high-density integration and high-performance applications, and providing strong support for the further development of integrated circuits. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] Figure 1 is a schematic structural diagram of embodiment 1 of the present invention; Figure 2 is a schematic structural diagram of embodiment 2 of the present invention; Figure 3 is a schematic structural diagram of embodiment 3 of the present invention; Figure 4 is a schematic structural diagram of embodiment 4 of the present invention; Figure 5 is a schematic structural diagram of embodiment 5 of the present invention; Figure 6 is a schematic structural diagram of embodiment 6 of the present invention; Figure 7 It is a structural diagram of Example 7 of the present invention.

[0015] In the figure: 1. drain; 2. source; 3. gate; 4. N substrate layer; 5. N drift layer; 6. P+ layer; 7. N well layer; 8. P well layer; 9. lightly doped N layer; 10. laterally symmetrical P- layer; 11. semicircular P- layer; 12. heavily doped N layer; 13. semi-elliptical P- layer; 14. trapezoidal heavily doped N-type half layer; 15. Y-shaped heavily doped N-type half layer; 16. triangular heavily doped N-type half layer. DETAILED DESCRIPTION

[0016] In order to make the technical solution of the present invention clearer, the present invention is further described in detail below with reference to the accompanying drawings and specific embodiments.

[0017] like Figure 1-7 As shown, according to one aspect of the present invention, a method for preparing a thin film transistor MOSFET structure based on MoS2 is provided, comprising: Step 1: Select an N substrate layer 4 made of rigid glass, and ultrasonically clean it with acetone, ethanol, and deionized water in sequence to remove surface organic matter and impurity particles. Then, dry it in an oven, and then treat it with oxygen plasma to improve its surface activity. By selecting rigid glass as the N substrate layer 4, the heat resistance requirements of subsequent high-temperature processes are met. Acetone is used to dissolve surface oily organic matter, and ethanol is used to remove residual acetone and further degrease. Deionized water is used to rinse residual chemical reagents and particulate impurities to avoid impurities causing subsequent thin film deposition defects. At the same time, plasma bombardment of the glass surface introduces polar groups such as hydroxyl groups, thereby increasing surface energy, enhancing adhesion with the subsequently deposited N drift layer 4, and reducing the risk of interface delamination.

[0018] Step 2: Deposit an N drift layer 5 on the N substrate layer 4 using low-pressure chemical vapor deposition technology. The reaction gas is a mixture of silane and phosphine. After deposition, high-temperature annealing is performed in a nitrogen atmosphere to eliminate lattice defects generated during the deposition process. Silane provides a silicon skeleton, and phosphine serves as a donor impurity source. By adjusting the ratio of the two, the doping concentration of the N drift layer 5 is precisely controlled to ensure that it is an N-type semiconductor. At the same time, high-temperature annealing in a nitrogen atmosphere rearranges the lattice atoms, eliminating defects such as vacancies and dislocations generated by disordered atomic arrangement during the deposition process, thereby improving carrier mobility.

[0019] Step 3: A rectangular mask pattern of a lightly doped N layer 9 is formed in the middle area of ​​the N drift layer 5 by photolithography technology, and then nitrogen ions are implanted into the rectangular mask pattern area by ion implantation process to form a lightly doped N layer 9. After the implantation is completed, the photoresist is removed, and then a new photolithography mask is defined to form an arc-shaped area of ​​the side-symmetrical P-layer 10, and boron ions are implanted. The side-symmetrical P-layer 10 is formed into an arc-shaped cross-section by a thermal diffusion process to ensure that its bottom end contacts the upper surface of the N substrate layer 4. After the implantation is completed, it is placed in an annealing furnace to repair lattice damage; the lightly doped N layer 9 is located in the N drift layer 5 In the middle, as an auxiliary channel for carrier transmission, its low doping characteristics can reduce the on-resistance, and at the same time form a doping gradient with the surrounding area to optimize the electric field distribution. The side-symmetrical P-layer 10 can disperse the electric field concentration at the corner through the arc structure design, thereby improving the device breakdown voltage. The bottom end contacts the N substrate layer 4 to form a "lateral PN junction", further optimizing the electric field distribution of the N drift layer 5 and suppressing the avalanche breakdown on the drain 1 side. Through thermal diffusion, boron ions diffuse along the arc path to form a smooth doping profile. Annealing repairs the lattice damage caused by ion implantation, activates impurities, and restores the semiconductor conductivity.

[0020] Step 4: Define a semicircular area 1 inside the lightly doped N layer 9 by photolithography, then use ion implantation to implant boron ions into the semicircular area 1 to form a semicircular P- layer 11, ensuring that its bottom end is in contact with the upper surface of the N substrate layer 4, then define a semicircular area 2 outside the semicircular P- layer 11 by photolithography, and implant phosphorus ions into the semicircular area 2 to form a heavily doped N layer 12, making its inner side in close contact with the outer side of the semicircular P- layer 11. After the implantation is completed, place it in an annealing furnace to repair lattice damage; the semicircular P- layer 11 is part of the "field limiting ring". The N-type layer 11 is divided into two parts, forming a PN junction with the N-type layer, further dispersing the electric field by expanding the space charge region, and improving the voltage resistance of the device. The heavily doped N layer 12 forms a low-resistance channel by high phosphorus doping, connecting the drain 1 and the N drift layer 5, reducing the contact resistance, and forming a "complementary doping structure" with the inner semicircular P-layer 11 to optimize the carrier transport path. At the same time, the semicircular design makes the interface between the semicircular P-layer 11 and the heavily doped N layer 12 smooth, avoiding the electric field concentration caused by the right-angle structure. The close contact between the two ensures the continuous transition of carriers from the N layer to the P-layer, reducing interface scattering.

[0021] Step 5: A semi-elliptical area is defined on the top of the heavily doped N layer 12 through a photolithography process. Boron ions are implanted into the semi-elliptical area using an ion implantation process to form a semi-elliptical P-layer 13. Annealing is then performed to activate the implanted impurity ions. The heavily doped N layer 12 has a semi-elliptical profile to ensure a smooth transition of doping concentration from the center to the edge, thereby avoiding carrier traps caused by the steep interface and improving the switching speed of the device.

[0022] Step 6: Then, trapezoidal regions are defined on the left and right sides of the lightly doped N layer 9 by photolithography, and phosphorus ions are implanted into the trapezoidal regions using an ion implantation process to form a trapezoidal heavily doped N-type half layer 14. Annealing is then performed to further activate the impurities and repair lattice damage. The trapezoidal structure of the two trapezoidal heavily doped N-type half layers 14 can increase the contact area with the source 2 metal and reduce the contact resistance. The left-right symmetrical distribution ensures uniform current distribution on both sides of the device, avoiding thermal failure caused by excessive local current.

[0023] Step seven: Using a combination of photolithography and ion implantation, corresponding impurities are injected into designated areas in sequence to form a P+ layer 6, an N-well layer 7, and a P-well layer 8, wherein the P+ layer 6 is injected with boron ions, the N-well layer 7 is injected with phosphorus ions, and the P-well layer 8 is injected with boron ions. After the implantation is completed, annealing is performed to activate the impurities and repair the lattice damage. The three-layer structure together constitutes the core conductive channel region of the device. The P+ layer 6 provides a low-resistance carrier injection path, and the N-well layer 7 and the P-well layer 8 form a conductive channel under the control of the gate voltage. The annealing treatment activates the impurities and repairs the lattice, ensuring the excellent performance of the channel region.

[0024] Step 8: Finally, through photolithography or sputtering process, metal layers are deposited and patterned in sequence to form ohmic contacts and Schottky contacts of drain 1, source 2 and gate 3; good electrode contact is the guarantee for the normal operation of the device. Ohmic contact ensures that carriers can be transmitted with low loss, and Schottky contact ensures that the gate effectively controls the channel to achieve high performance of the device.

[0025] Example 1 like Figure 1 As shown, a MoS2-based thin-film transistor MOSFET structure is provided, which includes a plurality of mutually parallel MOS cells. A single MOS cell includes a drain 1, a semiconductor epitaxial layer, a source 2, and a gate 3. The semiconductor epitaxial layer includes an N substrate layer 4, an N drift layer 5, a P+ layer 6, an N well layer 7, and a P well layer 8. A lightly doped N layer 9 is provided in the middle of the N drift layer 5 of the single MOS cell. The material of the N substrate layer 4 is made of rigid glass; The lightly doped N layer 9 in the middle of the N drift layer 5 can optimize the electric field distribution between the channel and the drain 1, reduce the abnormal transport of carriers, and thus suppress the increase of leakage current. The N substrate layer 4 made of rigid glass provides stable support, reducing structural defects caused by substrate instability. The synergistic effect of the P+ layer 6, N well layer 7, P well layer 8 and other layers makes the carrier transport more orderly and improves the switching speed of the device. At the same time, the reasonable layout of each layer reduces the aging speed of the device caused by excessive leakage current, enhances the stability during operation, and improves reliability, ultimately breaking the limitation of the leakage current problem on the performance improvement of the integrated circuit, and creating conditions for the realization of higher-performance integrated circuits.

[0026] Example 2 like Figure 2 As shown, a laterally symmetrical P-layer 10 is provided inside a single MOS cell and on the left and right sides of the N drift layer 5. The cross-sectional profiles of the two laterally symmetrical P-layers 10 are both arc-shaped, and the bottom ends of the two laterally symmetrical P-layers 10 are in contact with the upper surface of the N substrate layer 4. The laterally symmetrical P-layer 10 disposed inside a single MOS cell, on the left and right sides of the N-drift layer 5, has an arc-shaped profile that enables a uniform distribution of the electric field at the interface between the laterally symmetrical P-layer 10 and the surrounding N-type region, avoiding electric field concentration caused by right-angle or acute-angle structures, thereby reducing abnormal carrier multiplication and injection. The bilaterally symmetrical layout balances the electrical characteristics of the left and right sides of the device, ensuring symmetrical and stable carrier transport paths. The design of direct contact between the bottom end and the N-substrate layer 4 can expand the space charge region through the lateral PN junction formed by the laterally symmetrical P-layer 10 and the N-substrate layer 4, further optimizing the electric field distribution in the entire drift region, enhancing the suppression of the drain electric field from penetrating into the channel region, and at the same time improving the device's withstand voltage capability under reverse bias, reducing the risk of leakage and breakdown due to excessive local electric fields, and ultimately improving the overall stability and operational reliability of the device.

[0027] Example 3 like Figure 3 As shown, a semicircular P-layer 11 is formed inside the lightly doped N layer 9 by ion implantation, and the bottom end of the semicircular P-layer 11 contacts the upper surface of the N substrate layer 4; The semicircular P-layer 11 is formed inside the lightly doped N layer 9 by ion implantation. Its semicircular profile enables a smooth transition between the interface of the P-layer 11 and the surrounding lightly doped N layer 9, avoiding the electric field concentration caused by the steep boundary, and helping to optimize the local electric field distribution. The bottom end is in direct contact with the N substrate layer 4. The longitudinal PN junction formed by the P-layer 11 and the N substrate layer 4 can expand the space charge region, enhance the constraint on the movement of carriers near the channel, reduce the uncontrolled current between the drain and the source, and cooperate with the laterally symmetric P-layer 10 to further enhance the control ability of the gate 3 over the channel, suppress abnormal leakage caused by structural defects or electric field disorder, and thus enhance the stability and reliability of the device operation.

[0028] Example 4 like Figure 4 As shown, a heavily doped N layer 12 is formed inside the lightly doped N layer 9 and outside the semicircular P-layer 11 by ion implantation. The cross-sectional profile of the heavily doped N layer 12 is semicircular, and the inner side of the heavily doped N layer 12 contacts the outer side of the semicircular P-layer 11. A semicircular heavily doped N layer 12 is formed by ion implantation inside the lightly doped N layer 9 and outside the semicircular P-layer 11. Its semicircular outline forms a fitted arc interface with the outside of the semicircular P-layer 11, ensuring close contact and a smooth transition between the two, avoiding stress concentration and charge accumulation at the interface, and facilitating smooth transport of carriers between adjacent regions. The heavily doped characteristic gives this region a low resistance characteristic, which can serve as an efficient conduction channel for carriers, reducing energy loss during current transmission, and forming a complementary doping structure with the inner semicircular P-layer 11. Through the synergistic effect of the two, the electric field distribution inside the lightly doped N layer 9 is further optimized, the ability to control the potential of the channel region is enhanced, unnecessary leakage current paths are suppressed, and the switching response speed and working stability of the device are improved in conjunction with other layered structures.

[0029] Example 5 like Figure 5 As shown, a semi-elliptical P-layer 13 is formed on the top of the heavily doped N layer 12 by ion implantation, and a trapezoidal heavily doped N-type half layer 14 is formed on the left and right sides of the lightly doped N layer 9 and outside the heavily doped N layer 12 by ion implantation; The semi-elliptical P-layer 13 formed by ion implantation on the top of the heavily doped N layer 12, and the trapezoidal heavily doped N-type half-layer 14 formed by ion implantation on the left and right sides of the lightly doped N layer 9 and outside the heavily doped N layer 12, are formed. The curved profile of the semi-elliptical P-layer 13 smoothly connects with the top of the heavily doped N layer 12. During device operation, its P-type characteristics can regulate the electric field distribution at the top of the heavily doped N layer 12, suppressing abnormal carrier accumulation in this area and reducing leakage caused by excessive local electric fields. The trapezoidal structure of the trapezoidal heavily doped N-type half-layer 14 can expand the contact area with adjacent layers. Its heavy doping characteristics ensure a low-resistance path for carrier transmission. At the same time, the bilaterally symmetrical layout can balance the current distribution on both sides of the lightly doped N layer 9, avoiding local overheating caused by excessive current on one side. The semi-elliptical P-layer 13 and the trapezoidal heavily doped N-type half-layer 14 work together to further optimize the potential gradient within the entire lightly doped N layer 9, enhancing the gate's control accuracy over the channel, and improving the switching consistency and operational reliability of the device.

[0030] Example 6 like Figure 6 As shown, a Y-shaped heavily doped N-type half layer 15 is formed inside the lightly doped N-layer 9 by ion implantation, and the bottom end of the Y-shaped heavily doped N-type half layer 15 contacts the upper surface of the N substrate layer 4; The branches of the Y-shaped structure can form multi-path low-resistance conductive channels inside the lightly doped N layer 9, thereby improving the carrier transfer efficiency. At the same time, the junction of the main branch and the branch can disperse the current density to avoid overheating caused by local current concentration. The bottom end is in direct contact with the N substrate layer 4, and a stable conductive connection can be established from the substrate to the inside of the lightly doped N layer 9, thereby enhancing the electrical synergy between the various regions. The interface formed by the Y-shaped profile and the surrounding lightly doped N layer 9 can optimize the local electric field distribution, reduce scattering and loss during carrier transport, and cooperate with other doping layers to further enhance the gate's ability to control the channel, thereby enhancing the switching response speed and operating stability of the device.

[0031] Example 7 like Figure 7 As shown, a triangular heavily doped N-type half layer 16 is formed on the left and right sides of the lightly doped N-layer 9 by ion implantation, and the bottom ends of the two triangular heavily doped N-type half layers 16 are in contact with the upper surface of the N substrate layer 4; The apex of the triangular heavily doped N-type half layer 16 faces the interior of the device, and the bottom is connected to the N substrate layer 4. This shape causes the heavily doped region to gradually narrow from the substrate upward, forming a natural doping concentration gradient, which helps to smoothly transport carriers from the substrate to the channel region and reduce resistance mutations at the interface. The triangular structure symmetrically distributed on both sides can balance the current path inside the lightly doped N layer 9 and avoid unilateral carrier aggregation. At the same time, the sides of the triangle can disperse the local electric field and prevent abnormal carrier movement caused by electric field concentration. The contact between the bottom and the N substrate layer 4 strengthens the electrical connection between the substrate and the active area, and cooperates with other doped layers to optimize the device's conductive performance and gate control efficiency, thereby improving overall operating stability.

[0032] The above-described embodiments merely illustrate several implementations of the present invention, and while their descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the present invention. It should be noted that a person skilled in the art would be able to make numerous variations and improvements without departing from the spirit of the present invention, all of which fall within the scope of protection of the present invention. Therefore, the scope of protection of the present invention shall be determined by the appended claims.

Claims

1. A thin film transistor MOSFET structure based on MoS2, comprising a plurality of mutually parallel MOS cells, wherein a single MOS cell comprises a drain (1), a semiconductor epitaxial layer, a source (2) and a gate (3); the semiconductor epitaxial layer comprises an N substrate layer (4), an N drift layer (5), a P+ layer (6), an N well layer (7) and a P well layer (8), characterized in that: A lightly doped N layer (9) is provided in the middle of the N drift layer (5) of a single MOS cell; A lateral symmetric P-layer (10) is provided inside a single MOS cell and on the left and right sides of the N drift layer (5); the cross-sectional profiles of the two lateral symmetric P-layers (10) are both arc-shaped; and the bottom ends of the two lateral symmetric P-layers (10) are in contact with the upper surface of the N substrate layer (4).

2. The MoS2-based thin film transistor MOSFET structure according to claim 1, characterized in that: A semicircular P-layer (11) is formed inside the lightly doped N layer (9) by ion implantation, and the bottom end of the semicircular P-layer (11) is in contact with the upper surface of the N substrate layer (4).

3. The MoS2-based thin film transistor MOSFET structure according to claim 2, characterized in that: A heavily doped N layer (12) is formed inside the lightly doped N layer (9) and outside the semicircular P-layer (11) by ion implantation. The cross-sectional profile of the heavily doped N layer (12) is semicircular, and the inner side of the heavily doped N layer (12) contacts the outer side of the semicircular P-layer (11).

4. The MoS2-based thin film transistor MOSFET structure according to claim 3, characterized in that: A semi-elliptical P-layer (13) is formed on the top of the heavily doped N layer (12) by ion implantation.

5. The MoS2-based thin film transistor MOSFET structure according to claim 1, characterized in that: The material of the N substrate layer (4) is a rigid glass material.

6. The MoS2-based thin film transistor MOSFET structure according to claim 3, characterized in that: Trapezoidal heavily doped N-type half layers (14) are formed on the left and right sides of the lightly doped N layer (9) and outside the heavily doped N layer (12) by ion implantation, and the opposite sides of the two trapezoidal heavily doped N-type half layers (14) are in contact with the opposite sides of the two N drift layers (5) respectively.

7. The MoS2-based thin film transistor MOSFET structure according to claim 1, characterized in that: A Y-shaped heavily doped N-type half layer (15) is formed inside the lightly doped N layer (9) by ion implantation, and the bottom end of the Y-shaped heavily doped N-type half layer (15) is in contact with the upper surface of the N substrate layer (4).

8. The MoS2-based thin film transistor MOSFET structure according to claim 1, characterized in that: Triangular heavily doped N-type half layers (16) are formed on the left and right sides of the lightly doped N layer (9) by ion implantation, and the bottom ends of the two triangular heavily doped N-type half layers (16) are in contact with the upper surface of the N substrate layer (4).

9. A method for preparing a thin film transistor MOSFET structure based on MoS2, characterized in that: The MoS2 thin film transistor MOSFET structure applied to any one of claims 1-6, wherein the method for preparing the MoS2 thin film transistor MOSFET structure comprises the following steps: S1, selecting the N substrate layer (4) made of rigid glass, and ultrasonically cleaning it with acetone, ethanol, and deionized water in sequence to remove surface organic matter and impurity particles, then drying it in an oven, and then treating it with oxygen plasma to improve surface activity; S2, depositing the N drift layer (5) on the N substrate layer (4) using a low-pressure chemical vapor deposition technique, wherein the reaction gas is a mixture of silane and phosphine, and performing high-temperature annealing in a nitrogen atmosphere after the deposition is completed to eliminate lattice defects generated during the deposition process; S3, forming a rectangular mask pattern of the lightly doped N layer (9) in the middle area of ​​the N drift layer (5) by photolithography technology, and then using an ion implantation process to implant nitrogen ions into the rectangular mask pattern area to form the lightly doped N layer (9), after the implantation is completed, removing the photoresist, and then defining the arc-shaped area of ​​the side-symmetrical P-layer (10) by a new photolithography mask, implanting boron ions, and forming the side-symmetrical P-layer (10) into an arc-shaped cross-section by a thermal diffusion process, ensuring that its bottom end is in contact with the upper surface of the N substrate layer (4), and after the implantation is completed, placing it in an annealing furnace to repair lattice damage; S4, defining a semicircular area 1 inside the lightly doped N layer (9) by photolithography, then using an ion implantation process to implant boron ions into the semicircular area 1 to form the semicircular P-layer (11), ensuring that its bottom end is in contact with the upper surface of the N substrate layer (4), then defining a semicircular area 2 outside the semicircular P-layer (11) by photolithography, implanting phosphorus ions into the semicircular area 2 to form the heavily doped N layer (12), ensuring that its inner side is in close contact with the outer side of the semicircular P-layer (11), and after the implantation is completed, placing the semicircular area in an annealing furnace to repair lattice damage; S5, defining a semi-elliptical region on the top of the heavily doped N layer (12) by a photolithography process, and implanting boron ions into the semi-elliptical region to form the semi-elliptical P-layer (13) by an ion implantation process, and performing annealing to activate the implanted impurity ions after completion; S6, then defining a trapezoidal region on the left and right sides of the lightly doped N-type layer (9) by photolithography, and using an ion implantation process, implanting phosphorus ions into the trapezoidal region to form the trapezoidal heavily doped N-type half layer (14), followed by annealing to further activate the impurities and repair lattice damage; S7, using a combination of photolithography and ion implantation, sequentially implanting corresponding impurities in designated areas to form the P+ layer (6), the N-well layer (7), and the P-well layer (8), wherein the P+ layer (6) is implanted with boron ions, the N-well layer (7) is implanted with phosphorus ions, and the P-well layer (8) is implanted with boron ions. After the implantation is completed, annealing is performed to activate the impurities and repair lattice damage; S8. Finally, by photolithography or sputtering process, metal layers are sequentially deposited and patterned to form ohmic contacts and Schottky contacts of the drain (1), the source (2) and the gate (3).

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