Positioning method and system applied to advanced process SRAM (Static Random Access Memory) soft failure

Abstract

The invention provides a positioning method and system applied to soft failure of an advanced process SRAM (Static Random Access Memory). The method comprises the following steps: determining boundary conditions of failure of a chip; performing laser scanning test: scanning pixel points on the chip one by one by using laser under the condition around the boundary condition to excite Pass / Fail state change of the chip, so that a contrast difference is generated between a failure position and a normal position, and a laser scanning image and a contrast image are obtained; and superposing the laser scanning image and the contrast image to find a failure position on the laser scanning image, comparing the laser scanning image with the corresponding layout layer, and positioning a hot spot on the layout layer according to the failure position. According to the invention, the dynamic test of the chip can be realized through the combination of the existing light emission microscope equipment and the test machine, and the laser scanning function of the light emission microscope equipment is combined to actively excite the change of the state of the chip when the chip fails and is in a normal critical state, so that the failure position is positioned. And the yield and the reliability of the advanced integrated circuit SRAM are improved.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor failure analysis, and in particular to a positioning method and system for advanced process SRAM soft failure. Background Art

[0002] Soft failures in integrated circuits (ICs) typically occur when the chip's operating conditions are affected, and they only occur under specific operating conditions. Soft failures are sensitive to operating conditions and are easily affected by parameters such as temperature, voltage, and frequency. Soft failures can be caused by a variety of factors, including but not limited to: high gate contact resistance, lattice dislocations in the active area (AA), and high resistance between back-end-of-line (BEOL) metal interconnect layers.

[0003] For example, when a read or write test fails in an advanced integrated circuit SRAM (Static Random Access Memory), each group of failed bytes affects eight bytelines, appearing at the same edge of the four arrays of the instance. Each group is separated by 256 bytes. The length of the failed byte line is affected by the test frequency and test voltage. Figure 1 As shown, this type of failure is a soft failure. Figure 1 Fail bit mapping is the failure bit mapping, Scan@LV is the low-voltage scan mode, Scan@MV is the nominal voltage scan mode, and Scan@HV is the high-voltage scan mode.

[0004] Regarding this type of SRAM soft failure, these defects are often invisible during static testing, making it difficult for traditional analysis methods to capture transient fault characteristics. For example, traditional static failure localization methods such as EMMI (light emission microscopy) and OBIRCH (laser-induced resistance change detection) are limited in the number of probes required to apply signals and are unable to pinpoint these issues. The current field lacks solutions that can accurately locate SRAM soft failures, which exhibit spatial regularity and electrical parameter sensitivity under dynamic operating conditions, severely hindering yield improvement and reliability optimization for advanced process memory. Summary of the Invention

[0005] The application aims to provide a positioning method and system for advanced process SRAM soft failure, which can realize dynamic testing of a chip by combining an existing light emission microscope device with a testing machine, actively stimulate state changes of the chip in a chip failure and normal critical state by combining a laser scanning function of the light emission microscope device, and thus position the failure position, thereby improving the yield and reliability of advanced integrated circuit SRAM.

[0006] To achieve the above-mentioned purpose, the application provides a positioning method for advanced process SRAM soft failure, which comprises the following steps:

[0007] determining a boundary condition of chip failure;

[0008] laser scanning testing: using a laser to scan pixel points on the chip one by one under conditions around the boundary condition, so as to stimulate Pass / Fail state changes of the chip, make contrast differences between the failure position and the normal position, and obtain a laser scanning image and a contrast image;

[0009] superimposing the laser scanning image and the contrast image to find the failure position on the laser scanning image, and then comparing the laser scanning image and a corresponding layout layer, and positioning a hot spot on the layout layer according to the failure position.

[0010] Optionally, the boundary condition comprises a voltage boundary condition and a frequency boundary condition.

[0011] Optionally, the laser scanning testing is performed multiple times to obtain multiple contrast images, and the multiple contrast images are superimposed to determine the failure position.

[0012] Optionally, the laser scanning testing is performed by using a testing machine and a positioning machine.

[0013] Optionally, the method of the laser scanning testing comprises the following steps: when the laser scanning testing starts, the testing machine sends a Trigger signal to the positioning machine to make a laser beam of the positioning machine start scanning the pixel points, and the testing machine periodically sends the Trigger signal to the positioning machine to scan the pixel points one by one.

[0014] Optionally, the method of the laser scanning testing comprises the following steps: when the laser scanning testing starts, the testing machine starts to apply a predefined test vector sequence to the chip, obtains a Pass / Fail result after each test of the pixel points is completed, and feeds back the Pass / Fail result to the positioning machine.

[0015] Optionally, the positioning machine generates the contrast image after receiving the Pass / Fail result.

[0016] Optionally, Shmoo analysis is used to determine the boundary conditions under which the chip fails.

[0017] Optionally, samples are prepared according to the location of the hotspot, and physical properties of the samples are analyzed.

[0018] According to another aspect of the present invention, the present invention further provides a positioning system for advanced process SRAM soft failure, comprising:

[0019] A boundary condition determination module, which is used to determine the boundary conditions for chip failure;

[0020] a laser scanning test module, configured to use a laser to scan pixel points on the chip one by one under conditions around the boundary conditions, so as to stimulate a change in the pass / fail state of the chip, thereby generating a contrast difference between the failed position and the normal position, and obtaining a laser scanning image and a contrast image;

[0021] A hotspot positioning module is used to superimpose the laser scanning image and the contrast image to find the failure position on the laser scanning image, and then compare the laser scanning image with the corresponding layout layer to locate the hotspot on the layout layer according to the failure position.

[0022] As configured above, the present invention utilizes the characteristic that the Pass / Fail state of the chip's failure position is easily changed under near-boundary conditions. Laser scanning of the chip under near-boundary conditions is used to actively stimulate the Pass / Fail state change of the chip's failure position, creating a contrast difference between the failure position and the normal position, thereby locating the failure position. Furthermore, the present invention is primarily implemented through the synchronous operation of a tester and a positioning machine (such as a light emission microscope). The tester provides the chip with the power and signals required for operation, as well as a trigger signal to control the movement of the laser beam, and provides feedback of the Pass / Fail result to the positioning machine. The positioning machine uses a laser to scan and image the chip, scanning the chip point by point according to the trigger signal from the tester, providing excitation energy for the change in the chip's Pass / Fail state. It also receives the Pass / Fail result provided by the tester and calibrates the position affected by the laser scanning. In summary, the present invention can achieve dynamic testing of the chip by combining the existing light emission microscope with the tester. The laser scanning function of the light emission microscope actively stimulates the chip's state to change under the critical state between the chip's failure and normal state, thereby locating the failure position, thereby improving the yield and reliability of advanced integrated circuit SRAM. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] Those skilled in the art will appreciate that the accompanying drawings are provided for a better understanding of the present invention and do not constitute any limitation on the scope of the present invention.

[0024] Figure 1 Schematic diagram of the SRAM soft failure Byte distribution in the prior art;

[0025] Figure 2 Schematic diagram of a method for locating soft failures of advanced process SRAM according to an embodiment of the present invention;

[0026] Figure 3 Schematic diagram of Shmoo analysis results of a method for locating soft failures of advanced process SRAM according to an embodiment of the present invention;

[0027] Figure 4 A diagram illustrating a test program setting for a method for locating soft failures in advanced process SRAM according to an embodiment of the present invention;

[0028] Figure 5 A schematic diagram of a plurality of superimposed contrast images of a method for locating soft failures of advanced process SRAM according to an embodiment of the present invention;

[0029] Figure 6 A schematic diagram of a hotspot image and the position of the hotspot on a layout layer in a method for locating soft failures of advanced process SRAMs according to an embodiment of the present invention;

[0030] Figure 7 The SEM images, TEM images, and EDS images are of a method for locating soft failures in advanced process SRAM according to an embodiment of the present invention. DETAILED DESCRIPTION

[0031] In this document, unless otherwise specified, the terms "upper", "lower", "left", "right", "inside", "outside", "front", "back", "top", "bottom", etc. are used to indicate directions or positional relationships based on the accompanying drawings. They are only for the convenience of describing the present invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific direction and operation. Therefore, they cannot be understood as limiting the present invention.

[0032] The following is a more detailed description of the specific embodiments of the present invention with reference to schematic diagrams. The advantages and features of the present invention will become more apparent from the following description. It should be noted that the drawings are greatly simplified and not to exact scale, and are only used for the purpose of conveniently and clearly illustrating the embodiments of the present invention.

[0033] Figure 2 This is a schematic diagram of a method for locating soft failures of advanced process SRAM according to an embodiment of the present invention. Figure 2An embodiment of the present invention provides a method for locating soft failures in advanced SRAM (SRAM) processes. This method requires a tester and a positioning machine. The positioning machine can be a photoemission microscope (PEM), such as the Meridian WS ultra-low-temperature photoemission microscope equipped with a 1320nm laser module manufactured by Thermo Fisher Scientific. The tester can be an ATE tester (Automated Test Equipment) from MOSAID. The method includes steps S1, S2, and S3, which are described in detail below.

[0034] Step S1: Determine the boundary conditions for chip failure, including voltage boundary conditions and frequency boundary conditions.

[0035] Furthermore, Shmoo analysis can be used to determine the boundary conditions for chip failure. For example, the tester and the positioning machine are connected using a load board (interface conversion board), connecting wires and a pin card, and Shmoo analysis is used to determine the boundary conditions for chip failure. Figure 3 Analyze the results for Shmoo, Figure 3 In both (a) and (b), we can see the inclined dividing line. Figure 3 In both (a) and (b), the horizontal axis is voltage and the vertical axis is frequency. The inclined dividing line is the boundary condition for chip failure. One side of the inclined dividing line is the Pass state, and the other side is the Fail state.

[0036] Step S2: Laser scanning test: Use a test machine and a positioning machine to perform a laser scanning test. Use a laser to scan the pixels on the chip one by one under the conditions around the boundary conditions to stimulate the pass / fail state change of the chip, so that the failure position and the normal position have a contrast difference, and obtain a laser scanning image and a contrast image.

[0037] Specifically, the laser is used to scan the pixels on the chip one by one under the conditions around the boundary conditions, that is, the laser is used to scan under the conditions near the boundary. Figure 3 ,exist Figure 3 On the Pass side of (a), a point close to the boundary condition is selected. It can be understood that each point has a corresponding voltage and frequency. At the voltage and frequency of the point, the laser is used to scan the pixels on the chip one by one to obtain the contrast image on the Pass side. Similarly, on the Figure 3 On the Fail side of (b), a point close to the boundary condition is selected, and a laser is used to scan the pixels on the chip one by one at the voltage and frequency of the point to obtain a contrast image on the Fail side.

[0038] Furthermore, the laser scanning test method includes: when the laser scanning test starts, the test machine sends a trigger signal to the positioning machine so that the laser beam of the positioning machine starts to scan the pixel points, and the test machine periodically sends a trigger signal to the positioning machine to scan the pixel points one by one.

[0039] Furthermore, the laser scanning test method includes the following: At the start of the laser scanning test, the tester begins applying a predefined test vector sequence to the chip. After each pixel is tested, a Pass / Fail result is obtained, and the tester feeds the Pass / Fail result back to the alignment machine. Specifically, the tester begins applying the predefined test vector sequence to the chip at the same time as the trigger signal is sent to the alignment machine.

[0040] Specifically, the chip is laser scanned under near-boundary conditions. When the laser scanning test begins, the tester first provides a trigger signal to the laser beam of the positioning machine. After the trigger signal is received by the positioning machine, the laser beam begins to scan the first pixel point (pixel point) within the field of view. At the same time, the tester begins to apply a predefined test vector sequence to the chip. After the first pixel point test is completed, the tester provides a Pass / Fail feedback signal to the positioning machine. You can refer to Figure 4 , Figure 4 This is a schematic diagram of the test program settings. In the figure, Trigger Loop is the trigger loop, Test Loop is the test loop, Pass / Fail PULSE is the result pulse, LOOP START is the loop start point, and LOOP END is the loop end point. The test vector sequence is part of the test program. Specifically, they are a series of input signals in the test program used to verify the specific functions of the chip. It can be understood that the area between two adjacent dotted lines is a test of a pixel. Furthermore, after the positioning machine receives the Pass / Fail result, it generates a contrast image. Exemplarily, after receiving the Pass / Fail result, the positioning machine will mark the pixel point, and Pass and Fail will be marked with different colors to obtain a contrast image. For example, Pass is marked in black and Fail is marked in white. At this time, the positioning machine completes the detection of the first pixel point. After the detection is completed, the next Trigger signal is issued, and the laser beam will move to the next pixel point, repeating the previous steps until the scanning of all pixels in the entire field of view is completed.

[0041] Furthermore, multiple laser scanning tests are performed, that is, the chip is scanned multiple times to obtain multiple contrast images, and the multiple contrast images are superimposed to determine the failure location. Specifically in this embodiment, the contrast images of all Pass sides are superimposed to obtain Figure 5 (c) Superimpose all contrast images on the Fail side to obtain Figure 5 (d), it is understandable that Figure 5 The white spot in (c) is the failure location. Figure 5 The black spot in (d) is the failure position. The position of the white spot should be almost the same as the position of the black spot. The failure position is determined by combining the positions of the white spot and the black spot. For example, the failure position can be selected in the area where the white spot and the black spot positions overlap.

[0042] Step S3: Overlay the laser scanning image and the contrast image to find the failure location on the laser scanning image, then compare the laser scanning image with the corresponding layout layer (layout), and locate the hotspot on the layout layer according to the failure location.

[0043] For example, see Figure 6 ,Depend on Figure 6 It can be found that the hotspot is located at Via3. Figure 6 (e) is the hotspot image, Figure 6 (f) is a schematic diagram of the location of hot spots on the layout layer. Figure 6 The blue dots in the red box in (e) are hot spots. Figure 6 The red dot in the red box in (f) and pointed by the arrow of Via3 is the hot spot. It can be understood that Figure 6 In (f), Via3 is the third through hole, M3 is the third metal layer, and M4 is the fourth metal layer. It can be understood that due to the contrast difference / brightness difference on the contrast image, the failure location can be seen on the contrast image. By superimposing the laser scanning image and the contrast image, the failure location on the contrast image can be found on the corresponding laser scanning image, as shown in the figure. Figure 6 (e) Figure 6 (e) is a hotspot image, a schematic diagram of hotspots on a laser scanning image. Because laser scanning images contain many characteristic patterns (characteristic patterns can be understood as specific geometric shapes or patterns formed on the metal layer of a semiconductor device through processes such as photolithography and etching), locating hotspots on the layout layer is relatively easy with the reference of these characteristic patterns.

[0044] Then, samples are made according to the location of the hot spot, and the physical properties of the samples are analyzed to confirm the morphology of the failure location.

[0045] For example, PFA (physical failure analysis) is performed based on the hot spots to obtain samples. Figure 7 , Figure 7 (g) Figure 6 (f) Corresponding SEM (scanning electron microscope) image, Figure 7Y_CUT in (g) indicates cutting along the red dotted line, and the cut is observed using a TEM (transmission electron microscope). Figure 7 (h), Figure 7 The arrow in (h) indicates the Cu damage undervia3 (Cu damage at the bottom of Via3). Figure 7 (i) is an image observed using EDS (energy dispersive X-ray spectroscopy) after TEM, showing abnormal distribution of Cu (copper) and Ta (tantalum).

[0046] According to another aspect of the present invention, the present invention further provides a positioning system for advanced process SRAM soft failure, comprising:

[0047] A boundary condition determination module, which is used to determine the boundary conditions for chip failure;

[0048] The laser scanning test module is used to scan the pixels on the chip one by one using a laser under the conditions around the boundary conditions to stimulate the pass / fail state change of the chip, so that the failed position and the normal position have a contrast difference, and obtain a laser scanning image and a contrast image;

[0049] The hotspot positioning module is used to superimpose the laser scanning image and the contrast image to find the failure position on the laser scanning image, and then compare the laser scanning image with the corresponding layout layer to locate the hotspot on the layout layer according to the failure position.

[0050] As configured above, the present invention utilizes the characteristic that the Pass / Fail state of the chip's failure position is easily changed under near-boundary conditions. Laser scanning of the chip under near-boundary conditions is used to actively stimulate the change of the Pass / Fail state of the chip's failure position, so that the failure position and the normal position produce a contrast difference to find the failure position. Furthermore, the present invention is mainly implemented by the synchronous operation of a tester and a positioning machine (such as a light emission microscope). The function of the tester is to provide the chip with the power supply, signal and trigger signal required for operation and control the movement of the laser beam, and to feedback the Pass / Fail result to the positioning machine. The positioning machine uses laser to scan and image the chip, scans the chip point by point according to the trigger signal of the tester, provides excitation energy for the change of the Pass / Fail state of the chip, receives the Pass / Fail result provided by the tester, and calibrates the position affected by the laser scanning. In summary, the present invention can realize dynamic testing of the chip by combining the existing light emission microscope equipment with the tester, and actively stimulates the change of the chip state under the critical state between chip failure and normal state by combining the laser scanning function of the light emission microscope equipment, thereby locating the failure position, thereby improving the yield and reliability of advanced integrated circuit SRAM.

[0051] It should be noted that references in the specification to "one embodiment," "an embodiment," "a specific embodiment," "some embodiments," etc., merely indicate that the described embodiment may include a particular feature, structure, or characteristic. Furthermore, such phrases do not necessarily refer to the same embodiment. Furthermore, when a particular feature, structure, or characteristic is described in conjunction with an embodiment, it is within the knowledge of persons skilled in the relevant art to implement such feature, structure, or characteristic in conjunction with other embodiments, regardless of whether such feature, structure, or characteristic is explicitly described.

[0052] It should be noted that the various embodiments in this specification are described in a progressive manner, with each embodiment focusing on the differences from other embodiments. Reference can be made to the common and similar parts between the various embodiments. The systems disclosed in the embodiments are described briefly because they correspond to the methods disclosed in the embodiments. For relevant details, refer to the method description.

[0053] It should also be noted that although the present invention has been disclosed above with reference to preferred embodiments, the above embodiments are not intended to limit the present invention. For any person skilled in the art, without departing from the scope of the technical solution of the present invention, the technical content disclosed above can be used to make many possible changes and modifications to the technical solution of the present invention, or to modify it into an equivalent embodiment with equivalent changes. Therefore, any simple modification, equivalent change, and modification made to the above embodiments based on the technical essence of the present invention without departing from the content of the technical solution of the present invention still fall within the scope of protection of the technical solution of the present invention.

[0054] It should also be understood that, unless otherwise specified or indicated, the terms "first", "second", "third", etc. in the specification are only used to distinguish the various components, elements, steps, etc. in the specification, and are not used to indicate the logical relationship or sequential relationship between the various components, elements, steps, etc.

[0055] It should also be understood that the terms described herein are intended to describe particular embodiments only and are not intended to limit the scope of the invention. It should be noted that the singular forms "a" and "an" as used herein and in the appended claims include plural references unless the context clearly indicates otherwise. For example, a reference to "a step" or "a device" means a reference to one or more steps or devices, and may include secondary steps as well as secondary devices. All conjunctions used should be understood in their broadest sense. Also, the word "or" should be understood to have the definition of a logical "or" rather than a logical "exclusive or" unless the context clearly indicates otherwise. Furthermore, implementation of the methods and / or apparatus in embodiments of the present invention may include performing selected tasks manually, automatically, or in combination.

Claims

1. A method for locating soft failures of advanced process SRAM, characterized in that: include: Determine the boundary conditions for chip failure; Laser scanning test: Use laser to scan the pixels on the chip one by one under the conditions around the boundary conditions to stimulate the pass / fail state change of the chip, so that the failed position and the normal position have a contrast difference, and obtain a laser scanning image and a contrast image; The laser scanning image and the contrast image are superimposed to find the failure position on the laser scanning image, and then the laser scanning image is compared with the corresponding layout layer to locate the hot spot on the layout layer according to the failure position.

2. The method for locating soft failures of advanced process SRAM according to claim 1, wherein: The boundary conditions include voltage boundary conditions and frequency boundary conditions.

3. The method for locating soft failures of advanced process SRAM according to claim 1, wherein: Perform multiple laser scanning tests to obtain multiple contrast images, and superimpose the multiple contrast images to determine the failure position.

4. The method for locating soft failures of advanced process SRAM according to claim 1, wherein: The laser scanning test is performed using a testing machine and a positioning machine.

5. The method for locating soft failures of advanced process SRAM according to claim 4, wherein: The laser scanning test method includes: when the laser scanning test starts, the test machine sends a trigger signal to the positioning machine to enable the laser beam of the positioning machine to start scanning the pixel points, and the test machine periodically sends a trigger signal to the positioning machine to scan the pixel points one by one.

6. The method for locating soft failures of advanced process SRAM according to claim 5, wherein: The laser scanning test method includes: when the laser scanning test starts, the test machine starts to apply a predefined test vector sequence to the chip, and after each pixel point test is completed, a Pass / Fail result is obtained, and the test machine feeds back the Pass / Fail result to the positioning machine.

7. The method for locating soft failures of advanced process SRAM according to claim 6, wherein: After receiving the Pass / Fail result, the positioning machine generates the contrast image.

8. The method for locating soft failures of advanced process SRAM according to claim 1, wherein: The boundary conditions for the chip failure are determined by Shmoo analysis.

9. The method for locating soft failures of advanced process SRAM according to claim 1, wherein: Samples are prepared according to the positions of the hot spots, and physical properties of the samples are analyzed.

10. A positioning system for advanced process SRAM soft failure, characterized in that: include: A boundary condition determination module, which is used to determine the boundary conditions for chip failure; a laser scanning test module, configured to use a laser to scan pixel points on the chip one by one under conditions around the boundary conditions, so as to stimulate a change in the pass / fail state of the chip, thereby generating a contrast difference between the failed position and the normal position, and obtaining a laser scanning image and a contrast image; A hotspot positioning module is used to superimpose the laser scanning image and the contrast image to find the failure position on the laser scanning image, and then compare the laser scanning image with the corresponding layout layer to locate the hotspot on the layout layer according to the failure position.

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