IO core grain NoC network node high-speed interface circuit based on RISC-V

Abstract

The invention provides an IO core grain NoC network node high-speed interface circuit based on RISC-V. The IO core grain NoC network node high-speed interface circuit comprises PCIe, RapidIO, a DDR and a configuration management unit. The configuration management unit comprises an RISC-V instruction core, a CROSSBAR bus, a configuration unit and an AXI 1to6 conversion bridge; the configuration unit comprises an AXI one-to-six conversion bridge and a plurality of configuration bridges; and an AXI interface output by the CRO SSBAR bus is subjected to one-to-six processing. Through the innovative design that the configuration bridge unit is additionally arranged between the RISC-V core and the interface IP, efficient initialization configuration of IO equipment is achieved.

Description

Technical Field

[0001] The present invention belongs to the field of core technology, and in particular relates to a RISC-V-based IO core NoC network node high-speed interface circuit. Background Art

[0002] Under nanotechnology, chip design faces severe challenges such as rising manufacturing costs and declining yields. Chiplet technology has emerged as a key solution to these challenges. By stacking modular, miniaturized chiplets from different processes to form a chip, high performance can be achieved at a low cost. Chiplets can be categorized into various types based on their function, including compute, storage, control, and I / O.

[0003] When IO chips use the NoC network architecture, high-speed interface IPs such as PCIe, RapidIO, and DDR are initialized slowly through the NoC network routing method. In addition, the CPU will occupy routing node resources during the configuration process, affecting the overall system performance. Summary of the Invention

[0004] The present invention aims to solve the problems raised in the background technology and proposes a RISC-V-based IO chip NoC network node high-speed interface circuit.

[0005] The present application provides a RISC-V-based IO core NoC network node high-speed interface circuit, which includes PCIe, RapidIO, DDR, and a configuration management unit. The configuration management unit uses a RISC-V instruction core as a processor, is connected to the configuration channel of each IP on the chip through an AXI bus, and writes targeted driver software to implement the initialization configuration management function of each IP on the chip.

[0006] The configuration management unit includes RISC-V instruction core, CROSSBAR bus, configuration unit, and AXI 1to6 conversion bridge;

[0007] The RISC-V instruction core is the core operation control unit;

[0008] The CROSSBAR bus is the channel for data exchange between the configuration unit and other configuration units in the system;

[0009] The AXI 1to6 conversion bridge is the hub for data flow within the configuration unit;

[0010] The configuration unit includes an AXI 1-to-6 conversion bridge and multiple configuration bridges; the AXI interface output by the CROSSBAR bus performs 1-to-6 processing.

[0011] Furthermore, the configuration bridge includes a PCIe configuration bridge, a RapidIO configuration bridge, and a DDR configuration bridge;

[0012] The configuration bridge converts the configuration signals initiated by the RISC-V core through different protocols and transmits the configuration signals to different components of the NoD; the configuration bridge is used for the configuration of PCIe, Rapid IO and DDR; PCIe uses AXI and AHB; Rapid IO uses AXI and APB; DDR uses AHB and APB bus bridges.

[0013] Furthermore, the configuration bridge operates in two clock domains. The configuration unit clock of the RISC-V interface operates in the low clock domain, and each IP configuration interface operates in its own clock domain. Two asynchronous FIFO structures are used to complete the bridging of the two clock domains.

[0014] Furthermore, the RISC-V instruction core includes receiving data from the configuration unit through the CROSSBAR, and the data includes parameters required for instruction execution and configuration information to be processed;

[0015] On the other hand, the instruction execution results, control signals and other data generated by the RISC-V instruction core after executing operations and control logic are transmitted to the outside through CROSSBAR for feedback to other configuration interfaces in the configuration unit.

[0016] Furthermore, the RISC-V instruction core is bidirectionally connected to the CROSSBAR bus; the CROSSBAR bus is used to receive system global configuration parameters; and send control instructions to external modules.

[0017] Furthermore, the AXI 1to6 conversion bridge is used to receive data and instructions from the RISC-V instruction core. The data and instructions include various configuration commands and parameters for the PCIe configuration bridge, RapidIO configuration bridge, and DDR configuration bridge.

[0018] After receiving the data and instructions, the AXI 1to6 conversion bridge converts and adapts the single input AXI data according to the AXI bus protocol specification, and distributes it to the PCIe configuration bridge, RapidIO configuration bridge, and DDR configuration bridge.

[0019] Further, the PCIe configuration bridge is connected with the AXI 1to6 conversion bridge through the AXI-BUS, receives configuration instructions and parameters from the conversion bridge, performs configuration operation on PCIe related registers according to the AXI interface protocol standard, including setting the working mode of the PCIe device and allocating address space; meanwhile, the PCIe configuration bridge collects state information and data reading results of the PCIe device and returns them to the AXI 1to6 conversion bridge through the AXI-BUS; in addition, the PCIe configuration bridge is also connected with the external AHB-BUS and can perform data interaction with the physical layer of the PCIe IP through the AHB-BUS.

[0020] The RapidIO configuration bridge is used for communication with the AXI 1to6 conversion bridge through the AXI-BUS, receives configuration data and instructions sent by the conversion bridge, and performs configuration on the RapidIO IP registers according to the AXI interface protocol standard. The running state and configuration execution feedback of the RapidIO device are obtained through the RapidIO configuration bridge. The RapidIO configuration bridge is connected with the APB-BUS and interacts with the corresponding bus module outside, receives control signals of the physical layer of the RapidIO from the APB-BUS to assist configuration.

[0021] The DDR configuration bridge interacts with the AXI 1to6 conversion bridge through the AHB-BUS, receives DDR memory configuration instructions and parameters from the conversion bridge. The DDR configuration bridge is connected with the APB-BUS and interacts with the physical layer APB bus module of the DDR, receives read and write enable signals and state query instructions transmitted by the APB bus.

[0022] Further, the configuration process is as follows:

[0023] When the RISC-V instruction core detects the chip reset signal, it first detects the hardware preparation state of the Nandflash, PCIe and DDR.

[0024] When the preparation of a certain IP is completed and the initialization can be performed, the RISC-V instruction core performs initialization work of the corresponding IP. If the initialization of the corresponding IP is successful, the bit representing the state of the corresponding IP in the init_status array is changed from 1 representing no initialization to 0 representing successful initialization.

[0025] When all the IPs have been accessed for one round, the RISC-V instruction core checks the preparation state of the IP which has not been initialized successfully again. If the preparation state is OK, the initialization work of the corresponding IP is performed, and the init_status array is updated according to the initialization result.

[0026] Compared with the traditional method of mounting a CPU in a NoC network node and then initializing the configuration and detecting the high-speed interface IP registration with the help of an address routing table, the method of building a configuration bridge between the CPU and the high-speed interface IP proposed in the present invention can not only significantly reduce the number of NoC network nodes used and reduce system complexity, but also greatly reduce the delay in transmitting configuration data to the high-speed interface, greatly improve configuration efficiency, effectively reduce configuration and detection time, and provide a better choice for IO chip high-speed interface IP configuration under the NoC network architecture.

[0027] In order to more clearly illustrate the functional characteristics and structural parameters of the present invention, further description is given below with reference to the accompanying drawings and specific embodiments. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] Figure 1 This is a configuration unit architecture diagram provided in an embodiment of the present application;

[0029] Figure 2 This is a PCIe configuration unit architecture diagram provided in an embodiment of the present application;

[0030] Figure 3 This is a Rapid IO IP configuration diagram provided in an embodiment of the present application;

[0031] Figure 4 This is a diagram of the DDR IP configuration structure provided in an embodiment of the present application;

[0032] Figure 5 This is a structural diagram of a configuration unit provided in an embodiment of the present application;

[0033] Figure 6 This is a workflow diagram provided by an embodiment of the present application;

[0034] Figure 7 It is a configuration diagram of routing nodes;

[0035] Figure 8 This is a structural diagram of the configuration bridge method provided in an embodiment of the present application. DETAILED DESCRIPTION

[0036] The technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, rather than all the embodiments; based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of the present invention.

[0037] In I / O chiplets, high-speed interface IPs such as PCIe, RapidIO, and DDR require initial configuration of I / O devices during the initial startup of a NoC network system. However, I / O chiplets in NoC networks lack a master CPU to perform initialization and configuration of each peripheral high-speed I / O device. Therefore, a powerful configuration management unit is urgently needed to efficiently and accurately complete the initialization of high-speed interface IPs.

[0038] The present invention aims to achieve efficient initialization configuration of IO devices through the innovative design of adding a configuration bridge unit between the RISC-V core and the interface IP, breaking the bottleneck of existing technologies and improving the performance and stability of the entire system.

[0039] The interface circuitry comprises interconnect networks, IPs such as PCIe, RapidIO, and DDR, and a configuration management unit. The configuration management unit utilizes an advanced RISC-V instruction core as its processor, connecting to the configuration channels of each on-chip IP via an AXI bus. Targeted driver software is also written to implement initial configuration management for each on-chip IP. The configuration management unit comprises the RISC-V instruction core, the CROSS BAR bus, and the configuration unit.

[0040] The configuration unit includes an AXI 1-to-6 conversion bridge, a PCIe configuration bridge, a RapidIO configuration bridge, and a DDR configuration bridge. The three high-speed interfaces, PCIe, RapidIO, and DDR, each have independent controllers and physical layers and require separate configuration. Therefore, the AXI interface output by the CROSSBAR bus is divided into 1 and 6 to fully meet diverse configuration requirements.

[0041] The configuration management unit consists of the RISC-V instruction core, ITCM, DTCM, ICB bus, UART, and configuration bridge circuit; the NoC network consists of routers, resource network interfaces, channels, routing algorithms, and flow control mechanisms. IP cores such as PCIe, Rapid IO, DDR, and NF are mounted in the resource network interface.

[0042] Data Interaction with the RISC-V Instruction Core: The RISC-V instruction core, as the core arithmetic control unit, plays a crucial role. It receives data from the configuration unit via the CROSSBAR. This data includes key information such as the parameters required for instruction execution and configuration information awaiting processing. Furthermore, the RISC-V instruction core, after executing operations and controlling logic, generates instruction execution results, control signals, and other data. This data is then transmitted externally via the CROSSBAR for feedback to other configuration interfaces within the configuration unit, enabling efficient data exchange and coordinated system control.

[0043] CROSSBAR bus: The CROSSBAR bus is a key channel for data exchange between the configuration unit and other configuration units in the system. The RISC-V instruction core is bidirectionally connected to the CROSSBAR bus, enabling smooth data transmission and reception between the instruction core and the outside world. This bus receives global system configuration parameters to provide an accurate basis for subsequent configuration operations; it also sends control commands to external modules to precisely regulate the system's operating status and ensure stable operation of the entire system.

[0044] The AXI 1-to-6 bridge serves as the core hub for data flow within the configuration unit. The AXI 1-to-6 bridge receives data and instructions from the RISC-V instruction core, including various configuration commands and parameters for the PCIe configuration bridge, RapidIO configuration bridge, and DDR configuration bridge. Upon receiving the data and instructions, the AXI 1-to-6 bridge accurately converts and adapts the single input AXI data according to the AXI bus protocol specification, and efficiently distributes it to the PCIe configuration bridge, RapidIO configuration bridge, and DDR configuration bridge.

[0045] For example, when the RISC-V instruction core needs to configure the parameters of the PCIe configuration bridge, it will send data containing detailed configuration parameters and operation instructions to the AXI 1to6 conversion bridge. After a series of precise processing, the conversion bridge will accurately pass the data to the PCIe configuration bridge via AXI-BUS (AXI-BUS connected to the PCIe configuration bridge in the figure). Conversely, if the PCIe configuration bridge, RapidIO configuration bridge, and DDR configuration bridge generate feedback data, such as configuration status and data reading results, they will also be passed to the AXI 1to6 conversion bridge first. The conversion bridge will then organize and summarize this feedback data according to the protocol and return it to the RISC-V instruction core, allowing the instruction core to know the configuration execution status in real time, obtain relevant data results, and then make timely adjustments and optimizations to the system configuration.

[0046] The AXI 1-to-6 conversion bridge is a general design and will not be described in detail here.

[0047] The functions of the three configuration bridges are described in detail below.

[0048] PCIe Configuration Bridge

[0049] The PCIe configuration bridge is connected to the AXI 1to6 conversion bridge via AXI-BUS, receives configuration instructions and parameters from the conversion bridge, and performs configuration operations on PCIe-related registers in accordance with the AXI interface protocol standard, including setting the operating mode of the PCIe device and allocating address space. At the same time, the PCIe configuration bridge collects PCIe device status information (such as link status, device operating status, etc.) and data reading results, and transmits them back to the AXI 1to6 conversion bridge via AXI-BUS. In addition, the PCIe configuration bridge is also connected to the external AHB-BUS, and can exchange data with the physical layer of the PCIe IP via AHB-BUS.

[0050] The PCle IP system structure is as follows Figure 2 As shown below, combined with the above Figure 2 Provide a detailed description of the entire subsystem: The PCleIP system includes a clock reset unit, PCle CTRL, MISCE, PHY CREG, AHB MATRIX, and PHY;

[0051] The clock reset unit is used to generate clock and reset signals; its inputs include the clock required by the PCIe controller configuration port AXI_BUS, the PHY output pc1k, the auxiliary clock signal used by PCIe in low-power mode, and the system reset signal. The clock reset unit outputs and inputs include the various reset signals required by the PCIe controller configuration port AXI_BUS, the PHY reset signal, and the reset signal used by the controller. It is the clock and reset management module for the entire subsystem.

[0052] PCle CTRL is the core module that completes protocol conversion and requires register configuration through AXI_BUS;

[0053] MISCE stores the sideband signals of the PCIe controller. Since the signals need to be synchronized with the core clock of the controller, MISCE also includes an asynchronous bridge for clock synchronization between the configuration clock and the core clock.

[0054] PHY CREG is a module that stores PHY sideband signals. It is used to control and store PHY control and status signals and requires register configuration via AHB_BUS.

[0055] AHB MATRIX is a router that is used to complete the address decoding between the AHB bus MISCE and PHY CREG:

[0056] PHY is a high-speed SerDes used to generate differential pairs for data exchange. PCIe IP devices and external PCle exchange data through PHY.

[0057] Rapid IO Configuration Bridge

[0058] The RapidIO configuration bridge communicates with the AXI 1-to-6 conversion bridge via AXI-BUS, receiving configuration data and instructions from the conversion bridge and configuring the RapidIO IP registers according to the AXI interface protocol standard. The RapidIO configuration bridge obtains data such as the operating status of RapidIO devices (such as link bandwidth usage and node connection status) and configuration execution feedback (whether the configuration was successful). The RapidIO configuration bridge connects to the APB-BUS to interact with the corresponding external bus module and receives control signals from the APB-BUS to assist in configuration of the RapidIO physical layer.

[0059] Rapid IO IP system structure is as follows Figure 3 As shown below. Figure 3 , provides a detailed description of the entire configuration system: Rapid IO IP includes Rapid IO CTRL, MISCE, PHY CREG, APB MATRIX, and PHY;

[0060] Rapid IO CTRL is the core module that completes Rapid IO protocol conversion and configures registers through AXI_BUS;

[0061] The MISCE stores the Rapid IO controller's sideband signals. Since the signals in the MISCE need to be synchronized with the controller's core clock, the MISCE includes an asynchronous bridge for clock synchronization between the configuration clock and the core clock.

[0062] PHY CREG is a module that stores PHY sideband signals. It can control and store PHY control and status signals and needs to be configured through APB_BUS registers.

[0063] APB MATRIX is a router that completes the address decoding between MISCE and PHY CREG on the APB bus:

[0064] PHY is a high-speed SerDes used to generate differential pairs for data exchange. Rapid IO IP and external RapidIO devices exchange data through PHY.

[0065] DDR Configuration Bridge

[0066] The DDR configuration bridge interacts with the AXI 1to6 conversion bridge through AHB-BUS, and receives DDR memory configuration instructions and parameters (such as memory address allocation, read and write timing settings, etc.) from the conversion bridge; the DDR configuration bridge connects to APB-BUS, interacts with the DDR physical layer APB bus module, and receives read and write enable signals and status query instructions from the APB bus.

[0067] DDR is a double-bit-rate synchronous dynamic random access memory (SDRAM). Its data transfer rate is twice the system clock, outperforming traditional SDRAM. The DDR IP has two configuration channels, using the AHB and APB interfaces to access registers on the DDR IP controller and PHY, respectively.

[0068] The Slave Interface CTRL is the controller port of the DDR IP. It is mainly used to access the controller's internal registers to configure the controller's status and bit width, set the loading mode, and timing parameters for SDRAM initialization.

[0069] The PHY side is the PHY port of the DDR IP, which is mainly used to access the PHY port of the DDR. DDR training is located in the PHY. DDR training configures the port channel and the necessary process of corresponding physical layer control. Completing the training can ensure that the channel can transmit data correctly.

[0070] In summary, through clear bus connections and protocol adaptation, the various parts within the configuration unit realize the control of various configuration bridges through RIS CV instructions, and the data interaction between the configuration bridge and external buses and devices, ensuring the orderly implementation of system configuration functions and data flow.

[0071] The configuration bridge converts the configuration signals initiated by the RISC-V core through different protocols and transmits the configuration signals to different components of the NoD. The configuration bridge is used for the configuration of PCIe, Rapid IO, and DDR. PCIe uses AXI and AHB; Rapid IO uses AXI and APB; DDR uses AHB and APB bus bridges.

[0072] as follows Figure 5 As shown ( Figure 5 for Figure 1 The master device port of the configuration bridge is connected to the RISC-V core through the AXI bus interface to implement the configuration function.

[0073] According to the design requirements analysis, the configuration bridge works in two clock domains. The configuration unit clock of the RISC-V interface works in the low clock domain, and each IP configuration interface works in its own clock domain. In order to synchronize these two different clock domains, two asynchronous FIFO structures are used to complete the bridging of the two clock domains, namely Figure 5 The asynchronous bridge implementation unit.

[0074] After the bridge is configured as a device and is hung to the CROSSBAR bus, the configuration of each IP is completed in software by means of operating a register, and the work flow of the configuration software is as shown in the figure. Figure 6 The system first reads the state register of each IP in the NoC chip, confirms whether the reset is successful, completes the initialization configuration of RapidIO, DDR and PCIe according to the complexity of the configuration driver, pulls up the configuration completion flag signal lamp after the corresponding configuration is completed, or prints out the unfinished configuration information through UART.

[0075] The configuration bridge method provided by the application can realize the initialization configuration of high-speed interface IPs PCIe, RapidIO and DDR under the condition that the NoC network node is not mounted with a CPU, reduces the number of NoC network nodes and the routing time of configuration information in the network, and is suitable for the node register configuration of all NoC networks.

[0076] The way of configuring high-speed nodes by the routing node mode is as shown in the figure. Figure 7

[0077] The way of configuring high-speed nodes by the configuration bridge mode is as shown in the figure. Figure 8

[0078] As can be seen from the comparison, the configuration bridge method provided by the application can complete the initialization configuration of high-speed interfaces even if the NoC network node is not mounted with a CPU node.

[0079] The PCIe, RapidIO and DDR configuration method of high-speed interface IPs of the NoC network node based on RISC-V provided by the application has wide applicability, and is suitable for not only specific NoC network nodes but also the initialization configuration of all NoC network nodes.Compared with the traditional network routing mode configuration method, the application can significantly reduce the routing delay of configuration information while reducing the number of NoC network nodes, and greatly improves the system configuration efficiency.

[0080] Although the embodiments of the application have been shown and described, it can be understood by those skilled in the art that various changes, modifications, replacements and variations can be made to the embodiments without departing from the principles and spirits of the application, and the scope of the application is defined by the appended claims and their equivalents.​

Claims

1. A RISC-V based IO chip NoC network node high-speed interface circuit, characterized in that: It includes PCIe, RapidIO, DDR, and a configuration management unit. The configuration management unit uses a RISC-V instruction core as a processor, connects to the configuration channels of each IP on the chip through the AXI bus, and writes targeted driver software to implement the initialization configuration management function of each IP on the chip. The configuration management unit includes RISC-V instruction core, CROSSBAR bus, configuration unit, and AXI 1to6 conversion bridge; The RISC-V instruction core is the core operation control unit; The CROSSBAR bus is the channel for data exchange between the configuration unit and other configuration units in the system; The AXI 1to6 conversion bridge is the hub for data flow within the configuration unit; The configuration unit includes an AXI 1-to-6 conversion bridge and multiple configuration bridges; the AXI interface output by the CROSSBAR bus performs 1-to-6 processing.

2. The interface circuit according to claim 1, wherein: Configuration bridges include PCIe configuration bridge, RapidIO configuration bridge, and DDR configuration bridge; The configuration bridge converts the configuration signals initiated by the RISC-V core through different protocols and transmits the configuration signals to different components of the NoD; the configuration bridge is used for the configuration of PCIe, Rapid IO and DDR; PCIe uses AXI and AHB; Rapid IO uses AXI and APB; DDR uses AHB and APB bus bridges.

3. The interface circuit according to claim 1, wherein: The configuration bridge operates in two clock domains. The configuration unit clock of the RISC-V interface operates in the low clock domain, and each IP configuration interface operates in its own clock domain. Two asynchronous FIFO structures are used to complete the bridging of the two clock domains.

4. The interface circuit according to claim 1, wherein: The RISC-V instruction core receives data from the configuration unit through the CROSSBAR. The data includes parameters required for instruction execution and configuration information that needs to be processed. On the other hand, the instruction execution results, control signals and other data generated by the RISC-V instruction core after executing operations and control logic are transmitted to the outside through CROSSBAR for feedback to other configuration interfaces in the configuration unit.

5. The interface circuit according to claim 1, wherein: The RISC-V instruction core is bidirectionally connected to the CROSSBAR bus; the CROSSBAR bus is used to receive system global configuration parameters and send control instructions to external modules.

6. The interface circuit according to claim 1, wherein: The AXI 1-to-6 conversion bridge receives data and instructions from the RISC-V instruction core. The data and instructions include various configuration commands and parameters for the PCIe configuration bridge, RapidIO configuration bridge, and DDR configuration bridge. After receiving the data and instructions, the AXI 1to6 conversion bridge converts and adapts the single input AXI data according to the AXI bus protocol specification, and distributes it to the PCIe configuration bridge, RapidIO configuration bridge, and DDR configuration bridge.

7. The interface circuit according to claim 2, characterized in that: The PCIe configuration bridge connects to the AXI 1to6 conversion bridge via AXI-BUS, receives configuration instructions and parameters from the conversion bridge, and performs configuration operations on PCIe-related registers according to the AXI interface protocol standard, including setting the operating mode of the PCIe device and allocating address space. At the same time, the PCIe configuration bridge collects PCIe device status information and data reading results, and transmits them back to the AXI 1to6 conversion bridge via AXI-BUS. In addition, the PCIe configuration bridge is also connected to the external AHB-BUS, and can exchange data with the physical layer of PCIeIP via AHB-BUS; The RapidIO configuration bridge communicates with the AXI 1-to-6 conversion bridge via AXI-BUS, receives configuration data and instructions from the conversion bridge, and configures the RapidIO IP registers according to the AXI interface protocol standard. The RapidIO configuration bridge obtains the operating status of RapidIO devices and configuration execution feedback. The RapidIO configuration bridge connects to the APB-BUS to interact with the corresponding external bus module, receiving control signals from the APB-BUS to assist in configuration of the RapidIO physical layer. The DDR configuration bridge interacts with the AXI 1to6 conversion bridge through AHB-BUS, receiving DDR memory configuration instructions and parameters from the conversion bridge; the DDR configuration bridge connects to APB-BUS, interacts with the DDR physical layer APB bus module, and receives read and write enable signals and status query instructions from the APB bus.

8. The interface circuit according to claim 1, wherein: The configuration process is as follows: When the RISC-V instruction core detects the chip reset signal, it first checks the hardware readiness status of Nandflash, PCIe, and DDR; When an IP is ready and can be initialized, the RISC-V instruction core initializes the corresponding IP. If the initialization of the corresponding IP is successful, the digit in the init_status array representing the status of the corresponding IP is updated from 1, which indicates that the IP has not been initialized, to 0, which indicates that the initialization is successful. After all IPs have been visited once, the RISC-V instruction core checks the readiness status of the IPs that have not been initialized successfully again. If the readiness status is OK, the corresponding IP will be initialized and the init_status array will be updated according to the initialization result.

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