Multi-interface heat flow integrating instrument

Through the multi-standard input interface unit, heterogeneous switch matrix, optical-magnetic dual-coupling drive module and dynamic follow-up shielding system, the multi-standard input and anti-interference problems of traditional heat flow integrators are solved, automatic recognition and stable measurement of sensor signals are achieved, and the system's adaptability and anti-interference capabilities are improved.

CN120778253AInactive Publication Date: 2025-10-14DONGYING HUAWEI SOFTWARE TECH DEV CO LTD
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Patent Information

Application Number
CN202511029159.0
Authority / Receiving Office
CN · China
Patent Type
Applications(China)
Current Assignee / Owner
Filing Date
2025-07-25
Publication Date
2025-10-14
Estimated Expiration
Not applicable · inactive patent

AI Technical Summary

Technical Problem

Traditional heat flow integrators lack multi-standard input and automatic recognition capabilities, have poor interface compatibility, and have a single anti-interference method, making them difficult to adapt to the requirements of multi-source signal access and stable measurement in complex electromagnetic environments.

Method used

It adopts multi-standard input interface unit, heterogeneous switch matrix, optical-magnetic dual-coupling drive module and dynamic follow-up shielding system to realize automatic recognition and adaptive processing of various signal types, combines FPGA+MCU architecture for adaptive processing, and dynamically adjusts interference shielding performance.

Benefits of technology

It realizes automatic recognition and adaptation of multiple sensor signals, improves the system's adaptability and anti-interference ability, ensures measurement accuracy and stability, and reduces sampling errors, especially in high-frequency and high-power environments.

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Abstract

The invention relates to the technical field of integrating instruments, in particular to a multi-interface heat flow integrating instrument, which comprises a multi-system input interface unit, and is characterized in that pulse signals, 4-20mA current signals and differential voltage signals are accessed through a phoenix terminal array; the input end of the heterogeneous switch matrix is electrically connected with the output end of the multi-system input interface unit, and the heterogeneous switch matrix is used for matching signal types and frequency bands of output signals of different types of sensors; and the input end of the optomagnetic double-coupling driving module is connected with the control port of the heterogeneous switch matrix, so that the signal integrity and the system safety are improved. Compared with the prior art, by arranging the multi-system input interface unit, the standby power consumption is greatly reduced, the system response speed is improved, the structure has the characteristics of high adaptability, high compatibility and low power consumption, and a high-reliability and intelligent access platform is provided for parallel deployment of various heat flow sensors.
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Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of totalizing instruments, and in particular to a multi-interface heat flow totalizer. BACKGROUND

[0002] A heat flow totalizer is a key instrument for measuring and calculating the energy transmission of a medium during a heat exchange process, and is widely used in the fields of heating, ventilation, air conditioning (HVAC), industrial steam pipe networks, hot water circulation systems and energy metering. The basic principle is to obtain the volume or mass flow of the medium through a flow sensor, measure the temperature difference between the inlet and outlet of the medium through a temperature sensor, and combine thermodynamic parameters (such as specific heat capacity and density) to perform integral calculation, thereby accurately estimating the heat transmission per unit time.

[0003] With the diversification of application scenarios, heat flow totalizing systems face the demand for input of various interface signals from different types of sensors, such as high-frequency pulse output turbine flow meters, analog current type electromagnetic flow meters, voltage type thermocouple temperature sensors, and intelligent composite probes based on industrial field buses (such as RS485 / Modbus RTU). However, traditional heat flow totalizers generally only support fixed types of input signals (such as 4-20mA or pulse signals) and lack multi-standard input capability, requiring manual setting or replacement of input modules, do not support automatic identification of sensor interface types, have limited interface usage, poor flexibility, are not conducive to the integration of multiple source signals on site, and generally use fixed metal shells for shielding, grounding layers or single filters to handle interference, which cannot dynamically track noise changes and cannot provide targeted compensation electric fields. In particular, in high-frequency and high-power environments, common-mode interference superposition is prone to occur, leading to sampling errors or misjudgments. Therefore, the present application discloses a multi-interface heat flow totalizer. SUMMARY

[0004] Therefore, the present application aims to provide a multi-interface heat flow totalizer to solve the problems of traditional heat flow totalizers lacking multi-standard input and automatic identification capabilities, poor interface compatibility, and single anti-interference means, which makes it difficult to adapt to stable measurement requirements in multi-source signal access and complex electromagnetic environments.

[0005] To achieve the above purpose, the present application provides a multi-interface heat flow totalizer, which comprises: a multi-standard input interface unit for accessing pulse signals, 4-20mA current signals and differential voltage signals through a phoenix terminal array; a heterogeneous switch matrix, the input end of which is electrically connected to the output end of the multi-standard input interface unit, the heterogeneous switch matrix being composed of a three-level grouping switch array of a GaN pulse switch group, a SiC analog switch group and an IGBT power switch group, for matching the signal types and frequency bands of output signals of different types of sensors; Optical-magnetic dual coupling driving module, the input end is connected with the control port of the heterogeneous switch matrix, and an isolation driving mechanism composed of optical fiber signal transmission and magnetic resonance energy transmission is adopted to improve signal integrity and system safety. The main control processing unit receives output data of the heterogeneous switch matrix through an SPI bus, and realizes multi-channel parallel heat calculation and interface recognition adaptive processing based on an FPGA+MCU architecture. The dynamic following shielding system comprises a coaxial ring shielding ring array integrated in an inner layer of the PCB and a programmable voltage compensation electrode, and is used for dynamically adjusting interference shielding performance.

[0006] Preferably, the multi-standard input interface unit comprises a hardware feature extraction circuit, the hardware feature extraction circuit comprises an impedance spectrum scanning unit, a leakage current detection bridge, a time domain slope comparator and a feature matching state machine, the feature matching state machine is realized by FPGA hard logic, is used for receiving a digital coded signal output by the hardware feature extraction circuit, and outputs an interface type judgment result to a control port of the heterogeneous switch matrix through a pre-stored feature mapping table.

[0007] Preferably, the interface unit comprises a micro-power consumption maintaining circuit, in a non-working state, the interface is kept in a wake-up listening mode through a sub-threshold power supply; when the interface accesses an external signal or detects a weakly coupled disturbance signal, the main control can be woken up within 5 ms to enter a rapid identification process.

[0008] Preferably, the switching frequency of the GaN pulse switch group is greater than 1 MHz, and the conduction delay is less than 2 ns, which is used for processing high-frequency pulse signals output by a turbine flowmeter.

[0009] Preferably, the GaN switch group is configured with a resonant driving circuit, and the resonant driving circuit comprises an LC oscillator, the inductance of the LC oscillator is set to 0.22 mu H, and the capacitance is set to 2.2 nF, and the LC oscillator is pre-charged to 98%-99.5% of a target voltage before switching, so as to reduce conduction impact.

[0010] Preferably, the main control processing unit is configured with a reconfigurable channel mapping mechanism, and FPGA on-chip logic is used to realize logical path rebinding between any interface module and any heat flow calculation core, and to support dynamically constructing a neural style channel network according to task priority, signal quality and channel health degree.

[0011] Preferably, the main control processing unit is integrated with a delay compensation unit, and the delay compensation unit is used for correcting path propagation delay differences caused by different isolation modes and signal types.

[0012] Preferably, the voltage of the compensation electrode of the dynamic following shielding system satisfies Wherein k∈[0.92,0.99] is a real-time compensation coefficient, and the compensation response time is ≤100μs, is the real-time voltage of the compensation electrode, is the voltage of the signal line corresponding to the interference source.

[0013] Preferably, the compensation electrode adopts an interdigital electrode topology, the electrode width to pitch ratio is 1:1.2, and the electrode length matches the signal wavelength λ / 20.

[0014] Preferably, the multi-format input interface unit is built-in with an excitation element, which can test itself and its connected circuit through a heating resistor, an electromagnetic excitation coil or a piezoelectric vibrator, and the excitation response curve can be used to identify problems such as contact resistance degradation, joint virtual welding, sensor deposition and fouling, etc., and the test frequency is once a day or at a user-specified time period.

[0015] The beneficial effects of the present application are: 1. The multi-interface thermal flow integrator, by setting a multi-format input interface unit, supports pulse, 4-20mA current, differential voltage and other industrial standard signals through the phoenix terminal array, has wide compatibility and access ability, at the same time, the internal integrated hardware feature extraction circuit can identify the impedance spectrum, leakage current characteristics, signal slope and other electrical fingerprint characteristics of the sensor port, combined with the FPGA hard state machine logic, realizes the signal type discrimination and channel matching without manual intervention, effectively improves the intelligent level, in addition, the interface unit is configured with a micro-power maintenance circuit, which can realize ultra-low power consumption monitoring in the non-working state, and complete the rapid awakening within 5ms after detecting the weak coupling signal, greatly reducing the standby power consumption and improving the system response speed, the structure has high adaptability, strong compatibility and low power consumption characteristics, providing a high-reliability, intelligent access platform for parallel deployment of various thermal flow sensors.

[0016] 2. The multi-interface thermal flow integrator, by setting a heterogeneous switch matrix cooperating with an optical and magnetic double-coupling driving module, by introducing a heterogeneous switch matrix composed of GaN, SiC and IGBT three types of power / signal switches, and working with the optical and magnetic double-coupling driving module, the precise adaptation and channel isolation of multi-source heterogeneous signals (such as high-frequency pulse, analog current, high-power control signal) are realized, the switch matrix automatically matches the optimal transmission path according to the signal type, not only improves the processing speed, but also effectively avoids the crosstalk problem between different signal paths; and the optical and magnetic coupling driving module adopts optical fiber data channel and magnetic resonance energy transmission technology, realizes the double isolation of data and power, greatly improves the electrical safety and anti-interference ability of the system, and the combination of the two builds a highly modular, low-delay, high-isolation signal processing channel, effectively solves the problems of signal coupling, channel interference and power disturbance caused by the coexistence of multiple sensors in industrial scenes, and guarantees the data transmission integrity and operation accuracy.

[0017] 3. The multi-interface thermal flow totalizer, by setting a dynamic following shielding system, by integrating a coaxial ring-shaped shielding ring and a programmable compensation electrode in the PCB, combining the real-time sampled noise voltage, dynamically generating a compensation voltage similar to its amplitude, forming a reverse electric field in space through the interdigital electrode structure, achieving potential balance and common-mode interference suppression in the signal channel area, compared with the traditional static shielding structure, this scheme has the advantages of fast response speed and strong frequency following ability, especially suitable for high-frequency, high-speed pulse signal environment, its compensation coefficient k can be dynamically adjusted to improve the adaptability of the shielding system under different working conditions; The matching of the interdigital structure and the signal wavelength λ / 20 also enhances the electromagnetic resonance coupling efficiency, the overall scheme can significantly improve the signal integrity and stability of the thermal flow acquisition system in a strong interference environment, ensuring measurement accuracy and system anti-interference ability. BRIEF DESCRIPTION OF DRAWINGS

[0018] In order to more clearly illustrate the technical solutions of the present application or the prior art, the following will briefly introduce the drawings needed to be used in the embodiments or prior art description. Obviously, the drawings in the following description are only a part of the present application, and other drawings can also be obtained by those skilled in the art without creative labor.

[0019] Fig. 1 The working flowchart of the present application is shown in the figure; Fig. 2 The multi-standard input interface unit of the present application is shown in the figure; Fig. 3 The main control processing unit of the present application is shown in the figure. DETAILED DESCRIPTION

[0020] In order to make the purpose, technical scheme and advantages of the present application more clear, the present application will be further described in detail below in combination with specific embodiments.

[0021] It should be noted that, unless otherwise defined, technical terms or scientific terms used in the present application shall be understood as their common meanings to those who have ordinary skills in the art to which the present application pertains. The terms "first", "second" and similar terms used in the present application do not indicate any order, number or importance, but are only used to distinguish different components. The terms "include" or "contain" and similar terms mean that the elements or objects before the terms encompass the elements or objects listed after the terms and their equivalents, and do not exclude other elements or objects. The terms "connect" or "connected" and similar terms are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. The terms "upper", "lower", "left", "right" and the like are only used to indicate relative positional relationships, and when the absolute positions of the described objects change, the relative positional relationships can also change accordingly.

[0022] As shown in Figs. 1-3 The multi-interface heat flow integrator includes a multi-standard input interface unit, through which pulse signals, 4-20 mA current signals and differential voltage signals are accessed via a phoenix terminal array; a heterogeneous switch matrix, the input end of which is electrically connected to the output end of the multi-standard input interface unit, the heterogeneous switch matrix being a three-level grouping switch array composed of a GaN pulse switch group, a SiC analog switch group and an IGBT power switch group, for matching the signal types and frequency bands of output signals of different types of sensors; an optical-magnetic double-coupling driving module, the input end of which is connected to the control port of the heterogeneous switch matrix, adopting an isolation driving mechanism composed of optical signal transmission and magnetic resonance energy transmission to improve signal integrity and system security; a main control processing unit, which receives output data of the heterogeneous switch matrix through an SPI bus, is based on an FPGA+MCU architecture, and realizes multi-channel parallel heat calculation and interface recognition adaptive processing; a dynamic following shielding system, which includes a coaxial ring shielding ring array integrated in the inner layer of a PCB and a programmable voltage compensation electrode, for dynamically adjusting interference shielding performance. The various industrial signals output by the sensor are first connected to the multi-mode input interface unit through the phoenix terminal array. The system identifies the signal type in terms of primary voltage and current. The received signal is then transmitted to the heterogeneous switch matrix. The main control unit matches the switch channel (GaN / SiC / IGBT) according to the signal type, dynamically connects the required transmission path, and then the signal enters the optical-magnetic double-coupling driving module. The control signal is first transmitted by the optical fiber channel, and then the energy isolation amplification processing is realized through the magnetic resonance driving coil. The output driving signal is sent to the main control processing unit. The FPGA module inside the main control unit is responsible for multi-channel signal sampling, data buffering and mapping control. The MCU part performs heat flow calculation, protocol analysis and bus communication. The system simultaneously starts the dynamic following shielding system. According to the voltage feedback of the noise source on the sensor or line, the driving compensation electrode implements local electric field dynamic compensation to realize interference voltage suppression. The whole chain forms a closed-loop signal processing system with the ability of input self-identification, path self-configuration, signal self-isolation and anti-interference self-adaptation.

[0023] As shown in Figs. 1-3 The multi-mode input interface unit includes a hardware feature extraction circuit, which includes an impedance spectrum scanning unit, a leakage current detection bridge, a time domain slope comparator, and a feature matching state machine. The feature matching state machine is realized by FPGA hard logic and is used to receive the digital coded signal output by the hardware feature extraction circuit. The interface type judgment result is output to the heterogeneous switch matrix control port through the pre-stored feature mapping table. The interface unit includes a micro-power maintenance circuit, which keeps the interface in a wake-up listening mode under non-working state through sub-threshold power supply. When the interface accesses external signals or detects weakly coupled disturbance signals, the main control can be awakened within 5ms to enter the rapid identification process. When an interface is in a standby state, the interface is by default kept in a listening mode driven by a sub-threshold power supply, with extremely low power consumption, only maintaining a basic level sensing. When an external sensor is connected or a line senses an electrical disturbance (such as weakly coupled voltage or impedance change), the interface triggers an interruption, immediately activates the hardware feature extraction circuit, which is composed of an impedance spectrum scanning unit, a leakage current detection bridge, a slope comparator and other sub-modules, samples the electrical characteristics of the sensor, and outputs the feature data in the form of digital code to the FPGA internal state machine. The FPGA internal state machine reads the feature data and compares it with the known feature mapping library stored in the internal lookup table. After the comparison is completed, the interface type result (such as current type, pulse type, analog differential type, etc.) is output and fed back to the heterogeneous switch matrix control end to control the connection of the matching path, ensuring the correct configuration of the signal channel. The whole identification and path activation process responds within ≤5ms, and in the non-activated state, it runs with extremely low power consumption, which is suitable for long-time standby scenarios.

[0024] As shown in Figs. 1-3As shown, the switch frequency of the GaN pulse switch group is >1MHz, and the conduction delay is <2ns, which is used to process high-frequency pulse signals of turbine flowmeter output. The GaN switch group is configured with a resonant driving circuit, which contains an LC oscillator. The inductance of the LC oscillator is set to 0.22μH, and the capacitance is set to 2.2nF. The capacitor is pre-charged to 98%-99.5% of the target voltage before the switch action, which is used to reduce the conduction impact; When the master control detects that the access signal is a high-frequency pulse signal (such as turbine flowmeter output), that is, the heterogeneous switch matrix is switched to the GaN pulse switch channel, the system first activates the LC resonant driving circuit in the GaN sub-module. The oscillator composed of a 0.22μH inductor and a 2.2nF capacitor is responsible for completing the capacitor charging before the switch trigger, so that it reaches 98%-99.5% of the target voltage. This pre-charging process provides a near-ideal driving waveform for the GaN device turn-on. Then the master control triggers the GaN device to turn on, realizes signal path closure, and completes the non-delayed conduction of high-frequency pulse signals. Since the GaN device turn-on time is <2ns, combined with the resonant charging mechanism, the turn-on transient current is effectively reduced, the signal edge integrity is improved, and the electromagnetic interference emission is reduced. At the same time, the GaN path has very low on-resistance, which is suitable for accurate signal sampling and flow integration in high-frequency and high-speed scenarios.

[0025] As shown in Figs. 1-3 The master control processing unit is configured with a set of reconfigurable channel mapping mechanism. FPGA on-chip logic is used to realize the logical path rebinding between any interface module and any thermal flow calculation core. It supports dynamically building a neural-style path network according to task priority, signal quality, and channel health. A delay compensation unit is integrated in the master control processing unit, which is used to correct the path propagation delay difference caused by different isolation methods and signal types. The master control processing unit is preconfigured with a set of logical mapping management unit inside the FPGA, which is used to process the dynamic allocation between interface signal channels and thermal flow calculation units. During system operation, the channel mapping relationship is automatically reconfigured according to the interface connection state, signal quality, task priority, etc. The "neural-style" topology is realized, in which any input signal path can be bound to any calculation module. After mapping is established, the system analyzes the time delay of each channel physical path, identifies the transmission time difference caused by different isolation mechanisms (such as optical fiber path, magnetic resonance coil) or signal types, and starts the delay compensation module. The module is built-in digital delay chain (step precision ≤1ns), automatically loads compensation timing, and aligns all signals at the sampling point, so as to ensure that the heat integration algorithm processes the "time synchronization" of multi-channel sampling data, and improves the calculation accuracy and data consistency.

[0026] The compensation electrode voltage of the dynamic following shielding system satisfies , where k∈[0.92,0.99] is the real-time compensation coefficient, and the compensation response time is ≤100μs, To compensate the real-time voltage of the electrode, To represent the voltage of the signal line corresponding to the interference source, the compensation electrode adopts an interdigital electrode topology with an electrode width to spacing ratio of 1:1.2 and an electrode length matching the signal wavelength λ / 20; The system first monitors the possible interference components in the signal line in real time through the sampling lead arranged close to the signal channel, such as induced voltage fluctuations, capacitive coupling noise, etc. The signal is input to the high-bandwidth front-end ADC or analog follower module to extract the real interference voltage The main control system multiplies the voltage by the dynamically adjustable proportional coefficient (range 0.92–0.99), calculate the corresponding compensation voltage in real time The system then drives a high-speed DAC or PWM control module to output this voltage, which is then applied to an interdigitated compensation electrode array. This electrode array, composed of staggered metal finger structures with a length of 1 / 20 the signal wavelength, forms a highly efficient, locally coupled reverse electric field. The compensation field and the noise field are in opposite directions, achieving spatial potential neutralization and effectively suppressing common-mode interference, especially for high-frequency signals. The entire compensation response process is controlled within 100μs and features dynamic adjustment capabilities, continuously tracking changes in interference voltage and implementing a closed-loop anti-interference enhancement mechanism.

[0027] The multi-standard input interface unit has a built-in excitation element that can test itself and its connected circuits through a heating resistor, electromagnetic excitation coil, or piezoelectric vibrator. The excitation response curve can be used to identify problems such as contact resistance degradation, joint cold solder joints, and sensor deposition and scaling. The test frequency is once a day or at a user-specified time period. The system triggers the interface self-diagnosis process during a predetermined test period (such as early morning every day, or set remotely by the user). The main controller sends an excitation command to each channel, and the excitation elements inside each input interface module are activated in turn, including: micro-heating resistors (generating thermal disturbances), electromagnetic excitation coils (injecting alternating magnetic fields), or piezoelectric vibrators (generating micromechanical disturbances). The excitation signal is loaded onto the interface and its sensor connection structure. The main controller simultaneously collects its electrical response curve, such as voltage attenuation, response delay, amplitude change, parasitic impedance offset, etc., and compares and analyzes it with the reference standard response model. If a significant deviation is detected (such as increased capacitance, resistance degradation, abnormal response time), the system will determine it as a potential fault such as poor contact, cold solder joints, oxidation, or sensor fouling, and report it through the monitoring system and record it in the local log. This mechanism implements proactive interface health assessment, supports predictive maintenance, extends service life, and reduces the risk of downtime.

[0028] Those skilled in the art should understand that the above discussion of any embodiment is only intended to be illustrative and is not intended to be in any way limiting to the scope of the present application, including the claims that follow it; the above embodiments or technical features among different embodiments can also be combined, steps can be implemented in any order, and there are many other changes to the different aspects of the present application as described above, which are not provided in detail for the sake of brevity.

[0029] The present application is intended to cover all such alternatives, modifications, and variations as come within the scope of the broadest possible interpretation of the appended claims. Accordingly, any and all such alternatives, modifications, equivalents, improvements and the like are intended to be encompassed by the present application.

Claims

1. A multi-interface heat flow integrator, characterized in that: include: Multi-standard input interface unit, accessing pulse signals, 4-20mA current signals and differential voltage signals through the Phoenix terminal array; A heterogeneous switch matrix, whose input end is electrically connected to the output end of the multi-standard input interface unit, and the heterogeneous switch matrix is ​​a three-level grouped switch array consisting of a GaN pulse switch group, a SiC analog switch group, and an IGBT power switch group, used to match the signal type and frequency band of output signals of different types of sensors; An optical-magnetic dual-coupling drive module, whose input end is connected to the control port of the heterogeneous switch matrix, adopts an isolated drive mechanism composed of optical fiber signal transmission and magnetic resonance energy transmission to improve signal integrity and system safety; The main control processing unit receives the output data of the heterogeneous switch matrix through the SPI bus and implements multi-channel parallel heat calculation and interface identification adaptive processing based on the FPGA+MCU architecture; The dynamic follow-up shielding system includes a coaxial annular shielding ring array integrated into the inner layer of the PCB board and a programmable voltage compensation electrode for dynamically adjusting the interference shielding performance.

2. A multi-interface heat flow integrator according to claim 1, characterized in that: The multi-standard input interface unit includes a hardware feature extraction circuit, which includes an impedance spectrum scanning unit, a leakage current detection bridge, a time domain slope comparator, and a feature matching state machine. The feature matching state machine is implemented by FPGA hard logic and is used to receive the digital coding signal output by the hardware feature extraction circuit and output the interface type judgment result to the heterogeneous switch matrix control port through a pre-stored feature mapping table.

3. The multi-interface heat flow integrator according to claim 2, characterized in that: The interface unit includes a micro-power maintenance circuit, which keeps the interface in wake-up monitoring mode through a sub-threshold power supply in the non-working state; when the interface is connected to an external signal or detects a weak coupling disturbance signal, it can wake up the main control within 5ms to enter a fast identification process.

4. The multi-interface heat flow integrator according to claim 1, characterized in that: The GaN pulse switch group has a switching frequency greater than 1 MHz and a turn-on delay less than 2 ns, and is used to process high-frequency pulse signals output by a turbine flowmeter.

5. The multi-interface heat flow integrator according to claim 2, characterized in that: The GaN switch group is configured with a resonant drive circuit, including an LC oscillator. The inductance of the LC oscillator is set to 0.22μH and the capacitance is set to 2.2nF. Before the switching action, it is pre-charged to 98%-99.5% of the target voltage to reduce the conduction shock.

6. The multi-interface heat flow integrator according to claim 1, characterized in that: The main control processing unit is equipped with a reconfigurable channel mapping mechanism, which uses FPGA on-chip logic to realize the rebinding of logical paths between any interface module and any heat flow calculation core, and supports the dynamic construction of neural-style pathway networks based on task priority, signal quality, and channel health.

7. The multi-interface heat flow integrator according to claim 1, characterized in that: The main control processing unit is integrated with a delay compensation unit, which is used to correct the path propagation delay differences caused by different isolation methods and signal types.

8. The multi-interface heat flow integrator according to claim 1, characterized in that: The compensation electrode voltage of the dynamic follow-up shielding system satisfies , where k∈[0.92,0.99] is the real-time compensation coefficient, and the compensation response time is ≤100μs. To compensate the real-time voltage of the electrode, is the voltage of the signal line corresponding to the interference source.

9. The multi-interface heat flow integrator according to claim 8, characterized in that: The compensation electrodes adopt an interdigital electrode topology, with an electrode width to spacing ratio of 1:1.2, and an electrode length matching the signal wavelength λ / 20.

10. The multi-interface heat flow integrator according to claim 1, characterized in that: The multi-standard input interface unit has a built-in excitation element, which can test itself and its connection circuit through a heating resistor, an electromagnetic excitation coil or a piezoelectric vibrator. The excitation response curve can be used to identify problems such as contact resistance degradation, joint cold solder joints, sensor deposition and scaling. The test frequency is once a day or at a user-specified time period.

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