Photoetching technology implementation method for multi-chip high-density connection

Abstract

The invention discloses a photoetching technology implementation method for multi-chip high-density connection, a chip-level chip interconnection method, a mask plate line manufacturing method and photoetching equipment, and the photoetching technology implementation method comprises the following steps: selecting a first mask plate, and aligning and exposing the first mask plate and a first original pattern unit through a second alignment mark, transferring the first mask pattern to a first exposure area; longitudinally moving the substrate by M times of the longitudinal size of the original pattern for alignment exposure, and transversely moving by 1 time of the transverse size of the original pattern for alignment exposure to complete exposure of other M * 1 chipset exposure areas; a second mask is selected to be aligned with the first original pattern unit for exposure through a second alignment mark, and a second mask pattern is transferred to a second exposure area; and transversely moving the substrate by N times of the transverse size of the original pattern for alignment exposure, and longitudinally moving by 1 time of the longitudinal size of the original pattern for alignment exposure, thereby completing exposure of other 1 * N chipset exposure areas. According to the scheme, high-density interconnection of multiple chips is realized.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of computer, in particular to a photolithography technology implementation method for multi-chip high-density connection, a chip-level chip interconnection method, a mask line manufacturing method and a photolithography equipment. BACKGROUND

[0002] In modern semiconductor manufacturing, photolithography technology is a key step to realize high-density integrated circuits. The photolithography process forms the required circuit structure by accurately transferring the pattern on the mask to the photoresist on the silicon wafer surface. With the continuous improvement of integrated circuit integration, the requirement for the minimum critical dimension (CD) is becoming more and more strict. In the photolithography machine pattern exposure, the limit of the minimum critical dimension can be given by the Rayleigh's rule for resolution, which is shown in formula (1): Formula (1) Wherein, is the wavelength of the light source of the photolithography machine used, is the numerical aperture of the photolithography machine projection system used for exposure, is a regulation factor depending on the photolithography process, also known as Rayleigh constant, is the minimum size of the pattern. As can be seen from formula (1), there are three ways to reduce the minimum size of the pattern: shortening the exposure wavelength , increasing the numerical aperture , or reducing . It is difficult to reduce the minimum size of the pattern by the above three ways, and the cost is too high. In addition, with the continuous reduction of device size, the leakage problem caused by quantum tunneling effect is becoming more and more serious, which limits the feasibility of further reducing the minimum size of the pattern. Therefore, it is no longer feasible to simply rely on reducing the key size of the device to increase the number of transistors.

[0003] In order to accommodate more transistors, it is extremely important to manufacture larger chips. However, the maximum exposure field size of the traditional photolithography machine is limited to about 26mm × 33mm, which cannot meet the demand of manufacturing larger size chips. Although large exposure field size is achieved in some liquid crystal panel fields, the line size obtained by this method is too wide, which is difficult to meet the high-density integration demand of integrated circuits. Therefore, how to realize the high-density interconnection of multiple chips (such as multiple 26mm × 33mm size (such as 25mm × 32mm) chips) without changing the exposure field size has become a technical problem to be solved in photolithography technology. SUMMARY

[0004] The application provides a photolithography technology implementation method for multi-chip high-density connection, a chip-level chip interconnection method, a mask line manufacturing method and a photolithography equipment, which can realize multi-chip high-density interconnection under the condition that the exposure field size is unchanged, thereby forming a large-size chip, and providing photolithography technology support for MxN multi-chip high-density interconnection integration. The specific scheme is as follows: In a first aspect, the embodiments of the application provide a photolithography technology implementation method for multi-chip high-density connection, which is used for realizing the interconnection of MxN chips, and comprises the following steps: loading a to-be-exposed substrate with existing original pattern units into a stage of a photolithography equipment, and performing first alignment through a first alignment mark on the substrate; selecting a first mask for a first Mx1 chip group in the first MxN chip group on the substrate, aligning the first mask with a first original pattern unit in the first Mx1 chip group through a second alignment mark on the substrate, offsetting the substrate or the first mask by a preset offset distance, performing exposure, and transferring a preset pattern on the first mask to a first exposure area on the substrate; the first exposure area covers a scribe lane between M original pattern units in the first Mx1 chip group and at least part of a pattern area of each of the M original pattern units; repeating the steps of moving the substrate longitudinally by M times of the longitudinal size of the original pattern unit and performing the alignment and exposure, and repeating the steps of moving the substrate transversely by 1 times of the transverse size of the original pattern unit and performing the alignment, offsetting and exposure, to complete the exposure of the exposure areas corresponding to other Mx1 chip groups in the first MxN chip group and the exposure of the exposure areas corresponding to each Mx1 chip group in other MxN chip groups on the substrate; selecting a second mask for a first 1xN chip group in the first MxN chip group on the substrate, aligning the second mask with the first original pattern unit in the first 1xN chip group through the second alignment mark on the substrate, offsetting the substrate or the second mask by a preset offset distance, performing exposure, and transferring a preset pattern on the second mask to a second exposure area on the substrate; the second exposure area covers a scribe lane between N original pattern units in the first 1xN chip group and at least part of a pattern area of each of the N original pattern units; repeating the steps of moving the substrate by N times of the lateral size of the original pattern unit in the lateral direction and performing the alignment and exposure, and repeating the steps of moving the substrate by 1 times of the longitudinal size of the original pattern unit in the longitudinal direction and performing the alignment, offsetting and exposure, to complete the exposure of the exposure area corresponding to the other 1×N chip groups in the first M×N chip group and the exposure of the exposure area corresponding to each 1×N chip group in the other M×N chip groups on the substrate; wherein, for any M×N chip group, any original pattern unit and the original pattern unit adjacent to it form a connection through the exposure area formed by the first mask and / or the second mask; for any M×N chip group, the connection together with the M×N chip peripheral scribe lane has no interconnection line pattern which goes into the interior of the original pattern unit and connects the original pattern units; M and N are both integers greater than or equal to 1, and at least one of M and N is greater than or equal to 2.

[0005] In a second aspect, the embodiments of the present application provide a photolithography technology implementation method for multi-chip high-density connection, used for implementing interconnection of M×N chips, comprising: loading a substrate to be exposed on which original pattern units exist to a stage of a photolithography device, performing first alignment through first alignment marks on the substrate; for a first i×1 chip group in the first M×N chip group on the substrate, selecting a third mask, aligning the third mask with a second original pattern unit in the first i×1 chip group through second alignment marks on the substrate, offsetting the substrate or the third mask by a preset offset distance, performing exposure, and transferring a preset pattern on the third mask to a third exposure area on the substrate; the third exposure area covers the scribe lane between i original pattern units in the first i×1 chip group and at least part of the pattern area of each of the i original pattern units; repeating the steps of moving the substrate by M times of the longitudinal size of the original pattern unit in the longitudinal direction and performing the alignment and exposure, or repeating the steps of moving the substrate by N times of the lateral size of the original pattern unit in the lateral direction and performing the alignment, offsetting and exposure, to complete the exposure of the exposure area corresponding to the i×1 chip group corresponding to the first i×1 chip group in the other M×N chip groups on the substrate; repeating the exposure of the corresponding i×1 chip group other than the first i×1 chip group of the first M×N chip group, and repeating the longitudinal movement by M times of the longitudinal size of the original pattern unit or the lateral movement by N times of the lateral size of the original pattern unit, to complete the exposure of the corresponding area of the other corresponding i×1 chip in the other M×N chip group on the substrate; For a first 1xj chip group in the first MxN chip group on the substrate, a fourth mask is selected, the fourth mask is aligned with the second original pattern unit in the first 1xj chip group through a second alignment mark on the substrate, the substrate or the fourth mask is offset by a preset offset distance, exposure is performed, and a preset pattern on the fourth mask is transferred to a fourth exposure area on the substrate; the fourth exposure area covers a scribe lane between j original pattern units in the first 1xj chip group and at least part of a pattern area of each of the j original pattern units. The steps of moving the substrate longitudinally by M times the longitudinal size of the original pattern unit and performing the alignment and exposure are repeated, or the steps of moving the substrate transversely by N times the transverse size of the original pattern unit and performing the alignment, offsetting and exposure are repeated, to complete exposure of exposure areas of corresponding 1xj chip groups corresponding to the first 1xj chip group in other MxN chip groups on the substrate. The steps of moving the substrate longitudinally by M times the longitudinal size of the original pattern unit and performing the alignment and exposure are repeated, or the steps of moving the substrate transversely by N times the transverse size of the original pattern unit and performing the alignment, offsetting and exposure are repeated, to complete exposure of exposure areas of corresponding 1xj chip groups corresponding to the first 1xj chip group in other MxN chip groups on the substrate. Wherein, for any MxN chip group, any original pattern unit and an original pattern unit adjacent thereto form a connection through an exposure area formed by the third mask and / or the fourth mask; for any MxN chip group, there is no interconnection line pattern connecting original pattern units and extending into the interior of the original pattern unit on the peripheral scribe lane of the MxN chip connected together; M and N are both integers greater than or equal to 1, and at least one of M and N is greater than or equal to 2; i and j are both integers greater than or equal to 1, i≤M, j≤N, and when M is greater than or equal to 2, 2≤i, and when N is greater than or equal to 2, 2≤j.

[0006] In a third aspect, a chip-level chip interconnection method comprises: A substrate is provided, and a semiconductor structure comprising at least two semiconductor chips is formed on the substrate, each semiconductor chip having formed therein a chip-level interconnection, and there being no interconnection between the semiconductor chips; The photolithography steps for realizing the interconnection between the at least two semiconductor chips are realized by the implementation method of the photolithography technology according to the first aspect or the second aspect.

[0007] In a fourth aspect, an embodiment of the present application provides a mask line manufacturing method, comprising: The mask first line, the mask second line and the mask third line are made on a mask plate; the mask first line and the mask third line are connected, and the mask second line and the mask third line are connected; The mask first line is used for exposing a first line of the first aspect in a first overlapping area of a substrate; the mask second line is used for exposing a second line of the first aspect in the first overlapping area of the substrate; and the mask third line is used for exposing a third line of the first aspect in the first overlapping area of the substrate.

[0008] In the fifth aspect, the embodiments of the present application provide a photolithography device, which comprises two mask tables, three or four object tables, two upper and lower wafer systems and two wafer measurement systems.

[0009] Compared with the prior art, the present application has the following advantages: The embodiment of the application provides a photolithography technology implementation method for multi-chip high-density connection, which is used for realizing the interconnection of MxN chips, and comprises the following steps: loading a to-be-exposed substrate with original pattern units to a stage of a photolithography device, and performing first alignment through a first alignment mark on the substrate; selecting a first mask plate for a first Mx1 chip group in the first MxN chip group on the substrate, aligning the first mask plate with a first original pattern unit in the first Mx1 chip group through a second alignment mark on the substrate, performing exposure, and transferring a preset pattern on the first mask plate to a first exposure area on the substrate; the first exposure area covers a scribe lane between M original pattern units in the first Mx1 chip group and at least part of a pattern area of each of the M original pattern units; repeating the steps of moving the substrate longitudinally by M times of a longitudinal size of the original pattern unit and performing the alignment and exposure, and repeating the steps of moving the substrate transversely by 1 times of a transverse size of the original pattern unit and performing the alignment and exposure, completing exposure of exposure areas corresponding to other Mx1 chip groups in the first MxN chip group and exposure of exposure areas corresponding to each Mx1 chip group in other MxN chip groups on the substrate, so that the first mask plate forms interconnections between multiple Mx1 chip groups on the substrate; selecting a second mask plate for a first 1xN chip group in the first MxN chip group on the substrate, aligning the second mask plate with the first original pattern unit in the first 1xN chip group through the second alignment mark on the substrate, performing exposure, and transferring a preset pattern on the second mask plate to a second exposure area on the substrate; the second exposure area covers a scribe lane between N original pattern units in the first 1xN chip group and at least part of a pattern area of each of the N original pattern units; repeating the steps of moving the substrate transversely by N times of a transverse size of the original pattern unit and performing the alignment and exposure, and repeating the steps of moving the substrate longitudinally by 1 times of a longitudinal size of the original pattern unit and performing the alignment and exposure, completing exposure of exposure areas corresponding to other 1xN chip groups in the first MxN chip group and exposure of exposure areas corresponding to each 1xN chip group in other MxN chip groups on the substrate, so that the second mask plate forms interconnections between multiple 1xN chip groups on the substrate; wherein for any MxN chip group, any original pattern unit and an original pattern unit adjacent to the original pattern unit form a connection through an exposure area formed by the first mask plate and / or the second mask plate; for any MxN chip group, the interconnection line pattern connecting the MxN chips together does not extend into the original pattern unit and connects the original pattern units on a peripheral scribe lane of the MxN chips. M and N are both integers greater than or equal to 1, and at least one of M and N is greater than or equal to 2.Thus, two masks are used to realize the high-density interconnection of multiple chips without changing the size of the exposure field, thereby forming a large chip, and providing lithography technology support for the high-density interconnection integration of MxN large chips (such as multiple 26mm x 33mm or 25mm x 32mm chips).

[0010] In addition, in the prior art, when realizing chip interconnection, the interconnection is mainly realized by a board-level interconnection mode, which is usually realized by a circuit board after packaging. This mode has a complex structure and a large size. In use, signals need to be transmitted through a long circuit board path, which can cause high signal delay. In addition, long-distance wiring is prone to be affected by problems such as electromagnetic interference, which can cause signal distortion. Long lines and driving circuits can also cause large capacitive loads, which can increase power consumption. At the same time, larger line and solder joint sizes limit the interconnection density between chips and require larger size communication driving circuits, which further limits the interconnection density between chips. In comparison, the implementation method of the high-density interconnection lithography technology for multiple chips provided in the present application can realize chip-level interconnection. Thus, multiple chips can be connected together during chip manufacturing. In use, the signal transmission time can be significantly reduced due to the shortened interconnection distance, and the risk of signal distortion can be reduced, the signal integrity can be improved, and the parasitic load can be reduced, thereby reducing power consumption. In addition, the present application directly uses the existing high-performance lithography machine (such as a DUV lithography machine or an EUV lithography machine) for chip interconnection lithography. The minimum size of the line can reach 0.1um or even several nm, which can greatly improve the interconnection line density between chips, and finally form an MxN large chip (such as a 25mm x 32mm chip) with high-density interconnection between chips (such as an MxN x 25mm x 32mm chip). BRIEF DESCRIPTION OF DRAWINGS

[0011] Figure 1 FIG. 1 is a structural diagram of an example of a lithography device to which the implementation method of the high-density interconnection lithography technology for multiple chips provided in the present application is applied.

[0012] Figure 2 FIG. 2 is a schematic diagram of an example of a substrate in the implementation method of the high-density interconnection lithography technology for multiple chips provided in the present application.

[0013] Figure 3 FIG. 3 is a structural diagram of an EUV light source-based lithography device provided in the present application.

[0014] Figure 4 FIG. 4 is a structural diagram of another example of a lithography device to which the implementation method of the high-density interconnection lithography technology for multiple chips provided in the present application is applied.

[0015] Figure 5is a flow chart of a method for implementing a lithography technology of multi-chip high-density connection provided by an embodiment of the present application.

[0016] Figure 6 is a schematic diagram of an example of a first M×N chip group in a method for implementing a lithography technology of multi-chip high-density connection provided by an embodiment of the present application.

[0017] Figure 7 is a schematic diagram of an example of a first M×N chip group in a method for implementing a lithography technology of multi-chip high-density connection provided by an embodiment of the present application.

[0018] Figure 8 is a schematic diagram of an example of a relative position relationship between an original mask and a selected mask for performing exposure, and a position relationship between an exposure region to be formed and an original pattern unit covered by the exposure region to be formed in a method for implementing a lithography technology of multi-chip high-density interconnection provided by an embodiment of the present application.

[0019] Figure 9 is a schematic diagram of another example of a first M×N chip group in a method for implementing a lithography technology of multi-chip high-density connection provided by an embodiment of the present application.

[0020] Figure 10 is a schematic diagram of an example of forming a plurality of M×1 chip groups on the substrate using a first mask in a method for implementing a lithography technology of multi-chip high-density interconnection provided by an embodiment of the present application.

[0021] Figure 11 is a schematic diagram of an example of forming an exposure region of a 1×N chip group on the substrate using a second mask in a method for implementing a lithography technology of multi-chip high-density interconnection provided by an embodiment of the present application.

[0022] Figure 12 is a schematic diagram of another example of forming an exposure region of a 1×N chip group on the substrate using a second mask in a method for implementing a lithography technology of multi-chip high-density interconnection provided by an embodiment of the present application.

[0023] Figure 13 is a schematic diagram of an example of forming a plurality of 1×N chip groups on the substrate using a second mask in a method for implementing a lithography technology of multi-chip high-density interconnection provided by an embodiment of the present application.

[0024] Figure 14 is a schematic diagram of an example of a target pattern unit in a method for implementing a lithography technology of multi-chip high-density interconnection provided by an embodiment of the present application.

[0025] Figure 15FIG. 1 is a schematic diagram of an example of the first, second, and third lines in the implementation method of the multi-chip high-density interconnection photolithography technology provided by the embodiments of the present application.

[0026] Figure 16 FIG. 2 is a schematic diagram of an example of the fourth, fifth, and sixth lines in the implementation method of the multi-chip high-density interconnection photolithography technology provided by the embodiments of the present application.

[0027] Figure 17 FIG. 3 is a schematic diagram of an example of the first and second overlapping regions overlapping with each other in the implementation method of the multi-chip high-density interconnection photolithography technology provided by the embodiments of the present application.

[0028] Figure 18 FIG. 4 is a schematic diagram of an example of the first overlapping region including multiple sets of lines and the second overlapping region including multiple sets of lines in the implementation method of the multi-chip high-density interconnection photolithography technology provided by the embodiments of the present application.

[0029] Figure 19 FIG. 5 is a schematic diagram of an example of the overlapping region including multiple sets of lines in the implementation method of the multi-chip high-density interconnection photolithography technology provided by the embodiments of the present application.

[0030] Figure 20 FIG. 6 is a schematic diagram of an example of the exposure region formed by the third mask plate on the substrate in the implementation method of the multi-chip high-density interconnection photolithography technology provided by the embodiments of the present application.

[0031] Figure 21 FIG. 7 is a schematic diagram of an example of the exposure region formed by the fourth mask plate on the substrate in the implementation method of the multi-chip high-density interconnection photolithography technology provided by the embodiments of the present application.

[0032] Figure 22 FIG. 8 is a schematic diagram of an example of the exposure region formed by the third mask plate on the substrate in the implementation method of the multi-chip high-density interconnection photolithography technology provided by the embodiments of the present application.

[0033] Figure 23 FIG. 9 is a schematic diagram of an example of the exposure region formed by the fourth mask plate on the substrate in the implementation method of the multi-chip high-density interconnection photolithography technology provided by the embodiments of the present application. DETAILED DESCRIPTION

[0034] In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present application. However, it will be apparent to one skilled in the art that the present application can be practiced without the specific details set forth in this description. In other instances, well-known methods have not been described in detail in order not to unnecessarily obscure aspects of the present application.

[0035] It should be noted that the terms "first", "second", "third", etc. in the claims, specification and drawings of the present application are used to distinguish similar objects, and are not used to describe a specific order or sequence. The data used in this way can be interchangeable under appropriate circumstances, so that the embodiments of the present application described herein can be implemented in an order other than that illustrated or described herein. In addition, the terms "include", "have" and their variants are intended to cover non-exclusive inclusion, for example, a process, method, system, product or device that includes a series of steps or units does not have to be limited to only those steps or units clearly listed, but can include other steps or units not clearly listed or inherent to these processes, methods, products or devices.

[0036] It should be understood that in the embodiments of the present application, "at least one" means one or more, and "multiple" means two or more. "And / or" is only a description of the association relationship of the associated objects, which means that there can be three relationships, for example, A and / or B can represent the three cases of A alone, A and B together, and B alone. The character " / " generally represents an "or" relationship between the associated objects before and after it. "Including A, B and / or C" means including any one or any two or three of A, B and C.

[0037] It should be understood that in the embodiments of the present application, "B corresponding to A", "B corresponding to A", "A corresponding to B" or "B corresponding to A" means that B is associated with A, and B can be determined according to A. Determining B according to A does not mean that B is determined only according to A, but also can be determined according to A and / or other information.

[0038] Based on the reasons mentioned in the background, in order to realize multi-chip high-density interconnection to form a large-size chip without changing the size of the exposure field, the present application provides a multi-chip high-density connection photolithography technology implementation method and a chip-level chip interconnection method.

[0039] First, the application scenario of the multi-chip high-density connection photolithography technology implementation method and the chip-level chip interconnection method provided by the embodiments of the present application is introduced: The method provided by the embodiments of the present application can be applied to top or sub-top photolithography process, which is a step in the back-end of integrated circuit manufacturing, mainly used for forming the uppermost metal interconnection and contact hole structure. In the top or sub-top photolithography process, the multi-chip high-density connection photolithography technology implementation method and the chip-level chip interconnection method provided by the embodiments of the present application can be used to realize multi-chip high-density interconnection, thereby forming a large-size chip.

[0040] Exemplarily, two adjacent integrated circuit patterns have been formed on the substrate, and a hole pattern formed by a photolithography and etching process exists on each of the two adjacent integrated circuit patterns. For the two adjacent integrated circuit patterns, the interconnection between the two can be achieved by the following steps: first, a layer of metal (such as aluminum, copper, etc.) is deposited on the surface of the substrate, which not only covers the original metal pattern, but also fills into the formed hole pattern, thereby achieving electrical connection between the upper and lower metal layers; then, a photolithography technology is used to expose the required interconnection line pattern between the two adjacent integrated circuit patterns, and the unwanted metal part is removed by etching to leave the interconnection line, which covers the original hole pattern and connects the integrated circuit metal layer vertically through the hole pattern to the lower layer circuit, thereby achieving electrical connection between the two adjacent integrated circuit patterns; then, bonding pads are added so that the chip can be connected with external circuits in the subsequent packaging process. Finally, the wafer is cut into individual chip units including two adjacent integrated circuit patterns.

[0041] As shown in Figure 1 , it is a structure diagram of an example of a photolithography equipment applied by the photolithography technology implementation method for multi-chip high-density connection provided by the embodiment of the present application. The photolithography equipment comprises: A light source 100 is configured to provide an exposure light beam required for photolithography. The light source of the light source 100 can include but is not limited to one of a light source generated by a mercury lamp, a light source generated by an excimer laser, and an extreme ultraviolet (EUV) light source. The mercury lamp can emit light of multiple discrete wavelengths, including g-line (436 nm), i-line (365 nm), etc., which are suitable for photolithography processes with different resolution requirements. The excimer laser can generate ultraviolet light with a shorter wavelength, such as KrF (248 nm) and ArF (193 nm), and the shorter wavelength helps to improve the resolution of photolithography and is suitable for fine patterning requirements. The wavelength of the EUV light source is 13.5 nm, which is much shorter than the traditional DUV light source. This enables it to perform photolithography at a very high resolution, which is suitable for the most advanced semiconductor manufacturing processes. The generation method of the EUV light source includes but is not limited to converting a material into a plasma state with at least one element (such as xenon, lithium, or tin) having one or more emission lines in the EUV range.

[0042] A mask plate 200 is configured to provide a preset pattern required for exposure.

[0043] The projection system 300 is used to transfer the preset pattern on the mask 200 onto the substrate 500 to be exposed. The projection system 300 can be a conventional projection system with a reduction ratio of 4 to 10 times, or other reduction ratios. Specifically, the reduction ratio of the projection system 300 can be selected from any one of 4, 5, 8, and 10 times, or can be selected from one of 2.5, 2, 1.25, 1, 0.8, 0.5, 0.4, 0.2, 0.125, and 0.1. The desired reduction ratio can be selected based on the size of the original pattern unit produced in the previous layer, the minimum critical dimension requirement, and the size requirement of the exposure field to be formed (i.e., the first exposure area and the second exposure area). This application does not impose specific limitations on this.

[0044] The stage 400 is used to load the substrate 500 to be exposed and to perform stepping of the substrate 500 .

[0045] The substrate 500 may be a silicon substrate, a germanium substrate, a compound semiconductor substrate, a ceramic substrate, a glass substrate, a quartz substrate, a silicon substrate, or a metal substrate. The substrate may be circular or square.

[0046] like Figure 2 As shown, it is a schematic diagram of an example of a substrate in the method for realizing the photolithography technology for high-density connection of multiple chips provided in an embodiment of the present application. The substrate 500 can be a composite substrate consisting of a substrate 503 with an integrated circuit (including a silicon substrate, a germanium substrate, a compound semiconductor, etc.) and a carrier 502 (including a ceramic carrier, a glass carrier, a quartz carrier, a silicon carrier, a metal carrier, etc.) for supporting the substrate 503. By adopting the method for realizing the photolithography technology provided in an embodiment of the present application, the KGD (know good die) chip can be precisely bonded to the carrier 502, and then the composite substrate can be further interconnected at a high density through the present invention. Among them, the KGD (know good die) chip refers to an independent chip that has been verified to be functioning normally in wafer-level testing, and it has good functionality and reliability before being integrated into a more complex system.

[0047] The substrate 500 may be a substrate with integrated circuit patterns, or a substrate with metal wiring, and / or optical wiring, and / or microfluidic circuits, and / or MEMS circuits. In other words, when there is a need to connect several small functional structures into a larger functional structure, or when high-density connections are required, the methods provided in the embodiments of the present application can be used to achieve this.

[0048] That is, the implementation method of the photolithography technology provided in the embodiments of the present application is feasible for silicon wafers with patterns, and is also feasible for compound semiconductors or carrier boards with patterns, and can realize high-density interconnection of the compound semiconductors or carrier boards based on the same exposure field size and interconnection between multiple patterns. The compound semiconductors have the same ability to manufacture large-size chips as the traditional silicon wafers, and in order to realize high-density interconnection between the chips, the chips can be fixed on the carrier boards by using bonding technology (such as direct copper bonding).

[0049] The substrate of the carrier board can be a high-hardness and low-deformation substrate. Specifically, the carrier board can be one of a ceramic carrier board, a glass carrier board, a quartz carrier board, a silicon carrier board, and a metal carrier board.

[0050] When a photolithography machine with a large exposure field (for example, an exposure field of 50 mm×50 mm) is used, the implementation method of the photolithography technology provided in the embodiments of the present application can realize high-density interconnection of a large carrier board with a size of decimeters. It should be noted that optical interconnection between high-density chips is a key link to solve the communication between chips and chips or cards and cards, and by using the implementation method of the photolithography technology provided in the embodiments of the present application, a corresponding optical communication line can be manufactured, and the manufactured optical communication line has the advantages of narrow line width and high precision.

[0051] The substrate 500 can also be loaded with one or more of a silicon substrate, a germanium substrate, a compound semiconductor substrate, and a carrier board.

[0052] In this way, multiple small silicon wafers or small carrier boards can be installed on a large carrier board, which can improve the efficiency, and different models of small silicon wafers or small carrier boards can be installed on the large carrier board, so as to realize high-density interconnection of the different models of small silicon wafers or small carrier boards in a large-size chip mode.

[0053] When the substrate 500 is a substrate 502 loaded with multiple silicon substrates, or multiple germanium substrates, or multiple compound semiconductor substrates, or multiple carrier boards, the silicon substrates can be the same or different, and / or the germanium substrates can be the same or different, and / or the compound semiconductor substrates can be the same or different, and / or the carrier boards can be the same or different. The silicon substrates, the germanium substrates, the compound semiconductor substrates, and the carrier boards can be placed according to actual needs, and the present application does not limit this.

[0054] The size of the carrier board can be 40 mm to 4000 mm, for example, the size of the carrier board can be one of 40 mm, 80 mm, 100 mm, 150 mm, 300 mm, 600 mm, 1200 mm, 2400 mm, 3000 mm, 3600 mm, or 4000 mm.

[0055] It should be noted that since the projection lens used in the embodiment of the present application is a conventional projection lens with a reduced magnification, the lines it produces are thinner and the alignment accuracy is higher. In this case, in order to prevent multiple silicon substrates, germanium substrates, compound semiconductor substrates and carriers from not being able to connect, the silicon substrates, germanium substrates, compound semiconductor substrates and carriers can be placed with high precision. In this way, the problem of connection failure caused by only aligning a part of the components and other components being unable to be correctly aligned due to changes in relative positions can be effectively avoided. In particular, when processing silicon substrates, germanium substrates, compound semiconductor substrates and carriers of different sizes, it is necessary to accurately determine the position of each component and fill the chip-free area to ensure that the alignment accuracy meets actual needs and to ensure the stability of the glue coating and exposure. If the chip-free area is not filled, the photoresist may penetrate into it during the glue coating process, resulting in an uneven surface, thereby affecting the quality of subsequent processes.

[0056] exist Figure 1 In the photolithography device shown, the light source 100 forms an exposure beam through the illumination system. The exposure beam passes through the mask 200, and transfers the preset pattern on the mask 200 to the substrate 500 loaded on the stage 400 through the projection system 300. Thereafter, photolithography is performed on the photoresist material to form an exposure field pattern.

[0057] It should be noted that if the light source of the light source 100 is an EUV light source and the projection system 300 is a reflective projection system, Figure 3 As shown in FIG. 1 , it is a structural diagram of a lithography apparatus based on an EUV light source provided in an embodiment of the present application. Figure 3 In the illustrated lithography apparatus, the light source 100 generates an exposure beam through an illumination system. This exposure beam passes through the reticle 200 and is then reflected by the reflective projection system 300 onto the substrate 500 mounted on the stage 400. Subsequently, photolithography is performed on the photoresist material to form an exposure field pattern. This avoids the problem of extreme ultraviolet (EUV) light being easily absorbed by transparent materials, preventing the exposure beam from reaching the substrate.

[0058] If the light source 100 is a mercury lamp or excimer laser, an immersion liquid (such as deionized water) is filled between the projection system 300 and the substrate 500. Compared to traditional photolithography methods in which the exposure beam directly reaches the silicon wafer surface from the projection system, the embodiment of the present application increases the refractive index of the medium by filling the immersion liquid, thereby improving the numerical aperture (NA) of the optical system and reducing the minimum critical dimension.

[0059] The original pattern units present on the substrate 500 can be one or more of integrated circuit patterns, optical path patterns, microfluidic channels, metal wiring, sensor patterns. The integrated circuit pattern can be an integrated circuit pattern unit. The size of the integrated circuit pattern unit is less than 26mm x 33mm (e.g., 25mm x 32mm), and the specific size can be determined according to actual needs, which is not limited herein.

[0060] The type of integrated circuit can include, but is not limited to, at least one of an integrated circuit with integrated electrical functions, an integrated circuit with integrated optical-optoelectronic functions, and an integrated circuit with integrated sensor functions, that is, the implementation method of the photolithography technology provided in the embodiments of the present application can be applied to the chip to realize large-area high-density interconnection of the chip. The type of integrated circuit can be selected according to actual needs, which is not limited herein.

[0061] The integrated circuit can be an integrated circuit without completed pad fabrication or an integrated circuit with completed pad fabrication. That is, the implementation method of the photolithography technology provided in the embodiments of the present application is applicable to integrated circuits with or without pads. It should be noted that at the initial stage, there can be some pads on the chip, which are mainly used for internal interconnection or preliminary external connection. However, as the number of chips increases and the interconnection density increases, the existing pads can not be sufficient to meet the needs of all external connections. Therefore, after completing the high-density free connection of M x N chips, the pads can be further fabricated. The implementation method of the photolithography technology provided in the embodiments of the present application can generate a certain number of pads while completing the high-density chip interconnection, which not only simplifies the process flow, but also reduces the pattern fabrication level, thereby reducing the manufacturing cost and time consumption.

[0062] The integrated circuit pattern can be one layer of integrated circuit pattern or multiple layers of integrated circuit pattern. As the three-dimensional integrated circuit technology becomes more and more mature, the implementation method of the photolithography technology provided in the embodiments of the present application can also be applied to chips with multiple layers of integrated circuits stacked, that is, the method provided in the embodiments of the present application can also be effectively implemented under the condition of complex structures formed after multiple layers of circuits are integrated.

[0063] In the multiple layers of patterns, the materials of the patterns of different layers can be the same or different. In this way, silicon-based-silicon-based, or silicon-based-compound semiconductor, or silicon-based-carbon-based, or silicon-based-germanium-silicon semiconductor, etc. can be integrated together to obtain a complex large chip.

[0064] In the photolithography implementation methods provided in the embodiments of the present application, the integrated circuits in the original graphic units on the substrate to be exposed can be integrated circuits that have completed both the front-end of line (FEOL) and back-end of line (BEOL) processes, and / or integrated circuits that have partially completed both the front-end of line (FEOL) and back-end of line (BEOL) processes. The specific process step to start intervention can be selected based on actual needs to achieve the desired effect.

[0065] The substrate 500 further includes a primary alignment device 510, which is used to perform preliminary alignment on the substrate. It should be noted that when the substrate 500 does not have the primary alignment device 510, alignment can also be performed based on the shape of the substrate itself.

[0066] like Figure 4 , is a structural diagram of another example of a lithography device used in the method for implementing the lithography technology provided in an embodiment of the present application, wherein the lithography device includes one stage (such as stage 410), or two stages (such as stage 410 and stage 430), or three stages (such as stage 410, stage 420, stage 430), or four stages (such as stage 410, stage 420, stage 430, and stage 440). When there are two stages (such as stage 410 and stage 430), both stages are loaded with the silicon substrate, or the germanium substrate, or the compound semiconductor substrate, or the carrier. Figure 4 In the example shown in FIG, substrate 1500 is loaded on stage 410, and substrate 3500 is loaded on stage 430. The two stages are moved in turn under projection system 310 to complete exposure.

[0067] Furthermore, if Figure 4 As shown, the lithography apparatus includes two mask workstations, one corresponding to mask 210 and the other corresponding to mask 220, wherein each mask workstation is equipped with an independent projection system. Figure 4 In the example, the mask workbench corresponding to mask 210 corresponds to projection system 310 , and the mask workbench corresponding to mask 220 corresponds to projection system 320 .

[0068] In the case where the lithography apparatus includes two mask workstations and includes one stage (such as stage 410), or two stages (such as stage 410, stage 430), or three stages (such as stage 410, stage 420, stage 430), or four stages (such as stage 410, stage 420, stage 430, stage 440), each of the stages corresponds to a projection system for realizing exposure, and the one stage, or the two stages, or the three stages, or the four stages are respectively moved to the projection systems corresponding to the two mask workstations (respectively attached). Figure 4 The image is exposed under the projection system 310 and the projection system 320).

[0069] Furthermore, if Figure 4 As shown, in the case where the photolithography apparatus includes two mask workstations and three stages (such as stage 410, stage 420, stage 430), or four stages (such as stage 410, stage 420, stage 430, stage 440), the photolithography apparatus further includes two upper and lower silicon wafer systems (attached Figure 4 101 and 102 in the Figure 5 Silicon wafer measurement system 930 and silicon wafer measurement system 940).

[0070] In comparison, in the case where there is only one silicon wafer measurement system (such as silicon wafer measurement system 930), assuming there are three stages (such as stage 410, stage 420, and stage 430), where the wiring of stage 410 and stage 420 is in the front, and the wiring of stage 430 is in the back, since there is only one silicon wafer measurement system, the wiring system needs to be bypassed, and stage 410 needs to be moved to the left side of silicon wafer measurement system 930 before stage 420 can be moved to the measurement position. If stage 410 is moved to the bottom of projection system 320, stage 420 needs to be moved to the right side of projection system 320.

[0071] For example, taking four object tables (e.g., object table 410, object table 420, object table 430, and object table 440) as an example, object table 430 and object table 410 use wafer measurement system 930 and up-down wafer system 101, and the wiring system is front (object table 430) and back (object table 410); object table 440 and object table 420 use wafer measurement system 940 and up-down wafer system 102, and the wiring system is front (object table 420) and back (object table 440). In the whole process, the mask (e.g., mask 210 and mask 220) and the projection system (e.g., projection system 310 and projection system 320) are common resources. Through reasonable table rotation and path planning, each table can smoothly perform measurement, up-down wafer preparation, and projection exposure operations, and will not be interrupted or delayed due to path conflicts.

[0072] It can be seen that, in the case that the lithography apparatus includes two mask tables and includes three object tables or four object tables, when the lithography apparatus includes two up-down wafer systems and two wafer measurement systems, the mutual interference between the wiring systems can be effectively avoided, thereby improving the flexibility and efficiency of the lithography apparatus and ensuring that each object table can smoothly perform measurement, preparation, and projection exposure operations.

[0073] It should be understood that the left, right, front, and back described above are relative, and the object tables are actually operated on platform 10.

[0074] The above is an introduction to the lithography apparatus provided by the embodiments of the present application.

[0075] It should be noted that the implementation method of the lithography technology provided by the present application is mainly used to solve the interconnection between multiple large chips smaller than the traditional integrated circuit exposure field limit (about 26mm*33mm), and can realize high-density multi-chip interconnection without changing the exposure field size, thereby efficiently manufacturing larger chips than the chips manufactured by the traditional lithography method or manufacturing higher-density line carrier boards than the traditional carrier board manufacturing method under the premise of ensuring large area. These are the intended purposes of the present application, and will not be described here.

[0076] The technical solutions of the present application will be described in detail below through specific embodiments. It should be noted that the following specific embodiments can be combined with each other, and the same or similar concepts or processes may not be described in detail in some embodiments.

[0077] For example, Figure 1As shown is a flow chart of a method for implementing multi-chip high-density connection lithography technology according to the first embodiment of the present application, which is used to implement interconnection of M×N chips, and includes the following steps S101-S105.

[0078] Step S101: load a substrate to be exposed with existing original pattern units to a stage of a lithography device, and perform first alignment through first alignment marks on the substrate.

[0079] This step is used to preliminarily position the substrate to be exposed with existing original pattern units when the substrate is initially loaded to the stage.

[0080] The original pattern units generally refer to single integrated circuits (such as 25mm*32mm) slightly smaller than the maximum size (about 26mm*33mm) of an exposure field of a conventional lithography device (such as a DUV (deep ultraviolet) lithography device). The original pattern units can be single-exposure patterns formed by exposure using a projection system with a reduction ratio of 4-10 or other reduction ratios. For example, the original pattern units are single-exposure patterns formed by exposure using a projection system with a reduction ratio of 4; for another example, the original pattern units are single-exposure patterns formed by exposure using a projection system with a reduction ratio of 5; for another example, the original pattern units are single-exposure patterns formed by exposure using a projection system with a reduction ratio of 8; for another example, the original pattern units are single-exposure patterns formed by exposure using a projection system with a reduction ratio of 10. Taking a reduction ratio of 5 of the projection system as an example, the maximum size of the exposure field formed after synchronous scanning movement of the workpiece stage and the mask stage is generally 26mm*33mm. In this case, the maximum size of the original pattern units is generally less than or equal to 26mm*33mm.

[0081] It should be noted that 26mm*33mm is a special example, and in fact the original pattern units are generally slightly smaller than 26mm*33mm, such as 25mm*32mm, etc.

[0082] Optionally, before step S101, the method for implementing multi-chip high-density connection lithography technology according to the embodiment of the present application can further include the following step: preliminarily position the substrate through its own features or a primary alignment device (attached Figure 2 , attached Figure 7 , and attached Figure 7 510) on the substrate.

[0083] The substrate has first alignment marks (such as attached Figure 6The alignment marks 520 shown can be laser stepping alignment marks (LSA) and / or field image alignment marks (FIA), or alignment marks designed for the alignment system of the lithography apparatus involved in the present application. One or more first alignment marks can be provided on the substrate, which can be provided in the scribe lanes to avoid affecting the functional area of the chip.

[0084] Specifically, before starting the lithography, the substrate to be exposed is transferred from the carrier to the stage of the lithography apparatus by a mechanical arm or a vacuum suction system, at this time, the substrate is roughly placed at a certain position on the stage; then, the substrate is scanned by a high-resolution camera or other sensors installed on the lithography apparatus, preliminary alignment is performed by the primary alignment device 510 or the shape features of the substrate itself, and then accurate alignment of the substrate is performed by one or more first alignment marks, and preparation work before exposure is performed.

[0085] Step S102: For the first Mx1 chip group in the first MxN chip group on the substrate, a first mask plate is selected, the first mask plate is aligned with the first original pattern unit in the first Mx1 chip group by the second alignment mark on the substrate, the substrate or the first mask plate is offset by a preset offset distance, exposure is performed, and a preset pattern on the first mask plate is transferred to a first exposure area on the substrate; the first exposure area covers the scribe lane between the M original pattern units in the first Mx1 chip group and at least part of the pattern area of each of the M original pattern units.

[0086] This step is used to align the first original pattern unit in the first Mx1 chip group in the first MxN chip group on the substrate with the first mask plate after the substrate is preliminarily positioned, and accurately transfer the pattern of the first mask plate to the intended exposure area.

[0087] The MxN chip group refers to a chip area on the substrate which contains M original pattern units in the vertical direction and N original pattern units in the horizontal direction, where M and N are both integers greater than or equal to 1, M and N can be one of 1, 2, 3, etc., M and N can be the same or different, but at least one of them is greater than or equal to 2, and the specific values of M and N are not limited in the present application. For example, if four chips arranged in a 2x2 matrix (i.e., two chips distributed in the horizontal direction and two chips distributed in the vertical direction) are interconnected, M can be selected as 2 and N can be selected as 2; for example, if six chips arranged in a 2x3 matrix (i.e., two chips distributed in the horizontal direction and three chips distributed in the vertical direction) are interconnected, M can be selected as 2 and N can be selected as 3.

[0088] It should be noted that the substrate can include a plurality of M×N chip groups, each of which includes original graphic units arranged in the form of an M×N matrix. Each M×N chip group includes an M×1 chip group arranged in N columns in the vertical direction and a 1×N chip group arranged in M rows in the horizontal direction.

[0089] As shown in Figure 6 FIG. 1 is a schematic diagram of an example of an M×N chip group on a substrate in a method for implementing a lithography technology for multi-chip high-density connection provided by an embodiment of the present application, the substrate including a plurality of 2×3 chip groups arranged in the form of a 2-row 3-column matrix, namely, 2×3 chip group 101, 2×3 chip group 102, 2×3 chip group 103, 2×3 chip group 104, 2×3 chip group 105, 2×3 chip group 106, 2×3 chip group 107, and 2×3 chip group 108. It should be understood that Figure 7 FIG. 1 is an example in which M is 2 and N is 3, and is not intended to limit the present application.

[0090] It should be noted that the colored exposure regions in the drawings provided by the present application are used for clearer color distinction, and are not intended to limit the present application.

[0091] In the specific embodiment, the first M×N chip group can be any one of the plurality of M×N chip groups included on the substrate. As shown in Figure 7 FIG. 2 is a schematic diagram of an example of a first M×N chip group in a method for implementing a lithography technology for multi-chip high-density connection provided by an embodiment of the present application, the first M×N chip group including original graphic unit 610, original graphic unit 620, original graphic unit 630, and original graphic unit 640; the first original graphic unit can be original graphic unit 610, or original graphic unit 620, or original graphic unit 630, or original graphic unit 640. It should be understood that Figure 7 FIG. 2 is an example in which M is 2 and N is 2.

[0092] The first M×1 chip group can be any one of the N M×1 chip groups included in the first M×N chip group. Generally, the first original graphic unit is the uppermost or lowermost original graphic unit in the first M×1 chip group.

[0093] The substrate has a second alignment mark (as shown in Figure 8The second alignment marks can be laser stepping alignment marks (LSA) and / or field image alignment marks (FIA), or alignment marks designed for the lithography apparatus alignment system involved in the present application, similar to the first alignment marks. One or more second alignment marks can be provided on the substrate, and the second alignment marks can be provided in the scribe lanes to avoid affecting the functional areas of the chips.

[0094] Specifically, the substrate is controlled to move by the stage control, and the area to be exposed of the substrate is sent to under the projection system, and the first mask is accurately aligned with the first original pattern unit of the first Mxl chip group in the first MxN chip group by the one or more second alignment marks on the substrate.

[0095] It should be noted that the exposure field to be formed in the present application needs to connect two or more original pattern units, and there is generally an alignment offset problem, and therefore, the offset distance needs to be set in advance, and alignment and exposure are performed according to the offset position. That is, before performing the exposure, the substrate or the mask selected to perform the exposure (the first mask in step S102, and the second mask in the subsequent step S103) is offset by a preset offset distance. It should be noted that the offset distance can be set in the wafer alignment offset (offset) or in the mask alignment offset (offset), or a part of the wafer and a part of the mask are set, and the purpose of setting the offset distance can be achieved.

[0096] In an alternative embodiment, in the case where the second alignment marks are the alignment marks corresponding to the original pattern units, the mask selected to perform the exposure is preset with a corresponding offset distance in the mask program, and the step of "offsetting the substrate or the mask selected to perform the exposure by a preset offset distance" can be implemented by the following steps: when the mask selected to perform the exposure is loaded onto the mask table, the mask selected to perform the exposure is offset by the preset offset distance; or the substrate is offset by the preset offset distance.

[0097] In the present embodiment, the mask selected to perform the exposure is preset with a corresponding offset distance each time. That is, the first mask selected to perform the exposure in step S102 is preset with a corresponding offset distance, and other masks selected to perform the exposure in the subsequent steps are also respectively preset with respective corresponding offset distances. The first mask and the second mask are independent masks, and the offset distances corresponding to different masks are not necessarily the same.

[0098] In one implementation, the selected mask plate for exposure can be offset by the corresponding offset distance when the mask plate is loaded onto the mask plate table. Specifically, if the selected mask plate for exposure is the first mask plate, the first mask plate is offset by the corresponding offset distance when the first mask plate is loaded onto the mask plate table; if the selected mask plate for exposure is the second mask plate in the subsequent step, the second mask plate is offset by the corresponding offset distance when the second mask plate is loaded onto the mask plate table; and so on.

[0099] In another implementation, the substrate can be offset by the preset offset distance after the selected mask plate for exposure is aligned with the corresponding original pattern unit through the second alignment mark on the substrate. Specifically, if the selected mask plate for exposure is the first mask plate, the substrate is offset by the preset offset distance after the first mask plate is aligned with the first original pattern unit of the first MxN chip set through the second alignment mark on the substrate; if the selected mask plate for exposure is the second mask plate, the substrate is offset by the preset offset distance after the second mask plate is aligned with the first original pattern unit of the first MxN chip set through the second alignment mark on the substrate; and so on.

[0100] In this way, by offsetting the selected mask plate for exposure or offsetting the substrate, the selected mask plate for exposure and the substrate can have a preset offset distance, so that the pattern on the selected mask plate for exposure can be transferred to the exposure area to be exposed.

[0101] In another optional implementation, when the second alignment mark on the substrate is an alignment mark set for the exposure to be performed, the set offset distance is 0.

[0102] In another optional implementation, when the relative positional relationship between the position of the mask pattern of the selected mask plate for exposure in the mask plate and the position of the mask pattern of the original mask plate in the original mask plate is the same as the positional relationship between the exposure area to be formed and the original pattern unit covered by the exposure area to be formed, the set offset distance is 0; wherein the original mask plate is a mask plate used to manufacture the original pattern unit.

[0103] In this embodiment, the position of the mask pattern on the mask is offset when the mask is made, and the relative positional relationship between the position of the mask pattern of the selected mask in the mask after exposure of the selected mask and the position of the mask pattern of the original mask in the original mask (which can be determined based on the position of the center of the mask pattern of the selected mask relative to the center of the selected mask, and the position of the center of the mask pattern of the original mask relative to the center of the original mask) is the same as the positional relationship between the to-be-formed exposure area and the original pattern unit covered by the to-be-formed exposure area after exposure (which can be determined based on the position of the center of the to-be-formed exposure area relative to the center of the original pattern unit covered by the to-be-formed exposure area). In this case, when the mask and the substrate are aligned subsequently, a certain offset has already been generated between them, so that no further offset is needed, that is, the set offset distance is 0.

[0104] As shown in Figure 7 , it is a schematic diagram of an example of the relative positional relationship between the original mask and the selected mask after exposure, and the positional relationship between the to-be-formed exposure area and the original pattern unit covered by the to-be-formed exposure area in the implementation method of the multi-chip high-density interconnection photolithography technology provided by the embodiment of the present application. Among them, the center of the mask pattern 203 on the original mask 201 is aligned with the set center of the original mask 201, while the center of the mask pattern 204 on the selected mask 202 after exposure is slightly lower than the set center of the mask 202 (the set center of the mask 201 and 202 adopts the same rule according to the model of the photolithography machine), which guarantees that the positional relationship between the to-be-formed exposure area 720 and the original pattern unit 620 covered by the to-be-formed exposure area 720 without offset is that the region 726 corresponding to the original pattern unit 620 of the exposure area 720 overlaps the original pattern unit 620. That is, the relative positional relationship between the mask pattern 204 and the mask pattern 203 is the same as the positional relationship between the to-be-formed exposure area 720 and the original pattern unit 620 covered by the to-be-formed exposure area 720, and at this time, the set offset distance is 0.

[0105] Thus, by using the above-mentioned methods, the first mask plate is aligned to the first exposure area of the first mask plate pattern to be transferred by alignment and offsetting a preset offset distance before exposure is performed, so that the pattern of the first mask plate can be transferred to the first exposure area after exposure is performed. The first exposure area covers the scribe lane between the M original pattern units in the first Mxl chip group and at least part of the pattern area of each original pattern unit.

[0106] For example, as shown in FIG. 6, the first mask plate pattern is transferred to the first exposure area 700 covering the scribe lane between the first original pattern unit 620 and the original pattern unit 640 and part of the first original pattern unit 620 and part of the original pattern unit 640. Figure 9 For example, as shown in FIG. 6, the first mask plate pattern is transferred to the first exposure area 700 covering the scribe lane between the first original pattern unit 620 and the original pattern unit 640 and part of the first original pattern unit 620 and part of the original pattern unit 640.

[0107] For example, as shown in FIG. 6, the first mask plate pattern is transferred to the first exposure area 700 covering the scribe lane between the first original pattern unit 620 and the original pattern unit 640 and part of the first original pattern unit 620 and part of the original pattern unit 640. Figure 10 As shown in FIG. 7, another example of the first MxN chip group in the implementation method of the multi-chip high-density connection photolithography technology provided by the present application is shown. The first MxN chip group can include the original pattern unit 610, the original pattern unit 620, the original pattern unit 630, the original pattern unit 640, the original pattern unit 650 and the original pattern unit 660. The original pattern unit 620 is the first original pattern unit. In this example, the first mask plate pattern is transferred to the first exposure area 700 covering the scribe lane between the first original pattern unit 620 and the original pattern unit 640, the scribe lane between the original pattern unit 640 and the original pattern unit 660 and part of the first original pattern unit 620, the entire original pattern unit 640 and part of the original pattern unit 660. It should be noted that although the first exposure area 700 covers the entire original pattern unit 640, in the case where the original pattern unit 620, the original pattern unit 640 and the original pattern unit 660 are consistent, part of the original pattern unit 620 and part of the original pattern unit 660 are generally selected for line processing (line processing can be referred to the detailed description of the lines in the first overlap area and the second overlap area in the subsequent embodiments) for convenience. The entire area of the original pattern unit covered by the subsequent exposure area is similar to the entire area of the original pattern unit 640 covered by the first exposure area 700, which will not be described hereinafter.

[0108] Step S103: repeat the steps of moving the substrate longitudinally by M times the longitudinal size of the original pattern unit and performing the alignment and exposure, and repeat the steps of moving the substrate transversely by 1 times the transverse size of the original pattern unit and performing the alignment, offsetting and exposure, to complete the exposure of the exposure areas corresponding to the other Mxl chip groups in the first MxN chip group and the exposure of the exposure areas corresponding to the Mxl chip groups in the other MxN chip groups on the substrate.

[0109] This step is used to form a plurality of longitudinal M interconnections between chips in the Mxl chip group on the substrate. Specifically, it is used to implement the exposure of the exposure areas corresponding to the other Mxl chip groups in the first MxN chip group by the first mask and the exposure of the exposure areas corresponding to the Mxl chip groups in the other MxN chip groups on the substrate.

[0110] It should be noted that for the first mask, since it is used for the exposure of the exposure areas corresponding to the Mxl chip group, after the exposure of the exposure area corresponding to the first Mxl chip group in the first MxN chip group is completed, when the substrate is moved longitudinally for the exposure of the exposure areas corresponding to the Mxl chip groups in the other MxN chip groups longitudinally, since the longitudinal interconnection between M chips has been completed, the substrate can be moved longitudinally by M times the longitudinal size of the original pattern unit, so that the first mask is aligned with the original pattern unit on the substrate which is separated from the first original pattern unit by M-1 original pattern units, and then the alignment and exposure steps shown in step S102 are repeatedly performed, so that the preset pattern of the first mask is transferred to the exposure area corresponding to the Mxl chip group adjacent to the first Mxl chip group longitudinally; then the steps of moving the substrate longitudinally by M times the longitudinal size of the original pattern unit and performing the alignment and exposure are repeatedly performed to complete the exposure of the exposure areas corresponding to the Mxl chip groups in the other MxN chip groups longitudinally.

[0111] When the first mask is moved transversely for the exposure of the exposure areas corresponding to the other Mxl chip groups in the first MxN chip group and the exposure of the exposure areas corresponding to the Mxl chip groups in the other MxN chip groups transversely, since a plurality of adjacent chips are not connected transversely, the substrate can be moved transversely by 1 times the transverse size of the original pattern unit, so that the first mask is aligned with the original pattern unit on the substrate which is adjacent to the first original pattern unit, and then the alignment and exposure steps shown in step S102 are repeatedly performed, so that the preset pattern of the first mask is transferred to the exposure area corresponding to the other Mxl chip groups in the first MxN chip group; then the steps of moving the substrate transversely by 1 times the longitudinal size of the original pattern unit and performing the alignment and exposure are repeatedly performed to complete the exposure of the exposure areas corresponding to the Mxl chip groups in the other MxN chip groups transversely.

[0112] It should be noted that, since the general silicon wafer is round, not all patterns meet the Mx1 structure requirement. Assuming M is 2, after stepping, the covered area, one chip pattern is complete, and the other chip pattern is not complete. If the two are exposed and connected together, the chip with the complete pattern may form a connection relationship with the chip with the incomplete pattern, resulting in the chip without function. In this case, it is necessary to skip the exposure. In this way, the function of the chip with the complete pattern can be preserved. This needs to be noted when making a photolithography program. Similar situations also exist in 1xN, which will not be described hereinafter.

[0113] It should be noted that the longitudinal size of the original pattern unit and the transverse size of the original pattern unit can be the same or different. For example, the longitudinal size of the original pattern unit is 25 mm, and the transverse size of the original pattern unit is 32 mm. For another example, the longitudinal size and the transverse size of the original pattern unit are both 25 mm.

[0114] As shown in FIG. 1, a first original pattern unit 01 and a second original pattern unit 11 are arranged on a substrate 100. The first original pattern unit 01 and the second original pattern unit 11 are arranged in a 2x1 structure. Figure 10 As shown in FIG. 2, a first mask plate 200 is used to form an exposure area 207 covering the scribe lane between the first original pattern unit 01 and the second original pattern unit 11 in the first 2x1 chip group on the substrate 100. Figure 10 The following is a detailed description of the implementation method of the multi-chip high-density interconnection photolithography technology provided by the embodiment of the present application. The following description is given by taking M as 2 as an example. Specifically, First, the first mask plate is aligned with the first original pattern unit 01, and the substrate or the first mask plate is offset by a preset offset distance of the first mask plate, so as to form the exposure area 207 covering the scribe lane between the first original pattern unit 01 and the second original pattern unit 11 in the first 2x1 chip group on the substrate 100. After the exposure of the exposure area 207 is completed, the substrate is moved longitudinally by 2 times the longitudinal size of a single said original pattern unit, and the steps of aligning the substrate with the original pattern unit 21 in the second 2x1 chip set which is longitudinally located and adjacent to the first 2x1 chip set corresponding to the first original pattern unit 01 through the second alignment mark on the substrate, and offsetting by a preset offset distance, and exposing are repeatedly performed, so as to transfer the first mask pattern to the exposure area 208 covering the scribe lane between the original pattern unit 21 and the original pattern unit 31 in the second 2x1 chip set; or the substrate is moved transversely by 1 times the transverse size of a single said original pattern unit, and the steps of aligning the substrate with the original pattern unit 02 in the third 2x1 chip set which is transversely located and adjacent to the first 2x1 chip set corresponding to the first original pattern unit 01 through the second alignment mark on the substrate, and offsetting by a preset offset distance, and exposing are repeatedly performed, so as to transfer the first mask pattern to the exposure area 209 covering the scribe lane between the original pattern unit 02 and the original pattern unit 12 in the third 2x1 chip set; After the exposure of the exposure area 208 is completed, the substrate is moved longitudinally by 2 times the longitudinal size of a single said original pattern unit, and the steps of aligning the substrate with the original pattern unit 41 in the fourth 2x1 chip set which is longitudinally located and adjacent to the second 2x1 chip set corresponding to the first original pattern unit 01 through the second alignment mark on the substrate, and offsetting by a preset offset distance, and exposing are repeatedly performed, so as to transfer the first mask pattern to the exposure area 210 covering the scribe lane between the original pattern unit 41 and the original pattern unit 51 in the fourth 2x1 chip set; or the substrate is moved transversely by 1 times the transverse size of a single said original pattern unit, and the steps of aligning the substrate with the original pattern unit 22 in the fifth 2x1 chip set which is transversely located and adjacent to the second 2x1 chip set corresponding to the first original pattern unit 01 through the second alignment mark on the substrate, and offsetting by a preset offset distance, and exposing are repeatedly performed, so as to transfer the first mask pattern to the exposure area 211 covering the scribe lane between the original pattern unit 22 and the original pattern unit 32 in the fifth 2x1 chip set; After the exposure of the exposure area 209 is completed, the substrate is moved transversely by 1 times the transverse size of a single said original pattern unit, and the steps of aligning the substrate with the original pattern unit 03 in the sixth 2x1 chip set which is transversely located and adjacent to the third 2x1 chip set corresponding to the first original pattern unit 01 through the second alignment mark on the substrate, and offsetting by a preset offset distance, and exposing are repeatedly performed, so as to transfer the first mask pattern to the exposure area 212 covering the scribe lane between the original pattern unit 03 and the original pattern unit 13 in the sixth 2x1 chip set; After the exposure of the exposure regions 210, 211 and 212, the steps of moving, aligning and exposing are repeated to transfer the pattern of the first mask to other 2x1 chip group corresponding exposure regions.

[0115] Thus, the interconnection between chips in the multiple Mx1 chip groups on the substrate can be realized by the first mask. Figure 11 For example, the interconnection between chips in 18 2x1 chip groups (shown by the red dashed line) on the substrate is formed.

[0116] In step S104, a second mask is selected for the first 1xN chip group in the first MxN chip group on the substrate. The second mask is aligned with the first original pattern unit in the first 1xN chip group on the substrate by the second alignment mark on the substrate. The substrate or the second mask is offset by a preset offset distance. Exposure is performed to transfer the preset pattern on the second mask to a second exposure region on the substrate. The second exposure region covers the scribe lane between the N original pattern units in the first 1xN chip group and at least part of the pattern region of each original pattern unit.

[0117] This step is used to align the first original pattern unit in the first 1xN chip group in the first MxN chip group on the substrate with the second mask, and accurately transfer the pattern of the second mask to the intended exposure region.

[0118] Similar to the first Mx1 chip group, the first 1xN chip group can be any one of the M 1xN chip groups included in the first MxN chip group. Generally, the first original pattern unit is the rightmost or leftmost original pattern unit in the first 1xN chip group.

[0119] Specifically, the substrate is moved by the stage control to send the exposure region of the substrate to the projection system, and the second mask is accurately aligned with the first original pattern unit in the first 1xN chip group in the first MxN chip group by one or more second alignment marks on the substrate. Then, the substrate or the second mask is offset by a preset offset distance of the second mask, and the exposure step is performed to transfer the preset pattern on the second mask to cover the scribe lane between the N original pattern units in the first 1xN chip group and at least part of the pattern region of each original pattern unit.

[0120] For example, the interconnection between chips in 18 2x1 chip groups (shown by the red dashed line) on the substrate is formed. Figure 11Fig. 2 shows a schematic diagram of an example of exposing an exposure region of a 1 x N chip group on the substrate using the second mask in the implementation method of the multi-chip high-density interconnection photolithography technology provided by the embodiments of the present application. Figure 12 In the example where N is 2, the 1 x N chip group includes the original pattern unit 610 and the original pattern unit 620 which are horizontally adjacent, and the exposure region 800 covering the scribe lane between the original pattern unit 610 and the original pattern unit 620 and the partial region of the original pattern unit 610 and the partial region of the original pattern unit 620 is formed on the substrate after the second mask is aligned with the original pattern unit 610 and is offset.

[0121] As shown in Fig. 3, the exposure region 800 covers the scribe lane between the original pattern unit 610 and the original pattern unit 620 and the partial region of the original pattern unit 610 and the partial region of the original pattern unit 620. Figure 12 Fig. 4 shows a schematic diagram of another example of exposing an exposure region of a 1 x N chip group on the substrate using the second mask in the implementation method of the multi-chip high-density interconnection photolithography technology provided by the embodiments of the present application. Figure 13 In the example where N is 3, the 1 x N chip group includes the original pattern unit 600, the original pattern unit 610 and the original pattern unit 620 which are horizontally adjacent, and the exposure region 800 covering the scribe lane between the original pattern unit 600 and the original pattern unit 610, the scribe lane between the original pattern unit 610 and the original pattern unit 620 and the partial region of the original pattern unit 600, the whole region of the original pattern unit 610 and the partial region of the original pattern unit 620 is formed on the substrate after the second mask is aligned with the original pattern unit 600 and is offset.

[0122] Step S105: repeating the steps of moving the substrate horizontally by N times the horizontal size of the original pattern unit and performing the alignment and exposure, and repeating the steps of moving the substrate vertically by 1 times the vertical size of the original pattern unit and performing the alignment, offsetting and exposure, to complete the exposure of the exposure regions corresponding to other 1 x N chip groups in the first M x N chip group and the exposure of the exposure regions corresponding to each 1 x N chip group in other M x N chip groups on the substrate.

[0123] This step is used to form a plurality of 1 x N chip groups of horizontal N interconnections on the substrate. Specifically, it is used to implement the exposure of the exposure regions corresponding to other 1 x N chip groups in the first M x N chip group and the exposure of the exposure regions corresponding to each 1 x N chip group in other M x N chip groups on the substrate using the second mask.

[0124] It should be noted that, for the second mask, since it is applied to the exposure of the exposure area corresponding to the 1 × N chip group, after the exposure of the exposure area corresponding to the first 1 × N chip group in the first M × N chip group is completed, the first mask is moved laterally to perform the exposure of the exposure area corresponding to the 1 × N chip group in the other M × N chip group in the lateral direction. Since the interconnection of N chips in the lateral direction has been completed, the substrate can be moved laterally by N times the lateral size of the original graphic unit, so that the first mask is aligned with the original graphic unit on the substrate which is separated from the first original graphic unit by N-1 original graphic units, and then the alignment and exposure steps shown in step S104 are repeatedly performed, so that the preset pattern of the first mask is transferred to the exposure area corresponding to the 1 × N chip group adjacent to the first 1 × N chip group in the lateral direction. Then, the steps of moving the substrate laterally by N times the lateral size of the original graphic unit and performing the alignment and exposure are repeatedly performed to complete the exposure of the exposure area corresponding to the 1 × N chip group in the other M × N chip group in the lateral direction.

[0125] When the second mask is moved longitudinally to perform the exposure of the exposure area corresponding to the other 1 × N chip group in the first M × N chip group and the exposure area corresponding to each 1 × N chip group in the other M × N chip group in the longitudinal direction, since multiple adjacent chips are not connected in the longitudinal direction, the substrate can be moved longitudinally by 1 times the longitudinal size of the original graphic unit, so that the second mask is aligned with the original graphic unit on the substrate which is adjacent to the first original graphic unit. After that, the alignment and exposure steps shown in step S102 are repeatedly performed, so that the preset pattern of the second mask is transferred to the exposure area corresponding to the other 1 × N chip group in the first M × N chip group. Then, the steps of moving the substrate longitudinally by 1 times the longitudinal size of the original graphic unit and performing the alignment and exposure are repeatedly performed to complete the exposure of the exposure area corresponding to the 1 × N chip group in the other M × N chip group in the lateral direction.

[0126] As shown in Figure 13 Fig. 5 is a schematic view of an example of using the second mask to form the exposure area of the 1 × N chip group on the substrate in the implementation method of the multi-chip high-density interconnection photolithography technology provided by the embodiments of the present application, Figure 13 Here, M is taken as 2 and N is taken as 3 for introduction. Specifically: First, the second mask is aligned with the first original graphic unit 01, and the substrate or the second mask is offset by a preset offset distance, so as to form the exposure area 213 covering the scribe lane between the first original graphic unit 01 and the original graphic unit 02 in the first 1 × 3 chip group and the scribe lane between the original graphic unit 02 and the original graphic unit 03 on the substrate; After the exposure of the exposure area 213 is completed, the substrate is moved laterally by 3 times the lateral size of a single said original pattern unit, and the steps of aligning the substrate with the original pattern unit 04 in the second 1x3 chip set which is located longitudinally to the first 1x3 chip set and adjacent to the first 1x3 chip set and corresponding to the first original pattern unit 01, and offsetting by a preset offset distance, and exposing, through the second alignment mark on the substrate, are repeatedly performed, so as to transfer the second mask pattern to the exposure area 214 covering the scribe lane between the original pattern unit 04 and the original pattern unit 05 in the second 1x3 chip set, and the scribe lane between the original pattern unit 05 and the original pattern unit 06; or the substrate is moved longitudinally by 1 times the longitudinal size of a single said original pattern unit, and the steps of aligning the substrate with the original pattern unit 11 in the third 1x3 chip set which is located longitudinally to the first 1x3 chip set and adjacent to the first 1x3 chip set and corresponding to the first original pattern unit 01, and offsetting by a preset offset distance, and exposing, through the second alignment mark on the substrate, are repeatedly performed, so as to transfer the second mask pattern to the exposure area 215 covering the scribe lane between the original pattern unit 11 and the original pattern unit 12 in the third 1x3 chip set, and the scribe lane between the original pattern unit 12 and the original pattern unit 13.

[0127] After the exposure of the exposure area 215 is completed, the substrate is moved laterally by 3 times the lateral size of a single said original pattern unit, and the steps of aligning the substrate with the original pattern unit 14 in the fourth 1x3 chip set which is located longitudinally to the third 1x3 chip set and adjacent to the third 1x3 chip set and corresponding to the first original pattern unit 01, and offsetting by a preset offset distance, and exposing, through the second alignment mark on the substrate, are repeatedly performed, so as to transfer the second mask pattern to the exposure area 216 covering the scribe lane between the original pattern unit 14 and the original pattern unit 15 in the fourth 1x3 chip set, and the scribe lane between the original pattern unit 15 and the original pattern unit 16; or the substrate is moved longitudinally by 1 times the longitudinal size of a single said original pattern unit, and the steps of aligning the substrate with the original pattern unit 21 in the fifth 1x3 chip set which is located longitudinally to the third 1x3 chip set and adjacent to the third 1x3 chip set and corresponding to the first original pattern unit 01, and offsetting by a preset offset distance, and exposing, through the second alignment mark on the substrate, are repeatedly performed, so as to transfer the second mask pattern to the exposure area 217 covering the scribe lane between the original pattern unit 21 and the original pattern unit 22 in the fifth 1x3 chip set, and the scribe lane between the original pattern unit 22 and the original pattern unit 23. After the exposure of the exposure regions 214, 216 and 217, the steps of moving horizontally 3 times the horizontal size of a single original pattern unit, aligning, offsetting by a preset offset distance and exposing are repeated to transfer the pattern of the second mask to other exposure regions corresponding to the 1x3 chip group.

[0128] Thus, the interconnection between the chips in the multiple 1xN chip groups on the substrate is achieved by the second mask. Figure 6 For example, the interconnection between the chips in the 12 2x1 chip groups (the chip groups shown by the blue dashed lines) on the substrate is formed.

[0129] Thus, the interconnection between the chips in the multiple MxN chip groups on the substrate is achieved. Please refer to the attached drawings. Figure 14 The multiple 2x3 chip groups on the substrate are formed, which are 2x3 chip group 101, 2x3 chip group 102, 2x3 chip group 103, 2x3 chip group 104, 2x3 chip group 105, 2x3 chip group 106, 2x3 chip group 107 and 2x3 chip group 108.

[0130] Thus, the interconnection between the chips in the first MxN chip group and the interconnection between the chips in the other MxN chip groups are achieved. That is, the interconnection between the chips in the multiple MxN chip groups is achieved.

[0131] In these chip groups, for any MxN chip group, any original pattern unit and the original pattern unit adjacent to it are connected by the exposure regions formed by the first mask and / or the second mask; for any MxN chip group, the interconnection line pattern on the MxN chip peripheral scribe lane that connects together does not extend into the original pattern unit and connects the original pattern unit. Thus, a complete interconnection network can be formed in the MxN chip group, and the MxN chip group outside will not be affected by the scribe, so that unnecessary lines are cut off by the scribe knife and further connected together to cause short circuit failure problems.

[0132] It should be noted that the embodiment mainly illustrates the case that M and N are 2 or 3, and in fact, the present application mainly solves the interconnection between multiple large chips, which also includes the case that one of M and N is greater than or equal to 2 and the other is 1, such as M is 1 and N is 2, or M is 2 and N is 1. For these cases, when M or N is 1, the execution steps of M or N which is 1 are skipped and not exposed, that is, M or N which is 1 does not need to perform the selection mask, movement, alignment, bias and exposure steps. For example, when M is 1, the steps related to M are directly skipped, and vice versa. That is, when M and N are both greater than or equal to 2, the interconnection of MxN chips is realized through steps S101-S105.

[0133] When M is greater than or equal to 2 and N is 1, steps S104 and S105 are cancelled, and only steps S101-S103 are executed to realize the interconnection of MxN chips.

[0134] When N is greater than or equal to 2 and M is 1, steps S102 and S103 are cancelled, and only steps S101, S104 and S105 are executed to realize the interconnection of MxN chips.

[0135] In addition, M and N are selected to be 2 or 3, which is mainly determined by actual demand, and on the other hand, it is determined by the size of the exposure field. If the original pattern size is close to 26mmx33mm, the maximum exposure size of all conventional photolithography machines is about 26mmx33mm, and if the original pattern size is much smaller than 26mmx33mm, such as 20mmx25mm, it is easy to cover 3 original pattern parts and / or the entire original pattern using a conventional 26mmx33mm exposure field photolithography machine. Even if the original pattern is smaller, such as 20mmx15mm, more chips can be covered. Or in the case of not pursuing smaller line size, a larger exposure field photolithography machine, such as a 50mmx50mm exposure field photolithography machine, can also cover more chips. Here, it is not repeated one by one.

[0136] Optionally, the original pattern unit of the substrate to be exposed can also include a target pattern unit, which is a pattern unit that cannot form an MxN chip group interconnection. For example, Figure 15Fig. 1 is a schematic diagram of an example of a target pattern unit in a method for implementing a multi-chip high-density interconnection photolithography technology provided by embodiments of the present application. After the inter-chip interconnection of a plurality of 2x3 chip groups is completed, the substrate further includes a plurality of target pattern units, i1, i2, i3, i4, i5, i6, …, 0j, 1j, 2j, 3j, 4j, 5j, 6j, 7j, …, ij. To avoid waste, as described above, for cases where an MxN structure cannot be formed, these structures can be skipped when the photolithography program is made. Since the present application mainly connects existing functional integrated circuits, the functions thereof can be retained to achieve the functions of a single chip.

[0137] It should be noted that the sizes of the MxN chip groups and the target pattern units formed on the substrate by the present method are different, and the step distance of the dicing tool needs to be set to match the sizes. If necessary, the target pattern units need to be diced again (small pieces with multiple target pattern units are further diced).

[0138] In an alternative embodiment, the stage is one or two. When the stage is two, each of the stages is loaded with a substrate to be exposed.

[0139] When the stage is two, the plurality of stages can be controlled to move to the projection system in turn to complete exposure. During the alignment and exposure performed by the first stage, the second stage can be controlled to perform the steps of wafer loading and unloading and pre-alignment.

[0140] By moving to the projection system in turn to complete exposure, on the one hand, during the exposure performed by one stage, the other stage can perform other preparation work, such as loading of the substrate, preliminary alignment of the substrate, and the like. In an example, the plurality of stages includes a first stage and a second stage, and during the exposure performed by the first stage, the second stage can be controlled to perform the steps of wafer loading and unloading and pre-alignment. Here, the pre-alignment refers to preliminary alignment by the alignment marks on the substrate to be exposed loaded on the second stage.

[0141] For example, the photolithography machine includes a stage a and a stage b. During the alignment and exposure performed by the stage a, the stage b is controlled to perform the steps of wafer loading and unloading and pre-alignment. Correspondingly, during the alignment and exposure performed by the stage b, the stage a is controlled to perform the steps of wafer loading and unloading and pre-alignment. In this way, after the exposure performed by the first stage is completed, the exposure performed by the second stage can be started immediately, effectively reducing the time during which the photolithography machine is idle. On the other hand, the time consumed by the switching between the stages is shorter than the time consumed by the substrate replacement and preliminary alignment performed by a single stage, and almost seamless work flow can be achieved, thereby improving the photolithography efficiency.

[0142] In the embodiments of the present application, the top layer pattern material of each exposure region and the original graphic unit can be on the same layer material, and the same layer material is photoresist. In this way, on the one hand, one layer of metal layer and the corresponding process steps can be saved, and the connection between the original graphic units can be directly connected by metal lines without necessarily passing through hole connection. At the same time, in this case, each exposure region and the original graphic unit covered by the exposure region have an overlapping region. Each exposure region and the original graphic unit covered by the exposure region are connected through the overlapping region.

[0143] The overlapping region includes at least a first overlapping area in the exposure region and a second overlapping area in the top layer pattern of the original graphic unit. The first overlapping area can include a first line, a second line and a third line, and the second overlapping area can include a fourth line, a fifth line and a sixth line; the first line and the third line are connected, and the second line and the third line are connected; the fourth line and the sixth line are connected, and the sixth line and the fifth line are connected.

[0144] The first line is a line in the first overlapping area for connecting the first overlapping area and the second overlapping area; the fourth line is a line in the second overlapping area for connecting the first overlapping area and the second overlapping area; the second line is a line formed in the first overlapping area after the fourth line is expanded and contracted; the third line is a line in the first overlapping area for strengthening the connection between the first overlapping area and the second overlapping area; the fifth line is a line formed in the second overlapping area after the first line is expanded and contracted; and the sixth line is a line in the second overlapping area for strengthening the connection between the first overlapping area and the second overlapping area.

[0145] It should be noted that the first line, the second line, the third line, the fourth line, the fifth line and the sixth line here refer to a patterned structure formed on the surface of the substrate by a photoetching process. Taking a metal conductor as an example, the first line, the second line, the third line, the fourth line, the fifth line and the sixth line refer to the part that is not dissolved by the developer, that is, the first line, the second line, the third line, the fourth line, the fifth line and the sixth line are the part of the photoresist reserved, which represents part of the layout of the future circuit, and does not form a real conductive path. The conductive line (such as copper line) actually used for transmitting current is formed by subsequent processes.

[0146] When the photoresist used is positive photoresist, the part exposed to light will change chemically during the exposure process, so that these parts become more easily dissolved in the developer, that is, the photoresist in the exposed area is removed, and the unexposed area remains; when the photoresist used is negative photoresist, the part exposed to light will cross-link and solidify during the exposure process, and become more difficult to dissolve in the developer, that is, the unexposed part of the photoresist is removed by the developer, and the exposed part of the photoresist remains on the wafer.

[0147] In the embodiment of the present application, when the photoresist used is positive photoresist, the mask lines of the first line, the second line, the third line, the fourth line, the fifth line and the sixth line on the corresponding mask are all designed as non-transparent (Dark); when the photoresist used is negative photoresist, the mask lines of the first line, the second line, the third line, the fourth line, the fifth line and the sixth line on the corresponding mask are all designed as transparent (Clear). The actual situation is related to the positive photoresist and the negative photoresist, and is also related to the actual use. The embodiment mainly takes the metal wire as an example and the positive photoresist case, and other cases will not be described one by one.

[0148] The above first line to sixth line will be introduced below Figure 16 and Figure 15 The above first line to sixth line will be introduced below As shown in Figure 12 , it is a schematic diagram of an example of the first line, the second line and the third line in the implementation method of the multi-chip high-density interconnection photoetching technology provided by the present application. The area of the first overlap region in the overlap area is the area enclosed by the boundary (physical boundary or set boundary) 2036 of the exposure area to which the first overlap region belongs and the line 20351 corresponding to the boundary 2035 of the top layer pattern of the original pattern unit in the second overlap region in the first overlap region. The first overlap region includes the first line 2021, the second line 2022 and the third line 2034, and the second line 2022 is the line formed after the fourth line 2011 included in the second overlap region is expanded and contracted. The physical boundary is the real exposure field boundary. As shown in Figure 11 , if the set boundary covers the whole area of the original pattern unit 610, in order to realize the connection between the original pattern unit 610 and the original pattern unit 600 and the original pattern unit 610 and the original pattern unit 620, the exposure area 800 needs to be set with overlap region boundaries near the original pattern unit 600 side and the original pattern unit 620 side, and the set overlap region boundaries are the set boundaries. Through the set boundaries, the patterns on the 620 side of 610, 620 and 800 achieve the overlap effect similar to that shown in Figure 16 . In this embodiment, the exposure area 800 usually does not place patterns in the area between the two set boundaries, that is, it is not transparent. The following description of the boundaries is similar to this, and will not be described one by one.

[0149] As shown in Figure 17 Fig. 6 is a schematic view of an example of the fourth line, the fifth line and the sixth line in the implementation method of the multi-chip high-density interconnection photolithography technology provided by the embodiment of the present application. The area of the second overlap region in the overlapping area is the area enclosed by the boundary 2035 of the second overlap region and the line 20361 corresponding to the boundary 2036 of the first overlap region in the second overlap region. The second overlap region includes the fourth line 2011, the fifth line 2012 and the sixth line 2033. The fifth line 2012 is the line formed after the first line 2021 included in the first overlap region is expanded and contracted.

[0150] It can be seen that the second line has an expansion and contraction amount relative to the fourth line, and the fifth line has an expansion and contraction amount relative to the first line, that is, the width of the second line is greater than the width of the fourth line, and the width of the fifth line is greater than the width of the first line. In this way, when the first overlap region and the second overlap region are misaligned, the second line will not damage the fourth line, and the fifth line will not damage the first line, thereby avoiding the problem that the first overlap region and the second overlap region cannot be interconnected when the first overlap region and the second overlap region are misaligned.

[0151] It should be noted that the expansion and contraction amount of the second line relative to the fourth line is greater than or equal to a preset alignment deviation limit value between the first overlap region and the second overlap region, and the expansion and contraction amount of the fifth line relative to the first line is greater than or equal to the alignment deviation limit value.

[0152] For example, the expansion and contraction amount of the second line relative to the fourth line and the expansion and contraction amount of the fifth line relative to the first line can be 1.1 times, 1.2 times or 1.5 times of the preset alignment deviation limit value between the first overlap region and the second overlap region.

[0153] As shown in Figure 17 Fig. 7 is a schematic view of an example in which the first overlap region and the second overlap region overlap in the implementation method of the multi-chip high-density interconnection photolithography technology provided by the embodiment of the present application, Figure 15including 17-a and 17-b. Among them, 17-a is a schematic diagram when the first overlapping area and the second overlapping area are completely aligned, 17-b is a schematic diagram when the first overlapping area and the second overlapping area are misaligned, figure 203334-1 is the mutual overlapping part of the third line and the sixth line when the first overlapping area and the second overlapping area are aligned, figure 203334-2 is the mutual overlapping part of the third line and the sixth line when the first overlapping area and the second overlapping area are misaligned, it can be seen that the size (width) of figure 203334-2 is smaller than that of figure 203334-1. If the fifth line 2012 is not stretched and contracted, and only the original width of the first line 2021 is maintained, then when the first overlapping area and the second overlapping area are misaligned, the first line 2021 will appear in the area outside the fifth line 2012, resulting in the destruction of the first line 2021 in the first overlapping area. Correspondingly, if the second line 2022 is not stretched and contracted, and only the original width of the fourth line 2011 is maintained, then when the first overlapping area and the second overlapping area are misaligned, the fourth line 2011 will appear in the area outside the second line 2022, resulting in the destruction of the fourth line 2011 in the second overlapping area. By stretching and contracting the second line 2022 and the fifth line 2012, even in the case of misalignment, the fifth line 2012 still has enough unexposed photoresist, so as to ensure that the first line 2021 is within the coverage range of the fifth line 2012, and correspondingly, the second line 2022 also has enough unexposed photoresist, so as to ensure that the fourth line 2011 is also within the coverage range of the second line 2022, avoiding the risk of destroying the line in the other exposed area.

[0154] In this embodiment, the second line is set as a line with a stretching and contracting amount relative to the fourth line, and the fifth line is set as a line with a stretching and contracting amount relative to the first line, which can avoid the destruction of the line connecting the first overlapping area and the second overlapping area in the case of misalignment of the first overlapping area and the second overlapping area.

[0155] It should be noted that the second line is in the overlapping area and does not exceed the boundary of the first overlapping area in the overlapping area, and the fifth line is in the overlapping area and does not exceed the boundary of the second overlapping area in the overlapping area. The first line is in the overlapping area and does not exceed the boundary of the second overlapping area in the overlapping area, and the fourth line is in the overlapping area and does not exceed the boundary of the first overlapping area in the overlapping area. Figure 16 and Figure 18For example, the second line 2022 does not extend beyond the boundary 2036 of the first overlapping region within the overlapping area, and the fifth line 2012 does not extend beyond the boundary 2035 of the second overlapping region within the overlapping area. That is, in an area 20101 outside the boundary 2036 of the first overlapping region within the overlapping area, the line pattern of the first overlapping region does not exist, and the area 20101 is opaque; and in an area 20201 outside the boundary 2035 of the second overlapping region within the overlapping area, the line pattern of the second overlapping region does not exist, and the area 20201 is opaque.

[0156] In this way, the patterns generated by exposure of the first overlapping area and the second overlapping area are all within their respective boundaries, and the areas outside the boundaries are opaque areas, which will not damage the patterns generated by exposure.

[0157] In an optional embodiment, the first overlapping area includes multiple first lines, multiple second lines and multiple third lines; there is a first interval between each adjacent two first lines, a second interval between each adjacent two second lines, and a third interval between each adjacent two third lines.

[0158] The second overlapping area includes a plurality of fourth lines, a plurality of fifth lines and a plurality of sixth lines; there is a fourth interval between each adjacent two fourth lines, a fifth interval between each adjacent two fifth lines, and a sixth interval between each adjacent two sixth lines.

[0159] like Figure 18 2 is a schematic diagram illustrating an example of a first overlap region including multiple groups of lines and a second overlap region including multiple groups of lines in an implementation of the multi-chip high-density interconnect lithography technology provided by an embodiment of the present application. The first overlap region includes multiple first lines, namely, first line 20211, first line 20212, and first line 20213; multiple second lines, namely, second line 20221, second line 20222, and second line 20223; and multiple third lines, namely, third line 20341, third line 20342, and third line 20343. The second overlap region includes multiple fourth lines, namely, fourth line 20111, fourth line 20112, and fourth line 20113; multiple fifth lines, namely, fifth line 20121, fifth line 20122, and fifth line 20123; and multiple sixth lines, namely, sixth line 20331, sixth line 20332, and sixth line 20333.

[0160] The first interval is between every two adjacent first lines, the second interval is between every two adjacent second lines, and the third interval is between every two adjacent third lines. Figure 18 For example, the first intervals are 20161 and 20162, the second intervals are 20181 and 20182, and the third intervals are 20181 and 20182, respectively, because the second lines and the third lines in FIG. 2B have the same size. Figure 18 For example, the fourth intervals are 20151 and 20152, the fifth intervals are 20171 and 20172, and the sixth intervals are 20171 and 20172, respectively, because the fifth lines and the sixth lines in FIG. 2D have the same size.

[0161] The fourth interval is between every two adjacent fourth lines, the fifth interval is between every two adjacent fifth lines, and the sixth interval is between every two adjacent sixth lines. Figure 18 For example, the fourth intervals are 20151 and 20152, the fifth intervals are 20171 and 20172, and the sixth intervals are 20171 and 20172, respectively, because the fifth lines and the sixth lines in FIG. 2D have the same size. Figure 19 For example, the fourth intervals are 20151 and 20152, the fifth intervals are 20171 and 20172, and the sixth intervals are 20171 and 20172, respectively, because the fifth lines and the sixth lines in FIG. 2D have the same size.

[0162] The interval area 2018 and the interval area 2017 are light-transmitting areas, that is, the mask area corresponding to the interval area 2018 and the interval area 2017 is designed as a light-transmitting area on the mask to enable the light source to pass through the area. However, in the dry etching process, the etching rate difference phenomenon caused by the different pattern densities of the etched structure, that is, in the high-density pattern area (such as dense lines or through holes), the gas reactant is easily “consumed”, resulting in a decrease in the local reaction rate, while in the low-density area (such as isolated features), the reactant is more likely to reach the surface, and the etching rate is faster, which will make the high-density area etch slowly and the low-density area etch quickly, resulting in inconsistent minimum critical dimensions, affecting device performance and consistency. In order to avoid the above phenomenon, the interval area 2018 and the interval area 2017 can also be subjected to pattern filling treatment, that is, virtual patterns that do not affect the function are added in the interval area 2018 and the interval area 2017, thereby improving the overall pattern density of the interval area 2018 and the interval area 2017 and reducing the influence of the micro-loading effect. It should be noted that, due to the problem of twice exposure, the pattern filling of the overlapping area also needs to be paid attention to prevent the problem of adverse effects (such as the problem of falling off of fine lines (such as lines smaller than the minimum lithography resolution) after development) after overlapping (especially reasonable offset exposure) When the first overlapping area and the second overlapping area overlap in the longitudinal direction, the first interval is a lateral interval, and the second interval and the third interval are longitudinal intervals. When the first overlapping area and the second overlapping area overlap in the lateral direction, the first interval is a longitudinal interval, and the second interval and the third interval are lateral intervals.

[0163] When the first overlap region and the second overlap region overlap in the longitudinal direction, the fourth interval is an interval in the transverse direction, and the fifth interval and the sixth interval are intervals in the longitudinal direction. When the first overlap region and the second overlap region overlap in the transverse direction, the fourth interval is an interval in the longitudinal direction, and the fifth interval and the sixth interval are intervals in the transverse direction.

[0164] The first interval is greater than or equal to a minimum critical dimension of the lithographic apparatus. The fourth interval is greater than or equal to a minimum critical dimension of the lithographic apparatus.

[0165] When the size of the second line is greater than or equal to the size of the third line, the second interval is greater than or equal to a target value, which is a maximum of a minimum critical dimension of the lithographic apparatus and an alignment deviation limit value between the first overlap region and the second overlap region. When the size of the second line is less than the size of the third line, the third interval is greater than or equal to a target value.

[0166] When the size of the fifth line is greater than or equal to the size of the sixth line, the fifth interval is greater than or equal to a target value. When the size of the fifth line is less than the size of the sixth line, the sixth interval is greater than or equal to a target value.

[0167] In this way, the influence of misalignment can be prevented. On the one hand, the third lines 2034 of the first overlap region and the sixth lines 2033 of the second overlap region can be made thicker and / or longer. When made thicker, if the interval between the second lines is still greater than the target value and the interval between the fifth lines is greater than the target value, the interval between the third lines will become smaller. When the misalignment between the first overlap region and the second overlap region is close to the alignment deviation limit, the third lines 2034 of the first overlap region and the sixth lines 2033 of the second overlap region can have an unintended overlap, resulting in an extra overlap pattern.

[0168] In order to make full use of the overlap region, more lines can be included in the overlap region. Specifically, the first overlap region includes a plurality of first line sets, and the second overlap region includes a plurality of second line sets. Each of the first line sets includes a plurality of first lines, a plurality of second lines and a plurality of third lines. Each of the second line sets includes a plurality of fourth lines, a plurality of fifth lines and a plurality of sixth lines. Each of two adjacent first line sets has a first set interval. Each of two adjacent second line sets has a second set interval.

[0169] As Figure 20Fig. 1 is a schematic diagram of an example of an overlapping region including multiple line sets in an implementation of the multi-chip high-density interconnection photolithography technology provided in the embodiments of the present application. As shown, the first overlapping region includes multiple first line sets, each adjacent two of the first line sets having a first set interval, which are first set interval 20141 and first set interval 20142 respectively; the second overlapping region includes multiple second line sets, each adjacent two of the second line sets having a second set interval, which are second set interval 20241 and second set interval 20242 respectively.

[0170] When the first overlapping region and the second overlapping region overlap in the longitudinal direction, the first set interval and the second set interval are both intervals in the transverse direction. When the first overlapping region and the second overlapping region overlap in the transverse direction, the first set interval and the second set interval are both intervals in the longitudinal direction.

[0171] The first set interval and the second set interval are both greater than or equal to a target value. That is, the first set interval and the second set interval are both greater than or equal to the maximum of the minimum critical dimension of the photolithography equipment and the alignment deviation limit value between the first overlapping region and the second overlapping region.

[0172] It should be noted that there is a difference in reduction ratio between the mask layout and the actual exposure area on the substrate, and the lines, intervals, etc. need to be described for both the mask and the actual exposure area on the substrate. Based on the content of the present application, it is appropriate to consider the difference in reduction ratio between the two without further description.

[0173] It should be noted that the above overlapping region only solves the connection of one exposure area and one original pattern unit. In fact, it usually needs to solve the connection of one exposure area and two original pattern units, or the connection of multiple exposure areas and multiple original pattern units. In fact, each connection has an overlapping region, and each overlapping region has a first overlapping region of the exposure area and a second overlapping region of the top layer pattern of the original pattern unit, and the first overlapping region and the second overlapping region overlap. The processing method of the corresponding overlapping region can be processed by the above method.

[0174] In an optional implementation, the first exposure area and the second exposure area are on the same layer material or on different layer materials. The same layer material is the same layer photoresist or the same layer insulating layer (such as oxide, nitride, etc. dielectric material) or the same layer metal layer (such as aluminum, copper, etc. conductive material).

[0175] In one specific implementation, when the first exposure area and the second exposure area are on the same layer of material, the first exposure area and the second exposure area are on the same layer of photoresist; that is, the first exposure area and the second exposure area are exposure areas formed on the same layer of photoresist. When the first exposure area and the second exposure area are on the same layer of material but not on different layers of material from the top layer of the original graphic unit, in general, the line after development and etching is mainly connected with the hole of the original graphic unit and forms a connection with the original graphic unit, and only the alignment deviation between layers needs to be considered; when the first exposure area and the second exposure area are on the same layer of material and on the same layer of material as the original graphic unit, especially on the same layer of photoresist, the overlapping area needs to be processed as described above; in addition, when the first exposure area and the second exposure area are on the same layer of material and on the same layer of material as the original graphic unit, even if the same layer of material is not photoresist, such as when the first exposure area and the second exposure area are on the same metal layer as the top layer of the original graphic unit, the overlapping area still needs to be processed, and the overlapping area line processing method is similar to that when both are on the photoresist.

[0176] In the case where the first exposure area and the second exposure area will be on the same layer of photoresist, the photoetching equipment includes two mask workstations, and the two mask workstations are loaded with the first mask and the second mask, respectively.

[0177] The first exposure area and the second exposure area are generally on the same layer of material, but there are also cases where they are on different layers of material, such as installing different functional modules on the carrier plate for connection, some of which form electrical connections through the first exposure area, and some of which form optical connections through the second exposure area, and different materials may be used for processing.

[0178] The embodiment of the application provides a photolithography technology implementation method for multi-chip high-density connection, which is used for realizing the interconnection of M*N chips, and comprises the following steps: loading a to-be-exposed substrate with original pattern units to a stage of a photolithography device, and performing first alignment through a first alignment mark on the substrate; selecting a first mask plate for a first M*1 chip group in the first M*N chip group on the substrate, aligning the first mask plate with a first original pattern unit in the first M*1 chip group through a second alignment mark on the substrate, performing exposure, and transferring a preset pattern on the first mask plate to a first exposure area on the substrate; the first exposure area covers a scribe lane between M original pattern units in the first M*1 chip group and at least part of a pattern area of each of the M original pattern units; repeating the steps of moving the substrate longitudinally by M times of a longitudinal size of the original pattern unit and performing the alignment and exposure, and repeating the steps of moving the substrate transversely by 1 times of a transverse size of the original pattern unit and performing the alignment and exposure, completing exposure of exposure areas corresponding to other M*1 chip groups in the first M*N chip group and exposure of exposure areas corresponding to each M*1 chip group in other M*N chip groups on the substrate, so that the first mask plate forms interconnections between multiple M*1 chip groups on the substrate; selecting a second mask plate for a first 1*N chip group in the first M*N chip group on the substrate, aligning the second mask plate with the first original pattern unit in the first N*N chip group through the second alignment mark on the substrate, performing exposure, and transferring a preset pattern on the second mask plate to a second exposure area on the substrate; the second exposure area covers a scribe lane between N original pattern units in the first 1*N chip group and at least part of a pattern area of each of the N original pattern units; repeating the steps of moving the substrate transversely by N times of a transverse size of the original pattern unit and performing the alignment and exposure, and repeating the steps of moving the substrate longitudinally by 1 times of a longitudinal size of the original pattern unit and performing the alignment and exposure, completing exposure of exposure areas corresponding to other 1*N chip groups in the first M*N chip group and exposure of exposure areas corresponding to each 1*N chip group in other M*N chip groups on the substrate, so that the second mask plate forms interconnections between multiple 1*N chip groups on the substrate. For any M*N chip group, any original pattern unit and an original pattern unit adjacent to the original pattern unit form a connection through an exposure area formed by the first mask plate and / or the second mask plate; for any M*N chip group, the interconnection line pattern connecting the M*N chips together does not extend into the original pattern unit and connects the original pattern units on a peripheral scribe lane of the M*N chips. M and N are both integers greater than or equal to 1, and at least one of M and N is greater than or equal to 2.Thus, two masks are used to realize high-density interconnection of multiple chips without changing the size of the exposure field, thereby forming a large chip, and providing photolithography technical support for high-density interconnection integration of M×N large chips (such as multiple 26mm×33mm or 25mm×32mm chips).

[0179] In addition, in the prior art, when realizing chip interconnection, the interconnection is mainly realized by a board-level interconnection mode, which is usually realized by a circuit board after packaging. This mode has a complex structure and a large size. In use, signals need to be transmitted through a long circuit board path, which will cause high signal delay. In addition, long-distance wiring is easily affected by problems such as electromagnetic interference, which will cause signal distortion. Long lines and driving circuits will also cause large capacitive loads, which will inevitably increase power consumption. At the same time, larger line and solder pad sizes limit the interconnection density between chips on the one hand, and require larger size communication driving circuits, which further limit the interconnection density between chips. In comparison, the implementation method of the high-density interconnection photolithography technology for multiple chips provided in the present application can realize chip-level interconnection. Thus, multiple chips can be connected together during chip manufacturing. In use, due to the shortened interconnection distance, signal transmission time will be significantly reduced, and the risk of signal distortion can be reduced, signal integrity can be improved, and parasitic load can be reduced, thereby reducing power consumption. In addition, the present application directly uses the existing high-performance photolithography machine (such as a DUV photolithography machine or an EUV photolithography machine) for chip interconnection photolithography. The minimum size of the line can reach 0.1um or even several nm, which can greatly improve the interconnection line density between chips, and finally form a large chip (such as 25mm×32mm) with high-density interconnection between chips (such as M×N×25mm×32mm).

[0180] The second embodiment of the present application also provides a photolithography technology implementation method for high-density interconnection of multiple chips, which is used to realize interconnection of M×N chips, and includes the following steps S201-S207: Step S201: loading a to-be-exposed substrate with an original pattern unit to a stage of a photolithography device, and performing first alignment through a first alignment mark on the substrate; Step S202: for a first i x 1 chip group in the first M x N chip group on the substrate, a third mask is selected, the third mask is aligned with a second original pattern unit in the first i x 1 chip group through the second alignment mark on the substrate, the substrate or the third mask is offset by a preset offset distance, exposure is performed, and a preset pattern on the third mask is transferred to a third exposure area on the substrate; the third exposure area covers a scribe lane between i original pattern units in the first i x 1 chip group and at least part of a pattern area of each of the i original pattern units; Step S203: the steps of moving the substrate longitudinally by M times a longitudinal size of an original pattern unit and performing the alignment and exposure are repeated, or the steps of moving the substrate transversely by N times a transverse size of an original pattern unit and performing the alignment, offsetting and exposure are repeated, to complete exposure of exposure areas of corresponding i x 1 chip groups to the first i x 1 chip group in other M x N chip groups on the substrate; Step S204: the steps of performing exposure on corresponding i x 1 chip groups other than the first i x 1 chip group of the first M x N chip group are repeated, and the steps of moving longitudinally by M times a longitudinal size of a single original pattern unit or moving transversely by N times a transverse size of an original pattern unit are repeated, to complete exposure of corresponding areas of other i x 1 chips in other M x N chip groups on the substrate; Step S205: for a first 1 x j chip group in the first M x N chip group on the substrate, a fourth mask is selected, the fourth mask is aligned with the second original pattern unit in the first 1 x j chip group through the second alignment mark on the substrate, the substrate or the fourth mask is offset by a preset offset distance, exposure is performed, and a preset pattern on the fourth mask is transferred to a fourth exposure area on the substrate; the fourth exposure area covers a scribe lane between j original pattern units in the first 1 x j chip group and at least part of a pattern area of each of the j original pattern units; Step S206: the steps of moving the substrate longitudinally by M times a longitudinal size of an original pattern unit and performing the alignment and exposure are repeated, or the steps of moving the substrate transversely by N times a transverse size of an original pattern unit and performing the alignment, offsetting and exposure are repeated, to complete exposure of exposure areas of corresponding 1 x j chip groups to the first 1 x j chip group in other M x N chip groups on the substrate; Step S207: repeating the exposure of the corresponding 1 x j chip sets other than the first 1 x j chip set of the first M x N chip set, and repeating the longitudinal movement of the longitudinal dimension of the original graphic unit by M times or the lateral movement of the lateral dimension of the original graphic unit by N times, to complete the exposure of the corresponding regions of other 1 x j chip sets in other M x N chip sets on the substrate; Wherein, for any MxN chip group, any original pattern unit and the original pattern unit adjacent to it form a connection through the exposed area formed by the third mask and / or the fourth mask; for any MxN chip group, there is no interconnection line pattern on the peripheral scribe lane of the MxN chip which goes into the interior of the original pattern unit and connects the original pattern unit; M and N are both integers greater than or equal to 1, and at least one of M and N is greater than or equal to 2. i and j are both integers greater than or equal to 1, i≤M, j≤N, and when M is greater than or equal to 2, 2≤i, and when N is greater than or equal to 2, 2≤j. Wherein, when i or j is 1, the execution steps for i or j being 1 are skipped, and no exposure is performed, that is, i or j being 1 does not need to perform the selection mask, movement, alignment, offset and exposure steps. That is, when M and N are both greater than or equal to 2, i and j are both greater than or equal to 2, the interconnection of the MxN chips is realized through steps S201-S207. When M is greater than or equal to 2 and N is 1, i is greater than or equal to 2 and j is 1, steps S205, S206 and S207 are cancelled, and the interconnection of the MxN chips can be realized by only performing steps S201-S204. When N is greater than or equal to 2 and M is 1, i is 1 and j is greater than or equal to 2, steps S202, S203 and S204 are cancelled, and the interconnection of the MxN chips can be realized by only performing steps S201, S205-S207. The step "loading the original pattern unit existing substrate to be exposed to the stage of the lithography equipment, and performing first alignment through the first alignment mark on the substrate" in the embodiment is the same as step S101 in the first embodiment of the application, and reference can be made to the related description in the first embodiment of the application, which will not be repeated here. The difference from the first embodiment of the application is that the interconnection between the multiple i x 1 chip groups in each MxN chip group on the substrate is realized through the third mask, and the interconnection between the multiple 1 x j chip groups in each MxN chip group on the substrate is realized through the fourth mask, so as to realize the interconnection of the MxN chip group. By using such a method, as described above, if the size of the original pattern unit is close to the maximum size of the exposure field (such as about 26mm*33mm), the value of M and N has certain limitations when the method provided in the first embodiment of the application is used, and is usually not greater than 3; while the method provided in the second embodiment of the application (embodiment two) has no such limitation, and the value of M and N can be greater than 3, such as 4, 5, 6, 7, etc.

[0181] The first i x 1 chip set can be any one of the first M x N chip sets, for example, the first i x 1 chip set can be the i x 1 chip set at the upper left corner, or the i x 1 chip set at the upper right corner, or the i x 1 chip set at the lower left corner, or the i x 1 chip set at the lower right corner, or the i x 1 chip set in the middle, etc. The second original pattern unit can be any one of the pattern units in the first i x 1 chip set. Generally, the second original pattern unit can be the uppermost or the lowermost original pattern unit in the first i x 1 chip set.

[0182] In the embodiments of the present application, the substrate can be moved by the substrate stage control, and the area to be exposed of the substrate can be sent to the projection system, and the third mask plate can be accurately aligned with the second original pattern unit of the first i x 1 chip set in the first M x N chip set through one or more second alignment marks on the substrate, and the substrate or the third mask plate can be offset by a preset offset distance. In this way, before exposure is performed, the third mask plate can be aligned to the third exposure area of the pattern to be transferred of the third mask plate. The third exposure area covers the scribe lane between the i original pattern units in the first i x 1 chip set and at least part of the pattern area of each of the i original pattern units.

[0183] The accompanying drawings are incorporated into the present application to provide further understanding of the present application, which constitute a part of the present application. Figure 20 The first M x N chip set is the 3 x 3 chip set 109, the first i x 1 chip set is the chip set composed of the original pattern unit 01 and the original pattern unit 11 in the 3 x 3 chip set 109, and the second original pattern unit is the original pattern unit 01. After the third mask plate is aligned to the original pattern unit 01 and the substrate or the third mask plate is offset by a preset offset distance, exposure is performed, and the preset pattern on the third mask plate can be transferred to the exposure area 207 covering the scribe lane between the original pattern unit 01 and the original pattern unit 11, and part of the area of the original pattern unit 01 and part of the area of the original pattern unit 11.

[0184] It should be noted that for the third mask plate, since it is applied to exposure of the exposure area corresponding to the i x 1 chip set, after the exposure of the exposure area corresponding to the first i x 1 chip set in the first M x N chip set is completed by the third mask plate, the third mask plate can be moved longitudinally by M times the longitudinal size of the original pattern unit, or transversely by N times the transverse size of the original pattern unit, to complete the exposure of the exposure area corresponding to the chip set of the first i x 1 chip set in other M x N chip sets on the substrate.

[0185] The position of the chipset corresponding to the first i×1 chipset in the other M×N chipsets is the same as the position of the first i×1 chipset in the first M×N chipset. For example, if the first i×1 chipset is located in the upper left corner of the first M×N chipset, then the chipset corresponding to the first i×1 chipset in the other M×N chipsets is located in the upper left corner of the other M×N chipset; if the first i×1 chipset is located in the upper right corner of the first M×N chipset, then the chipset corresponding to the first i×1 chipset in the other M×N chipsets is located in the upper right corner of the other M×N chipset; if the first i×1 chipset is located in the lower left corner of the first M×N chipset, then the chipset corresponding to the first i×1 chipset in the other M×N chipsets is located in the lower left corner of the other M×N chipset; if the first i×1 chipset is located in the lower right corner of the first M×N chipset, then the chipset corresponding to the first i×1 chipset in the other M×N chipsets is located in the lower right corner of the other M×N chipset.

[0186] like Figure 20 , which is a schematic diagram of an example of an exposure area formed by exposing a substrate with N-fold lateral stepping and M-fold vertical stepping through a third mask in a method for realizing a multi-chip high-density connection lithography technology provided by an embodiment of the present application. Figure 21 The following is an example of M and N being 3. First, a third mask is selected to form an exposure area 207 on the substrate, covering the scribe line in the first 2×1 chip group in the first 3×3 chip group 109 (i.e., the scribe line between the original graphic unit 01 and the original graphic unit 11); After the exposure of the exposure area 207 is completed, the substrate is moved longitudinally by 3 times the longitudinal dimension of a single said original pattern unit, and the steps of aligning the substrate with the original pattern unit 31 in the 2x1 chip group (the original pattern unit 31 and the original pattern unit 41) in the second 3x3 chip group 110 corresponding to the first 2x1 chip group longitudinally and adjacent to the first 3x3 chip group 109, offsetting by a preset offset distance, and exposing through the second alignment mark on the substrate are repeatedly performed, so that the third mask pattern is transferred to the exposure area 208 covering the scribe lane between the original pattern unit 31 and the original pattern unit 41 in the second 3x3 chip group 110; or the substrate is moved laterally by 3 times the lateral dimension of a single said original pattern unit, and the steps of aligning the substrate with the original pattern unit 04 in the third 3x3 chip group 112 corresponding to the first 2x1 chip group laterally and adjacent to the first 3x3 chip group 109, offsetting by a preset offset distance, and exposing through the second alignment mark on the substrate are repeatedly performed, so that the third mask pattern is transferred to the exposure area 209 covering the scribe lane between the original pattern unit 04 and the original pattern unit 14 in the third 3x3 chip group 112; After the exposure of the exposure area 208 is completed, the substrate is moved longitudinally by 3 times the longitudinal dimension of a single said original pattern unit, and the steps of aligning the substrate with the original pattern unit 61 in the fourth 3x3 chip group 111 corresponding to the first 2x1 chip group longitudinally and adjacent to the second 3x3 chip group 110, offsetting by a preset offset distance, and exposing through the second alignment mark on the substrate are repeatedly performed, so that the third mask pattern is transferred to the exposure area 211 covering the scribe lane between the original pattern unit 61 and the original pattern unit 71 in the fourth 3x3 chip group 111; or the substrate is moved laterally by 3 times the lateral dimension of a single said original pattern unit, and the steps of aligning the substrate with the original pattern unit 34 in the fifth 3x3 chip group 113 corresponding to the first 2x1 chip group laterally and adjacent to the second 3x3 chip group 110, offsetting by a preset offset distance, and exposing through the second alignment mark on the substrate are repeatedly performed, so that the third mask pattern is transferred to the exposure area 210 covering the scribe lane between the original pattern unit 34 and the original pattern unit 44 in the fifth 3x3 chip group 113; After the exposure of exposure areas 209, 210 and 211 is completed respectively, the steps of vertically moving by 3 times the vertical size of a single original graphic unit or horizontally moving by 3 times the horizontal size of a single original graphic unit, aligning, offsetting by a preset offset distance and exposing are repeated, so as to transfer the pattern of the third mask to the exposure area of ​​the 2×1 chip group corresponding to the first 2×1 chip group in the other 3×3 chip groups.

[0187] After the third mask is used to expose the exposure area corresponding to the first i×1 chip group in the first M×N chip group and the exposure area corresponding to the i×1 chip group in the other M×N chip groups on the substrate, the third mask can be aligned, offset, and exposed with the corresponding i×1 chip groups other than the first i×1 chip group in the first M×N chip group, thereby completing the exposure of the exposure areas of the other i×1 chip groups in the first M×N chip group. Thereafter, the steps of longitudinally shifting the substrate by M times the longitudinal dimension of a single original graphic unit or transversely shifting the substrate by N times the transverse dimension of the original graphic unit, aligning, offsetting, and exposing are repeated to complete the exposure of the areas corresponding to the other i×1 chips in the other M×N chip groups on the substrate.

[0188] like Figure 22 , which is a schematic diagram of an example of an exposure area formed on a substrate by a third mask in a photolithography method for realizing multi-chip high-density connection provided by an embodiment of the present application. Specifically: First, the third mask is combined with the corresponding 2×1 chipsets (such as the 2×1 chipset consisting of the original graphics unit 02 and the original graphics unit 12, the 2×1 chipset consisting of the original graphics unit 03 and the original graphics unit 13, the 2×1 chipset consisting of the original graphics unit 11 and the original graphics unit 21, the 2×1 chipset consisting of the original graphics unit 12 and the original graphics unit 22) in the first 3×3 chipset 109 except the first 2×1 chipset (the original graphics unit 01 and the original graphics unit 11). If the third mask is aligned with the original graphic unit 02 in the 2×1 chipset consisting of the original graphic unit 02 and the original graphic unit 12, and offset by a preset offset distance and the exposure steps are performed, the third mask pattern is transferred to the exposure area 213 covering the scribe line between the original graphic unit 02 and the original graphic unit 12 in the first 3×3 chipset 109; After the exposure of the exposure area 213 is completed, the substrate is moved longitudinally by 3 times the longitudinal dimension of a single said original pattern unit, and the steps of aligning the original pattern unit 32 in the 2x1 chip set (original pattern unit 32 and original pattern unit 42) corresponding to the 2x1 chip set composed of the original pattern unit 02 and the original pattern unit 12 in the second 3x3 chip set 110 located longitudinally and adjacent to the first 3x3 chip set 109 on the substrate through the second alignment mark on the substrate, and offsetting by a preset offset distance, and exposing are repeatedly performed, so that the third mask pattern is transferred to the exposure area 215 covering the scribe lane between the original pattern unit 32 and the original pattern unit 42 in the second 3x3 chip set 110; or the substrate is moved laterally by 3 times the lateral dimension of a single said original pattern unit, and the steps of aligning the original pattern unit 05 in the 2x1 chip set (original pattern unit 05 and original pattern unit 15) corresponding to the 2x1 chip set composed of the original pattern unit 02 and the original pattern unit 12 in the third 3x3 chip set 112 located laterally and adjacent to the first 3x3 chip set 109 on the substrate through the second alignment mark on the substrate, and offsetting by a preset offset distance, and exposing are repeatedly performed, so that the third mask pattern is transferred to the exposure area 214 covering the scribe lane between the original pattern unit 05 and the original pattern unit 15 in the third 3x3 chip set 112; After the exposure of the exposure area 215 is completed, the substrate is moved longitudinally by 3 times the longitudinal size of a single original pattern unit, and the steps of aligning the original pattern unit 62 in the 2x1 chip group (the original pattern unit 62 and the original pattern unit 72) in the fourth 3x3 chip group 111 corresponding to the 2x1 chip group composed of the original pattern unit 02 and the original pattern unit 12 in the second 3x3 chip group 110 and adjacent to the second 3x3 chip group 110 on the longitudinal direction of the second 3x3 chip group 110, and offsetting by a preset offset distance, and exposing are repeatedly performed through the second alignment mark on the substrate, so that the third mask pattern is transferred to the exposure area 217 covering the scribe lane between the original pattern unit 62 and the original pattern unit 72 in the fourth 3x3 chip group 111; or the substrate is moved laterally by 3 times the lateral size of a single original pattern unit, and the steps of aligning the original pattern unit 35 in the 2x1 chip group (the original pattern unit 35 and the original pattern unit 45) in the fifth 3x3 chip group 113 corresponding to the 2x1 chip group composed of the original pattern unit 02 and the original pattern unit 12 on the lateral direction of the second 3x3 chip group 110 and adjacent to the second 3x3 chip group 110, and offsetting by a preset offset distance, and exposing are repeatedly performed through the second alignment mark on the substrate, so that the third mask pattern is transferred to the exposure area 216 covering the scribe lane between the original pattern unit 35 and the original pattern unit 45 in the fifth 3x3 chip group 113. After the exposure of the exposure areas 214, 216 and 217 is completed, the steps of moving longitudinally by 3 times the longitudinal size of a single original pattern unit or moving laterally by 3 times the lateral size of a single original pattern unit, aligning, offsetting by a preset offset distance, and exposing are repeatedly performed, so that the third mask pattern is transferred to the exposure area of the 2x1 chip group corresponding to the 2x1 chip group composed of the original pattern unit 02 and the original pattern unit 12 in the other 3x3 chip group.

[0189] …and so on, for the other corresponding 2×1 chip groups (such as the 2×1 chip group composed of original pattern unit 03 and original pattern unit 13, the 2×1 chip group composed of original pattern unit 12 and original pattern unit 22, the 2×1 chip group composed of original pattern unit 12 and original pattern unit 22, the 2×1 chip group composed of original pattern unit 13 and original pattern unit 23) in the first 3×3 chip group 109 other than the first 2×1 chip group (the original pattern unit 01 and the original pattern unit 11) and the 2×1 chip group composed of the original pattern unit 02 and the original pattern unit 12, the steps of alignment, biasing by a preset offset distance, and exposure are performed to transfer the preset pattern on the third mask to the corresponding exposure area of the other corresponding 2×1 chip group. Then, the steps of longitudinal movement by 3 times the longitudinal size of a single original pattern unit, or lateral movement by 3 times the lateral size of a single original pattern unit, alignment, biasing by a preset offset distance, and exposure are repeatedly performed to transfer the preset pattern on the third mask to the corresponding exposure area of the other 2×1 chip group on the other 3×3.

[0190] Through the above steps, the interconnection between the chips in each i×1 chip group in the M×N chip group is completed using the third mask. Then, the interconnection between the chips in each 1×j chip group in the M×N chip group can be completed using a fourth mask.

[0191] The first 1×j chip group is a 1×j chip group adjacent to the first i×1 chip group and containing a second original pattern unit in the first M×N chip group.

[0192] In the embodiments of the present application, the substrate can be moved by the stage control, and the area to be exposed of the substrate is sent to the projection system, and the fourth mask is accurately aligned with the second original pattern unit of the first 1×j chip group in the first M×N chip group through one or more second alignment marks on the substrate, and the substrate or the fourth mask is biased by a preset offset distance. In this way, before exposure, the fourth mask can be aligned to the fourth exposure area of the pattern of the fourth mask to be transferred. The fourth exposure area covers the scribe lane between the j original pattern units in the first 1×j chip group and at least part of the pattern area of each original pattern unit in the j original pattern units.

[0193] The accompanying drawings are incorporated into the present application to provide further understanding of the present application. Figure 22For example, the first M×N chipset is a 3×3 chipset 109, the first i×1 chipset is a chipset consisting of the original graphic unit 01 and the original graphic unit 02 in the 3×3 chipset 109, and the second original graphic unit is the original graphic unit 01. After the fourth mask is aligned with the original graphic unit 01 and the substrate or the fourth mask is offset by a preset offset distance and exposure is performed, the preset pattern on the fourth mask can be transferred to the exposure area 219 covering the scribe line between the original graphic unit 01 and the original graphic unit 02, as well as a portion of the original graphic unit 01 and a portion of the original graphic unit 02.

[0194] It should be noted that, for the fourth mask, since it is used for the exposure of the exposure area corresponding to the 1×j chip group, after the exposure of the exposure area corresponding to the first 1×j chip group in the first M×N chip group is completed through the fourth mask, the fourth mask can be moved longitudinally by M times the longitudinal size of the original graphic unit, or horizontally by N times the horizontal size of the original graphic unit, so as to complete the exposure of the exposure area of ​​the chip group corresponding to the first 1×j chip group in the other M×N chip groups on the substrate.

[0195] The position of the chipset corresponding to the first 1×j chipset in the other M×N chipsets is the same as the position of the first 1×j chipset in the first M×N chipset. For example, if the first 1×j chipset is located in the upper left corner of the first M×N chipset, then the chipset corresponding to the first 1×j chipset in the other M×N chipsets is located in the upper left corner of the other M×N chipsets; if the first 1×j chipset is located in the upper right corner of the first M×N chipset, then the chipset corresponding to the first 1×j chipset in the other M×N chipsets is located in the upper right corner of the other M×N chipsets; if the first 1×j chipset is located in the lower left corner of the first M×N chipset, then the chipset corresponding to the first 1×j chipset in the other M×N chipsets is located in the lower left corner of the other M×N chipsets; if the first 1×j chipset is located in the lower right corner of the first M×N chipset, then the chipset corresponding to the first 1×j chipset in the other M×N chipsets is located in the lower right corner of the other M×N chipsets.

[0196] like Figure 22 , which is a schematic diagram of an example of an exposure area formed by exposing a substrate with N-fold lateral stepping and M-fold vertical stepping through a fourth mask in the method for realizing a multi-chip high-density connection lithography technology provided by an embodiment of the present application. Figure 23 The following is an example of M and N being 3. First, a fourth mask is selected to form an exposure area 219 on the substrate, covering the scribe line within the first 1×2 chip group in the first 3×3 chip group 109 (ie, the scribe line between the original graphic unit 01 and the original graphic unit 02); After exposure of the exposure area 220, the substrate is moved longitudinally by 3 times the longitudinal dimension of a single said original pattern unit, and the steps of aligning the substrate with the original pattern unit 61 in the 1x2 chip group corresponding to the first 1x2 chip group in the fourth 3x3 chip group 111 (the original pattern unit 61 and the original pattern unit 62) located longitudinally in the second 3x3 chip group 110 and adjacent to the second 3x3 chip group 110, offsetting by a preset offset distance, and exposing are repeatedly performed through the second alignment marks on the substrate, so that the fourth mask pattern is transferred to an exposure area 223 covering the scribe lane between the original pattern unit 61 and the original pattern unit 62 in the fourth 3x3 chip group 111; or the substrate is moved laterally by 3 times the lateral dimension of a single said original pattern unit, and the steps of aligning the substrate with the original pattern unit 34 in the 1x2 chip group corresponding to the first 1x2 chip group in the fifth 3x3 chip group 113 (the original pattern unit 34 and the original pattern unit 35) located laterally in the second 3x3 chip group 110 and adjacent to the second 3x3 chip group 110, offsetting by a preset offset distance, and exposing are repeatedly performed through the second alignment marks on the substrate, so that the fourth mask pattern is transferred to an exposure area 222 covering the scribe lane between the original pattern unit 34 and the original pattern unit 35 in the fifth 3x3 chip group 113. After exposure of the exposure area 220, the substrate is moved longitudinally by 3 times the longitudinal dimension of a single said original pattern unit, and the steps of aligning the substrate with the original pattern unit 61 in the 1x2 chip group corresponding to the first 1x2 chip group in the fourth 3x3 chip group 111 (the original pattern unit 61 and the original pattern unit 62) located longitudinally in the second 3x3 chip group 110 and adjacent to the second 3x3 chip group 110, offsetting by a preset offset distance, and exposing are repeatedly performed through the second alignment marks on the substrate, so that the fourth mask pattern is transferred to an exposure area 223 covering the scribe lane between the original pattern unit 61 and the original pattern unit 62 in the fourth 3x3 chip group 111; or the substrate is moved laterally by 3 times the lateral dimension of a single said original pattern unit, and the steps of aligning the substrate with the original pattern unit 34 in the 1x2 chip group corresponding to the first 1x2 chip group in the fifth 3x3 chip group 113 (the original pattern unit 34 and the original pattern unit 35) located laterally in the second 3x3 chip group 110 and adjacent to the second 3x3 chip group 110, offsetting by a preset offset distance, and exposing are repeatedly performed through the second alignment marks on the substrate, so that the fourth mask pattern is transferred to an exposure area 222 covering the scribe lane between the original pattern unit 34 and the original pattern unit 35 in the fifth 3x3 chip group 113. After the exposure areas 221, 222 and 223 are respectively exposed, the steps of longitudinally moving 3 times the longitudinal size of a single original graphic unit or transversely moving 3 times the transverse size of a single original graphic unit, aligning, offsetting by a preset offset distance and exposing are repeated, so as to transfer the pattern of the fourth mask to the exposure area of ​​the 1×2 chip group corresponding to the first 1×2 chip group in the other 3×3 chip groups.

[0197] After the fourth mask is used to expose the exposure areas corresponding to the first 1×j chip group in the first M×N chip group and the exposure areas corresponding to the first 1×j chip group in the other M×N chip groups on the substrate, the fourth mask can be aligned, offset, and exposed with the corresponding 1×j chip groups other than the first 1×j chip group in the first M×N chip group, thereby completing the exposure of the exposure areas of the other 1×j chip groups in the first M×N chip group. Thereafter, the steps of longitudinally shifting the substrate by M times the longitudinal dimension of a single original graphic unit, or transversely shifting the substrate by N times the transverse dimension of the original graphic unit, and then aligning, offsetting, and exposing are repeated to complete the exposure of the areas corresponding to the other 1×j chips in the other M×N chip groups on the substrate.

[0198] like ​ , which is a schematic diagram of an example of an exposure area formed on a substrate by a fourth mask in a photolithography method for realizing multi-chip high-density connection provided by an embodiment of the present application. Specifically: First, the fourth mask is combined with the corresponding 1×2 chipsets (such as the 1×2 chipset consisting of the original graphics unit 02 and the original graphics unit 03, the 1×2 chipset consisting of the original graphics unit 11 and the original graphics unit 12, the 1×2 chipset consisting of the original graphics unit 12 and the original graphics unit 13, the 1×2 chipset consisting of the original graphics unit 21 and the original graphics unit 22) in the first 3×3 chipset 109 except the first 1×2 chipset (the original graphics unit 01 and the original graphics unit 02). If the fourth mask is aligned with the original pattern unit 02 in the 1×2 chipset consisting of the original pattern unit 02 and the original pattern unit 03, and is offset by a preset offset distance and the exposure steps are performed, the fourth mask pattern is transferred to the exposure area 225 covering the scribe line between the original pattern unit 02 and the original pattern unit 03 in the first 3×3 chipset 109; After the exposure of the exposure area 225 is completed, the substrate is moved longitudinally by 3 times the longitudinal dimension of a single said original pattern unit, and the steps of aligning the original pattern unit 32 in the 1x2 chip group (original pattern units 32 and 33) in the second 3x3 chip group 110 corresponding to the 1x2 chip group composed of the original pattern unit 02 and the original pattern unit 03 in the first 3x3 chip group 109, and offsetting by a preset offset distance, and exposing through the second alignment mark on the substrate are repeated, so that the fourth mask pattern is transferred to the exposure area 227 covering the scribe lane between the original pattern unit 32 and the original pattern unit 33 in the second 3x3 chip group 110; or the substrate is moved transversely by 3 times the transverse dimension of a single said original pattern unit, and the steps of aligning the original pattern unit 05 in the 1x2 chip group (original pattern units 05 and 06) in the third 3x3 chip group 112 corresponding to the 1x2 chip group composed of the original pattern unit 02 and the original pattern unit 03 in the first 3x3 chip group 109, and offsetting by a preset offset distance, and exposing through the second alignment mark on the substrate are repeated, so that the fourth mask pattern is transferred to the exposure area 226 covering the scribe lane between the original pattern unit 05 and the original pattern unit 06 in the third 3x3 chip group 112. After the exposure of the exposure area 227 is completed, the substrate is moved longitudinally by 3 times the longitudinal size of a single said original pattern unit, and the steps of aligning the original pattern unit 62 in the 1x2 chip group (original pattern unit 62 and original pattern unit 63) in the fourth 3x3 chip group 111 corresponding to the 1x2 chip group composed of the original pattern unit 02 and the original pattern unit 03 in the second 3x3 chip group 110 and moving the substrate by a preset offset distance and exposing are repeatedly performed through the second alignment mark on the substrate, so that the fourth mask pattern is transferred to the exposure area 229 covering the scribe lane between the original pattern unit 62 and the original pattern unit 63 in the fourth 3x3 chip group 111; or the substrate is moved laterally by 3 times the lateral size of a single said original pattern unit, and the steps of aligning the original pattern unit 35 in the 1x2 chip group (original pattern unit 35 and original pattern unit 36) in the fifth 3x3 chip group 113 corresponding to the 1x2 chip group composed of the original pattern unit 02 and the original pattern unit 03 and moving the substrate by a preset offset distance and exposing are repeatedly performed through the second alignment mark on the substrate, so that the fourth mask pattern is transferred to the exposure area 228 covering the scribe lane between the original pattern unit 35 and the original pattern unit 36 in the fifth 3x3 chip group 113. After the exposure of the exposure areas 226, 228 and 229 is completed, the steps of moving longitudinally by 3 times the longitudinal size of a single original pattern unit or moving laterally by 3 times the lateral size of a single original pattern unit, aligning and moving by a preset offset distance and exposing are repeatedly performed, so that the fourth mask pattern is transferred to the exposure area of the 1x2 chip group corresponding to the 1x2 chip group composed of the original pattern unit 02 and the original pattern unit 03 in the other 3x3 chip group.

[0199] …and so on, for the other corresponding 1x2 chip groups (such as the 1x2 chip group composed of the original pattern unit 11 and the original pattern unit 12, the 1x2 chip group composed of the original pattern unit 12 and the original pattern unit 13, the 1x2 chip group composed of the original pattern unit 21 and the original pattern unit 22, the 1x2 chip group composed of the original pattern unit 22 and the original pattern unit 23) in the first 3x3 chip group 109 except the first 1x2 chip group (the original pattern unit 01 and the original pattern unit 02) and the 1x2 chip group composed of the original pattern unit 02 and the original pattern unit 03, the steps of alignment, biasing by a preset offset distance and exposure are performed to transfer the preset pattern on the fourth mask to the exposure area corresponding to the other corresponding 1x2 chip groups; then, the steps of longitudinal movement by 3 times the longitudinal size of a single original pattern unit, or lateral movement by 3 times the lateral size of a single original pattern unit, and alignment and biasing by a preset offset distance and exposure are repeatedly performed to transfer the preset pattern on the fourth mask to the exposure area corresponding to the other 1x2 chip groups on the other 3x3.

[0200] Thus, the interconnection between chips in the first MxN chip group and the interconnection between chips in the other MxN chip groups is completed. That is, the interconnection between chips in the plurality of MxN chip groups is completed.

[0201] In addition, as mentioned above, the original pattern units of the substrate to be exposed can also include target pattern units which cannot form MxN chip group interconnections. To avoid waste, as mentioned above, for the case that MxN chip groups cannot be formed, these structures can be skipped when the photolithography program is made. Since the present application mainly connects the existing functional integrated circuits, the functions thereof are retained to realize the functions of a single chip, and appropriate processing is performed when the chip is diced, which will not be repeated here.

[0202] It should be noted that the lateral movement and the longitudinal movement in the first embodiment and the second embodiment of the present application do not have a prior sequence in execution. In the specific implementation, the lateral movement can be performed first and then the longitudinal movement, or the longitudinal movement can be performed first and then the lateral movement. The specific sequence can be set based on the capability of the actual photolithography machine to complete the exposure.

[0203] The third embodiment of the present application provides a chip-level chip interconnection method, comprising the following steps: providing a substrate, forming a semiconductor structure comprising at least two semiconductor chips on the substrate, each semiconductor chip has formed intra-chip interconnection, and there is no interconnection between the semiconductor chips; and performing a photolithography step to realize the interconnection between the at least two semiconductor chips by the method for realizing multi-chip high-density connection provided by the first embodiment of the present application or the method for realizing multi-chip high-density connection provided by the first embodiment of the present application. In this embodiment, 2, 3, 4, 6, 8 or 9 semiconductor chips have been fabricated on the substrate through photolithography, etching, deposition and other processes. Moreover, the internal metal layer (such as copper interconnection line) inside each semiconductor chip has formed intra-chip interconnection, but there is no interconnection between the semiconductor chips.

[0204] The at least two semiconductor chips can be arranged laterally, longitudinally, or in a matrix. For example, the substrate forms a semiconductor structure including 1x2 semiconductor chips; for another example, the substrate forms a semiconductor structure including 2x1 semiconductor chips; for still another example, the substrate forms a semiconductor structure including 2x3 semiconductor chips. Each semiconductor chip can be a single-exposure pattern region formed by a projection system exposure with a reduction ratio of 4-10 times or other reduction ratio. For example, each semiconductor chip is a single-exposure pattern region formed by a projection system exposure with a reduction ratio of 4 times; for another example, each semiconductor chip is a single-exposure pattern region formed by a projection system exposure with a reduction ratio of 5 times; for still another example, each semiconductor chip is a single-exposure pattern region formed by a projection system exposure with a reduction ratio of 8 times; for still another example, each semiconductor chip is a single-exposure pattern region formed by a projection system exposure with a reduction ratio of 10 times. Taking a reduction ratio of 5 times of the projection system as an example, the size of each semiconductor chip formed is generally at most 26 mm x 33 mm. It should be understood that the size of each semiconductor chip formed can also be less than 26 mm x 33 mm, such as 25 mm x 32 mm, etc., and the size can be less than the maximum size. The specific size of the semiconductor chip is not limited further in the present application. A single semiconductor chip can be understood as a original pattern unit in the implementation method of the multi-chip high-density interconnection photolithography technology provided in the first embodiment. In the case where the substrate is provided as described above, the photolithography step of interconnection between the at least two semiconductor chips can be implemented by the implementation method of the multi-chip high-density interconnection photolithography technology provided in the first embodiment or the implementation method of the photolithography technology for multi-chip interconnection provided in the second embodiment. It should be noted that the photolithography step of interconnection between the at least two semiconductor chips implemented by the implementation method of the multi-chip high-density interconnection photolithography technology provided in the first embodiment or the implementation method of the photolithography technology for multi-chip interconnection provided in the second embodiment can be referred to the foregoing related description of the implementation method of the multi-chip high-density interconnection photolithography technology provided in the first embodiment or the implementation method of the photolithography technology for multi-chip interconnection provided in the second embodiment, which is not described herein. It can be seen that the chip-level chip interconnection method provided in the embodiments can implement high-density interconnection of integrated circuits and provide photolithography technology support for high-density interconnection of multiple large chips.

[0205] The third embodiment of the present application further provides a manufacturing method of mask lines, comprising the following steps: manufacturing a mask first mask line, a mask second mask line and a mask third mask line on a mask; the mask first mask line and the mask third mask line are connected, and the mask second mask line and the mask third mask line are connected; wherein the mask first mask line is used to expose a first exposure area of a substrate to form the first line as described in the first embodiment of the present application; the mask second mask line is used to expose the first exposure area of the substrate to form the second line as described in the first embodiment of the present application; and the mask third mask line is used to expose the first exposure area of the substrate to form the third line as described in the first embodiment of the present application. The fourth embodiment of the present application further provides a photolithography device, comprising two mask workstations, three or four object tables, two upper and lower silicon wafer systems and two silicon wafer measurement systems. The photolithography device has been described in detail in the foregoing, and thus will not be described here.

[0206] Although the present application is disclosed with the preferred embodiments, it is not intended to limit the present application, and any person skilled in the art can make possible changes and modifications without departing from the spirit and scope of the present application. Therefore, the protection scope of the present application should be defined by the scope of the claims of the present application.

Claims

1. A method for realizing multi-chip high-density connection by photolithography technology, used to realize the interconnection of M×N chips, characterized in that: include: Loading a substrate to be exposed with existing pattern units onto a stage of a lithography apparatus, and performing a first alignment using a first alignment mark on the substrate; For a first M×1 chip group in a first M×N chip group on the substrate, selecting a first mask, aligning the first mask with a first original pattern unit in the first M×1 chip group using a second alignment mark on the substrate, offsetting the substrate or the first mask by a preset offset distance, performing exposure, and transferring the preset pattern on the first mask to a first exposure area on the substrate; The first exposure area covers the scribe lines between the M original graphic units in the first M×1 chipset and at least a portion of the graphic area of ​​each of the M original graphic units; Repeating the steps of longitudinally moving the substrate by M times the longitudinal size of the original graphic unit and performing the alignment and exposure, and repeating the steps of transversely moving the substrate by 1 times the transverse size of the original graphic unit and performing the alignment, biasing, and exposure, to complete exposure of exposure areas corresponding to other M×1 chip groups in the first M×N chip group and exposure of exposure areas corresponding to each of the other M×1 chip groups in the other M×N chip groups on the substrate; For a first 1×N chip group in a first M×N chip group on the substrate, selecting a second mask, aligning the second mask with the first original pattern unit in the first 1×N chip group using a second alignment mark on the substrate, offsetting the substrate or the second mask by a preset offset distance, performing exposure, and transferring the preset pattern on the second mask to a second exposure area on the substrate; The second exposure area covers the scribing streets between the N original pattern units in the first 1×N chip group and at least a portion of the pattern area of ​​each of the N original pattern units; Repeating the steps of laterally moving the substrate by N times the lateral size of the original graphic unit and performing the alignment and exposure, and repeating the steps of longitudinally moving the substrate by 1 times the longitudinal size of the original graphic unit and performing the alignment, biasing, and exposure, to complete exposure of exposure areas corresponding to other 1×N chip groups in the first M×N chip group and exposure of exposure areas corresponding to each 1×N chip group in other M×N chip groups on the substrate; For any M×N chipset, any original graphic unit is connected to its adjacent original graphic unit through the exposure area formed by the first mask and / or the second mask; for any M×N chipset, no interconnection line pattern that penetrates into the interior of the original graphic unit and connects the original graphic units is present on the peripheral dicing streets of the connected M×N chips; Both M and N are integers greater than or equal to 1, and at least one of M and N is greater than or equal to 2.

2. The method according to claim 1, characterized in that In a case where the second alignment mark is an alignment mark corresponding to an original pattern unit, and the substrate or the mask selected for performing the exposure is preset with a corresponding offset distance, offsetting the substrate or the first mask by the preset offset distance includes: When loading the first mask onto the mask workbench, offsetting the first mask by a preset offset distance; or The substrate is offset by a predetermined offset distance.

3. The method according to claim 1, characterized in that In a case where the second alignment mark is an alignment mark set for exposure to be performed, the set offset distance is 0.

4. The method according to claim 1, wherein When the second alignment mark is an alignment mark corresponding to an original pattern unit, and the relative positional relationship between the position of the mask pattern of the first mask in the mask and the position of the mask pattern of the original mask in the original mask is the same as the positional relationship between the exposure area to be formed, the exposure area to be formed, and the original pattern unit corresponding to the second alignment mark used, the set offset distance is 0; The original mask is the mask used to make the original graphic unit.

5. The method according to claim 1, wherein When the top graphic material of each exposure area and the original graphic unit is in the same layer of photoresist, there is an overlapping area between each exposure area and the covered original graphic unit, and each exposure area and the covered original graphic unit are connected through the overlapping area.

6. The method according to claim 5, wherein the overlapping area at least includes a first overlapping area in the exposure area and a second overlapping area of ​​the top layer pattern of the original pattern unit.

7. The method according to claim 6, characterized in that The first overlapping area includes a first line, a second line, and a third line; the second overlapping area includes a fourth line, a fifth line, and a sixth line; the first line is connected to the third line and the second line is connected to the third line; the fourth line is connected to the sixth line and the sixth line is connected to the fifth line; Among them, the first line is a line in the first overlapping area used to connect the first overlapping area and the second overlapping area; the fourth line is a line in the second overlapping area used to connect the first overlapping area and the second overlapping area; the second line is a line formed in the first overlapping area after the fourth line is expanded and shrunk; the third line is a line in the first overlapping area that strengthens the connection between the first overlapping area and the second overlapping area; the fifth line is a line formed in the second overlapping area after the first line is expanded and shrunk; the sixth line is a line in the second overlapping area that strengthens the connection between the first overlapping area and the second overlapping area.

8. The method according to claim 7, characterized in that Also includes: The expansion and contraction amount of the second line relative to the fourth line is greater than or equal to the alignment deviation limit value between the first overlapping area and the second overlapping area; Furthermore, the expansion and contraction amount of the fifth line relative to the first line is greater than or equal to the alignment deviation limit value.

9. The method according to claim 7 or claim 8, characterized in that: The second line is in the overlapping area and does not exceed the boundary of the first overlapping area in the overlapping area. The fifth line is in the overlapping area and does not exceed the boundary of the second overlapping area in the overlapping area.

10. The method according to claim 7, characterized in that Also includes: The first overlapping area includes a plurality of first lines, a plurality of second lines and a plurality of third lines; there is a first interval between each adjacent two first lines, a second interval between each adjacent two second lines, and a third interval between each adjacent two third lines.

11. The method according to claim 10, characterized in that When the first overlapping area and the second overlapping area overlap in the longitudinal direction, the first interval is a lateral interval, and the second interval and the third interval are longitudinal intervals.

12. The method according to claim 10, characterized in that When the first overlapping area and the second overlapping area overlap in the transverse direction, the first interval is a longitudinal interval, and the second interval and the third interval are transverse intervals.

13. The method according to any one of claims 10 to 12, characterized in that The first interval is greater than or equal to a minimum critical dimension of the lithographic equipment.

14. The method according to any one of claims 10 to 12, characterized in that When the size of the second line is greater than or equal to the size of the third line, the second interval is greater than or equal to a target value, which is the maximum value of the minimum critical dimension of the lithography equipment and the alignment deviation limit value between the first overlap area and the second overlap area.

15. The method according to any one of claims 10 to 12, characterized in that When the size of the second line is smaller than the size of the third line, the third interval is greater than or equal to a target value.

16. The method according to claim 13, characterized in that Also includes: The second overlapping area includes a plurality of fourth lines, a plurality of fifth lines and a plurality of sixth lines; There is a fourth interval between every two adjacent fourth lines, a fifth interval between every two adjacent fifth lines, and a sixth interval between every two adjacent sixth lines.

17. The method according to claim 16, characterized in that When the first overlapping area and the second overlapping area overlap in the longitudinal direction, the fourth interval is a lateral interval, and the fifth interval and the sixth interval are longitudinal intervals.

18. The method according to claim 16, characterized in that When the first overlapping area and the second overlapping area overlap in the transverse direction, the fourth interval is a longitudinal interval, and the fifth interval and the sixth interval are transverse intervals.

19. The method according to any one of claims 16 to 18, characterized in that The fourth interval is greater than or equal to a minimum critical dimension of the lithographic apparatus.

20. The method according to any one of claims 16 to 18, characterized in that When the size of the fifth line is greater than or equal to the size of the sixth line, the fifth interval is greater than or equal to a target value.

21. The method according to any one of claims 16 to 18, characterized in that When the size of the fifth line is smaller than the size of the sixth line, the sixth interval is greater than or equal to a target value.

22. The method according to claim 13, wherein The first overlapping area includes multiple first line sets, and the second overlapping area includes multiple second line sets; each of the first line sets includes multiple first lines, multiple second lines and multiple third lines; each of the second line sets includes multiple fourth lines, multiple fifth lines and multiple sixth lines; there is a first set interval between each adjacent two first line sets; and there is a second set interval between each adjacent two second line sets.

23. The method according to claim 22, characterized in that When the first overlapping area and the second overlapping area overlap in the longitudinal direction, the first set interval and the second set interval are both intervals in the transverse direction.

24. The method according to claim 22, characterized in that When the first overlapping area and the second overlapping area overlap in the horizontal direction, the first set interval and the second set interval are both intervals in the vertical direction.

25. The method according to any one of claims 22 to 24, characterized in that The first set interval and the second set interval are both greater than or equal to a target value.

26. A method for realizing multi-chip high-density connection by photolithography technology, used to realize the interconnection of M×N chips, characterized in that: include: Loading a substrate to be exposed with existing pattern units onto a stage of a lithography apparatus, and performing a first alignment using a first alignment mark on the substrate; For a first i×1 chip group in a first M×N chip group on the substrate, selecting a third mask, aligning the third mask with a second original pattern unit in the first i×1 chip group using a second alignment mark on the substrate, offsetting the substrate or the third mask by a preset offset distance, performing exposure, and transferring the preset pattern on the third mask to a third exposure area on the substrate; The third exposure area covers the scribe lines between the i original graphic units in the first i×1 chipset and at least a portion of the graphic area of ​​each of the i original graphic units; Repeating the steps of longitudinally moving the substrate by M times the longitudinal size of the original graphic unit and performing the alignment and exposure, or repeating the steps of transversely moving the substrate by N times the transverse size of the original graphic unit and performing the alignment, biasing, and exposure, to complete exposure of an exposure area of ​​an i×1 chip group corresponding to the first i×1 chip group among other M×N chip groups on the substrate; Repeating the exposure for corresponding i×1 chip groups other than the first i×1 chip group of the first M×N chip group, and repeatedly performing the longitudinal shift by M times the longitudinal size of a single original graphic unit, or the transverse shift by N times the transverse size of the original graphic unit, to complete the exposure of corresponding areas of other corresponding i×1 chips in other M×N chip groups on the substrate; For a first 1×j chip group in a first M×N chip group on the substrate, selecting a fourth mask, aligning the fourth mask with the second original pattern unit in the first 1×j chip group using a second alignment mark on the substrate, offsetting the substrate or the fourth mask by a preset offset distance, performing exposure, and transferring the preset pattern on the fourth mask to a fourth exposure area on the substrate; The fourth exposure area covers the scribing streets between the j original pattern units in the first 1×j chip group and at least a portion of the pattern area of ​​each of the j original pattern units; Repeating the steps of longitudinally moving the substrate by M times the longitudinal size of the original pattern unit and performing the alignment and exposure, or repeating the steps of transversely moving the substrate by N times the transverse size of the original pattern unit and performing the alignment, biasing, and exposure, to complete exposure of the exposure area of ​​the 1×j chip group corresponding to the first 1×j chip group in other M×N chip groups on the substrate; Repeating the exposure for corresponding 1×j chip groups other than the first 1×j chip group of the first M×N chip group, and repeatedly performing the longitudinal shift M times the longitudinal size of a single original graphic unit, or the transverse shift N times the transverse size of the original graphic unit, to complete the exposure of corresponding areas of other corresponding 1×j chips in other M×N chip groups on the substrate; For any M×N chipset, any original graphic unit is connected to its adjacent original graphic unit via the exposure area formed by the third mask and / or the fourth mask; for any M×N chipset, no interconnection line pattern that penetrates into the interior of the original graphic unit and connects the original graphic units is present on the peripheral dicing streets of the connected M×N chips; M and N are both integers greater than or equal to 1, and at least one of M and N is greater than or equal to 2; i and j are both integers greater than or equal to 1, i≤M, j≤N, and when M is greater than or equal to 2, 2≤i, and when N is greater than or equal to 2, 2≤j.

27. A chip-level chip interconnection method, characterized in that: include; Providing a substrate, forming a semiconductor structure including at least two semiconductor chips on the substrate, wherein each semiconductor chip has formed intra-chip interconnection, and there is no interconnection between the semiconductor chips; The photolithography step of interconnecting the at least two semiconductor chips is achieved by the photolithography technology implementation method described in any one of claims 1 to 26.

28. A method for manufacturing mask lines, characterized in that: include: Making a first mask line, a second mask line and a third mask line on the mask; The first line of the mask is connected to the third line of the mask and the second line of the mask is connected to the third line of the mask; The first line of the mask is used to expose the first overlapping area of ​​the substrate to form the first line as described in claim 7; the second line of the mask is used to expose the first overlapping area of ​​the substrate to form the second line as described in claim 7; and the third line of the mask is used to expose the first overlapping area of ​​the substrate to form the third line as described in claim 7.

29. A lithographic apparatus, characterized in that: It includes 2 mask workstations, 3 or 4 stage, 2 upper and lower silicon wafer systems and 2 silicon wafer measurement systems.

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