Methods and systems for inspecting integrated circuit layout layers

Abstract

This invention discloses a method and system for inspecting the layout layers of an integrated circuit. The method includes the following steps: obtaining a first truth table for all layers of the integrated circuit; classifying different types of devices according to the first truth table; inspecting the layout according to a first-type specific layer rule for the same type of device in the seed layer region to obtain confirmed first-type specific layer rules; combining the confirmed first-type specific layer rules with second-type specific layer rules for the corresponding type of device in the seed layer region to construct a second truth table; obtaining calculation formulas for each layer in the seed layer region of the corresponding type of device according to the second truth table; extracting the seed layer from the layout according to the calculation formulas; if it cannot be extracted, the layer corresponding to the second-type specific layer rule in the layout has an error; otherwise, it is error-free. This invention greatly improves the efficiency and accuracy of layout inspection.

Description

Technical Field

[0001] This invention relates to the field of semiconductor integrated circuit layout inspection technology, and in particular to a method and system for inspecting the layout layers of integrated circuits. Background Technology

[0002] In advanced manufacturing processes, as device structures become more complex and more layers are used, multiple or missing seedlayer definitions can lead to incorrect seedlayer definitions in layout versus schematic (LVS) checks, making it impossible to correctly identify devices in the layout diagram and requiring a significant amount of time for troubleshooting.

[0003] In current troubleshooting methods, the initial DTT (Device Truth Table) contains layer information for the entire device. However, when LVS identifies a device, it requires accurate layer information for the seedlayer region. The total number of layers in the entire device is typically greater than the number of layers in the seedlayer region. Therefore, manual inspection of the layout is necessary to determine the specific layer information contained within the seedlayer region.

[0004] like Figure 1 As shown, the truth values ​​of specific layers A1, A2, B, and C of Device X1 and Device X2 are first obtained based on the DTT of the outermost yellow area (Device region), as shown in Table 1 below:

[0005] Table 1 DTT of Device Area

[0006]

[0007] The operation method for directly obtaining the seed layer (red area) based on the truth values ​​"1" or "0" of each layer of different Devices is as follows:

[0008] seedlayerX1 =(( layer A1 and layer A2)and layer B) not layer C

[0009] seedlayerX2 =(( layer A1 and layer A2)not layer B) and layer C

[0010] Taking Device X1 as an example, after obtaining the result, it is directly extracted from the GDS (Gross Layout). If the device can be extracted, it means the seedlayer region calculation is correct. If the device cannot be extracted, it means the result is incorrect, and it is necessary to compare device X1 layer by layer in the layout to find which layers have deviations. After finding the deviations, the calculation method of seedlayer X1 is corrected. After the correction is completed, the device is extracted from the layout again to see if it is successful. Therefore, multiple iterations are required to obtain the correct result. It can be seen that in this method, the layer that exists in the yellow Device region may not exist in the red seedlayer region, and the seedlayer calculation formula obtained based on this may be incorrect. Moreover, if there is an error in the original layout, the extracted seedlayer will also be incorrect. In addition, this method requires searching for devices on the layout one by one, which is inefficient. Summary of the Invention

[0011] The main objective of this invention is to provide a method and system for accurately and efficiently identifying the seed layer region hierarchy of devices in an integrated circuit layout.

[0012] The technical solution adopted in this invention is:

[0013] A method for inspecting integrated circuit layout layers is provided, comprising the following steps:

[0014] Obtain the first truth table for all layers of the integrated circuit, and classify the different types of devices based on the first truth table;

[0015] The layout is checked according to the first type of specific layer rule for the same type of device in the seed layer region to obtain the confirmed first type of specific layer rule;

[0016] The confirmed first type of specific layer rules are combined with the second type of specific layer rules for the corresponding type of device in the seed layer region to construct a second truth table;

[0017] The calculation formulas for each layer of the seed layer region of the corresponding type of device are obtained from the second truth table.

[0018] The seed layer is extracted from the layout according to the calculation formula. If it cannot be extracted, the layer corresponding to the second type of specific layer rule in the layout is incorrect; otherwise, it is correct.

[0019] Following the above technical solution, the first type of specific layer rule is the attribute of a certain type of layer that exists in the integrated circuit but whose existence in the seed layer region is uncertain.

[0020] Following the above technical solution, the second type of specific layer rule determines the attributes existing in the seed layer region for a certain type of layer.

[0021] Following the above technical solution, when checking the layout according to the first type of specific layer rules, all layers in the layout that correspond to the first type of specific layer rules are marked.

[0022] Following the above technical solution, the layers in the layout that correspond to the first type of specific layer rules are highlighted.

[0023] Following the above technical solution, devices of the same type are processed simultaneously.

[0024] The present invention also provides an integrated circuit layout layer inspection system, comprising:

[0025] The device classification module is used to obtain the first truth table of all layers of the integrated circuit and classify different types of devices according to the first truth table;

[0026] The specific layer rule confirmation module is used to check the layout according to the first type of specific layer rule of the same type of device in the seed layer region, and obtain the confirmed first type of specific layer rule;

[0027] The seed layer truth table construction module is used to combine the confirmed first type of specific layer rules with the second type of specific layer rules of the corresponding type of device in the seed layer region to obtain the second truth table.

[0028] The seed layer verification module is used to obtain the calculation formulas for each layer of the seed layer region of the corresponding type of device based on the second truth table; and to extract the seed layer from the layout according to the calculation formula. If it cannot be extracted, the layer corresponding to the second type of specific layer rule in the layout is incorrect; otherwise, it is correct.

[0029] Following the above technical solution, the first type of specific layer rule is an attribute of a certain type of layer that exists in the integrated circuit but whose existence in the seed layer region is uncertain.

[0030] Following the above technical solution, the second type of specific layer rule determines the attributes existing in the seed layer region for a certain type of layer.

[0031] Following the above technical solution, when the specific layer rule confirmation module checks the layout according to the first type of specific layer rule, it marks all the layers in the layout that correspond to the first type of specific layer rule.

[0032] The present invention also provides a computer storage medium storing a computer program executable by a processor, the computer program performing the integrated circuit layout layer inspection method described in the above technical solution.

[0033] The beneficial effects of this invention are as follows: This invention summarizes the rules for the existence of certain layers in the seed layer region for the same type of device, checks and confirms this through the layout, and then constructs a truth table (DTT) for the seed layers of different devices of the same type by combining the rules of other layers. Based on this DTT, the calculation formula for the corresponding seed layer is obtained. Finally, the layout is extracted according to the calculation formula, and the correctness of the corresponding layers in the layout is determined based on the extraction results. An unexpected effect is that this invention summarizes specific layer rules based on the attributes of different types of devices, performs a preliminary check on the layout based on these rules, and then constructs a truth table for the device by combining other specific layer rules. This allows for the rapid acquisition of a corrected truth table, and a secondary check of the layout can determine whether the corresponding layers in the layout are incorrect. This enables the rapid and accurate definition of the seed layer and the rapid identification of whether there are errors in the devices in the layout. The check results do not completely depend on the layout itself and do not require layer-by-layer comparison, greatly improving the efficiency and accuracy of layout checks.

[0034] Furthermore, the first type of specific layer refers to the layer that exists in the integrated circuit, but whose existence in the seed layer region is uncertain. By checking the layout, the specific layer existing in the seed layer region can be determined, and the correctness of the layout can be verified accordingly. The second type of specific layer refers to the layer that is certain to exist in the seed layer region. When both types of specific layers can be accurately determined, the DTT of the seedlayer obtained accordingly is accurate, thereby improving the accuracy of layout detection.

[0035] Furthermore, devices of the same type can be processed together, allowing for the inspection of many devices at once, which greatly reduces the time required for PDK (Process Design Kit) engineers.

[0036] Of course, any product implementing this invention does not necessarily need to achieve all of the advantages described above at the same time. Attached Figure Description

[0037] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0038] Figure 1 This is a layout diagram of an integrated circuit, where the red box represents the seedlayer area and the yellow box represents the entire device area.

[0039] Figure 2 This is a flowchart of an integrated circuit layout layer inspection method according to an embodiment of the present invention;

[0040] Figure 3 This is a schematic diagram of the integrated circuit layout layer inspection system structure according to an embodiment of the present invention. Detailed Implementation

[0041] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the invention.

[0042] It should be noted that the illustrations provided in the embodiments of the present invention are only schematic representations of the basic concept of the present invention. Therefore, the drawings only show the components related to the present invention and are not drawn according to the number, shape and size of the components in actual implementation. In actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.

[0043] In this invention, it should also be noted that the terms "center," "upper," "lower," "left," "right," "vertical," "horizontal," "inner," and "outer," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are used only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application. Furthermore, the terms "first" and "second" are used only for descriptive and distinguishing purposes and should not be construed as indicating or implying relative importance.

[0044] Furthermore, it should be noted that the features of the various embodiments of the present invention can be combined or integrated in whole or in part, and as those skilled in the art will understand, they can interact and operate in different ways. Each embodiment can be implemented independently of each other or in association with one another.

[0045] like Figure 2 As shown, the integrated circuit layout layer inspection method of this embodiment includes the following steps:

[0046] S1. Obtain the first truth table of all layers of the integrated circuit, and classify the different types of devices according to the first truth table;

[0047] S2. Based on the first type of specific layer rule for the same type of device in the seed layer region, check the layout to obtain the confirmed first type of specific layer rule;

[0048] S3. Combine the confirmed first type of specific layer rules with the second type of specific layer rules of the corresponding type of device in the seed layer region to construct a second truth table;

[0049] S4. Based on the second truth table, obtain the calculation formulas for each layer of the seed layer region of the corresponding type of device;

[0050] S5. Extract the seed layer from the layout according to the calculation formula. If it cannot be extracted, the layer corresponding to the second type of specific layer rule in the layout is incorrect; otherwise, it is correct.

[0051] In step S2, the first type of specific layer rule is an attribute of a certain type of layer that exists in the integrated circuit but whose existence in the seed layer region (i.e., the seedlayer region) is uncertain, or an attribute that cannot exist simultaneously in the seedlayer region.

[0052] It is understandable that certain layers in different integrated circuits may have other attributes. This invention uses these attributes as rules for these layers, and by using these rules to check the layout layers of integrated circuits, the efficiency of the inspection can be greatly improved.

[0053] Depend on Figure 1 As can be seen, the yellow box contains all device layers, while the red box represents the seedlayer region, which contains only some layers. Different devices have different seedlayer regions (i.e., they contain different layers). Depending on the properties of different devices, some layers may exist in the seedlayer region, while others may not, which needs to be determined by examining the layout.

[0054] For example, two devices (i.e., device X1 and device X2) are both of type MOS. Layer B and layer C are certain to exist in the seed layer region (layer B exists in the seed layer region of device X1, and layer C exists in the seed layer region of device X2), while the existence of layers A1 and A2 is uncertain in the seed layer region.

[0055] For layers A1 and A2, specific rules can be set, and corresponding software can be used to check them in the layout, marking all layers A1 and A2 in the layout (e.g., using highlighting). Based on the marking (e.g., highlighting) results, the existence of layers A1 and A2 for all devices of the same type in the seedlayer area can be directly determined.

[0056] For example, layer A1 and layer A2 are NP (i.e., N). +(a highly doped N layer) and PP (i.e., P) + When the layer is highly p-doped, only one rule needs to be set: whether the gate region (i.e., the seed layer region of the MOS) simultaneously contains both NP and PP. If there is no highlight, then in PMOS, layer A1 and layer A2 are 0 and 1 respectively, and in NMOS, layer A1 and layer A2 are 1 and 0 respectively. If there is a highlight, then layer A1 and layer A2 are both 1 (at this point, it is necessary to further confirm whether both are 1, because under normal circumstances, layer A1 and layer A2 cannot coexist in PMOS or NMOS).

[0057] Therefore, the DTT of the seedlayer regions of device X1 and device X2 is shown in Table 2 below:

[0058] Table 2 DTT in the Seedlayer region

[0059]

[0060] Based on the DTT of this seedlayer region, the calculation formula for the final seedlayer of the two devices is obtained:

[0061] seedlayer X1 =(( layer A1 not layer A2)and layer B) not layer C

[0062] seedlayer X2 =(( layer A2 not layer A1)not layer B) and layer C

[0063] If the above calculation formula is used to extract the layout, and it cannot be extracted, it means that there is an error in layer B and layer C in the layout. If it can be extracted, then layer B and layer C in the layout are correct. This allows for a quick check of the correctness of the layout, rather than relying entirely on the layout as in existing technical solutions.

[0064] Similarly, the DTT of the seedlayer region of other types of devices can be obtained, and the calculation formula of the seedlayer can be obtained accordingly. The layout is then extracted based on the calculation formula, and the extraction results are used to determine whether there are errors in the specific layer that conforms to the second type of specific layer rules.

[0065] In practical applications, especially in advanced processes, DTT is often very complex with many layers. The method described in the above embodiments of the present invention can check all layers of the seedlayer region at once, and can also check many devices of the same type at once, greatly reducing the time of PDK engineers.

[0066] To implement the above method embodiments, such as Figure 3 As shown, the present invention also provides an integrated circuit layout layer inspection system, which mainly includes:

[0067] The device classification module is used to obtain the first truth table of all layers of the integrated circuit and classify different types of devices according to the first truth table;

[0068] The specific layer rule confirmation module is used to check the layout according to the first type of specific layer rule of the same type of device in the seed layer region, and obtain the confirmed first type of specific layer rule;

[0069] The seed layer truth table construction module is used to combine the confirmed first type of specific layer rules with the second type of specific layer rules of the corresponding type of device in the seed layer region to obtain the second truth table.

[0070] The seed layer verification module is used to obtain the calculation formulas for each layer of the seed layer region of the corresponding type of device based on the second truth table; and to extract the seed layer from the layout according to the calculation formula. If it cannot be extracted, the layer corresponding to the second type of specific layer rule in the layout is incorrect; otherwise, it is correct.

[0071] Furthermore, the first type of specific layer rule is an attribute of a certain type of layer that is uncertain to exist in the seed layer region, and the second type of specific layer rule is an attribute of a certain type of layer that is certain to exist in the seed layer region.

[0072] When the specific layer rule confirmation module checks the layout according to the first type of specific layer rule, it marks all the layers in the layout that correspond to the first type of specific layer rule. Specifically, it highlights all the layers in the layout that correspond to the first type of specific layer rule.

[0073] The various modules of this system are mainly used to implement the various steps of the method embodiment, which will not be described in detail here.

[0074] This application also provides a computer-readable storage medium, such as flash memory, hard disk, multimedia card, card-type memory (e.g., SD or DX memory), random access memory (RAM), static random access memory (SRAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), programmable read-only memory (PROM), magnetic memory, disk, optical disk, server, app store, etc., which stores a computer program, and the program implements corresponding functions when executed by a processor. When executed by a processor, the computer-readable storage medium of this embodiment implements the integrated circuit layout hierarchy inspection method of the method embodiment.

[0075] In summary, this invention summarizes the rules for the existence of specific layers in the seed layer region for the same type of device, verifies this through layout checks, and then constructs a truth table (DTT) for seed layers of different devices of the same type by combining the rules of other specific layers. Based on this truth table, the calculation formula for the corresponding seed layer is obtained. Finally, the layout is extracted using this calculation formula, and the correctness of the corresponding layers in the layout is determined based on the extraction results. An unexpected benefit is that this invention summarizes specific layer rules based on the attributes of different types of devices, performs a preliminary layout check based on these rules, and then constructs a truth table for the device by combining the rules of other specific layers. This allows for the rapid acquisition of a corrected truth table, and a secondary check of the layout can determine whether the corresponding layers in the layout are incorrect. This enables the rapid and accurate definition of seed layers and the quick identification of device errors in the layout. The check results do not entirely depend on the layout itself and do not require layer-by-layer comparison, greatly improving check efficiency and accuracy.

[0076] It should be noted that, depending on the implementation needs, the various steps / components described in this application can be broken down into more steps / components, or two or more steps / components or parts of the operation of steps / components can be combined into new steps / components to achieve the purpose of this invention.

[0077] The order of the steps in the above embodiments does not imply the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this application.

[0078] It should be understood that those skilled in the art can make improvements or modifications based on the above description, and all such improvements and modifications should fall within the protection scope of the appended claims.

Claims

1. A method for inspecting the layout layers of an integrated circuit, characterized in that, Includes the following steps: Obtain the first truth table for all layers of the integrated circuit, and classify the different types of devices based on the first truth table; The layout is checked according to the first type of specific layer rule for the same type of device in the seed layer region to obtain the confirmed first type of specific layer rule; the first type of specific layer rule is the attribute of a certain type of layer that exists in the integrated circuit but whose existence in the seed layer region is uncertain; The confirmed first-class specific layer rules are combined with the second-class specific layer rules for the corresponding type of device in the seed layer region to construct a second truth table; the second-class specific layer rules determine the attributes of a certain type of layer that exist in the seed layer region; The calculation formulas for each layer of the seed layer region of the corresponding type of device are obtained from the second truth table. The seed layer is extracted from the layout according to the calculation formula. If it cannot be extracted, the layer corresponding to the second type of specific layer rule in the layout has an error. Conversely, there is no error.

2. The method for inspecting integrated circuit layout layers according to claim 1, characterized in that, When checking the layout according to the first type of specific layer rule, all layers in the layout that correspond to the first type of specific layer rule are marked.

3. The method for inspecting integrated circuit layout layers according to claim 1, characterized in that, Simultaneous processing of devices of the same type.

4. A system for inspecting the layout hierarchy of an integrated circuit, characterized in that, include: The device classification module is used to obtain the first truth table of all layers of the integrated circuit and classify different types of devices according to the first truth table; The specific layer rule confirmation module is used to check the layout according to the first type of specific layer rule of the same type of device in the seed layer region, and obtain the confirmed first type of specific layer rule; the first type of specific layer rule is the attribute of a certain type of layer that exists in the integrated circuit but whose existence in the seed layer region is uncertain; The seed layer truth table construction module is used to combine the confirmed first type of specific layer rules with the second type of specific layer of the corresponding type of device in the seed layer region to obtain the second truth table; the second type of specific layer rules determine the attributes of a certain type of layer in the seed layer region; The seed layer verification module is used to obtain the calculation formula of each layer of the seed layer region of the corresponding type of device according to the second truth table; extract the seed layer from the layout according to the calculation formula; if it cannot be extracted, the layer corresponding to the second type of specific layer rule in the layout has an error. Conversely, there is no error.

5. The integrated circuit layout layer inspection system according to claim 4, characterized in that, When the specific layer rule confirmation module checks the layout according to the first type of specific layer rule, it marks all the layers in the layout that correspond to the first type of specific layer rule.

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