Data sampling timing error evaluation method based on evaluation model

Abstract

The invention discloses a data sampling timing error evaluation method based on an evaluation model, relates to the technical field of timing error evaluation, and solves the problem that timing error evaluation is not accurate enough. Wherein the sampling module realizes undistorted receiving and clock signal frequency output of a clock signal through a CMOS clock input circuit, a third-order digital phase-locked loop circuit and a DSP digital signal processing chip, and a Fourier phase difference algorithm removes harmonic interference to solve a phase difference between the clock signal and an ideal clock signal; the clock signal feature recognition unit adopts a convolutional neural network to carry out iterative training on a training set of the timing error evaluation module to obtain an error evaluation module, the error evaluation module and the time migration algorithm module realize accurate calculation of a timing error value, and the timing error value calculation accuracy is greatly improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of timing error evaluation, and more particularly to a data sampling timing error evaluation method based on an evaluation model. BACKGROUND

[0002] The timing error evaluation method can improve the clock accuracy and stability of the system, and is suitable for various application fields that require accurate timing. The method can provide higher clock accuracy, and by dynamically tracking the timing error in the sampling interval, the clock performance of the system can be more accurately evaluated. The sampling interval dynamic tracking method can evaluate the timing error of the system in real time, which can quickly detect changes in the timing error and take appropriate compensation measures in time. The method can adaptively evaluate and compensate the timing error according to the actual situation, and it can adjust parameters according to different working environments and conditions to meet the needs of different application fields. The timing error evaluation method is mainly based on modeling and estimating the timing error in the sampling interval. It compares the difference between the system clock and the reference clock, and infers the size and trend of the timing error according to the actual measurement data. However, the accuracy of the timing error evaluation method cannot meet the requirements.

[0003] In the prior art, the data sampling timing error evaluation method based on the evaluation model has many drawbacks. On the one hand, the sampling module may experience jitter or distortion during the reception of the clock signal from the device under test, resulting in distortion of the clock signal. The lack of clock recovery function to recover and reconstruct the received clock signal, the phase difference calculation between the clock signal and the ideal clock signal is easily affected by harmonic interference, which affects the phase difference calculation result. On the other hand, the actual application situation is not considered, and the influence of other factors on the timing error value is not considered. Therefore, the present application proposes a data sampling timing error evaluation method based on an evaluation model, which aims to evaluate the error of the device under test. SUMMARY

[0004] In view of the above technical deficiencies, the present application discloses a data sampling timing error evaluation method based on an evaluation model, a sampling module receives a clock signal from a device under test using a CMOS clock input circuit, a third-order digital phase-locked loop circuit is used to realize frequency recovery and clock reconstruction of the clock signal, a DSP digital signal processing chip is used to process the clock signal and output the clock signal frequency, solving the distortion problem in the clock signal receiving process, a Fourier phase difference algorithm is used to remove harmonic interference from the clock signal and the ideal clock signal, the phase difference between the clock signal and the ideal clock signal is calculated, solving the problem of harmonic interference affecting the phase difference calculation result, a clock signal feature recognition unit determines the clock signal and the influence parameter through time domain feature extraction and time domain analysis, a convolutional neural network is used to iteratively train the training set of the timing error evaluation module to obtain an error evaluation module, and the timing error value is obtained through the error evaluation module and a time offset algorithm module, solving the problem of the influence of actual factors on the timing error value.

[0005] In view of the above technical deficiencies, the present application discloses a data sampling timing error evaluation method based on an evaluation model, a sampling module receives a clock signal from a device under test using a CMOS clock input circuit, a third-order digital phase-locked loop circuit is used to realize frequency recovery and clock reconstruction of the clock signal, a DSP digital signal processing chip is used to process the clock signal and output the clock signal frequency, solving the distortion problem in the clock signal receiving process, a Fourier phase difference algorithm is used to remove harmonic interference from the clock signal and the ideal clock signal, the phase difference between the clock signal and the ideal clock signal is calculated, solving the problem of harmonic interference affecting the phase difference calculation result, a clock signal feature recognition unit determines the clock signal and the influence parameter through time domain feature extraction and time domain analysis, a convolutional neural network is used to iteratively train the training set of the timing error evaluation module to obtain an error evaluation module, and the timing error value is obtained through the error evaluation module and a time offset algorithm module, solving the problem of the influence of actual factors on the timing error value. Step one, receiving a clock signal from a device under test through a sampling module, the sampling module comprising a clock receiving unit, a clock signal recovery unit and a frequency output unit; In step one, the output end of the clock receiving unit is connected with the input end of the clock signal recovery unit, and the output end of the clock signal recovery unit is connected with the input end of the frequency output unit; Step two, using a Fourier phase difference algorithm to remove harmonic interference from the clock signal and the ideal clock signal, and calculating the phase difference between the clock signal and the ideal clock signal; Step three, using a timing error evaluation module to evaluate the clock signal influence factors and calculate the timing error value, the timing error evaluation method comprising a clock signal feature recognition unit, an evaluation model establishment unit and a timing error calculation unit; In step three, the output end of the clock signal feature recognition unit is connected with the input end of the evaluation model establishment unit, and the output end of the evaluation model establishment unit is connected with the input end of the timing error calculation unit; Step four, waiting for the next clock signal and repeating the above steps to realize dynamic tracking; Step five, using an online data analysis platform to further analyze and process the timing error value, the online data analysis platform viewing the timing error result through dragging and rolling zoom operation, and facilitating user analysis of data through error curve.

[0006] As a further technical scheme of the present application, the clock signal receiving unit adopts a CMOS clock input circuit to receive the clock signal from the device under test, the CMOS clock input circuit is connected with the device under test through a network time protocol server, the network time protocol server establishes a synchronous time relationship with the device under test through a network time protocol, and the equal-interval synchronous reception of the clock signal is realized. The clock receiving unit is also provided with a phase noise estimator and an adaptive filter, which analyzes the phase jitter characteristics of the input clock signal in real time and dynamically adjusts the compensation parameters. The clock signal receiving unit also integrates the PTP network clock with an accuracy of ±20ns and the Beidou / GPS satellite clock with an accuracy of ±10ns, and the clock signal receiving unit is built-in with an anti-interference electromagnetic shielding cavity, adopts a multi-layer PCB differential wiring design, and cooperates with an active noise cancellation circuit to improve the electromagnetic interference suppression ratio of the 50MHz-2GHz frequency band to more than 60dB. The clock receiving unit is also provided with a phase noise estimator and an adaptive filter, which analyzes the phase jitter characteristics of the input clock signal in real time and dynamically adjusts the compensation parameters.

[0007] As a further technical scheme of the present application, the clock signal recovery unit adopts a third-order digital phase-locked loop circuit to realize the frequency recovery of the clock signal, the third-order digital phase-locked loop circuit includes a frequency tracking module, a feedback adjustment module and a distortion recovery module, the frequency tracking module filters the clock signal through a filter of the third-order digital phase-locked loop circuit, the feedback adjustment module controls the feedback adjustment of the filtered clock signal through a digital controller and a voltage-controlled oscillator of the third-order digital phase-locked loop circuit, the digital controller generates an analog converted correction signal, the voltage-controlled oscillator adjusts the output frequency of the clock signal according to the analog converted correction signal, and the distortion recovery module makes the third-order digital phase-locked loop circuit in a locked state through the feedback loop control of the voltage-controlled oscillator, realizes the distortion recovery of the clock signal, the output end of the frequency tracking module is connected with the input end of the feedback adjustment module, and the output end of the feedback adjustment module is connected with the input end of the distortion recovery module.

[0008] As a further technical scheme of the present application, the frequency output unit adopts a DSP digital signal processing chip to process the clock signal and output the clock signal frequency, the DSP digital signal processing chip adopts a frequency synthesis algorithm to perform amplitude weighting superposition and digital analog conversion processing on the clock signal, and obtains the clock signal frequency.

[0009] As a further technical scheme of the present application, the working method of the Fourier phase difference algorithm is as follows: Step one, harmonic filtering processing is performed on the clock signal and the ideal clock signal through a harmonic filter, and the harmonic component is removed and the fundamental component is retained, the harmonic filter realizes the filtering of the harmonic component through the resonance characteristics of a resonance circuit; Step two, Fourier transform the fundamental wave components of the filtered clock signal and the ideal clock signal, the Fourier transform is obtained by frequency weighted summation of the clock signal and the ideal clock signal, the Fourier fundamental wave spectrum expression of the clock signal and the ideal clock signal is: In formula (1), is the Fourier fundamental wave spectrum of the clock signal, is the sampling interval of the clock signal, is the clock signal, t is time, is the Fourier fundamental wave spectrum of the ideal clock signal, is the sampling interval of the ideal clock signal, is the ideal clock signal, is the frequency of the clock signal, is the frequency of the ideal clock signal;Step three, calculate the fundamental wave phase angle of the clock signal and the ideal clock signal at the frequency point by the phase formula, obtain the relative time offset of the clock signal and the ideal clock signal, the fundamental wave phase angle calculation formula of the clock signal and the ideal clock signal is: In formula (2), indicates the inverse trigonometric function, is the imaginary part of the clock signal fundamental wave spectrum, is the real part of the clock signal fundamental wave spectrum, is the fundamental wave phase angle of the clock signal, is the imaginary part of the ideal clock signal fundamental wave spectrum, is the real part of the ideal clock signal fundamental wave spectrum, is the fundamental wave phase angle of the ideal clock signal;Step four, finally, subtract the fundamental wave phase angle of the clock signal from the fundamental wave phase angle of the ideal clock signal, obtain the phase difference between the clock signal and the ideal clock signal.

[0010] As a further technical scheme of the application, the working method of the evaluation model establishing unit is: step one, normalize the influence parameters of the clock signal by decimal scaling normalization, introduce the feature importance weight matrix W, dynamically adjust the scaling factor according to the contribution degree of each influence parameter to the timing error, calculate the parameter importance by gradient back propagation, the output function of the feature importance weight matrix is: In formula (3), Loss is the model loss function for the i th impact parameter; The feature importance weight matrix is represented; the decimal scaling normalization scales the impact parameters of the clock signal to the training set of the timing error evaluation module through the maximum value scaling; wherein the timing error evaluation module comprises a timing extraction module, a difference operator estimation module, a spatio-temporal pyramid convolutional network model, a weighted fusion module, a Bayesian uncertainty quantification module, an acceleration module and a data dynamic updating module; Step two, then the training set of the timing error evaluation module is iteratively trained by using a convolutional neural network to obtain an error evaluation module, the convolutional neural network extracts and combines the impact parameters of the clock signal through a convolution kernel, and then iteratively updates the error evaluation module weight through a residual network to obtain an error evaluation module with optimal recognition effect; Step three, finally, the accuracy of the error evaluation module is verified by using a confusion matrix optimizer, the confusion matrix optimizer calculates the precision of the error evaluation module by using a moment estimation algorithm, and the calculation formula of the precision of the error evaluation module is: In formula (4), R is the precision of the error evaluation module, is the evaluation value of the error evaluation module, is the evaluation value subscript of the error evaluation module, n is the evaluation frequency of the error evaluation module, and m is the error evaluation actual value, is the weighted average value of the moment estimation algorithm. As a further technical solution of the present application, the timing error calculation unit comprises an FPGA chip main control module and an error evaluation module, a time offset algorithm module, a signal processing module, a reconfigurable computing unit, an anti-interference computing module and a loss function accelerator connected with the FPGA chip main control module; As a further technical solution of the present application, the timing error calculation unit obtains a timing error value through an error evaluation module and a time offset algorithm module, the error evaluation module measures the influence of the impact parameters of the clock signal on the timing error value to obtain a loss value, and the time offset algorithm module calculates the timing error value according to the loss value and the phase difference between the clock signal and the ideal clock signal, the calculation formula of the loss value is: In formula (5), K is the loss value, z is the temperature change value, u is the power fluctuation value, x is the mechanical vibration frequency, g is the average noise of external electromagnetic noise and radio frequency noise, is the loss function mean square error; the calculation formula of the timing error value is: In formula (6), Q is the timing error value, and h is the relative time offset, The time offset algorithm module is a timing error conversion value. As a further technical solution of the application, the timing extraction module aligns the clock signal waveforms of different time periods through the dynamic time warping method, captures the timing correlation, introduces the Transformer architecture to model the timing dependence in the long sequence through the gating mechanism, and outputs the timing feature vector; The difference operator estimation module improves the computing capacity by simulating the central difference operator through a 3x3 convolution kernel, optimizes the operator parameters through back propagation, and adaptively fits the local change pattern of the signal; and different step length difference operators are applied in parallel to capture the change trend of different time granularity; an adaptive difference scale selection mechanism is proposed to fuse the attention mechanism to weight the difference results of different scales and enhance the flexibility of feature expression; The spatio-temporal pyramid convolutional network model extracts spatial features of multiple receptive fields in parallel by using different dilated rate cavity convolutions, performs time pooling of different windows on the timing feature map to capture hierarchical time features of short-term fluctuations and long-term trends, and fuses spatio-temporal feature maps of different scales through cross-layer connection or gating mechanism to output feature representation containing multi-resolution information; The weighted fusion module maps features of different sources to the same dimensional space through 1x1 convolution or fully connected layer, adaptively combines the features output by multiple modules to improve the accuracy of error evaluation, proposes a dynamic feature selection strategy to enhance the generalization ability of the model to different environmental scenarios through data-driven adaptive weight learning, and introduces a cross-modal feature correlation analysis method to guide the update of the weighting matrix and improve the rationality of the fusion; The Bayesian uncertainty quantification module introduces Gaussian distribution parameter probability weights in the fully connected layer, and approximates the posterior distribution through variational inference or Markov chain Monte Carlo method; the double-branch uncertainty estimation method is used to estimate the accidental uncertainty and cognitive uncertainty in parallel; The acceleration module maps the convolution layer and the pooling layer to the parallel logic unit of the FPGA to realize hardware-level pipeline calculation of the convolution kernel; the continuous convolution-batch normalization-activation operation is combined to reduce the memory access overhead; the calculation branch is dynamically switched according to the complexity of the input signal; The data dynamic update module uses the isolation forest or statistical threshold method to detect abnormal samples, filters outlier data generated by sensor failure or sudden interference, uses elastic weight consolidation or memory replay technology to retain historical knowledge when updating the model, and avoids catastrophic forgetting.

[0011] As a further technical scheme of the application, the signal processing module dynamically adjusts the sensor output signal amplitude through a programmable gain amplifier (PGA), filters out high-frequency noise with an anti-aliasing filter, avoids sampling distortion, cuts off ground loop interference through an optical coupling isolation circuit, ensures electrical isolation of the power fluctuation signal and the clock signal, converts analog signals into digital quantities through a multi-channel high-speed ADC, ensures the timing alignment of temperature, vibration and other environmental parameters and the clock signal through a synchronous sampling timer, detects the phase difference of the clock signal, compares the phase of the measured clock and the reference clock through a digital phase discriminator, and outputs a phase difference signal with nanosecond-level resolution. The reconfigurable computing unit maps the multi-scale convolution kernel in the space-time pyramid convolution network to the FPGA parallel computing unit, realizes hardware-level acceleration of convolution operation through pipeline technology, calculates the mean square error in the loss function, designs a special addition tree circuit, and parallelly accumulates N sample error values, and the calculation delay is reduced from 100 mu s of CPU to 5 mu s of FPGA; FPGA is responsible for high-speed signal processing and algorithm acceleration, CPU processes control logic and system scheduling, and DSP performs complex floating-point operation; according to real-time calculation load, dynamically adjust the hardware configuration, reduce the peak power consumption by 30% under the premise of maintaining the accuracy. The anti-interference computing module deploys a multi-layer electromagnetic shielding cover with a conductivity > 5e6 S / m in front of the sensor, and a pi-shaped filter circuit at the power input end to suppress radio frequency interference in the 50MHz~2GHz frequency band; the temperature of the clock circuit is monitored in real time by a constant temperature crystal oscillator or a temperature sensor, and the clock frequency compensation coefficient is dynamically adjusted by using a linear interpolation algorithm; the least mean square (LMS) algorithm is used to separate the noise component from the mixed signal, and the signal-to-noise ratio is improved by 20dB. The loss function accelerator uses a carry lookahead adder (CLA) to realize parallel accumulation of N sample errors, decouples the calculation time and the number N of samples, integrates a floating-point operation unit (FPU) to accelerate complex operations such as square root and exponential for gradient calculation optimization, and designs a reverse computation graph hardware mapping for gradient backpropagation in the convolutional neural network, converts gradient matrix operations into distributed memory access and parallel multiplication and accumulation operations of FPGA, and the gradient calculation speed is improved by 5 times.

[0012] The application has the following positive and beneficial effects: The present invention discloses a data sampling timing error evaluation method based on an evaluation model. The sampling module adopts a CMOS clock input circuit to receive a clock signal from a device under test, adopts a third-order digital phase-locked loop circuit to realize the frequency recovery and clock reconstruction of the clock signal, adopts a DSP digital signal processing chip to process the clock signal and output the clock signal frequency, thereby realizing distortion-free reception of the clock signal, adopts a Fourier phase difference algorithm to calculate the phase difference between the clock signal and the ideal clock signal, and has the ability to resist harmonic interference and practicality, a clock signal feature recognition unit determines the clock signal and influencing parameters through time domain feature extraction and time domain analysis, adopts a convolutional neural network to iteratively train the training set of the timing error evaluation module to obtain an error evaluation module, and the error evaluation module and the time offset algorithm module obtain a timing error value, thereby realizing accurate calculation of the timing error value. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are only some embodiments of the present invention. Those skilled in the art can also derive other drawings based on these drawings without inventive work, among which: Figure 1 This is an overall flow chart of a data sampling timing error evaluation method based on an evaluation model of the present invention; Figure 2 This is a flowchart of the Fourier phase difference algorithm used in the present invention; Figure 3 Establishing a unit workflow diagram for the evaluation model adopted by the present invention; Figure 4 This is a schematic diagram of the sampling module architecture used in the present invention; Figure 5 This is a schematic diagram of the timing error evaluation module architecture used in the present invention. DETAILED DESCRIPTION

[0014] The following, in conjunction with the accompanying drawings, provides a clear and complete description of the technical solutions in the embodiments herein. Obviously, the described embodiments represent only a portion of the embodiments herein, and not all of them. It should be understood that these descriptions are merely illustrative and are not intended to limit the scope of the present invention. Furthermore, descriptions of well-known structures and technologies are omitted in the following description to avoid unnecessary confusion regarding the concepts of the present invention.

[0015] like Figures 1-5 As shown, a data sampling timing error evaluation method based on an evaluation model includes the following steps: Step one, receiving the clock signal from the device under test through the sampling module, the sampling module includes a clock receiving unit, a clock signal recovery unit and a frequency output unit; In step one, the output end of the clock receiving unit is connected with the input end of the clock signal recovery unit, and the output end of the clock signal recovery unit is connected with the input end of the frequency output unit. Step two, using Fourier phase difference algorithm to remove harmonic interference of clock signal and ideal clock signal, and calculating the phase difference between clock signal and ideal clock signal. Step three, using timing error evaluation module to evaluate the influencing factors of clock signal and calculate the timing error value, the timing error evaluation method includes clock signal feature recognition unit, evaluation model establishment unit and timing error calculation unit. In step three, the output end of the clock signal feature recognition unit is connected with the input end of the evaluation model establishment unit, and the output end of the evaluation model establishment unit is connected with the input end of the timing error calculation unit. Step four, waiting for the next clock signal, repeating the above steps to realize dynamic tracking. Step five, using online data analysis platform to further analyze and process the timing error value, the online data analysis platform can view the timing error result through dragging and rolling zoom operation, and the error curve can facilitate user to analyze data.

[0016] In further embodiments, the clock signal receiving unit receives the clock signal from the device under test using a CMOS clock input circuit, the CMOS clock input circuit is connected with the device under test through a network time protocol server, the network time protocol server establishes a synchronous time relationship with the device under test through a network time protocol, and realizes equal interval synchronous reception of the clock signal. The clock signal receiving unit also integrates a PTP network clock with a precision of ±20ns, a Beidou / GPS satellite clock with a precision of ±10ns, and an anti-interference electromagnetic shielding cavity is built-in in the clock signal receiving unit. A multi-layer PCB differential wiring design is adopted, and an active noise cancellation circuit is used to improve the electromagnetic interference suppression ratio of the 50MHz-2GHz frequency band to more than 60dB. The clock receiving unit is also provided with a phase noise estimator and an adaptive filter, which can analyze the phase jitter characteristics of the input clock signal in real time and dynamically adjust the compensation parameters.

[0017] In specific embodiments, the integrated PTP network clock (accuracy ±20 ns), Beidou / GPS satellite clock (accuracy ±10 ns) and local temperature compensated crystal oscillator (TCXO, accuracy ±50 ns) three types of clock sources, through the dynamic weight fusion algorithm (based on fuzzy logic decision) real-time calculation of each clock source reliability, when the target device clock signal signal-to-noise ratio <15dB, automatically switch to satellite clock as the main reference source, realize the stable reception of clock signal in complex electromagnetic environment, the signal effective capture rate from 85% to 99.2%.

[0018] In specific embodiments, the multi-layer PCB differential wiring design is adopted, and the active noise cancellation circuit is used to improve the electromagnetic interference suppression ratio of 50MHz-2GHz frequency band to more than 60dB, which is 3 times higher than the traditional receiving unit. Through the dynamic threshold detection algorithm (threshold automatically adjusted 0.2V-5V with signal amplitude), burst pulse interference (such as peak noise with duration <10ns) is identified and removed, and the sliding window interpolation method (window length 5-50 cycles adaptively adjusted) is used to repair the signal missing segment, and the time domain waveform integrity is improved to more than 98%. A variable step size phase-locked loop (PLL) + adaptive notch filter cascade structure is used to automatically identify the interference frequency and generate the notch coefficient for the harmonic interference in the range of 10Hz-100MHz (such as power frequency 50Hz and its 2-20th harmonic), and in the extreme scenario of THD=30%, the signal harmonic distortion can be reduced to less than 5%, which is 40% higher than the traditional phase-locked loop recovery accuracy.

[0019] In specific applications, a dynamic sampling rate adaptive adjustment mechanism is introduced in the frequency output link: a built-in frequency change rate monitoring module (resolution 0.1Hz / μs) is used to calculate the frequency change rate (Δf / Δt) of the input clock signal in real time, and when a frequency mutation (Δf>10%fs) is detected, the output sampling rate is automatically adjusted through a segmented oversampling strategy: 2 times oversampling (sampling rate 20MS / s) is used in low frequency band (<10MHz), and 4 times oversampling (sampling rate 4GS / s) is used in medium and high frequency band (10MHz-1GHz), and an anti-aliasing FIR filter (cutoff frequency dynamically matches 0.4 times Nyquist frequency of sampling rate) is used to reduce the sampling aliasing error of 1GHz clock signal from 12% of traditional fixed sampling to 1.5%. In specific applications, a temperature compensation frequency correction algorithm is designed: a MEMS temperature sensor (accuracy ±0.1℃) is integrated to monitor the working temperature of the frequency output unit in real time, and the output frequency compensation coefficient is dynamically adjusted based on a quadratic polynomial fitting model (fitting error <0.05ppm / ℃) to solve the problem of sampling frequency deviation caused by traditional crystal oscillator temperature drift, and the frequency stability is improved to ±0.5ppm in the wide temperature range of -40℃~85℃.

[0020] In a specific application, an intelligent decision-making closed loop is constructed between the clock receiving unit, the signal recovery unit, and the frequency output unit: the receiving unit outputs the quality indicators (signal-to-noise ratio, harmonic distortion, frequency stability) of the three-way clock signal in real time, the signal recovery unit selects the optimal input signal through a multi-index weighted evaluation model (the weight coefficients are dynamically allocated based on the analytic hierarchy process), and when the quality of a single signal does not meet the standard, a multi-source signal fusion recovery mode (such as Kalman filter fusion of satellite clock and local crystal oscillator) is triggered. In a specific application, the frequency output unit feeds back the timing error statistics (such as Allan variance, root mean square error) of the output signal to the signal recovery unit, forming an error closed loop correction mechanism, and through adaptive adjustment of the recovery algorithm parameters (such as PLL loop bandwidth, notch filter Q value), the overall error of the sampling module is dynamically optimized, and the error convergence speed is improved by 5 times compared with the traditional open loop structure. In a further specific embodiment, the clock receiving unit is also provided with a phase noise estimator and an adaptive filter, which analyzes the phase jitter characteristics of the input clock signal in real time and dynamically adjusts the compensation parameters.

[0021] The technical implementation of the phase noise estimator and the adaptive filter in the clock receiving unit is described in detail, covering working principles, design points, and embodiments. This design is suitable for high-frequency clock synchronization systems (such as 5G base stations, high-speed SerDes, satellite communication, etc.), and can significantly improve the stability of the clock signal.

[0022] Real-time quantification of the phase jitter of the input clock signal includes: Time domain indicators: period jitter, cycle-to-cycle jitter Frequency domain indicators: phase noise power spectral density (PSD) The above innovations closely focus on the sampling module architecture of step one, optimizing the whole link from signal reception, recovery to output, and improving the sampling accuracy and anti-interference ability through multi-technology fusion and intelligent control.

[0023] In further embodiments, the error curve is a common visualization method that can help users more intuitively understand the distribution and trend of timing errors. Users can analyze the deviation and stability of the data through the error curve to find out abnormal points and trends, optimize their data analysis process and results, and use the error curve to display the trend of the data. The error curve is usually displayed using a line chart, with the horizontal axis representing time or sample number and the vertical axis representing error size. Users can observe the trend of the error curve to understand the fluctuation and trend of the data, and then perform data preprocessing and analysis. Online data analysis platforms are an important method for data analysis, which can improve user efficiency and decision-making accuracy. The popularity and development of online data analysis platforms provide us with more convenient and efficient data analysis methods.

[0024] The network time protocol is a protocol for establishing a synchronous time relationship between a network time protocol server and a device under test. The network time protocol server establishes a connection with the device under test and communicates using the network time protocol to ensure that the clock signals between the two are synchronized. The network time protocol server provides accurate time information and sends it to the device under test. The device under test receives and processes the time information and then adjusts its clock as needed to keep it synchronized with the network time protocol server's clock. In order to achieve equal interval synchronization of the clock signal, the network time protocol server periodically sends time information to the device under test. In this way, within a certain time interval, the device under test can receive the clock signal from the network time protocol server and adjust its own clock to synchronize with it. In further embodiments, the clock signal recovery unit uses a third-order digital phase-locked loop circuit to recover the frequency of the clock signal. The third-order digital phase-locked loop circuit includes a frequency tracking module, a feedback adjustment module, and a distortion recovery module. The frequency tracking module filters the clock signal through a filter in the third-order digital phase-locked loop circuit. The feedback adjustment module controls the feedback adjustment of the filtered clock signal through a digital controller and a voltage-controlled oscillator in the third-order digital phase-locked loop circuit. The digital controller generates an analog converted correction signal, and the voltage-controlled oscillator adjusts the output frequency of the clock signal according to the analog converted correction signal. The distortion recovery module controls the third-order digital phase-locked loop circuit to be in a locked state through a feedback loop of the voltage-controlled oscillator, achieving distortion recovery of the clock signal. The output of the frequency tracking module is connected to the input of the feedback adjustment module, and the output of the feedback adjustment module is connected to the input of the distortion recovery module.

[0025] In further embodiments, the frequency output unit uses a DSP digital signal processing chip to process the clock signal and output the frequency of the clock signal. The DSP digital signal processing chip uses a frequency synthesis algorithm to perform amplitude weighting superposition and digital analog conversion processing on the clock signal to obtain the frequency of the clock signal.

[0026] In a specific embodiment, the digital controller generates a correction signal for analog conversion through an internal correction circuit. The digital controller usually has one or more analog-to-digital converters for converting analog input signals into digital signals. Before analog conversion, the digital controller calibrates the analog-to-digital converter to ensure the accuracy and precision of its output. The correction signal can be divided into two types: zero-point correction and gain correction. Zero-point correction is to eliminate the deviation of the analog-to-digital converter output at zero input. The digital controller measures and records the output value of the analog-to-digital converter at zero input, and adjusts the output accordingly so that the output is zero at zero input. Gain correction is to eliminate the amplification or reduction error of the analog-to-digital converter output at non-zero input. The digital controller uses a known reference signal or standard signal as input, measures and records the output value of the ADC, and then calculates the appropriate gain correction value by comparing the difference between the actual output and the expected output, and applies it to subsequent analog conversion.

[0027] The process of obtaining the clock signal frequency of the DSP digital signal processing chip is as follows: 1. Amplitude weighting superposition: the DSP digital signal processing chip internally performs amplitude weighting superposition through a frequency synthesis algorithm to superimpose the clock signal according to a certain proportion, thereby generating a new clock signal; 2. The clock signal after amplitude weighting superposition is input into a digital-to-analog converter, and the DSP digital signal processing chip controls the change of its output voltage or current according to the input digital data and clock signal; 3. By adjusting the amplitude weighting superposition proportion and the size of the voltage or current output by the DSP digital signal processing chip, the frequency of the finally generated clock signal can be realized; in the frequency synthesis algorithm, first, multiple input clock signals are needed as reference signals, these reference signals can have different frequencies and phases, then, by weighting the amplitude of each reference signal and performing superposition operation, i.e. adding them together, the weighting proportion of the amplitude can be set according to the demand to realize the required clock signal characteristics, when performing amplitude weighting superposition, the phase relationship and amplitude difference between the reference signals need to be considered, which can be realized by adjusting the amplitude and phase of each reference signal, after appropriate adjustment and superposition operation, a new clock signal can be generated, whose frequency and characteristics are determined by the input signal.

[0028] In a further embodiment, the working method of the Fourier phase difference algorithm is: Step one, harmonic filter the clock signal and ideal clock signal through harmonic filter, remove harmonic component and retain fundamental component, the harmonic filter realizes the filtering of harmonic component through the resonance characteristics of the resonant circuit; In specific embodiments, on the basis of traditional fixed-frequency harmonic filter, a dynamic multi-frequency tracking notch filter is innovatively designed: a fast Fourier transform (FFT) + wavelet packet decomposition (WPD) joint frequency spectrum analysis algorithm is adopted, the input clock signal is scanned for full spectrum every 20 ms (frequency resolution 0.1 Hz), and the interference frequency points of harmonic order ≥ 3 and amplitude > 5% of the fundamental wave are automatically identified (supporting tracking of more than 10 harmonic frequencies at the same time). For each identified harmonic frequency, the LC resonance circuit parameters are dynamically configured (the capacitance value is adjusted in real time through a digital potentiometer, and the adjustment accuracy is 0.1 pF), so that the resonance frequency accurately matches the harmonic frequency, and the specific harmonic is suppressed. In a strong interference environment with THD=40%, the suppression ratio of characteristic harmonics such as 5, 7, and 11 is 65 dB, which is 25 dB higher than that of the traditional fixed-frequency filter. A phase compensation type harmonic filter architecture is also adopted: a negative feedback phase correction network is introduced into the LC resonance filter circuit, the phase offset of the fundamental wave signal is detected in real time (the detection accuracy is 0.01°), the compensation capacitance value is dynamically adjusted, and the phase distortion of the fundamental wave signal in the filtering process is ensured to be <0.05°. A multi-stage filtering + phase equalization cascading structure is adopted: the front-stage filter adopts a low-Q value resonance circuit (Q=20-50) to realize wide-band harmonic suppression, the rear-stage adopts a high-Q value resonance circuit (Q=100-200) for fine filtering, and a all-pass phase correction network is inserted in the middle, which controls the group delay fluctuation of the fundamental wave signal within ±1 ns while effectively filtering out harmonics, solving the problem of timing error amplification caused by phase distortion of traditional filters. An adaptive filtering system based on reinforcement learning is constructed to design a harmonic feature filter parameter mapping model: through a deep Q network (DQN) algorithm, the harmonic spectrum features (frequency, amplitude, and phase) are taken as inputs, and the filter parameters (capacitance value, inductance value, and damping coefficient) are taken as outputs, and the optimal parameter configuration under different harmonic scenarios is accumulated in the training stage. In online operation, the system quickly matches the optimal configuration scheme from the pre-trained parameter space according to the real-time detected harmonic features, and makes a small exploratory adjustment through the ε-greedy strategy, so that the filter completes parameter self-optimization within 10 ms. In the scenario where the harmonic components dynamically change (such as fluctuating frequency >1 Hz), the filtering effect is improved by more than 30% compared with the traditional adaptive method. When designing a three-dimensional integrated filter module, at the hardware level, the LC resonance circuit, phase compensation network, and temperature compensation circuit are integrated in the LTCC (low temperature co-fired ceramic) multilayer substrate, the layout of the traces is optimized through electromagnetic field simulation (the coupling coefficient between adjacent resonance circuits <0.01), and the internal crosstalk of the module is reduced.

[0029] Integrated environmental sensing sensor array: real-time monitoring of environmental parameters such as temperature (-40℃~+85℃), humidity (5%~95% RH), vibration (0.1g~20g), etc., dynamically adjusting filtering parameters based on multivariate regression model, for example, 0.02% capacitance value drift is automatically compensated for every 10℃ change in temperature, making the frequency response of the filter fluctuate <±0.5% within a wide temperature and humidity range. By monitoring key indicators such as the quality factor (Q value), insertion loss, and phase response of the resonant circuit, a health status evaluation model is constructed using principal component analysis (PCA) algorithm, and when the Q value drops by more than 20%, an automatic warning is triggered (warning accuracy ≥95%). Step two, Fourier transform is performed on the fundamental wave components of the filtered clock signal and the ideal clock signal, which is obtained by frequency-weighted summation of the clock signal and the ideal clock signal, and the frequency spectrum representation corresponding to the clock signal and the ideal clock signal is obtained. The Fourier fundamental wave spectrum expression of the clock signal and the ideal clock signal is: In formula (1), is the Fourier fundamental wave spectrum of the clock signal, is the sampling interval of the clock signal, is the clock signal, t is time, is the Fourier fundamental wave spectrum of the ideal clock signal, is the sampling interval of the ideal clock signal, is the ideal clock signal, is the frequency of the clock signal, is the frequency of the ideal clock signal; Step three, the fundamental wave phase angle of the clock signal and the ideal clock signal at the frequency point is calculated through the phase formula, and the relative time offset of the clock signal and the ideal clock signal is obtained. The fundamental wave phase angle calculation formula of the clock signal and the ideal clock signal is: In formula (2), represents the inverse trigonometric function, is the imaginary part of the clock signal fundamental wave spectrum, is the real part of the clock signal fundamental wave spectrum, is the fundamental wave phase angle of the clock signal, is the imaginary part of the ideal clock signal fundamental wave spectrum, is the real part of the ideal clock signal fundamental wave spectrum, is the fundamental wave phase angle of the ideal clock signal; the imaginary part and the real part of the clock signal fundamental wave spectrum are obtained by transforming the clock signal Fourier fundamental wave spectrum expression, A is the amplitude of the clock signal Fourier fundamental wave spectrum, is the sine value of the phase angle of the clock signal, is the cosine value of the phase angle of the clock signal, the imaginary part and the real part of the ideal clock signal fundamental wave spectrum are obtained by transforming the ideal clock signal Fourier fundamental wave spectrum expression, the Fourier fundamental wave spectrum amplitude of the ideal clock signal, the Fourier fundamental wave spectrum amplitude of the ideal clock signal, the Fourier fundamental wave spectrum amplitude of the ideal clock signal; Step four, subtract the fundamental wave phase angle of the clock signal from the fundamental wave phase angle of the ideal clock signal to obtain the phase difference between the clock signal and the ideal clock signal. In specific embodiments, the harmonic filter is an electronic device that filters out harmonic components through the resonance characteristics of a resonant circuit. At the resonant frequency, the resonant circuit produces a high-Q (quality factor) resonance peak, so that the signals near this frequency can be amplified, while other frequency signals are suppressed. When the input signal passes through the wave filter, if the input signal contains harmonic components with the same or similar resonant frequency, these components will be amplified and highlighted, while other frequency signals will be attenuated, thus achieving the filtering of harmonic components. Fourier transform is a mathematical tool used to represent a function as a weighted sum of sine and cosine functions of different frequencies. In the time domain, a signal can be represented as a waveform that changes over time, while in the frequency domain, a signal can be represented as the amplitude and phase of different frequency components. For clock signals and ideal clock signals, we can consider them as periodic functions and apply Fourier transform to obtain their corresponding frequency spectrum representation. First, by sampling the clock signal and the ideal clock signal, we obtain discrete data points. Then, we apply discrete Fourier transform (DFT) or fast Fourier transform (FFT) to these data points to calculate the frequency spectrum. The Fourier phase difference algorithm calculates the phase difference results as shown in Table 2: As shown in Table 1, four test groups are set up, and two methods are used to calculate the fundamental wave phase angle of the clock signal and the ideal clock signal. Method 1 is cross-correlation method, which performs cross-correlation operation on the clock signal and the ideal clock signal, finds the maximum correlation peak value between them, and then determines the phase difference. Method 2 uses the Fourier phase difference algorithm to remove filter interference to calculate the fundamental wave phase angle of the clock signal and the ideal clock signal. The error of method 1 is greater than that of method 2, which shows that the Fourier phase difference algorithm of the present application has outstanding technical effects in removing filter interference to calculate the fundamental wave phase angle of the clock signal and the ideal clock signal.

[0030] In further embodiments, the clock signal feature recognition unit converts the clock signal into a time-domain image using a waveform timing diagram, determines the clock signal and the influence parameters through time-domain feature extraction and time-domain analysis, and the influence parameters of the clock signal at least include temperature change value, power fluctuation value, mechanical vibration frequency, external electromagnetic noise amount and radio frequency noise amount. In further embodiments, the working method of the evaluation model establishment unit is as follows: step one, the influence parameters of the clock signal are normalized by using decimal scaling normalization, a feature importance weight matrix W is introduced, a scaling factor is dynamically adjusted according to the contribution of each influence parameter to the timing error, the importance of the parameters is calculated through gradient back propagation, and the output function of the feature importance weight matrix W is: In formula (3), is the i th influence parameter, and Loss is the model loss function; indicates the feature importance weight matrix; the decimal scaling normalization scales the influence parameters of the clock signal to the training set of the timing error evaluation module through maximum and minimum scaling; wherein the timing error evaluation module includes a timing extraction module, a difference operator estimation module, a spatio-temporal pyramid convolutional network model, a weighted fusion module, a Bayesian uncertainty quantification module, an acceleration module and a data dynamic updating module; step two, then the training set of the timing error evaluation module is iteratively trained using a convolutional neural network to obtain an error evaluation module, the convolutional neural network extracts and combines the influence parameters of the clock signal through a convolution kernel, and iteratively updates the error evaluation module weight through a residual network to obtain an error evaluation module with optimal recognition effect; Step three, finally, the accuracy of the error evaluation module is verified using a confusion matrix optimizer, the confusion matrix optimizer calculates the precision of the error evaluation module through a matrix estimation algorithm, and the calculation formula of the precision of the error evaluation module is: In formula (4), R is the precision of the error evaluation module, is the evaluation value of the error evaluation module, is the index of the evaluation value of the error evaluation module, n is the evaluation times of the error evaluation module, and m is the actual value of the error evaluation, ​is the weighted average of the moment estimation algorithm. In specific embodiments, the convolutional neural network is a deep learning model widely used in computer vision and image processing, which mainly functions to extract features and classify input data, and can also be used to establish a timing error evaluation module. The principle of the convolutional neural network is based on the working mode of the human visual system, which extracts features in the input data through multiple convolution and pooling operations, and maps these features to the corresponding output categories through a fully connected layer. The basic principles of the convolutional neural network are as follows: 1. The convolutional layer is the core part of the convolutional neural network, which uses a set of learnable filters (also known as convolution kernels) to perform sliding window operations on the input data, calculating the convolution operation results between each filter and the input data. This can effectively capture the local spatial relationships in the input data and extract features of different scales and directions; 2. After each convolution operation, a nonlinear activation function is usually introduced to increase the nonlinear representation ability of the network and make the network better adapt to complex data distribution; 2. The pooling layer is used to reduce the dimension of the feature map and preserve key information. Common pooling operations include max pooling and average pooling, which select the maximum or average value in the local region as the output, respectively, to reduce the size and number of parameters of the feature map; 3. After multiple convolution and pooling operations, the obtained feature map can be flattened into a one-dimensional vector and classified or regressed through a fully connected layer. The fully connected layer maps the input features to the output categories and calculates the final classification probability or regression result through an activation function; 4. The convolutional neural network uses a loss function to measure the error between the predicted result and the true label. Common loss functions include cross-entropy loss, mean squared error, etc. To minimize the loss function, the convolutional neural network uses the backpropagation algorithm to calculate the gradient of each parameter in the network and uses an optimization algorithm (such as stochastic gradient descent) to update the parameters. The convolutional neural network establishes a timing error evaluation module, and the precision of the timing error evaluation module is shown in Table 3: As shown in Table 2, four test groups are set up, and two methods are used to establish a timing error evaluation module, and the precision of the timing error evaluation module is calculated. Method 3 uses a logistic regression statistical method to establish a timing error evaluation module, and method 4 uses a convolutional neural network to establish a timing error evaluation module. The precision of the timing error evaluation module in method 3 is less than that in method 4, indicating that the convolutional neural network for establishing a timing error evaluation module has outstanding technical effects.

[0031] In further embodiments, the timing error calculation unit includes an FPGA chip main control module, an error evaluation module connected to the FPGA chip main control module, a time offset algorithm module, a signal processing module, a reconfigurable calculation unit, an anti-interference calculation module, and a loss function accelerator. The timing error calculation unit obtains a timing error value through an error evaluation module and a time offset algorithm module, the error evaluation module obtains a loss value by measuring the influence of the influence parameters of the clock signal on the timing error value, and the time offset algorithm module calculates the timing error value according to the loss value and the phase difference between the clock signal and the ideal clock signal, and the calculation formula of the loss value is: In formula (5), K is the loss value, z is the temperature change value, u is the power fluctuation value, x is the mechanical vibration frequency, g is the average noise of external electromagnetic noise and radio frequency noise, is the loss function mean square error; and the calculation formula of the timing error value is: In formula (6), Q is the timing error value, h is the relative time offset, is the timing error conversion value of the time offset algorithm module. In specific embodiments, the acquisition of the original data amount is realized through the following sensor deployment: Temperature change value (ΔT): through the integrated DS18B20 digital temperature sensor (accuracy ±0.5℃), deployed near the target device clock module, temperature data is collected every 100ms; Power fluctuation value (ΔV): LTC1966 power monitoring chip is used to monitor the power supply voltage in real time (accuracy ±0.1% Vcc), and high-frequency sampling (1kHz) is triggered when the fluctuation exceeds ±5%; Mechanical vibration frequency (f): MEMS vibration sensor (such as ADXL345) is installed to detect 0.1-1000Hz vibration signal, and the main frequency component is extracted through FFT algorithm; Electromagnetic noise amount (g): a wideband radio frequency noise sensor (such as R&S®HMS2710) is used to cover 100kHz-6GHz frequency band, and noise power spectral density (PSD) is calculated in real time.

[0032] Each sensor data is converted into a digital signal through an ADC module (such as ADS1256, 24-bit accuracy), and random noise is removed through Kalman filtering, and then normalized (0-1 standardization) to input the error evaluation module.

[0033] High-precision phase detection is realized through FPGA (such as Xilinx Zynq), and digital phase-locked loop (DPLL) is used to compare the rising edges of the input clock and the ideal clock, with a resolution of 1ps; The relative time offset (Δφ) takes the average of the phase difference of 100 consecutive periods to reduce the influence of random jitter. The time offset algorithm module uses piecewise linear fitting, taking ξ=1 in the low frequency band (<10 MHz) and ξ=0.5 in the high frequency band (≥10 MHz) to compensate for the period nonlinear error of high frequency signals. The final timing error value (ε) is the root mean square (RMS) of the phase difference error and the environmental loss value, which comprehensively reflects the cumulative influence of time domain jitter and environmental interference. After preprocessing the environmental data and phase difference data, the error calculation unit calculates the comprehensive results containing time domain and environmental errors through formulas (4) and (5), and finally outputs the comprehensive results, realizing the closed-loop tracking of "parameter acquisition model calculation error tracing". When the prediction error of 5 consecutive periods is >50ns, the incremental learning algorithm is triggered, and the loss function parameters (α, β, γ, δ) are retrained using the latest 24 hours of data, with an update period of 1 hour. In the edge computing node (such as NVIDIA Jetson Nano), through the task scheduler, the computing power is preferentially allocated to high error scenarios (such as ΔT>20℃ or g>-80dBm), ensuring the real-time performance of calculation (delay<10ms) under complex working conditions. The main controller: ARM+FPGA heterogeneous architecture (such as TI Sitara AM5728) is adopted, ARM core (dual-core Cortex-A15) is responsible for logical control and algorithm scheduling, FPGA unit (Artix-7) realizes phase detection, FFT and other high-speed calculations; 1GB DDR3 memory and 16GB eMMC storage are integrated to support real-time data caching and model parameter storage.

[0034] Analog front end (AFE): Clock signal conditioning circuit: contains limiting amplifier (LTC6268) and Schmidt trigger (SN74LVC1G14) to condition the input clock signal amplitude to 3.3V CMOS level; Multi-channel ADC: ADS127L01 (8 channels, 16 bits, 1MSPS) is used to synchronously collect temperature, voltage, vibration and other analog signals. The parameter information is shown in Table 4. Through the above hardware architecture and algorithm design, the timing error evaluation system can realize high-precision and real-time clock signal error analysis in complex industrial environments, meeting the stringent requirements of intelligent power grid synchronous clock monitoring, communication base station timing calibration and other scenarios. In specific embodiments, the time offset algorithm module calculates the current timing error value based on the phase difference between the clock signal and the ideal clock signal, and corrects the timing error value according to the loss value. Specifically, the time offset algorithm module calculates the current timing error by performing error operation on the phase difference between the clock signal and the ideal clock signal, and then adjusts the timing error value according to the loss value to improve the precision of the timing error value. The time offset algorithm module is mainly used for accurate calculation of the timing error value and is widely used in computer networks, communication systems, aerospace and other fields. Specifically, it can improve the precision and stability of the clock signal by improving the timing error value, reducing the timing error, thereby improving the reliability and performance of the system. At the same time, it can also reduce the system's requirements for high-precision crystal oscillator and clock source, reducing system cost and complexity. The time offset algorithm module obtains the timing error value result as shown in Table 5: As shown in Table 5, four test groups are set up, and two methods are used to obtain the timing error value result. Method 5 uses the timestamp comparison method to calculate the timing error value, and method 6 uses the time offset algorithm module to calculate the timing error value based on the loss value and the phase difference between the clock signal and the ideal clock signal. The error of the timing error value calculated by method 5 is greater than that of method 6. It can be seen that the time offset algorithm module of the present application has outstanding technical effects in calculating the timing error value.

[0035] The time sequence extraction module aligns the clock signal waveforms of different time periods through the dynamic time warping method, captures the time sequence correlation, introduces the Transformer architecture to model the time sequence dependence in long sequences through the gating mechanism, and outputs the time sequence feature vector; The difference operator estimation module simulates the central difference operator through a 3x3 convolution kernel to improve the calculation ability, optimizes the operator parameters through back propagation, and adaptively fits the local change pattern of the signal; and applies different step length difference operators in parallel to capture different time granularity change trends; through the adaptive difference scale selection mechanism, the attention mechanism is fused to weight the difference results of different scales, enhancing the flexibility of feature expression; The spatio-temporal pyramid convolutional network model extracts spatial features of multiple receptive fields in parallel through the use of different dilated rate hole convolutions, performs time pooling of time sequence feature maps of different windows, captures hierarchical time features of short-term fluctuations and long-term trends, and outputs feature representations containing multi-resolution information through cross-layer connection or gating mechanism to fuse spatio-temporal feature maps of different scales; The weighted fusion module maps features of different sources to the same dimensional space through 1x1 convolution or full connection layer, adaptively combines the features output by multiple modules, improves the accuracy of error evaluation, proposes a dynamic feature selection strategy, enhances the generalization ability of the model to different environmental scenes through data-driven adaptive weight learning, introduces a cross-modal feature correlation analysis method to guide the update of the weighting matrix, and improves the rationality of the fusion. The Bayesian uncertainty quantification module introduces Gaussian distribution parameter probability weights in the full connection layer, and approximates the posterior distribution through variational inference or Markov chain Monte Carlo method;Through a double-branch uncertainty estimation method, the accidental uncertainty and the cognitive uncertainty are estimated in parallel. The acceleration module maps the convolution layer and the pooling layer to the parallel logic unit of FPGA, realizes the hardware-level pipeline calculation of the convolution kernel, combines the continuous convolution-batch normalization-activation operation, reduces the memory access overhead, and dynamically switches the calculation branch according to the complexity of the input signal. The data dynamic update module uses the isolation forest or the statistical threshold method to detect abnormal samples, filters the outlier data generated due to sensor failure or sudden interference, adopts the elastic weight consolidation or memory replay technology, retains historical knowledge when updating the model, and avoids catastrophic forgetting.

[0036] As a further technical solution of the application, the signal processing module dynamically adjusts the amplitude of the sensor output signal through a programmable gain amplifier PGA, filters high-frequency noise with an anti-aliasing filter to avoid sampling distortion;Through an optical coupling isolation circuit, the ground loop interference is cut off, ensuring the electrical isolation of the power fluctuation signal and the clock signal;Analog signals are converted into digital quantities by using a multi-channel high-speed ADC, and the timing alignment of temperature, vibration and other environmental parameters and the clock signal is ensured by using a synchronous sampling timer;The phase difference of the clock signal is detected;The phase difference signal with nanosecond resolution is output by comparing the phase of the measured clock and the reference clock through a digital phase discriminator; In specific embodiments, the raw analog signals output by various sensors (temperature, vibration, electromagnetic field, etc.) are first input into a programmable gain amplifier (PGA). The PGA adjusts the amplification factor in real time according to the gain strategy preset by the microcontroller: when the signal amplitude is below the threshold (e.g. <100mV), the gain is automatically increased to the highest 32dB; when the signal amplitude approaches saturation (e.g. >2.8V), the gain is gradually reduced to the lowest 6dB. In the event of a sudden increase in mechanical vibration, the PGA reduces the gain from 24dB to 12dB within 200μs to prevent signal clipping. The gain-adjusted signal enters an anti-aliasing filter (fourth-order Butterworth active filter). The filter operating parameters: the cutoff frequency is dynamically set to 0.4 times the target sampling rate (e.g. when the sampling rate is 1MHz, fc=400kHz), and the stopband attenuation is >80dB @ 1.2×fc. Effect: filters out RF interference (typical value: 900MHz mobile phone signal attenuation 120dB) coupled by sensor wires. The filtered signal passes through a high-speed optocoupler isolation circuit to eliminate 100Hz ripple interference caused by power supply ground loop current. The isolated analog signal enters a multi-channel high-speed ADC (18-bit resolution, 8 channels in parallel). Synchronous control flow: the synchronous sampling timer receives the trigger pulse from the main clock system, and the timer sends the CONVST signal to all ADC channels at the same time. Each channel starts the conversion within a ±50ps time window.

[0037] The reconfigurable computing unit maps the multi-scale convolution kernel in the spatio-temporal pyramid convolution network to the FPGA parallel computing unit, realizes hardware-level acceleration of convolution operation through pipeline technology, designs a special addition tree circuit for mean square error calculation in the loss function, and parallelly accumulates N sample error values, reducing the calculation delay from 100μs of CPU to 5μs of FPGA; FPGA is responsible for high-speed signal processing and algorithm acceleration, CPU processes control logic and system scheduling, and DSP performs complex floating-point operations; according to real-time calculation load, dynamically adjust the hardware configuration, reduce the peak power consumption by 30% while maintaining the accuracy; The working process of the reconfigurable computing unit is a highly cooperative and dynamically optimized process, which realizes high performance and low power consumption of timing error evaluation through hardware algorithm cooperative design. The following is a detailed description of its core workflow: In specific embodiments, task initialization and configuration, CPU startup and parameter setting, CPU initialization system, load basic configuration parameters (such as convolution kernel size, sample number N, error threshold). According to the application scene (such as laboratory environment or industrial site), read the pre-trained spatio-temporal pyramid convolution network weight parameters from the storage. FPGA configuration and resource allocation, CPU sends the initial configuration bit stream to FPGA, configures the reconfigurable logic unit of FPGA (such as convolution engine, addition tree circuit). FPGA allocates DSP modules for convolution operation, BRAM for caching intermediate data, and LUT for building control logic according to task requirements. DSP initialization, CPU starts DSP, loads the program library of Bayesian uncertainty quantization and other complex floating point operations. Set up the data transmission channel between DSP and FPGA (such as high-speed serial port or shared memory). Then signal processing and feature extraction, data input and preprocessing, FPGA receives multi-channel sensor data (clock signal, temperature, voltage, vibration, etc.) through the ADC interface. The programmable gain amplifier (PGA) dynamically adjusts the signal amplitude, and the anti-aliasing filter filters out high-frequency noise. When performing spatio-temporal pyramid convolution operation, multi-scale feature extraction, FPGA's convolution engine performs 3x3, 7x7, 15x15, etc. Different scale convolution operations are performed in parallel to extract the multi-resolution spatio-temporal features of the clock signal. The data flows in the pipeline according to the order of "input buffer → convolution kernel loading → multiplication and accumulation operation → result output", and the pipeline period of each stage is 2-5ns, realizing high-frequency parallel processing of convolution operation. In specific embodiments, the convolution results of different scales are merged through a weighted fusion module to generate a feature vector containing multi-scale information. The feature vector is cached to the on-chip memory of FPGA, waiting for subsequent processing.

[0038] Then error calculation and optimization, mean square error (MSE) calculation, FPGA's dedicated addition tree circuit receives the feature vector and target value, and calculates the error square of each sample in parallel. The error square value is quickly accumulated through a tree structure (such as a 16-value addition tree only needs 4-level calculation), and finally divided by the sample number N to get the MSE. The calculation delay is only 5μs, which is 20 times faster than CPU. Then Bayesian uncertainty quantization, PGA sends the MSE result to DSP, DSP executes Monte Carlo Dropout and other algorithms to calculate the uncertainty (such as variance) of error prediction. The uncertainty result is fed back to FPGA for dynamic adjustment of model weight or sampling strategy. The loss function optimization process needs to set FPGA to calculate the gradient and update the model weight according to the MSE and uncertainty result. In specific applications, set up a special circuit to accelerate gradient calculation (such as transpose convolution) to further improve optimization efficiency.

[0039] In the process of dynamic reconfiguration and power optimization, when performing load monitoring and analysis, the CPU monitors the computing load of the FPGA and DSP in real time (such as task queue length, resource utilization). Analyze the current computing bottleneck (such as convolution operation saturation, addition tree waiting data). In specific embodiments, hardware configuration needs to be dynamically adjusted. In specific embodiments, under light load, the CPU sends a low-power configuration bit stream to the FPGA, turns off part of the convolution engine, and reduces the clock frequency (such as from 200MHz to 100MHz). In specific embodiments, under heavy load, all computing resources are activated, the clock frequency is increased, and even dedicated computing modules are added through partial reconfiguration. Clock gating stops clock supply to unused modules, reducing power consumption by 15-20%. Voltage frequency scaling (DVFS) dynamically adjusts the voltage according to the load (such as from 1.2V to 0.9V), and the power consumption is proportional to the square of the voltage. Multiple functions reuse the same hardware module (such as the addition tree circuit is used for other calculations when idle). In specific embodiments, the FPGA integrates all computing results to generate the final timing error value and uncertainty confidence interval. The results are transmitted to the CPU through a high-speed interface (such as USB 3.0 or Ethernet). The CPU evaluates the error results and triggers corresponding actions (such as clock calibration, alarm, and data recording). The system enters the next round of data acquisition and processing cycle, forming a closed-loop feedback mechanism. This research maps the rule calculation in neural networks (such as convolution) to FPGA hardware, and the irregular control logic is processed by the CPU, and the complex floating-point operation is given to the DSP, realizing complementary advantages. Through spatial parallelism, multiple convolution kernels process features in different regions simultaneously. Through time parallelism, pipeline technology enables different computing stages to overlap execution.

[0040] Through load-aware dynamic reconfiguration, the peak power consumption is reduced by 30% while maintaining computing accuracy, significantly improving energy efficiency. The total delay from data input to error result output is ≤100μs, meeting the needs of industrial real-time control systems. Among them, the 5G base station clock synchronization: real-time monitoring and compensation of crystal oscillator frequency drift, ensuring the synchronization accuracy between base stations to ±10ns. With this reconfigurable computing unit, the timing error evaluation system achieves computing performance close to supercomputers in resource-constrained embedded devices, while maintaining low power consumption advantages, providing core technical support for industrial-grade high-precision timing applications.

[0041] The anti-interference computing module deploys a multi-layer electromagnetic shield with conductivity > 5e6 S / m in front of the sensor, and a π-type filter circuit at the power input end to suppress radio frequency interference in the 50MHz-2GHz frequency band; a constant temperature crystal oscillator or temperature sensor is used to monitor the clock circuit temperature in real time, and a linear interpolation algorithm is used to dynamically adjust the clock frequency compensation coefficient; the least mean square (LMS) algorithm is used to separate noise components from mixed signals, and the signal-to-noise ratio is improved by 20dB. The loss function accelerator uses a carry lookahead adder (CLA) to realize parallel accumulation of N sample errors, decouples the calculation time from the number of samples N, integrates a floating point operation unit (FPU) to accelerate complex operations such as square root and exponential for gradient calculation optimization, and designs a reverse computation graph hardware mapping for gradient backpropagation in convolutional neural networks, converting gradient matrix operations into distributed memory access and parallel multiplication and accumulation operations on the FPGA, with a 5-fold increase in gradient calculation speed.

[0042] A three-layer structure is used, with the inner layer being a high permeability material (such as μ-metal), the middle layer being a high conductivity material (such as copper, with a conductivity of 5.96e7 S / m), and the outer layer being an aluminum alloy (with a conductivity of 3.5e7 S / m) The shield thickness is optimized through simulation (typical values: inner layer 0.5mm, middle layer 1mm, outer layer 2mm). The joints are sealed with finger springs or conductive rubber to ensure electromagnetic continuity. Key interfaces (such as sensor signal lines) use feedthrough filters with a cutoff frequency of 10MHz. An LC π-type structure is used, with L1=10μH (high-frequency ferrite beads), C1=C2=100nF (multilayer ceramic capacitors). A TVS diode (response time < 1ns) is connected in parallel at the power input to suppress surge interference. The filter cutoff frequency is designed to be 5MHz, providing > 60dB attenuation in the 50MHz-2GHz frequency band. A high-precision OCXO (frequency stability ±10^-9) is used, with a built-in PID controller to maintain the crystal oscillator temperature at 85°C±0.1°C. A PT1000 temperature sensor (accuracy ±0.1°C) is installed near the crystal oscillator. A digital PID algorithm is implemented in the FPGA, with a sampling period of 1ms and a PWM signal output to control the heating resistor.

[0043] While specific embodiments of the application have been described above, it will be appreciated that those skilled in the art within the scope of the application can make modifications, substitutions and changes in the form and details of the method and system described above without departing from the spirit and scope of the application. For example, it is well within the scope and spirit of the application to combine various of the illustrative steps of the above methods to carry out essentially the same function to achieve essentially the same result in substantially the same way. Accordingly, the scope of the application should be determined sole by the appended claims.

Claims

1. A data sampling timing error evaluation method based on an evaluation model, characterized by: The steps include: Step 1: Receive a clock signal from the device under test through a sampling module, wherein the sampling module includes a clock receiving unit, a clock signal recovery unit, and a frequency output unit; In step 1, the output end of the clock receiving unit is connected to the input end of the clock signal recovery unit, and the output end of the clock signal recovery unit is connected to the input end of the frequency output unit; Step 2: Using a Fourier phase difference algorithm to remove harmonic interference from the clock signal and the ideal clock signal, and calculate the phase difference between the clock signal and the ideal clock signal; Step 3: Using a timing error evaluation module to evaluate factors affecting the clock signal and calculate a timing error value, the timing error evaluation method includes a clock signal feature recognition unit, an evaluation model establishment unit, and a timing error calculation unit; In step three, the output end of the clock signal feature recognition unit is connected to the input end of the evaluation model establishment unit, and the output end of the evaluation model establishment unit is connected to the input end of the timing error calculation unit; Step 4: Wait for the next clock signal and repeat the above steps to achieve dynamic tracking; Step 5: Use an online data analysis platform to further analyze and process the timing error value. The online data analysis platform allows users to view the timing error results through dragging and scrolling operations, and uses error curves to facilitate user data analysis.

2. The data sampling timing error evaluation method based on the evaluation model according to claim 1, characterized in that: The clock signal receiving unit uses a CMOS clock input circuit to receive a clock signal from the device under test. The CMOS clock input circuit is connected to the device under test through a network time protocol server. The network time protocol server establishes a synchronous time relationship with the device under test through the network time protocol to achieve equally spaced synchronous reception of clock signals. The clock signal receiving unit also integrates a PTP network clock with an accuracy of ±20ns and a Beidou / GPS satellite clock with an accuracy of ±10ns. The clock signal receiving unit also has a built-in anti-interference electromagnetic shielding cavity, adopts a multi-layer PCB board differential routing design, and cooperates with an active noise cancellation circuit to increase the electromagnetic interference suppression ratio in the 50MHz-2GHz frequency band to more than 60dB. The clock receiving unit is also provided with a phase noise estimator and an adaptive filter to analyze the phase jitter characteristics of the input clock signal in real time and dynamically adjust the compensation parameters.

3. The data sampling timing error evaluation method based on the evaluation model according to claim 1, characterized in that: The clock signal recovery unit adopts a third-order digital phase-locked loop circuit to realize the frequency recovery of the clock signal, and identifies and eliminates burst pulse interference through a dynamic threshold detection algorithm; the third-order digital phase-locked loop circuit includes a frequency tracking module, a feedback adjustment module and a distortion recovery module. The frequency tracking module filters the clock signal through the filter of the third-order digital phase-locked loop circuit, and the feedback adjustment module performs feedback adjustment and control on the filtered clock signal through the digital controller and voltage-controlled oscillator of the third-order digital phase-locked loop circuit. The digital controller generates an analog conversion correction signal, and the voltage-controlled oscillator adjusts the output frequency of the clock signal according to the analog conversion correction signal. The distortion recovery module puts the third-order digital phase-locked loop circuit into a locked state through the feedback loop control of the voltage-controlled oscillator to realize the distortion recovery of the clock signal. The output end of the frequency tracking module is connected to the input end of the feedback adjustment module, and the output end of the feedback adjustment module is connected to the input end of the distortion recovery module.

4. The data sampling timing error evaluation method based on the evaluation model according to claim 1, characterized in that: The frequency output unit uses a DSP digital signal processing chip to process the clock signal and output the clock signal frequency. The DSP digital signal processing chip uses a frequency synthesis algorithm to perform amplitude weighted superposition and digital-to-analog conversion on the clock signal to obtain the clock signal frequency.

5. The data sampling timing error evaluation method based on the evaluation model according to claim 1, characterized in that: The working method of the Fourier phase difference algorithm is: Step 1: Perform harmonic filtering on the clock signal and the ideal clock signal through a harmonic filter to remove harmonic components and retain the fundamental component. The harmonic filter achieves harmonic component filtering through the resonance characteristics of the resonant circuit; Step 2: Perform Fourier transform on the fundamental components of the filtered clock signal and the ideal clock signal. The Fourier transform obtains the frequency spectrum representation corresponding to the clock signal and the ideal clock signal by weighted summation of the frequencies of the clock signal and the ideal clock signal. The Fourier fundamental spectrum expression of the clock signal and the ideal clock signal is: In formula (1), is the Fourier fundamental spectrum of the clock signal, is the sampling interval of the clock signal, is the clock signal, t is the time, is the Fourier fundamental spectrum of the ideal clock signal, is the sampling interval of the ideal clock signal, is an ideal clock signal, is the frequency of the clock signal, is the frequency of the ideal clock signal; step three, calculate the fundamental phase angle of the clock signal and the ideal clock signal at the frequency point by the phase formula to obtain the relative time offset of the clock signal and the ideal clock signal. The fundamental phase angle calculation formula of the clock signal and the ideal clock signal is: In formula (2), represents the inverse trigonometric function, is the imaginary part of the fundamental spectrum of the clock signal, is the real part of the fundamental spectrum of the clock signal, is the fundamental phase angle of the clock signal, is the imaginary part of the fundamental spectrum of the ideal clock signal, is the real part of the fundamental spectrum of the ideal clock signal, is the fundamental phase angle of the ideal clock signal; step 4, finally subtracting the fundamental phase angle of the clock signal from the fundamental phase angle of the ideal clock signal to obtain the phase difference between the clock signal and the ideal clock signal.

6. The data sampling timing error evaluation method based on the evaluation model according to claim 1, characterized in that: The clock signal feature recognition unit uses a waveform timing diagram to convert the clock signal into a time domain image, and determines the clock signal and influencing parameters through time domain feature extraction and time domain analysis. The influencing parameters of the clock signal include at least temperature change value, power supply fluctuation value, mechanical vibration frequency, external electromagnetic noise amount and radio frequency noise amount.

7. The data sampling timing error evaluation method based on the evaluation model according to claim 1, characterized in that: The working method of the evaluation model building unit is: Step 1: Normalize the parameters affecting the clock signal using fractional scaling normalization, introduce the feature importance weight matrix W, dynamically adjust the scaling factor according to the contribution of each influencing parameter to the timing error, calculate the parameter importance through gradient back propagation, and the feature importance weight matrix The output function is: In formula (3), is the i-th influencing parameter, Loss is the model loss function; represents a feature importance weight matrix; the decimal scaling normalization scales the influencing parameters of the clock signal to the training set of the timing error evaluation module through maximum value scaling; wherein the timing error evaluation module includes a timing extraction module, a differential operator estimation module, a spatiotemporal pyramid convolutional network model, a weighted fusion module, a Bayesian uncertainty quantification module, an acceleration module and a data dynamic update module; Step 2: Then, a convolutional neural network is used to iteratively train the training set of the timing error evaluation module to obtain an error evaluation module. The convolutional neural network extracts and merges the influencing parameters of the clock signal through the convolution kernel, and then iteratively updates the error evaluation module weights through the residual network to achieve an error evaluation module with optimal recognition effect; Step 3: Finally, the accuracy of the error evaluation module is verified using a confusion matrix optimizer. The confusion matrix optimizer calculates the accuracy of the error evaluation module using a moment estimation algorithm. The calculation formula for the accuracy of the error evaluation module is: In formula (4), R is the accuracy of the error evaluation module, is the evaluation value of the error evaluation module, is the evaluation value subscript of the error evaluation module, n is the evaluation times of the error evaluation module, m is the actual value of the error evaluation, is the weighted average of the moment estimation algorithm.

8. The data sampling timing error evaluation method based on the evaluation model according to claim 1, characterized in that: The timing error calculation unit includes an FPGA chip main control module and an error evaluation module connected to the FPGA chip main control module, a time offset algorithm module, a signal processing module, a reconfigurable computing unit, an anti-interference computing module and a loss function accelerator; The timing error calculation unit obtains a timing error value through an error evaluation module and a time offset algorithm module. The error evaluation module measures the influence of the influencing parameters of the clock signal on the timing error value through a loss function to obtain a loss value. The time offset algorithm module calculates the timing error value based on the loss value and the phase difference between the clock signal and the ideal clock signal. The calculation formula of the loss value is: In formula (5), K is the loss value, z is the temperature change value, u is the power supply fluctuation value, x is the mechanical vibration frequency, g is the average noise amount of external electromagnetic noise and radio frequency noise, is the mean square error of the loss function; the calculation formula of the timing error value is: In formula (6), Q is the timing error value, h is the relative time offset, It is the timing error conversion value of the time offset algorithm module.

9. The data sampling timing error evaluation method based on the evaluation model according to claim 7, characterized in that: The timing extraction module uses a dynamic time warping method to align clock signal waveforms in different time periods to capture timing correlations. It also introduces a Transformer architecture to model timing dependencies in long sequences through a gating mechanism and outputs a timing feature vector. The difference operator estimation module improves computing power by simulating a central difference operator using a 3×3 convolution kernel. It optimizes operator parameters through backpropagation to adaptively fit local signal variation patterns. It also applies difference operators of different step sizes in parallel to capture changing trends at different time granularities. It also proposes an adaptive difference scale selection mechanism that integrates the weighted difference results of different scales using an attention mechanism to enhance the flexibility of feature expression. The spatiotemporal pyramid convolutional network model uses dilated convolutions with different expansion rates to extract spatial features of multiple receptive fields in parallel, performs time pooling of different windows on the time series feature maps, captures the hierarchical temporal features of short-term fluctuations and long-term trends, and fuses spatiotemporal feature maps of different scales through cross-layer connections or gating mechanisms to output feature representations containing multi-resolution information. The weighted fusion module maps features from different sources to the same dimensional space through 1×1 convolution or fully connected layers, adaptively weighting and combining features output by multiple modules to improve the accuracy of error assessment. It also proposes a dynamic feature selection strategy and enhances the model's generalization ability to different environmental scenarios through data-driven adaptive weight learning. It also introduces a cross-modal feature correlation analysis method to guide the update of the weighting matrix and improve the rationality of fusion. The Bayesian uncertainty quantification module introduces Gaussian distribution parameter probability weights in the fully connected layer, approximates the posterior distribution through variational inference or Markov chain Monte Carlo method; and estimates aleatoric uncertainty and epistemic uncertainty in parallel through a two-branch uncertainty estimation method; The acceleration module maps the convolutional and pooling layers to the parallel logic units of the FPGA to implement hardware-level pipeline calculations of the convolution kernels; combines continuous convolution-batch normalization-activation operations to reduce memory access overhead; and dynamically switches calculation branches based on the complexity of the input signal. The data dynamic update module uses isolation forest or statistical threshold methods to detect abnormal samples, filter outlier data caused by sensor failure or sudden interference, and adopts elastic weight consolidation or memory playback technology to retain historical knowledge when updating the model to avoid catastrophic forgetting.

10. The data sampling timing error evaluation method based on the evaluation model according to claim 8, characterized in that: The signal processing module dynamically adjusts the amplitude of the sensor output signal through a programmable gain amplifier (PGA), and uses an anti-aliasing filter to filter out high-frequency noise and avoid sampling distortion. It cuts off ground loop interference through an optocoupler isolation circuit to ensure electrical isolation between the power supply fluctuation signal and the clock signal. It uses a multi-channel high-speed ADC to convert analog signals into digital quantities, and uses a synchronous sampling timer to ensure that environmental parameters such as temperature and vibration are aligned with the timing of the clock signal. It also performs phase difference detection on the clock signal: a digital phase detector compares the phase of the measured clock with the reference clock and outputs a phase difference signal with nanosecond resolution. The reconfigurable computing unit maps the multi-scale convolution kernels in the spatiotemporal pyramid convolutional network to the FPGA parallel computing unit, achieving hardware-level acceleration of convolution operations through pipelining technology. For the mean square error calculation in the loss function, a dedicated addition tree circuit is designed to accumulate N sample error values ​​in parallel, reducing computational latency from 100μs on the CPU to 5μs on the FPGA. The FPGA is responsible for high-speed signal processing and algorithm acceleration, while the CPU handles control logic and system scheduling, and the DSP performs complex floating-point operations. The hardware configuration is dynamically adjusted based on the real-time computing load, reducing peak power consumption by 30% while maintaining accuracy. The anti-interference calculation module deploys a multi-layer electromagnetic shield with a conductivity of > 5e6 S / m at the front end of the sensor, coupled with a π-type filter circuit at the power input to suppress radio frequency interference in the 50MHz to 2GHz frequency band. The module monitors the clock circuit temperature in real time using a constant-temperature crystal oscillator or temperature sensor, and dynamically adjusts the clock frequency compensation coefficient using a linear interpolation algorithm. The module also uses a least mean square (LMS) algorithm to separate noise components from mixed signals, improving the signal-to-interference ratio by 20dB. The loss function accelerator uses a carry-lookahead adder (CLA) to implement parallel accumulation of N sample errors, decoupling the calculation time from the number of samples N. It integrates a floating-point arithmetic unit (FPU) to accelerate complex operations such as square roots and exponentials to optimize gradient calculations. For gradient backpropagation in convolutional neural networks, a reverse calculation graph hardware mapping is designed, converting gradient matrix operations into distributed memory access and parallel multiplication and accumulation operations on the FPGA, thereby increasing the gradient calculation speed by 5 times.

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