Unsealing analysis method for integrated circuit

Abstract

The invention discloses an unsealing analysis method for an integrated circuit, which comprises the following steps of: 1, confirming a laser area: putting the integrated circuit into a laser machine table, importing an X-ray diagram into operation software of the laser machine table, and dragging the X-ray diagram to coincide with a back image of the integrated circuit; and step 2, removing the plastic package body by laser: positioning a laser area of the integrated circuit and carrying out laser treatment until the base is exposed, and forming an integrated circuit groove on the back surface of the integrated circuit at the same time. The invention belongs to the field of semiconductor integrated circuits, and particularly relates to an unsealing analysis method of an integrated circuit. According to the method, the back unsealing area of the integrated circuit is accurately positioned through the laser machine table and the sample X-ray diagram, and the problem that welding spots on a base are not electrically connected due to the fact that the chip base is removed through a traditional method is effectively solved, so that hot spot analysis can be effectively carried out, and the laboratory analysis capability is improved.

Description

Technical Field

[0001] The present invention belongs to the technical field of semiconductor integrated circuits, and in particular relates to an integrated circuit unsealing analysis method. Background Art

[0002] In today's digital age, integrated circuits (ICs), as core components of modern electronic devices, are widely used in key areas such as communications, computers, automotive electronics, and aerospace. The performance and reliability of ICs are directly linked to the stable operation of the entire electronic system, making failure analysis and performance testing crucial. Backside hotspot analysis, an effective method for accurately locating abnormally hot areas within ICs and identifying potential failure points, plays a vital role in IC quality assessment and fault diagnosis. Currently, the commonly used unsealed analysis method for backside hotspot analysis involves inverting the sample and laser-treating the bottom to remove the plastic seal, exposing the sample base. Next, under a low-magnification microscope, the base is removed with tweezers to expose the silver adhesive. The silver adhesive is then soaked in acetone for 10 minutes, softened, and scraped off with tweezers to expose the silicon substrate on the backside of the chip, allowing hotspot analysis to proceed. However, this traditional method has significant limitations. It is only applicable to samples without solder joints on the base. For samples with solder joints on the base, hotspot analysis may experience electrical disconnection, making it impossible to accurately capture hotspot information during chip operation, significantly impacting the validity and accuracy of the analysis results. With the rapid advancement of integrated circuit technology, packaging formats are constantly innovating. An increasing number of integrated circuits are adopting complex packaging structures, many of which have solder joints on their bases. Furthermore, in advanced packaging technologies such as system-in-package (SiP) and flip-chip packaging, base solder joints are an indispensable component. Traditional decapsulation analysis methods are no longer sufficient for backside hotspot analysis of samples with these bases, severely restricting the performance of integrated circuit failure analysis. To adapt to new trends in integrated circuit technology and address the technical challenges of existing backside hotspot analysis methods when dealing with samples with bases containing solder joints, there is an urgent need to develop a new decapsulation analysis method for integrated circuits. This method should be able to effectively remove the packaging material and expose the silicon substrate on the backside of the chip while ensuring electrical connectivity. This method would enable accurate backside hotspot analysis of various integrated circuit samples, providing reliable technical support for integrated circuit quality control, failure diagnosis, and performance optimization. Summary of the Invention

[0003] In view of the above situation, in order to overcome the defects of the prior art, the present invention provides an integrated circuit unsealing analysis method, which effectively solves the problem in the current market that the solder joints on the base are not electrically connected due to the removal of the chip base.

[0004] The technical solution adopted by the present invention is as follows: The present invention proposes an integrated circuit unsealing analysis method,

[0005] Step 1: Confirm the laser area: Place the integrated circuit into the laser machine, import the X-ray image into the laser machine's operating software, and drag the X-ray image to overlap the image of the back of the integrated circuit;

[0006] Step 2: Laser removal of the plastic package: Locate the area of ​​the integrated circuit to be lasered and perform lasering until the base is exposed, while forming an integrated circuit groove on the back of the integrated circuit;

[0007] Step 3: Use aqua regia to remove the base: Place the integrated circuit on a heating table and drip aqua regia into the integrated circuit slot to corrode and remove the base, leaving only the base part where the solder joint is located;

[0008] Step 4: Remove the silver glue to expose the back of the chip.

[0009] Furthermore, after dragging the X-ray image to overlap with the back image of the integrated circuit in step 1, the back of the integrated circuit is first fully lasered to thin the plastic package, and then the chip area is framed according to the X-ray image.

[0010] Furthermore, in the step 2, the area of ​​the integrated circuit to be lasered is selected, and the area to be lasered does not belong to the solder joint area on the base.

[0011] Furthermore, in step three, the aqua regia is prepared by mixing hydrochloric acid and nitric acid in a ratio of 3 to 1.

[0012] Furthermore, in step 4, the back side of the chip is exposed, and finally an X-ray image is used to confirm the effect, ensuring that the solder joints on the base are retained while the back side of the chip is exposed.

[0013] Furthermore, the step 4 of removing the silver paste includes: firstly soaking the integrated circuit in a cleaning solution, and removing the silver paste under a microscope after it softens, thereby exposing the back side of the chip.

[0014] Furthermore, the cleaning liquid may be acetone.

[0015] Furthermore, it includes an integrated circuit, a plastic package is provided on the integrated circuit, pin one and pin two are provided at both ends of the bottom of the integrated circuit, silver glue is provided above the base, a chip is provided above the silver glue, pin one is connected to the solder point provided on the chip through a solder wire, and pin two is connected to the solder point provided on the base through a solder wire.

[0016] The beneficial effects achieved by the present invention using the above structure are as follows: This solution proposes a method for analyzing the unsealing of integrated circuits. Through a laser machine and a sample X-ray image, the unsealing area on the back can be accurately located. This method solves the problem of no electrical connection between the solder joints on the base caused by using traditional methods to remove the chip base, thereby effectively performing hotspot analysis and improving laboratory analysis capabilities. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Figure 1 A schematic diagram of the confirmation laser area of ​​an integrated circuit decapsulation analysis method proposed by the present invention;

[0018] Figure 2 A schematic diagram of laser removal of part of the plastic package of an integrated circuit unsealing analysis method proposed by the present invention;

[0019] Figure 3 A schematic diagram of aqua regia base removal in an integrated circuit unsealing analysis method proposed by the present invention;

[0020] Figure 4 A schematic diagram of removing silver glue in an integrated circuit unsealing analysis method proposed by the present invention;

[0021] Figure 5 A schematic diagram of an integrated circuit slot for an integrated circuit unsealing analysis method proposed by the present invention.

[0022] Among them, 1. integrated circuit; 2. plastic package; 3. pin one; 31. pin two; 4. base; 5. silver glue; 6. chip; 7. welding wire; 8. X-ray image; 9. back of integrated circuit; 10. integrated circuit slot; 11. solder joint.

[0023] The accompanying drawings are used to provide further understanding of the present invention and constitute a part of the specification. They are used to explain the present invention together with the embodiments of the present invention and do not constitute a limitation of the present invention. DETAILED DESCRIPTION

[0024] The technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, rather than all the embodiments; based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of the present invention.

[0025] In the description of the present invention, it should be understood that terms such as "upper", "lower", "front", "back", "left", "right", "top", "bottom", "inside" and "outside" indicating directions or positional relationships are based on the directions or positional relationships shown in the accompanying drawings. They are only for the convenience of describing the present invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific direction, be constructed and operated in a specific direction. Therefore, they should not be understood as limiting the present invention.

[0026] like Figure 1-Figure 5 As shown, the present invention proposes an integrated circuit unsealing analysis method.

[0027] Step 1: Confirm the laser area: Place the integrated circuit (IC) with its back side 9 facing upwards into the laser machine. Adjust the lens to the appropriate magnification and import the high-definition X-ray image 8 into the laser machine's operating software. Use the software calibration function to ensure that the X-ray image 8 matches the actual size of the integrated circuit 1 at the pixel level (error ≤ 5μm). Use the coordinate alignment tool to drag the X-ray image 8 to ensure that the positioning mark on the back side 9 of the integrated circuit completely overlaps with the X-ray image 8, providing a coordinate reference for subsequent precise laser processing.

[0028] Step 2: Laser removal of the plastic package: Corresponding to the outline of the chip 6 in the X-ray image 8, the area where the chip 6 is located is selected as the laser area through the software, while avoiding the area of ​​the solder joints 11 on the base 4. Laser layer by layer until the base 4 is completely exposed to avoid damaging the solder joints 11 and the internal electrical connections. At the same time, an integrated circuit groove 10 is formed on the back side 9 of the integrated circuit.

[0029] Step 3: Remove the base with aqua regia: Fix the integrated circuit 1 on the heating table to improve the reaction efficiency. Use a dropper to absorb the freshly prepared aqua regia and slowly drip it into the groove of the integrated circuit 1 to ensure that the aqua regia completely covers the base 4 area; after reacting for 5 seconds, immediately rinse with anhydrous acetone (each rinse time ≤ 10 seconds to prevent excessive corrosion), and then place the integrated circuit 1 on the heating table (temperature 80-100℃); repeat the above steps until the base 4 is completely corroded, leaving only the solder joint 11 area and the silver glue 5 under the chip 6.

[0030] Step 4: Remove the silver glue: Immerse the integrated circuit 1 in analytical grade acetone solution (the liquid surface must completely cover the silver glue area) and soak it at room temperature for 10 minutes to fully soften the silver glue 5; then move it to the stage of a low-magnification microscope (magnification 20-50x) and use pointed tweezers (tip diameter ≤ 0.1mm) to gently scrape along the interface between the silver glue 5 and the chip 6 to avoid scratching the chip silicon substrate; after scraping, rinse the chip surface with ultrapure water and expose the back of the chip 6 after drying to provide a complete silicon surface for subsequent hotspot analysis.

[0031] After the four corners on the back side of the integrated circuit 9 in step 1 completely overlap with the four corners on the X-ray image 8, the thickness of the plastic package 2 is first thinned from the initial value to 200-300μm through a global laser thinning process to reduce the difficulty of subsequent local laser processing; then, based on the position coordinates of the solder joint 11 in the X-ray image 8, the avoidance area parameters are set in the software to ensure that the selected chip 6 area does not overlap with the solder joint 11 area, achieving precise positioning and a laser effect without damaging the solder joints.

[0032] After lasering the integrated circuit 1 base in step 2, the surface of the base 4 is observed in real time through a microscope. If any residual plastic package debris is found, it needs to be cleaned and removed. The X-ray image 8 is then called a second time, and the positional relationship between the chip 6 area and the solder joint 11 area is verified through the software overlay function. After confirmation, a second laser trimming is performed to ensure that the base 4 is completely exposed except for the area where the solder joint 11 is located.

[0033] In step 3, aqua regia is prepared by mixing hydrochloric acid and nitric acid in a ratio of 3 to 1 (nitric acid is poured slowly into hydrochloric acid to avoid a violent reaction), and is prepared and used immediately to avoid volatilization loss; the temperature of the heating table needs to be monitored in real time by a thermocouple to ensure a uniform reaction temperature and prevent local overheating from causing corrosion in the solder joint 11 area.

[0034] After the back of the chip 6 is exposed in step 4, the X-ray image 8 and the actual object need to be compared again by double image superposition through a microscope to ensure that the solder joints on the base (4) are retained while the back of the chip (6) is exposed. It is confirmed whether the solder joint 11 area on the base 4 is completely retained and whether there is no silver glue residue on the back of the chip 6; if an abnormality is found, it can be adjusted through local etching (for residual silver glue) or solder joint repair (for slight corrosion) process to ensure that the electrical connection requirements of the hot spot analysis are met.

[0035] Immersing in the cleaning solution causes the silver glue 5 to swell and soften, and then mechanically removed under a microscope to separate the silver glue 5 from the back of the chip 6. The cleaning solution prevents physical scratches on the surface of the chip 6, ensuring the integrity of the circuit layer on the back of the chip 6, facilitating subsequent failure analysis.

[0036] Acetone, as an organic solvent, is miscible with the resin component in the silver glue 5, destroying the molecular structure of the silver glue 5 and causing it to lose its adhesive force. At the same time, it has no corrosive effect on the chip 6 and the base 4. There is little residue after cleaning, which does not affect subsequent microscopic observation and testing.

[0037] The plastic package 2 wraps the internal structure, the chip 6 is bonded to the base 4 through silver glue 5, the pin 1 3 is connected to the chip 6 solder point through the welding wire 7, and the pin 2 31 is connected to the base 4 solder point to form a complete electrical path.

[0038] The above is the overall workflow of the present invention. Just repeat this step next time you use it.

[0039] It should be noted that, in this document, relational terms such as first and second, etc., are used only to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations. Moreover, the terms "comprises," "comprising," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that includes a list of elements includes not only those elements but also other elements not explicitly listed, or elements inherent to such process, method, article, or apparatus.

[0040] While embodiments of the present invention have been shown and described, it will be appreciated by those skilled in the art that various changes, modifications, substitutions, and variations may be made to these embodiments without departing from the principles and spirit of the invention, and that the scope of the invention is defined by the appended claims and their equivalents.

[0041] The present invention and its embodiments are described above. This description is not restrictive. The drawings show only one embodiment of the present invention, and the actual structure is not limited thereto. In short, if a person skilled in the art is inspired by this and, without departing from the purpose of the present invention, designs structures and embodiments similar to this technical solution without inventiveness, they shall fall within the scope of protection of the present invention.

Claims

1. A method for analyzing the unsealing of an integrated circuit, characterized by: Step 1: Confirm the laser area: Place the integrated circuit (1) into the laser machine, import the X-ray image (8) into the operating software of the laser machine, and drag the X-ray image (8) to overlap the image of the back of the integrated circuit (9); Step 2: Laser removal of the plastic package: locate the area of ​​the integrated circuit (1) to be lasered and perform lasering until the base is exposed, and at the same time form an integrated circuit groove (10) on the back side (9) of the integrated circuit; Step 3: Use aqua regia to remove the base: Place the integrated circuit (1) on a heating table, drip aqua regia into the groove of the integrated circuit (1), so that the base is corroded and removed, leaving only the base portion where the solder joint is located; Step 4: Remove the silver glue to expose the back of the chip (6).

2. The method for analyzing the unsealing of an integrated circuit according to claim 1, wherein: After dragging the X-ray image (8) to overlap with the image of the back side of the integrated circuit (9) in step 1, the back side of the integrated circuit (9) is firstly subjected to full laser treatment to thin the plastic package (2), and then the chip area is framed corresponding to the X-ray image (8).

3. The method for analyzing the unsealing of an integrated circuit according to claim 1, wherein: In the step 2, the area of ​​the integrated circuit (1) that needs laser treatment is selected, and the area that needs laser treatment does not belong to the solder joint area on the base (4).

4. The method for analyzing the unsealing of an integrated circuit according to claim 1, wherein: In the step 3, aqua regia is prepared by mixing hydrochloric acid and nitric acid in a ratio of 3 to 1.

5. The method for analyzing the unsealing of an integrated circuit according to claim 1, wherein: In the fourth step, the back of the chip (6) is exposed, and finally the effect is confirmed by an X-ray image (8) to ensure that the solder joints on the base (4) are retained while the back of the chip (6) is exposed.

6. The method for analyzing the unsealing of an integrated circuit according to claim 1, wherein: Removing the silver glue in step 4 includes: first soaking the integrated circuit (1) in a cleaning solution, and removing the silver glue (5) under a microscope after it softens, exposing the back of the chip (6).

7. The method for analyzing the unsealing of an integrated circuit according to claim 6, wherein: The cleaning liquid may be acetone.

8. The method for analyzing the unsealing of an integrated circuit according to claim 1, wherein: The invention comprises an integrated circuit (1), wherein a plastic package (2) is provided on the integrated circuit (1), pin 1 (3) and pin 2 (31) are provided at both ends of the bottom of the integrated circuit (1), silver glue (5) is provided above the base (4), a chip (6) is provided above the silver glue (5), the pin 1 (3) is connected to a soldering point provided on the chip (6) through a soldering wire (7), and the pin 2 (31) is connected to a soldering point provided on the base (4) through a soldering wire (7).

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