PCBA automatic test system and method

Abstract

The invention relates to a PCBA automatic testing system and method, and relates to the technical field of PCBA automatic testing, and the system comprises a multi-source data collection module which is used for collecting chip dynamic power consumption waveform, PCB interlayer temperature gradient, and multi-source data of signal loop impedance change, and eliminating the sampling delay error of a sensor through a synchronous collection time sequence alignment algorithm; transmitting the acquired multi-source data to a dynamic modeling engine; according to the invention, by dynamically fusing the multi-physical-quantity data and adaptively generating the test path, the system can detect the fault of the PCBA more comprehensively and accurately, the detection efficiency is improved, and the false detection rate is reduced; the thermal aging and faults of the PCB are predicted by using a dynamic modeling engine, so that potential failure risks can be found in advance, and a powerful guarantee is provided for quality control of the PCB; and the test path is automatically generated according to the dynamic modeling result and the data of the fault knowledge graph, so that the workload and error of manually planning the test path are reduced.

Description

Technical Field

[0001] The present application relates to the technical field of PCBA automated testing, and in particular to a PCBA automated testing system and method. Background Art

[0002] With the rapid development of science and technology, the application scope of electronic equipment continues to expand, playing a vital role in key fields such as medical and automotive electronics. As a core component of electronic equipment, the performance and reliability of printed circuit boards (PCBs) directly affect the stable operation of the entire system. As the requirements for device functionality and performance in these fields continue to increase, PCB quality inspection has become extremely critical.

[0003] Accurate and efficient detection technology is of great significance. It can not only ensure product quality and reduce the defective rate in the production process, but also effectively improve the production efficiency and economic benefits of enterprises, and promote the high-quality development of related industries. Traditionally, the detection of PCBs has mainly adopted the traditional ICT (In-Circuit Test, online test) test method, which mainly focuses on detecting electrical indicators such as open and short circuits and component parameters. When detecting open and short circuits, it is generally by applying a specific voltage or current, and then measuring the resistance value in the circuit to determine whether there is an open circuit or short circuit; for the detection of component parameters, various measuring instruments are used to measure parameters such as resistance, capacitance, and inductance, and compare them with standard values ​​to determine whether the components are qualified. However, the traditional ICT test method has obvious limitations: For example, on the one hand, it is difficult to meet some special testing needs: for example, when detecting hidden defects inside devices, such as cold solder joints and thermal stress damage, traditional methods are difficult to detect because they are not directly reflected in open circuits, short circuits, and conventional component parameters. In addition, when evaluating the EMC compatibility and long-term aging reliability of PCBs, existing test methods are also inadequate, lacking the ability to dynamically predict thermodynamic failures and signal interference. In the medical and automotive electronics fields, there are strict requirements for the EMC compatibility and long-term aging reliability of PCBs, and traditional methods cannot provide a strong guarantee for the quality of PCBs in these fields. On the other hand, there are serious deficiencies in test path planning: traditional methods often rely on manual experience. For some high-density boards, such as PCBs using BGA packaging, which have dense pins and complex wiring, manually planned test paths are difficult to fully cover all areas where problems may exist, resulting in the emergence of test blind spots and a high missed detection rate.

[0004] In summary, traditional PCB inspection methods are unable to predict hidden faults such as chip aging, and their fixed test paths are inefficient and have high false positive rates, making them unable to meet the PCB quality inspection requirements of today's electronic devices. To improve the accuracy, comprehensiveness, and efficiency of PCB inspection, it is urgent to develop a PCBA automated testing system and method that can effectively address these issues.

[0005] The above information disclosed in this Background section is only for enhancement of understanding of the background of the present disclosure and therefore it may contain information that does not form the prior art that is already known to a person of ordinary skill in the art. Summary of the Invention

[0006] In view of the deficiencies in the prior art, the present invention provides a PCBA automated testing system and method, which solves the problems mentioned in the above background technology.

[0007] To achieve the above objectives, the present invention is implemented through the following technical solutions: a PCBA automated testing system and method, including a multi-source data acquisition module: collecting multi-source data such as chip dynamic power consumption waveforms, PCB interlayer temperature gradients, and signal loop impedance changes, and using a synchronous acquisition timing alignment algorithm to eliminate sensor sampling delay errors, and transmitting the collected multi-source data to a dynamic modeling engine; Dynamic modeling engine: Based on multi-source data, the dynamic power consumption waveform is input into the device life prediction model built on the LSTM network to output the chip's remaining effective time (RUL). The system also establishes a heat conduction equation between PCB layers, uses real-time temperature data to modify simulation parameters, and predicts hot spots after 24 hours of aging. It also uses frequency domain impedance scanning to identify crosstalk coupling paths between high-speed signal lines. Fault Knowledge Graph Module: Stores ≥100,000 sets of PCB board aging failure case libraries and component process deviation data, supports federated learning and cross-factory encrypted updates, and provides data support for the dynamic modeling engine and FPGA hardware acceleration module; FPGA hardware acceleration module: Built-in parallel computing architecture enables fast calculations for the dynamic modeling engine, achieving millisecond-level response for dynamic modeling and real-time optimization of genetic algorithms for test path optimization; Path actuator unit: includes a multi-axis motion platform and probe card components, and receives instructions from the FPGA hardware acceleration module to carry out testing.

[0008] Optionally, the multi-source data acquisition module includes a dynamic power consumption acquisition unit, an infrared thermal imaging unit, and a vector network analysis unit, wherein the dynamic power consumption acquisition unit acquires the chip dynamic power consumption waveform, and the sampling rate is ≥1MHz; The infrared thermal imaging unit collects the temperature gradient between PCB layers with an accuracy of ±0.5°C; The vector network analysis unit utilizes a vector network analyzer to collect signal loop impedance changes.

[0009] Optionally, the dynamic modeling engine includes an LSTM life prediction submodule, a thermodynamic simulation submodule, and an EMC interference analysis submodule, wherein the LSTM life prediction submodule builds a device life prediction model based on an LSTM network, inputs a dynamic power consumption waveform, and outputs the chip's remaining effective time RUL; The thermodynamic simulation submodule establishes the heat conduction equation between PCB layers and modifies the simulation parameters in combination with real-time temperature data to predict the hotspot area after 24 hours of aging. The EMC interference analysis submodule identifies crosstalk coupling paths between high-speed signal lines through frequency domain impedance scanning.

[0010] Optionally, the path actuator unit includes a multi-axis motion platform and a probe card assembly, wherein the multi-axis motion platform fixes the probe card assembly through a rigid connector, and the multi-axis motion platform can achieve precise movement in multiple directions, driving the probe card assembly to a specified test position; the probe card assembly includes a flexible circuit board substrate, an impedance matching circuit, and at least three discrete probe arrays arranged on the surface, wherein the discrete probe arrays are arranged in a ring and the spacing is 0.3 mm ± 0.05 mm. The flexible circuit board substrate is a polyimide flexible substrate; The operating frequency of the impedance matching circuit is DC-6 GHz.

[0011] Optionally, the synchronous acquisition steps of the synchronous acquisition timing alignment algorithm are as follows: Assign a hardware timestamp marker to each sensor; Based on the power consumption waveform, the temperature and impedance data delays are compensated by Lagrange interpolation method. Establish a cross-channel data correlation matrix with an error tolerance of ≤10ns.

[0012] Optionally, the processing steps of the LSTM life prediction submodule are as follows: Use the PCB board aging failure case library and component process deviation data in the fault knowledge graph module to train and learn the LSTM model to obtain a trained LSTM model; The trained LSTM model input sensor collects the dynamic power consumption waveform time series of the PCB board; The trained LSTM model outputs the remaining effective time RUL of the PCB board.

[0013] Optionally, the processing steps of the thermodynamic simulation submodule are as follows: Establish the heat conduction equation between PCB layers, where the expression of the heat conduction equation is Where ρ is the material density of the PCB board, C p Expressed as specific heat capacity, It is expressed as the temperature field distribution between PCB layers changing with time, and k is expressed as the thermal conductivity between PCB layers. is represented by the Laplace operator, T is temperature, t is time, q v Expressed as the internal heat source intensity of the PCB board; Receive temperature sensor data in real time and correct simulation parameters through Kalman filtering; Output 24-hour aging hotspot coordinate set.

[0014] A PCBA automated testing method includes the following steps: S1. Data acquisition: The multi-source data acquisition module collects multi-source data on chip dynamic power consumption waveforms, PCB interlayer temperature gradients, and signal loop impedance changes, and uses a synchronous acquisition timing alignment algorithm to eliminate multi-sensor sampling delay errors. S2, data fusion: using the federated Kalman filter algorithm to fuse the collected multi-source data; S3. Dynamic Modeling: The dynamic power consumption waveform is input into the device life prediction model built based on the LSTM network to output the chip's remaining effective time (RUL). A heat conduction equation is established between PCB layers, and simulation parameters are corrected based on real-time temperature data to predict the coordinate area of ​​aging hotspots. Frequency-domain impedance scanning is used to identify crosstalk coupling paths between high-speed signal lines. S4, Path Generation: The FPGA hardware acceleration module deploys a parallel computing architecture, uses the coordinates of high-risk devices and hotspots as the initial population, and generates the optimal test path through a genetic algorithm; S5. Graded warning: The risk is divided into three levels according to the failure probability output by dynamic modeling, including the warning level, which records data without interrupting the test; the waiting level, which reduces the path scanning speed; and the stop level, which terminates the test and issues an alarm.

[0015] A computer device includes: a memory and a processor; the memory stores a computer program, and the processor implements the steps of the above-mentioned PCBA automatic testing system when executing the computer program.

[0016] A computer-readable storage medium stores a computer program, which, when executed by a processor, implements the steps of the above-mentioned PCBA automated testing system.

[0017] In summary, this application includes at least one of the following beneficial technical effects: 1. By dynamically fusing multi-physical quantity data and adaptively generating test paths, the system can detect PCBA faults more comprehensively and accurately, thereby improving detection efficiency and reducing false detection rates. 2. By using a dynamic modeling engine to predict PCB thermal aging and failure, potential failure risks can be discovered in advance, providing strong support for PCB quality control; 3. By automatically generating test paths based on the results of dynamic modeling and data from the fault knowledge graph, the workload and errors of manually planning test paths are reduced. At the same time, the system can adapt to the testing requirements of complex processes such as BGA / HDI, improving test coverage and accuracy. It can also dynamically integrate multi-physical quantity data and adaptively generate test paths, effectively solving the problems of traditional detection methods' inability to predict hidden faults and low test efficiency, providing a more efficient and accurate solution for PCBA quality inspection. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, a brief introduction to the drawings required for use in the embodiments will be given below. Obviously, the drawings described below are only some embodiments recorded in the present invention. For ordinary technicians in this field, other drawings can also be obtained based on these drawings.

[0019] Figure 1 This is a module block diagram of the PCBA automated testing system of the present invention.

[0020] Figure 2 This is a structural block diagram of the multi-source data acquisition module of the present invention.

[0021] Figure 3 This is a structural block diagram of the dynamic modeling engine of the present invention.

[0022] Figure 4 Schematic diagram of the process of the PCBA automated testing method of the present invention. DETAILED DESCRIPTION

[0023] Example embodiments will now be described more fully with reference to the accompanying drawings. However, example embodiments can be implemented in many forms and should not be construed as limited to the examples set forth herein; rather, these example embodiments are provided so that the description of this disclosure will be thorough and complete and will fully convey the concepts of the example embodiments to those skilled in the art.

[0024] Example: The present invention provides Figure 1The PCBA automated testing system and method shown include a multi-source data acquisition module that collects multi-source data such as chip dynamic power consumption waveforms, PCB interlayer temperature gradients, and signal loop impedance changes, and uses a synchronous acquisition timing alignment algorithm to eliminate sensor sampling delay errors. The collected multi-source data is then transmitted to a dynamic modeling engine. Dynamic modeling engine: Based on multi-source data, the dynamic power consumption waveform is input into the device life prediction model built on the LSTM network to output the chip's remaining effective time (RUL). The system also establishes a heat conduction equation between PCB layers, uses real-time temperature data to modify simulation parameters, and predicts hot spots after 24 hours of aging. It also uses frequency domain impedance scanning to identify crosstalk coupling paths between high-speed signal lines. Fault Knowledge Graph Module: Stores ≥100,000 sets of PCB board aging failure case libraries and component process deviation data, supports federated learning and cross-factory encrypted updates, and provides data support for the dynamic modeling engine and FPGA hardware acceleration module; FPGA hardware acceleration module: Built-in parallel computing architecture enables fast calculations for the dynamic modeling engine, achieving millisecond-level response for dynamic modeling and real-time optimization of genetic algorithms for test path optimization; Path actuator unit: includes a multi-axis motion platform and probe card components, and receives instructions from the FPGA hardware acceleration module to carry out testing.

[0025] It is further explained that the multi-source data acquisition module includes a dynamic power consumption acquisition unit, an infrared thermal imaging unit, and a vector network analysis unit, wherein the dynamic power consumption acquisition unit acquires the chip dynamic power consumption waveform, and the sampling rate is ≥1MHz; The infrared thermal imaging unit collects the temperature gradient between PCB layers with an accuracy of ±0.5°C; The vector network analysis unit utilizes a vector network analyzer to collect signal loop impedance changes.

[0026] It is further explained that the dynamic modeling engine includes an LSTM life prediction submodule, a thermodynamic simulation submodule, and an EMC interference analysis submodule. The LSTM life prediction submodule builds a device life prediction model based on the LSTM network, inputs the dynamic power consumption waveform, and outputs the chip's remaining effective time RUL; The thermodynamic simulation submodule establishes the heat conduction equation between PCB layers and modifies the simulation parameters in combination with real-time temperature data to predict the hotspot area after 24 hours of aging. The EMC interference analysis submodule identifies crosstalk coupling paths between high-speed signal lines through frequency domain impedance scanning.

[0027] It is further explained that the path actuator unit includes a multi-axis motion platform and a probe card assembly, wherein the multi-axis motion platform fixes the probe card assembly through a rigid connector, and the multi-axis motion platform can achieve precise movement in multiple directions, driving the probe card assembly to a designated test position; the probe card assembly includes a flexible circuit board substrate, an impedance matching circuit, and at least three discrete probe arrays arranged on the surface, wherein the discrete probe arrays are arranged in a ring and the spacing is 0.3mm±0.05mm; The flexible circuit board substrate is a polyimide flexible substrate; The operating frequency of the impedance matching circuit is DC-6 GHz.

[0028] It is further explained that the synchronous acquisition steps of the synchronous acquisition timing alignment algorithm are as follows: Assign a hardware timestamp marker to each sensor; Based on the power consumption waveform, the temperature and impedance data delays are compensated by Lagrange interpolation method. Establish a cross-channel data correlation matrix with an error tolerance of ≤10ns.

[0029] It is further explained that the processing steps of the LSTM life prediction submodule are as follows: Use the PCB board aging failure case library and component process deviation data in the fault knowledge graph module to train and learn the LSTM model to obtain a trained LSTM model; The trained LSTM model input sensor collects the dynamic power consumption waveform time series of the PCB board; The trained LSTM model outputs the remaining effective time RUL of the PCB board.

[0030] It is further explained that the processing steps of the thermodynamic simulation submodule are as follows: Establish the heat conduction equation between PCB layers, where the expression of the heat conduction equation is Where ρ is the material density of the PCB board, C p Expressed as specific heat capacity, It is expressed as the temperature field distribution between PCB layers changing with time, and k is expressed as the thermal conductivity between PCB layers. is represented by the Laplace operator, T is temperature, t is time, q v Expressed as the internal heat source intensity of the PCB board; Receive temperature sensor data in real time and correct simulation parameters through Kalman filtering; Output 24-hour aging hotspot coordinate set.

[0031] It is further explained that the FPGA hardware acceleration module includes a first computing unit and a second computing unit, wherein the first computing unit is used for LSTM forward propagation calculation with a delay of <1ms; The second computing unit runs a genetic algorithm to optimize the test path, and the iteration period is less than 0.1s.

[0032] It is further explained that a PCBA automated testing method includes the following steps: S1. Data acquisition: The multi-source data acquisition module collects multi-source data on chip dynamic power consumption waveforms, PCB interlayer temperature gradients, and signal loop impedance changes, and uses a synchronous acquisition timing alignment algorithm to eliminate multi-sensor sampling delay errors. S2, data fusion: using the federated Kalman filter algorithm to fuse the collected multi-source data; S3. Dynamic Modeling: The dynamic power consumption waveform is input into the device life prediction model built based on the LSTM network to output the chip's remaining effective time (RUL). A heat conduction equation is established between PCB layers, and simulation parameters are corrected based on real-time temperature data to predict the coordinate area of ​​aging hotspots. Frequency-domain impedance scanning is used to identify crosstalk coupling paths between high-speed signal lines. S4, Path Generation: The FPGA hardware acceleration module deploys a parallel computing architecture, uses the coordinates of high-risk devices and hotspots as the initial population, and generates the optimal test path through a genetic algorithm; S5. Graded warning: The risk is divided into three levels according to the failure probability output by dynamic modeling, including the warning level: recording data without interrupting the test; the waiting level: reducing the path scanning speed; and the stop level: terminating the test and issuing an alarm.

[0033] It is further explained that the optimization steps of the test path executed by the genetic algorithm in step S4 are as follows: Encoding: test point coordinates are converted into binary gene strings; Selection: Roulette wheel selection of the top 20% individuals in fitness; Crossover: Get the crossover probability of two points; Mutation: Calculate Gaussian mutation probability based on crossover probability; Termination condition: Iterate until convergence or fitness change < 0.1%.

[0034] It is further explained that the hierarchical warning triggering dynamic response in step S5 includes the FPGA hardware acceleration module sending an emergency stop instruction to the path execution mechanism when a stop-test level risk is detected; The path actuator retracts the discrete probe array and initiates the safety isolation protocol; The fault knowledge graph module records failure coordinates and environmental parameters.

[0035] The above formulas are all dimensionless and numerical calculations. The formulas are obtained by collecting a large amount of data and performing software simulation to obtain the most recent real situation. The preset parameters in the formulas are set by technicians in this field according to actual conditions.

[0036] The above embodiments can be implemented in whole or in part by software, hardware, firmware or any other combination. When implemented using software, the above embodiments can be implemented in whole or in part in the form of a computer program product. The computer program product includes one or more computer instructions or computer programs. When the computer instructions or computer program are loaded or executed on a computer, the process or function described in the embodiment of the present application is generated in whole or in part. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. The computer instructions can be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another computer-readable storage medium. For example, the computer instructions can be transmitted from one website, computer, server or data center to another website, computer, server or data center via wired or wireless (e.g., infrared, wireless, microwave, etc.) means. The computer-readable storage medium can be any available medium that can be accessed by a computer or a data storage device such as a server or data center that contains one or more available media sets. The available medium can be a magnetic medium (e.g., a floppy disk, a hard disk, a tape), an optical medium (e.g., a DVD), or a semiconductor medium. The semiconductor medium can be a solid-state drive.

[0037] It should be understood that in the various embodiments of the present application, the size of the serial numbers of the above-mentioned processes does not mean the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present application.

[0038] Those skilled in the art will appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professional and technical personnel can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0039] The above description is merely a specific embodiment of the present application, but the scope of protection of the present application is not limited thereto. Any changes or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in this application should be included in the scope of protection of this application. Therefore, the scope of protection of this application should be based on the scope of protection of the claims.

Claims

1. A PCBA automated testing system, characterized in that: Includes a multi-source data acquisition module: It collects multi-source data such as chip dynamic power consumption waveform, PCB inter-layer temperature gradient, and signal loop impedance change, and uses a synchronous acquisition timing alignment algorithm to eliminate sensor sampling delay errors, and transmits the collected multi-source data to the dynamic modeling engine; Dynamic modeling engine: Based on multi-source data, the dynamic power consumption waveform is input into the device life prediction model built on the LSTM network to output the chip's remaining effective time (RUL). The system also establishes a heat conduction equation between PCB layers, uses real-time temperature data to modify simulation parameters, and predicts hot spots after 24 hours of aging. It also uses frequency domain impedance scanning to identify crosstalk coupling paths between high-speed signal lines. Fault Knowledge Graph Module: Stores ≥100,000 sets of PCB board aging failure case libraries and component process deviation data, supports federated learning and cross-factory encrypted updates, and provides data support for the dynamic modeling engine and FPGA hardware acceleration module; FPGA hardware acceleration module: Built-in parallel computing architecture enables fast calculations for the dynamic modeling engine, achieving millisecond-level response for dynamic modeling and real-time optimization of genetic algorithms for test path optimization; Path actuator unit: includes a multi-axis motion platform and probe card components, and receives instructions from the FPGA hardware acceleration module to carry out testing.

2. A PCBA automated testing system according to claim 1, characterized in that: The multi-source data acquisition module includes a dynamic power consumption acquisition unit, an infrared thermal imaging unit, and a vector network analysis unit, wherein the dynamic power consumption acquisition unit acquires the chip dynamic power consumption waveform, and the sampling rate is ≥1MHz; The infrared thermal imaging unit collects the temperature gradient between PCB layers with an accuracy of ±0.5°C; The vector network analysis unit utilizes a vector network analyzer to collect signal loop impedance changes.

3. A PCBA automated testing system according to claim 2, characterized in that: The dynamic modeling engine includes an LSTM life prediction submodule, a thermodynamic simulation submodule, and an EMC interference analysis submodule. The LSTM life prediction submodule builds a device life prediction model based on an LSTM network, inputs a dynamic power consumption waveform, and outputs the chip's remaining effective time (RUL). The thermodynamic simulation submodule establishes the heat conduction equation between PCB layers and modifies the simulation parameters in combination with real-time temperature data to predict the hotspot area after 24 hours of aging. The EMC interference analysis submodule identifies crosstalk coupling paths between high-speed signal lines through frequency domain impedance scanning.

4. A PCBA automated testing system according to claim 3, characterized in that: The path actuator unit includes a multi-axis motion platform and a probe card assembly, wherein the multi-axis motion platform fixes the probe card assembly through a rigid connector and can achieve precise movement in multiple directions, driving the probe card assembly to a designated test position; the probe card assembly includes a flexible circuit board substrate, an impedance matching circuit, and at least three discrete probe arrays arranged on the surface, wherein the discrete probe arrays are arranged in a ring and have a spacing of 0.3 mm ± 0.05 mm. The flexible circuit board substrate is a polyimide flexible substrate; The operating frequency of the impedance matching circuit is DC-6 GHz.

5. A PCBA automated testing system according to claim 4, characterized in that: The synchronous acquisition steps of the synchronous acquisition timing alignment algorithm are as follows: Assign a hardware timestamp marker to each sensor; Based on the power consumption waveform, the temperature and impedance data delays are compensated by Lagrange interpolation method. Establish a cross-channel data correlation matrix with an error tolerance of ≤10ns.

6. A PCBA automated testing system according to claim 5, characterized in that: The processing steps of the LSTM life prediction submodule are as follows: Use the PCB board aging failure case library and component process deviation data in the fault knowledge graph module to train and learn the LSTM model to obtain a trained LSTM model; The trained LSTM model input sensor collects the dynamic power consumption waveform time series of the PCB board; The trained LSTM model outputs the remaining effective time RUL of the PCB board.

7. A PCBA automated testing system according to claim 6, characterized in that: The processing steps of the thermodynamic simulation submodule are as follows: Establish the heat conduction equation between PCB layers, where the expression of the heat conduction equation is Where ρ is the material density of the PCB board, C p Expressed as specific heat capacity, It is expressed as the temperature field distribution between PCB layers changing with time, and k is expressed as the thermal conductivity between PCB layers. is represented by the Laplace operator, T is temperature, t is time, q v Expressed as the internal heat source intensity of the PCB board; Receive temperature sensor data in real time and correct simulation parameters through Kalman filtering; Output 24-hour aging hotspot coordinate set.

8. A PCBA automated testing method, implemented according to a PCBA automated testing system according to any one of claims 1 to 7, characterized in that: The steps include: S1. Data acquisition: The multi-source data acquisition module collects multi-source data on chip dynamic power consumption waveforms, PCB interlayer temperature gradients, and signal loop impedance changes, and uses a synchronous acquisition timing alignment algorithm to eliminate multi-sensor sampling delay errors. S2, data fusion: using the federated Kalman filter algorithm to fuse the collected multi-source data; S3. Dynamic Modeling: The dynamic power consumption waveform is input into the device life prediction model built based on the LSTM network to output the chip's remaining effective time (RUL). A heat conduction equation is established between PCB layers, and simulation parameters are corrected based on real-time temperature data to predict the coordinate area of ​​aging hotspots. Frequency-domain impedance scanning is used to identify crosstalk coupling paths between high-speed signal lines. S4, Path Generation: The FPGA hardware acceleration module deploys a parallel computing architecture, uses the coordinates of high-risk devices and hotspots as the initial population, and generates the optimal test path through a genetic algorithm; S5. Graded warning: The risk is divided into three levels according to the failure probability output by dynamic modeling, including the warning level: recording data without interrupting testing; Waiting for inspection level: reduce the path scanning speed; Stop testing level: terminate the test and alarm.

9. A computer device comprising: A memory and a processor; the memory stores a computer program, wherein the processor implements the steps of a PCBA automated testing system according to any one of claims 1 to 7 when executing the computer program.

10. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the steps of a PCBA automatic testing system according to any one of claims 1 to 7 are implemented.

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