Semiconductor structure and manufacturing method thereof

Abstract

The embodiment of the invention provides a semiconductor structure and a manufacturing method thereof, the semiconductor structure comprises a first dielectric layer and a first metal layer located in the first dielectric layer, and the first dielectric layer does not cover the top surface of the first metal layer; a self-assembled monolayer covering a portion of the top surface of the first metal layer; the second dielectric layer is located on the first dielectric layer and covers the self-assembly single layer; the third dielectric layer is located on the second dielectric layer and is in bonding connection with the second dielectric layer; the first through hole penetrates through the second dielectric layer and at least part of the third dielectric layer; the barrier layer at least covers the side wall of the first through hole and does not cover the bottom of the first through hole; the second through hole is located below the first through hole and communicated with the first through hole, and the second through hole exposes part of the top surface of the first metal layer and part of the side wall of the self-assembled single layer; and the conductive plug covers the barrier layer in the first through hole and fills the first through hole and the second through hole, and the conductive plug is in direct contact connection with the first metal layer.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor technology, and in particular to a semiconductor structure and a manufacturing method thereof. Background Art

[0002] As the feature size of integrated circuits continues to shrink and device interconnect density continues to increase, vertical interconnection based on through-silicon via (TSV) technology in 3D stacking has gradually led the development of packaging technology, with its advantages of short interconnection distances and high-density integration. For example, memory cells (such as dynamic random access memory) and CMOS logic control units can be interconnected through TSVs that penetrate the bonding layer to achieve interconnection between stacked chips.

[0003] However, as the scale of interconnects continues to expand, there are still many problems in the TSV manufacturing process that need to be improved. Summary of the Invention

[0004] An embodiment of the present disclosure provides a semiconductor structure, comprising: a first dielectric layer, and a first metal layer located within the first dielectric layer, wherein the first dielectric layer does not cover a top surface of the first metal layer; a self-assembled monolayer covering a portion of the top surface of the first metal layer; a second dielectric layer, located on the first dielectric layer and covering the self-assembled monolayer; a third dielectric layer, located on the second dielectric layer and bonded to the second dielectric layer; a first through hole, passing through the second dielectric layer and at least a portion of the third dielectric layer; a barrier layer, covering at least a sidewall of the first through hole and not covering a bottom of the first through hole; a second through hole, located below the first through hole and connected to the first through hole, the second through hole exposing a portion of the top surface of the first metal layer and a portion of the sidewall of the self-assembled monolayer; A conductive plug covers the barrier layer in the first through hole and fills the first through hole and the second through hole, wherein the conductive plug is in direct contact with the first metal layer.

[0005] In some embodiments, the semiconductor structure further includes an isolation structure located in the second dielectric layer and covering a top surface of the first dielectric layer surrounding the first metal layer, wherein a top surface of the isolation structure protrudes from a top surface of the self-assembled monolayer.

[0006] In some embodiments, the material of the isolation structure is doped with carbon and / or nitrogen, and the total mass percentage of the carbon and nitrogen elements in the isolation structure is m1, which is between 10% and 40%.

[0007] In some embodiments, the ratio of the etching rate of the second dielectric layer to the etching rate of the isolation structure is in a range of 5:1 to 20:1; and / or, The ratio of the etching rate of the third dielectric layer to the etching rate of the isolation structure ranges from 5:1 to 20:1.

[0008] In some embodiments, the materials of the isolation structure, the second dielectric layer, and the third dielectric layer independently include at least one of silicon oxide, silicon carbon nitride, silicon oxynitride, silicon oxycarbide, borophosphosilicate glass, and tetraethoxysilane. The total mass percentage of carbon and nitrogen elements in the second dielectric layer is in the range of m2, and the total mass percentage of carbon and nitrogen elements in the third dielectric layer is in the range of m3. m1 is greater than m2, and the difference between the two is in the range of 10% to 30%; m1 is greater than m3, and the difference between the two is in the range of 10% to 30%.

[0009] In some embodiments, the lower sidewall of the first through hole exposes a portion of the sidewall of the isolation structure, and the exposed sidewall of the isolation structure is an inclined sidewall, so that the width of the portion of the first through hole that exposes the inclined sidewall of the isolation structure in a direction parallel to the plane of the first dielectric layer tends to decrease in a direction perpendicular to the plane of the first dielectric layer and from the first through hole to the first dielectric layer.

[0010] In some embodiments, the thickness of the self-assembled monolayer ranges from 1 nm to 3 nm.

[0011] In some embodiments, the first through hole penetrates the second dielectric layer and a portion of the third dielectric layer, and the semiconductor structure further includes: a trench structure located in the third dielectric layer, wherein the first through hole is located below and communicates with the trench structure, and the barrier layer further covers a sidewall and a portion of a bottom surface of the trench structure; The second metal layer covers the barrier layer in the trench structure, fills the trench structure and is connected to the conductive plug.

[0012] The present disclosure also provides a method for manufacturing a semiconductor structure, including: Providing a first dielectric layer, and forming a first metal layer in the first dielectric layer, wherein the first dielectric layer does not cover a top surface of the first metal layer; forming a first initial self-assembled monolayer on the first metal layer; forming a second dielectric layer on the first dielectric layer, wherein the second dielectric layer covers the first initial self-assembled monolayer; Providing a third dielectric layer, placing the third dielectric layer above the second dielectric layer and bonding the third dielectric layer to the second dielectric layer; forming a first through hole, wherein the first through hole penetrates the second dielectric layer and at least a portion of the third dielectric layer and exposes a portion of the first initial self-assembled monolayer; forming a barrier layer, wherein the barrier layer at least covers the sidewalls of the first through hole and does not cover the bottom of the first through hole; Removing the exposed first initial self-assembled monolayer from the bottom of the first through-hole to form a second through-hole, with the remaining first initial self-assembled monolayer serving as a self-assembled monolayer, wherein the second through-hole is located below and communicates with the first through-hole, and the second through-hole exposes a portion of the top surface of the first metal layer and a portion of the sidewall of the self-assembled monolayer; A conductive plug is formed, where the conductive plug covers the barrier layer in the first through hole and fills the first through hole and the second through hole, and the conductive plug is in direct contact with the first metal layer.

[0013] In some embodiments, before forming the second dielectric layer on the first dielectric layer, the method further includes: An initial isolation structure is formed, where the initial isolation structure covers a top surface of the first dielectric layer surrounding the first metal layer, and the second dielectric layer further covers the initial isolation structure.

[0014] In some embodiments, forming a first initial self-assembled monolayer on the first metal layer to form an initial isolation structure includes: forming a second initial self-assembled monolayer on the first metal layer; forming an initial isolation structure, wherein the initial isolation structure covers a top surface of the first dielectric layer located around the first metal layer; Part of the thickness of the second initial self-assembled monolayer is removed, and the remaining second initial self-assembled monolayer serves as the first initial self-assembled monolayer, the thickness of the first initial self-assembled monolayer ranges from 1 nm to 3 nm, and the top surface of the initial isolation structure protrudes from the top surface of the first initial self-assembled monolayer.

[0015] In some embodiments, forming a first through hole includes: The third dielectric layer, the second dielectric layer, and the initial isolation structure are etched to form the first through hole. The initial isolation structure remaining after etching serves as the isolation structure. The lower sidewall of the first through hole exposes a portion of the sidewall of the isolation structure, and the exposed sidewall of the isolation structure is an inclined sidewall. As the etching depth gradually increases, the width of the removed initial isolation structure in a direction parallel to the plane of the first dielectric layer decreases, so that the width of the portion of the first through hole that exposes the inclined sidewall of the isolation structure in a direction parallel to the plane of the first dielectric layer decreases in a direction perpendicular to the plane of the first dielectric layer and from the first through hole to the first dielectric layer.

[0016] In some embodiments, the ratio of the etching rate of the second dielectric layer to the etching rate of the initial isolation structure is in a range of 5:1 to 20:1; and / or, The ratio of the etching rate of the third dielectric layer to the etching rate of the initial isolation structure ranges from 5:1 to 20:1.

[0017] In some embodiments, the first through hole penetrates the second dielectric layer and a portion of the third dielectric layer. Before forming the first through hole, the method further includes: A trench structure is formed in the third dielectric layer, wherein the first through hole is located below the trench structure and communicates with the trench structure; the barrier layer also covers the sidewalls and a portion of the bottom surface of the trench structure; While forming the conductive plug, the method further includes: synchronously forming a second metal layer, wherein the second metal layer covers the barrier layer in the trench structure, fills the trench structure and is connected to the conductive plug.

[0018] In the embodiment of the present disclosure, alignment of the first through hole can be achieved by forming a self-assembled monolayer on the first metal layer, and the barrier layer is not easily adsorbed on the surface of the self-assembled monolayer (the barrier layer will not be adsorbed on the surface of the self-assembled monolayer after cleaning), thereby avoiding the formation of a barrier layer at the bottom of the first through hole, and further avoiding the formation of a barrier layer between the conductive plug and the first metal layer. The conductive plug is directly contacted and connected with the first metal layer, reducing the RC resistance of the conductive plug and improving the performance of the semiconductor structure.

[0019] The details of one or more embodiments of the present disclosure are set forth in the accompanying drawings and the description below. Other features and advantages of the present disclosure will become apparent from the description and the drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the following briefly introduces the drawings required for use in the embodiments. Obviously, the drawings described below are only some embodiments of the present disclosure. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0021] Figure 1 A schematic structural diagram of a semiconductor structure provided by some embodiments of the present disclosure; Figure 2 Schematic diagrams of semiconductor structures provided in other embodiments of the present disclosure; Figure 3 A flowchart of a method for manufacturing a semiconductor structure provided in some embodiments of the present disclosure; Figure 4 Schematic diagram of the structure of the semiconductor structure provided in some embodiments of the present disclosure during the manufacturing process Figure 1 ; Figure 5 Schematic diagram of the structure of the semiconductor structure provided in some embodiments of the present disclosure during the manufacturing process Figure 2 ; Figure 6 Schematic diagram of the structure of the semiconductor structure provided in some embodiments of the present disclosure during the manufacturing process Figure 3 ; Figure 7 Schematic diagram of the structure of the semiconductor structure provided in some embodiments of the present disclosure during the manufacturing process Figure 4 ; Figure 8 Schematic diagram of the structure of the semiconductor structure provided in some embodiments of the present disclosure during the manufacturing process Figure 5 ; Figure 9 Schematic diagram of the structure of the semiconductor structure provided in some embodiments of the present disclosure during the manufacturing process Figure 6 ; Figure 10 Schematic diagram of the structure of the semiconductor structure provided in some embodiments of the present disclosure during the manufacturing process Figure 7 ; Figure 11 Schematic diagram of the structure of the semiconductor structure provided in some embodiments of the present disclosure during the manufacturing process Figure 8 ; Figure 12 Schematic diagram of the structure of the semiconductor structure provided in some embodiments of the present disclosure during the manufacturing process Figure 9 ; Figure 13 Schematic diagram of the structure of the semiconductor structure provided in some embodiments of the present disclosure during the manufacturing process Figure 10 ; Figure 14Schematic diagram of the structure of the semiconductor structure provided in some embodiments of the present disclosure during the manufacturing process Figure 10 one; Figure 15 Schematic diagram of the structure of the semiconductor structure during the manufacturing process provided in other embodiments of the present disclosure Figure 10 two; Figure 16 Schematic diagram of the structure of the semiconductor structure during the manufacturing process provided in other embodiments of the present disclosure Figure 10 three; Figure 17 Schematic diagram of the structure of the semiconductor structure during the manufacturing process provided in other embodiments of the present disclosure Figure 10 Four. DETAILED DESCRIPTION

[0022] Exemplary embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. Although exemplary embodiments of the present disclosure are shown in the accompanying drawings, it should be understood that the present disclosure can be implemented in various forms and should not be limited by the specific embodiments described herein. Instead, these embodiments are provided to enable a more thorough understanding of the present disclosure and to fully convey the scope of the present disclosure to those skilled in the art.

[0023] In the following description, numerous specific details are provided to provide a more thorough understanding of the present disclosure. However, it will be apparent to those skilled in the art that the present disclosure can be practiced without one or more of these details. In other instances, certain technical features known in the art are not described to avoid confusion with the present disclosure; that is, all features of actual embodiments are not described herein, nor are well-known functions and structures described in detail.

[0024] In the drawings, the sizes of layers, regions, elements and their relative sizes may be exaggerated for clarity. Like reference numerals denote like elements throughout.

[0025] It should be understood that when an element or layer is referred to as being "on, adjacent to, connected to, or coupled to" another element or layer, it may be directly on, adjacent to, connected to, or coupled to the other element or layer, or there may be intervening elements or layers. In contrast, when an element is referred to as being "directly on, directly adjacent to, directly connected to, or directly coupled to" another element or layer, there may be no intervening elements or layers. It should be understood that although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers, and / or parts, these elements, components, regions, layers, and / or parts should not be limited by these terms. These terms are merely used to distinguish one element, component, region, layer, or part from another element, component, region, layer, or part. Therefore, without departing from the teachings of the present disclosure, the first element, component, region, layer, or part discussed below may be represented as a second element, component, region, layer, or part. However, when the second element, component, region, layer, or part is discussed, it does not necessarily mean that the first element, component, region, layer, or part exists in the present disclosure.

[0026] Spatially relative terms such as "under," "beneath," "below," "under," "above," "above," etc., may be used herein for convenience of description to describe the relationship of an element or feature shown in the figures to other elements or features. It should be understood that in addition to the orientations shown in the figures, the spatially relative terms are intended to include different orientations of the device in use and operation. For example, if the device in the drawings is turned over, then the elements or features described as "under" or "beneath" or "beneath" the other elements will be oriented "above" the other elements or features. Thus, the exemplary terms "under" and "under" can include both the above and below orientations. The device can be oriented otherwise (rotated 90 degrees or in other orientations) and the spatial descriptors used herein are interpreted accordingly.

[0027] The purpose of the terms used herein is only to describe specific embodiments and is not intended to limit the present disclosure. When used herein, the singular forms "a", "an", and "the" are intended to include the plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "comprising" and / or "comprising", when used in this specification, determine the presence of the features, integers, steps, operations, elements and / or parts, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or groups. When used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0028] In through-silicon via (TSV) interconnection technology, as the interconnection scale continues to expand and the feature size of integrated circuits continues to shrink, the RC resistance of the TSV increases significantly, thereby affecting the performance of the semiconductor structure.

[0029] Based on this, the technical solution of the embodiment of the present disclosure is proposed. In the embodiment of the present disclosure, by forming a self-assembled monolayer on the first metal layer, alignment of the first through-hole can be achieved, and the barrier layer is not easily adsorbed on the surface of the self-assembled monolayer (after cleaning, the barrier layer will not be adsorbed on the surface of the self-assembled monolayer), thereby avoiding the formation of a barrier layer at the bottom of the first through-hole, and further avoiding the formation of a barrier layer between the conductive plug and the first metal layer. The conductive plug is directly connected to the first metal layer, reducing the RC resistance of the conductive plug and improving the performance of the semiconductor structure.

[0030] To make the above-mentioned purposes, features, and advantages of the present disclosure more clearly understood, the following detailed description of the specific embodiments of the present disclosure is provided in conjunction with the accompanying drawings. When describing the embodiments of the present disclosure, for ease of explanation, the schematic diagrams may be partially enlarged to a different scale than the general scale. Moreover, the schematic diagrams are merely examples and should not limit the scope of protection of the present disclosure.

[0031] like Figure 1 As shown, the semiconductor structure includes: a first dielectric layer 11, and a first metal layer 12 located in the first dielectric layer 11, wherein the first dielectric layer 11 does not cover the top surface of the first metal layer 12; a self-assembled monolayer 13 covering a portion of the top surface of the first metal layer 12; a second dielectric layer 15 located on the first dielectric layer 11 and covering the self-assembled monolayer 13; a third dielectric layer 16 located on the second dielectric layer 15 and bonded to the second dielectric layer 15; a first through hole 181 penetrating the second dielectric layer 15 and at least a portion of the third dielectric layer 16; The barrier layer 19 covers at least the sidewalls of the first through hole 181 and does not cover the bottom of the first through hole 181; the second through hole 182 is located below the first through hole 181 and is connected to the first through hole 181, and the second through hole 182 exposes a portion of the top surface of the first metal layer 12 and a portion of the sidewalls of the self-assembled monolayer 13; the conductive plug 21 covers the barrier layer 19 located in the first through hole 181 and fills the first through hole 181 and the second through hole 182, and the conductive plug 21 is in direct contact with the first metal layer 12.

[0032] In actual operation, the semiconductor structure may further include a first substrate (not shown). The first dielectric layer 11 may be located on the first substrate. Multiple functional structures, such as transistors, capacitors, word lines, and bit lines, may be formed on the surface and within the first substrate. An interconnect structure (not shown) may also be formed within the first dielectric layer 11. The first metal layer 12 may be electrically connected to the functional structures via the interconnect structure. The first substrate may include a wafer, such as a silicon wafer.

[0033] In some embodiments, the first dielectric layer 11 may be a single-layer structure or a multi-layer structure, and the material of the first dielectric layer 11 may include one or more of oxide (e.g., silicon oxide), nitride (e.g., silicon nitride), oxynitride (e.g., silicon oxynitride), silicon oxycarbide, borophosphosilicate glass, tetraethoxysilane, and the like.

[0034] like Figure 1 As shown, there may be multiple first metal layers 12 , and the multiple first metal layers 12 may be spaced apart in the first dielectric layer 11 , and the top surface of the first metal layer 12 may be flush with the top surface of the first dielectric layer 11 .

[0035] In actual operation, the first dielectric layer 11 may be patterned, and then a conductive material may be filled into the patterned first dielectric layer 11 to form the first metal layer 12. The material of the first metal layer 12 may include tungsten (W), copper (Cu), titanium (Ti), tantalum (Ta), nickel (Ni), tin (Sn), chromium (Cr), gold (Au), silver (Ag), or any other combination thereof.

[0036] In some embodiments, the semiconductor structure may further include an isolation structure 14 located within the second dielectric layer 15 and covering the top surface of the first dielectric layer 11 located around the first metal layer 12. The top surface of the isolation structure 14 may protrude above the top surface of the self-assembled monolayer 13. In some embodiments, the second dielectric layer 15 also covers the top surface of the isolation structures 14 and fills the gaps between the isolation structures 14.

[0037] In actual operation, the semiconductor structure may further include a second substrate (not shown), which may be located on a surface of the third dielectric layer 16 facing away from the first dielectric layer 11. The second substrate may include a wafer, such as a silicon wafer.

[0038] In actual operation, the first through hole 181 can be formed by etching at least the second dielectric layer 15 and the third dielectric layer 16. The second through hole 182 is located below the first through hole 181, and the orthographic projections of the first through hole 181 and the second through hole 182 on the plane of the first dielectric layer 11 at least partially overlap with the orthographic projections of the first metal layer 12 on the plane of the first dielectric layer 11, so that the second through hole 182 can expose a portion of the first metal layer 12, and the conductive plugs 21 located in the first through hole 181 and the second through hole 182 can be electrically connected to the first metal layer 12.

[0039] In actual operation, you can first Figure 8As shown, a first initial self-assembled monolayer 13' is formed covering the first metal layer 12. The self-assembled monolayer molecules in the first initial self-assembled monolayer 13' (i.e., the self-assembled monolayer molecules in the self-assembled monolayer 13) are amphiphilic molecules of long-chain carbon atoms, consisting of a head group, a molecular chain, and a tail group. The head group of the self-assembled monolayer molecule has a strong chemical adsorption force with the metal material, and it can be arranged in an orderly manner on the surface of the first metal layer 12; then, as shown Figure 9 、 Figure 10 as well as Figure 12 As shown, a second dielectric layer 15 and a third dielectric layer 16 may be formed, and at least a portion of the second dielectric layer 15 and a portion of the third dielectric layer 16 may be removed to form a first through hole 181, wherein the first through hole 181 exposes a portion of the first initial self-assembled monolayer 13'; then, as shown Figure 13 As shown, a barrier layer 19 is formed, and the barrier layer 19 at least covers the sidewalls of the first through hole 181. Since the barrier layer 19 is difficult to nucleate on the surface of the first initial self-assembled monolayer 13', it is possible to avoid the formation of the barrier layer 19 at the bottom of the first through hole 181 (the barrier layer 19 is only suspended on the surface of the first initial self-assembled monolayer 13', and after cleaning, the barrier layer 19 will not be adsorbed and formed on the surface of the first initial self-assembled monolayer 13'); then, as shown in FIG. Figure 14 As shown, the first initial self-assembled monolayer 13 ′ exposed by the bottom of the first through hole 181 can be removed to form a second through hole 182 , and the remaining first initial self-assembled monolayer 13 ′ constitutes a self-assembled monolayer 13 , which covers a portion of the top surface of the first metal layer 12 .

[0040] In some embodiments, the material of self-assembled monolayer 13 (i.e., the material of first initial self-assembled monolayer 13') may include, but is not limited to, alkylthiols, such as octadecylthiol. For example, when the material of self-assembled monolayer 13 includes alkylthiols, the sulfur atoms in self-assembled monolayer 13 can form strong chemical bonds with metal atoms in first metal layer 12 (e.g., copper), and can be arranged in an orderly manner on the surface of first metal layer 12, thereby selectively forming first initial self-assembled monolayer 13' on the surface of first metal layer 12.

[0041] In this way, in the embodiment of the present disclosure, by forming the first initial self-assembled monolayer 13' on the first metal layer 12, the alignment of the first through hole 181 can be achieved, and the barrier layer 19 is not easily adsorbed on the surface of the first initial self-assembled monolayer 13' (the barrier layer 19 will not be adsorbed on the surface of the first initial self-assembled monolayer 13' after cleaning), thereby avoiding the formation of the barrier layer 19 at the bottom of the first through hole 181, and further avoiding the formation of the barrier layer 19 between the conductive plug 21 and the first metal layer 12. The conductive plug 21 is directly contacted and connected with the first metal layer 12, thereby reducing the RC resistance of the conductive plug 21 and improving the performance of the semiconductor structure.

[0042] In some embodiments, the thickness of the self-assembled monolayer 13 ranges from 1 nm to 3 nm, for example, 1 nm, 2 nm, 3 nm, etc. By controlling the thickness of the self-assembled monolayer 13 (that is, the thickness of the first initial self-assembled monolayer 13') within the above range, the barrier layer 19 can be effectively prevented from nucleating on the surface of the first initial self-assembled monolayer 13'.

[0043] like Figure 1 As shown, in some embodiments, the orthographic projection of the first through hole 181 on the plane of the first dielectric layer 11 may also partially overlap with the orthographic projection of the isolation structure 14 on the plane of the first dielectric layer 11 .

[0044] like Figure 1 As shown, in some embodiments, the lower sidewall of the first through-hole 181 may expose a portion of the sidewall of the isolation structure 14. The exposed sidewall of the isolation structure 14 is an inclined sidewall, so that the width of the portion of the first through-hole 181 that exposes the inclined sidewall of the isolation structure 14 in a direction parallel to the plane of the first dielectric layer 11 decreases in a direction perpendicular to the plane of the first dielectric layer 11 and pointing from the first through-hole 181 to the first dielectric layer 11. The width here and below refers to the width in a direction parallel to the plane of the first dielectric layer 11.

[0045] In actual operation, you can first Figure 7 As shown, an initial isolation structure 14' is formed, and the initial isolation structure 14' covers the top surface of the first dielectric layer 11 located around the first metal layer 12, and the second dielectric layer 15 also covers the initial isolation structure 14'; then, as shown Figure 12 As shown, the third dielectric layer 16, the second dielectric layer 15, and the initial isolation structure 14' can be etched to form a first through hole 181. The initial isolation structure 14' remaining after etching serves as the isolation structure 14. As the etching depth gradually increases, the width of the removed initial isolation structure 14' tends to decrease, so that the width of the portion of the first through hole 181 that exposes the inclined sidewall of the isolation structure 14 tends to decrease in a direction perpendicular to the plane of the first dielectric layer 11 and pointing from the first through hole 181 to the first dielectric layer 11.

[0046] In some embodiments, the material of isolation structure 14 (i.e., the material of initial isolation structure 14 ′) is doped with carbon and / or nitrogen. The total mass percentage of carbon and nitrogen in isolation structure 14 is m1, and m1 is between 10% and 40%, for example, 10%, 15%, 20%, 30%, 40%, etc. The mass percentage of carbon in isolation structure 14 can be 0, indicating that isolation structure 14 does not contain carbon. Alternatively, the mass percentage of nitrogen in isolation structure 14 can be 0, indicating that isolation structure 14 does not contain nitrogen. Alternatively, the mass percentage of both nitrogen and carbon in isolation structure 14 can be greater than 0, indicating that isolation structure 14 contains both nitrogen and carbon.

[0047] By controlling the total mass percentage of carbon and nitrogen in the material of the isolation structure 14 within the aforementioned range, the etching rate of the initial isolation structure 14' can be reduced during the formation of the first through-hole 181, thereby improving the etching selectivity between the second dielectric layer 15 and the initial isolation structure 14'. In some embodiments, the ratio of the etching rate of the second dielectric layer 15 to the etching rate of the isolation structure 14 can be in a range of 5:1 to 20:1, for example, 5:1, 10:1, 15:1, 20:1, etc.

[0048] Thus, by controlling the second dielectric layer 15 and the isolation structure 14 to have a larger etching selectivity, during the formation of the first through hole 181, as the etching depth increases, the etching width of the initial isolation structure 14' gradually decreases, thereby forming the first through hole 181 with a gradually decreasing lower width.

[0049] In the embodiment of the present disclosure, the isolation structure 14 electrically isolates the conductive plug 21 from other first metal layers 12 except the first metal layer 12 electrically connected to the conductive plug 21. In the embodiment of the present disclosure, along a direction perpendicular to the plane of the first dielectric layer 11 and directed from the first through-hole 181 toward the first dielectric layer 11, the width of the lower portion of the first through-hole 181 gradually decreases, while the width of the isolation structure 14 whose sidewalls are exposed by the first through-hole 181 gradually increases. The distance between the conductive plug 21 and other first metal layers 12 in a direction parallel to the plane of the first dielectric layer 11 gradually increases. This enhances the isolation effect of the isolation structure 14, reduces parasitic capacitance, improves the withstand voltage characteristics of the conductive plug 21, and prevents or reduces leakage.

[0050] In some embodiments, the ratio of the etching rate of the third dielectric layer 16 to the etching rate of the isolation structure 14 ranges from 5:1 to 20:1, for example, 5:1, 10:1, 15:1, 20:1, etc. In this way, the etching consistency of the second dielectric layer 15 and the third dielectric layer 16 can be maintained, and the morphology quality of the first through hole 181 located in the second dielectric layer 15 and the third dielectric layer 16 can be improved.

[0051] In some embodiments, the materials of the isolation structure 14, the second dielectric layer 15, and the third dielectric layer 16 independently include at least one of silicon oxide, silicon carbonitride, silicon oxynitride, silicon oxycarbide, borophosphosilicate glass, and tetraethoxysilane. The total mass percentage of carbon and nitrogen in the second dielectric layer 15 is in the range of m2, and the total mass percentage of carbon and nitrogen in the third dielectric layer 16 is in the range of m3. m1 is greater than m2, and the difference between the two is in the range of 10% to 30% (including endpoint values, such as 10%, 15%, 20%, 30%, etc.); m1 is greater than m3, and the difference between the two is in the range of 10% to 30% (including endpoint values, such as 10%, 15%, 20%, 30%, etc.).

[0052] The values ​​of m2 and m3 may both be greater than or equal to 0; the mass percentage of carbon and / or the mass percentage of nitrogen in the second dielectric layer 15 may be greater than or equal to 0; and the mass percentage of carbon and / or the mass percentage of nitrogen in the third dielectric layer 16 may also be greater than or equal to 0. For example, the second dielectric layer 15 and the third dielectric layer 16 may be made of silicon oxide, and may contain no nitrogen or carbon. The isolation structure 14 may be made of silicon oxynitride, and the mass percentage of silicon, oxygen, and nitrogen in the isolation structure 14 may be 48.369%, 27.5417%, and 24.1114%.

[0053] In this way, by controlling the difference between m1 and m2, and the difference between m1 and m3 within the above range, the etching selectivity ratio of the second dielectric layer 15 and the isolation structure 14, and the etching selectivity ratio of the third dielectric layer 16 and the isolation structure 14 can be adjusted within the required range.

[0054] like Figure 1 As shown, in some embodiments, the first through hole 181 penetrates the second dielectric layer 15 and a portion of the third dielectric layer 16. The semiconductor structure may further include: a trench structure 17 located within the third dielectric layer 16; the first through hole 181 is located below and communicates with the trench structure 17; a barrier layer 19 also covers the sidewalls and a portion of the bottom surface of the trench structure 17; and a second metal layer 22 covering the barrier layer 19 located within the trench structure 17, filling the trench structure 17, and connecting to the conductive plug 21. Here, the portion of the bottom surface of the trench structure 17 covered by the barrier layer 19 refers to the bottom surface of the trench structure 17 not penetrated by the first through hole 181.

[0055] In some embodiments, the barrier layer 19 may also cover the top surface of the third dielectric layer 16, and the top surface of the second metal layer 22 may be flush with the top surface of the barrier layer 19. In subsequent processes, a planarization process may be performed to remove the barrier layer 19 and the second metal layer 22 above the plane of the top surface of the third dielectric layer 16.

[0056] In actual operation, the material of the barrier layer 19 may include titanium, tantalum, titanium nitride, tantalum nitride and other materials with barrier function.

[0057] In actual operation, conductive material may be filled into the first through hole 181 , the second through hole 182 and the trench structure 17 to form a conductive plug 21 and a second metal layer 22 , respectively. The second metal layer 22 is electrically connected to the first metal layer 12 through the conductive plug 21 .

[0058] In actual operation, the materials of the conductive plug 21 and the second metal layer 22 may include tungsten (W), copper (Cu), titanium (Ti), tantalum (Ta), nickel (Ni), tin (Sn), chromium (Cr), gold (Au), silver (Ag), etc. or any other combination.

[0059] Figure 1 The semiconductor structure shown includes a trench structure 17 located in the third dielectric layer 16 and a second metal layer 22 located in the trench structure 17 . A first through hole 181 is located below the trench structure 17 and penetrates the second dielectric layer 15 and a portion of the third dielectric layer 16 .

[0060] But not limited to this, such as Figure 2 As shown, in some other embodiments of the present disclosure, the trench structure 17 may not be formed in the third dielectric layer 16. The first through hole 181 may completely penetrate the second dielectric layer 15 and the third dielectric layer 16. The barrier layer 19 may cover the sidewalls of the first through hole 181 and the top surface of the third dielectric layer 16. The top surface of the conductive plug 21 may be flush with the top surface of the barrier layer 19. In subsequent processes, a planarization process may be performed to remove the barrier layer 19 and the conductive plug 21 located above the plane of the top surface of the third dielectric layer 16.

[0061] The present disclosure also provides a method for manufacturing a semiconductor structure. Figure 3 As shown, the method includes the following steps: Step S101: providing a first dielectric layer, and forming a first metal layer in the first dielectric layer, wherein the first dielectric layer does not cover a top surface of the first metal layer; Step S102, forming a first initial self-assembled monolayer on the first metal layer; Step S103: forming a second dielectric layer on the first dielectric layer, wherein the second dielectric layer covers the first initial self-assembled monolayer; Step S104: providing a third dielectric layer, placing the third dielectric layer above the second dielectric layer and bonding the third dielectric layer to the second dielectric layer; Step S105 , forming a first through hole, wherein the first through hole penetrates the second dielectric layer and at least a portion of the third dielectric layer, and exposes a portion of the first initial self-assembled monolayer; Step S106: forming a barrier layer, wherein the barrier layer at least covers the sidewalls of the first through hole and does not cover the bottom of the first through hole; Step S107: removing the exposed first initial self-assembled monolayer from the bottom of the first through-hole to form a second through-hole, with the remaining first initial self-assembled monolayer serving as the self-assembled monolayer. The second through-hole is located below the first through-hole and communicates with the first through-hole, and the second through-hole exposes a portion of the top surface of the first metal layer and a portion of the sidewall of the self-assembled monolayer. Step S108 : forming a conductive plug, wherein the conductive plug covers the barrier layer in the first through hole and fills the first through hole and the second through hole, and the conductive plug is in direct contact with the first metal layer.

[0062] The manufacturing method provided by the present disclosure is described in detail below with reference to the accompanying drawings.

[0063] First, execute step S101, as Figure 4 As shown, a first dielectric layer 11 is provided, and a first metal layer 12 is formed in the first dielectric layer 11 , and the first dielectric layer 11 does not cover the top surface of the first metal layer 12 .

[0064] In practice, the method for manufacturing a semiconductor structure may further include providing a first substrate (not shown), forming a first dielectric layer 11 on the first substrate, and forming multiple functional structures on and within the first substrate, such as transistors, capacitors, word lines, and bit lines. An interconnect structure (not shown) may also be formed within the first dielectric layer 11, and the first metal layer 12 may be electrically connected to the functional structures via the interconnect structure. The first substrate may include a wafer, such as a silicon wafer.

[0065] In actual operation, the first dielectric layer 11 can be a single-layer structure or a multi-layer structure. The material of the first dielectric layer 11 can include one or more of oxides (such as silicon oxide), nitrides (such as silicon nitride), oxynitrides (such as silicon oxynitride), silicon oxycarbide, borophosphosilicate glass, tetraethoxysilane, etc.

[0066] In actual operation, the first dielectric layer 11 may be patterned, and then a conductive material may be filled into the patterned first dielectric layer 11 to form the first metal layer 12. The material of the first metal layer 12 may include tungsten (W), copper (Cu), titanium (Ti), tantalum (Ta), nickel (Ni), tin (Sn), chromium (Cr), gold (Au), silver (Ag), or any other combination thereof.

[0067] like Figure 4 As shown, there may be multiple first metal layers 12 , and the multiple first metal layers 12 may be spaced apart in the first dielectric layer 11 , and the top surface of the first metal layer 12 may be flush with the top surface of the first dielectric layer 11 .

[0068] Next, execute step S102, as shown in FIG. Figures 5 and 6 as well as Figure 8 As shown, a first initial self-assembled monolayer 13 ′ is formed on the first metal layer 12 .

[0069] like Figure 7 As shown, in some embodiments, the method may further include: forming an initial isolation structure 14', the initial isolation structure 14' covering the top surface of the first dielectric layer 11 around the first metal layer 12. In some embodiments, the initial isolation structure 14' may be disposed around the first initial self-assembled monolayer 13'.

[0070] See again Figures 5 to 8 In some embodiments, forming a first initial self-assembled monolayer 13' on the first metal layer 12 to form an initial isolation structure 14' includes: A second initial self-assembled monolayer 13 ″ (eg, Figures 5 and 6 ); An initial isolation structure 14' is formed, and the initial isolation structure 14' covers the top surface of the first dielectric layer 11 located around the first metal layer 12 (eg Figure 7 ); A portion of the second initial self-assembled monolayer 13'' is removed, and the remaining second initial self-assembled monolayer 13'' is used as the first initial self-assembled monolayer 13', and the top surface of the initial isolation structure 14' protrudes from the top surface of the first initial self-assembled monolayer 13' (e.g. Figure 8 ).

[0071] See again Figures 5 and 6 In some embodiments, the second initial self-assembled monolayer 13'' can be formed specifically by the following method: first, as shown in FIG. Figure 5 As shown in FIG. (1), a self-assembled monolayer (SAM) solution containing self-assembled monolayer molecules 131 is prepared, and the self-assembled monolayer solution is spin-coated on the surface of the first dielectric layer 11 and the first metal layer 12; then, as shown in FIG. Figure 5 As shown in FIG. (2), the substrate spin-coated with the self-assembled monolayer solution is heated to a preset temperature (e.g., 150°C) under an inert atmosphere (e.g., N2) and maintained for a preset time (e.g., 3 minutes) to provide energy to the self-assembled monolayer molecules 131, promote the adsorption of the self-assembled monolayer molecules 131 on the surface of the first metal layer 12, and improve the orderliness and density of the self-assembled monolayer molecules 131; then, as shown in FIG. Figure 5As shown in FIG. (3), a first cleaning process is performed to remove the excess self-assembled monolayer molecules 131 that are weakly bonded to the surfaces of the first dielectric layer 11 and the first metal layer 12. The remaining self-assembled monolayer molecules 131 form a second initial self-assembled monolayer 13'' to form a surface of the first metal layer 12 as shown in FIG. Figure 6 A second initial self-assembled monolayer 13 ″ is shown.

[0072] Self-assembled monolayer molecules 131 are amphiphilic molecules composed of long-chain carbon atoms, consisting of a head group, a molecular chain, and a tail group. The head group of self-assembled monolayer molecules 131 exhibits strong chemical adsorption to the metal material. In some embodiments, the material of the second initial self-assembled monolayer 13'' may include, but is not limited to, alkylthiols, such as octadecylthiol. For example, when the material of the second initial self-assembled monolayer 13'' includes alkylthiols, the sulfur atoms in the second initial self-assembled monolayer 13'' can form strong chemical bonds with the metal atoms in the first metal layer 12 (e.g., copper) and can be arranged in an orderly manner on the surface of the first metal layer 12. The adsorption between the self-assembled monolayer molecules 131 and the first dielectric layer 11 is primarily physical adsorption, resulting in weaker adsorption. Therefore, during the first cleaning process, the self-assembled monolayer molecules 131 located on the surface of the first dielectric layer 11 can be removed, leaving the remaining self-assembled monolayer molecules 131 adsorbed in an orderly manner on the first metal layer 12.

[0073] See again Figure 7 In actual operation, the initial isolation structure 14 ′ can be formed by one or more thin film processes including chemical vapor deposition (CVD), plasma enhanced chemical vapor deposition (PECVD), physical vapor deposition (PVD), atomic layer deposition (ALD), etc.

[0074] The material of the initial isolation structure 14' has a weak bonding force with the second initial self-assembled monolayer 13". During the deposition of the initial isolation structure 14', the material of the initial isolation structure 14' has a weak bonding force with the surface of the second initial self-assembled monolayer 13", making it difficult for the initial isolation structure 14' to be adsorbed on the surface of the second initial self-assembled monolayer 13". In actual operation, after depositing the material of the initial isolation structure 14', a second cleaning process may be performed to remove the material of the initial isolation structure 14' that is weakly bonded to the second initial self-assembled monolayer 13", thereby achieving self-alignment and selective formation of the initial isolation structure 14' on the top surface of the first dielectric layer 11 surrounding the first metal layer 12.

[0075] See again Figure 6 and Figure 8In some embodiments, before forming the initial isolation structure 14', a thicker second initial self-assembled monolayer 13'' can be first formed on the surface of the first metal layer 12. After forming the initial isolation structure 14', a portion of the second initial self-assembled monolayer 13'' can be removed to form a thinner first initial self-assembled monolayer 13'. In the embodiment of the present disclosure, the thicker second initial self-assembled monolayer 13'' is formed first, which can avoid removing a portion of the second initial self-assembled monolayer 13'' located on the surface of the first metal layer 12 during the second cleaning process, resulting in insufficient thickness of the remaining second initial self-assembled monolayer 13''.

[0076] In actual operation, a dry etching process may be used to remove a portion of the second initial self-assembled monolayer 13 ″.

[0077] In some embodiments, the thickness of the first initial self-assembled monolayer 13' is in the range of 1 nm to 3 nm, for example, 1 nm, 2 nm, 3 nm, etc. By controlling the thickness of the first initial self-assembled monolayer 13' within the above range, the subsequently formed barrier layer 19 (see Figure 13 ) nucleates on the surface of the first initial self-assembled monolayer 13'.

[0078] Next, execute step S103, as shown in FIG. Figure 9 As shown, a second dielectric layer 15 is formed on the first dielectric layer 11 , and the second dielectric layer 15 covers the first initial self-assembled monolayer 13 ′.

[0079] In actual operation, the material layer of the second dielectric layer 15 can be formed by one or more thin film processes such as chemical vapor deposition (CVD), plasma enhanced chemical vapor deposition (PECVD), physical vapor deposition (PVD), atomic layer deposition (ALD), etc., and then a planarization process is performed on the material layer of the second dielectric layer 15 to form the second dielectric layer 15.

[0080] In some embodiments, the initial isolation structure 14 ′ may be formed before forming the second dielectric layer 15 , and the second dielectric layer 15 further covers the initial isolation structure 14 ′.

[0081] Specifically, forming the second dielectric layer 15 on the first dielectric layer 11 includes: forming the second dielectric layer 15 on the first dielectric layer 11, wherein the second dielectric layer 15 covers the first initial self-assembled monolayer 13' and the initial isolation structures 14' and fills the gaps between the initial isolation structures 14'.

[0082] Next, execute step S104, as shown in FIG. Figure 10 As shown, a third dielectric layer 16 is provided, and the third dielectric layer 16 is placed above the second dielectric layer 15 and bonded to the second dielectric layer 15 .

[0083] In some embodiments, the method may further include providing a second substrate (not shown), wherein the third dielectric layer 16 may be formed on a side surface of the second substrate. After the third dielectric layer 16 is formed on the surface of the second substrate, a surface of the second dielectric layer 15 facing away from the first substrate and a surface of the third dielectric layer 16 facing away from the second substrate may be bonded together. The second substrate may include a wafer, such as a silicon wafer.

[0084] Then, execute step S105, as shown in FIG. Figure 12 As shown, a first through hole 181 is formed, which penetrates the second dielectric layer 15 and at least a portion of the third dielectric layer 16 and exposes a portion of the first initial self-assembled monolayer 13 ′.

[0085] See also Figure 11 In some embodiments, the first through hole 181 penetrates the second dielectric layer 15 and a portion of the third dielectric layer 16. Before forming the first through hole 181, the method may further include: forming a trench structure 17 in the third dielectric layer 16, wherein the first through hole 181 is located below the trench structure 17 and is connected to the trench structure 17.

[0086] like Figure 12 As shown, in some embodiments, the projected area of ​​the trench structure 17 on the plane of the first dielectric layer 11 may be larger than the projected area of ​​the first through hole 181 on the plane of the first dielectric layer 11 .

[0087] In some embodiments, the orthographic projection of the first through hole 181 on the plane of the first dielectric layer 11 at least partially overlaps with the orthographic projection of the first initial self-assembled monolayer 13 ′ on the plane of the first dielectric layer 11 , so that the bottom of the first through hole 181 partially exposes the first initial self-assembled monolayer 13 ′.

[0088] In some embodiments, the orthographic projection of the first through hole 181 on the plane of the first dielectric layer 11 may also partially overlap with the orthographic projection of the initial isolation structure 14 ′ on the plane of the first dielectric layer 11 . Part of the initial isolation structure 14 ′ is also removed during the formation of the first through hole 181 .

[0089] Specifically, forming the first through hole 181 may include: The third dielectric layer 16, the second dielectric layer 15, and the initial isolation structure 14' are etched to form a first through-hole 181. The initial isolation structure 14' remaining after etching serves as the isolation structure 14. The lower sidewall of the first through-hole 181 exposes a portion of the sidewall of the isolation structure 14. The exposed sidewall of the isolation structure 14 is an inclined sidewall. As the etching depth gradually increases, the width of the removed initial isolation structure 14' in a direction parallel to the plane of the first dielectric layer 11 decreases, so that the width of the portion of the first through-hole 181 exposing the inclined sidewall of the isolation structure 14 in a direction parallel to the plane of the first dielectric layer 11 decreases in a direction perpendicular to the plane of the first dielectric layer 11 and from the first through-hole 181 to the first dielectric layer 11.

[0090] In some embodiments, the material of isolation structure 14 is doped with carbon and / or nitrogen. The total mass percentage of carbon and nitrogen in isolation structure 14 is m1, and m1 is between 10% and 40%, for example, 10%, 15%, 20%, 30%, 40%, etc. The mass percentage of carbon in isolation structure 14 can be 0, indicating that isolation structure 14 does not contain carbon. Alternatively, the mass percentage of nitrogen in isolation structure 14 can be 0, indicating that isolation structure 14 does not contain nitrogen. Alternatively, the mass percentage of both nitrogen and carbon in isolation structure 14 can be greater than 0, indicating that isolation structure 14 contains both nitrogen and carbon.

[0091] By controlling the total mass percentage of carbon and nitrogen in the material of the isolation structure 14 within the aforementioned range, the etching rate of the first through-hole 181 can be reduced, thereby improving the etching selectivity between the second dielectric layer 15 and the initial isolation structure 14'. In some embodiments, the ratio of the etching rate of the second dielectric layer 15 to the etching rate of the initial isolation structure 14' can be in a range of 5:1 to 20:1, for example, 5:1, 10:1, 15:1, 20:1, etc.

[0092] In this way, by controlling the second dielectric layer 15 and the initial isolation structure 14' to have a larger etching selectivity, during the process of forming the first through hole 181, as the etching depth increases, the etching width of the initial isolation structure 14' gradually decreases, thereby gradually reducing the width of the lower portion of the first through hole 181 to obtain the required morphology of the first through hole 181.

[0093] In the subsequent process, a conductive plug 21 electrically connected to the first metal layer 12 may be formed (see Figure 1), a portion of the conductive plug 21 is located within the first through-hole 181, and the isolation structure 14 electrically isolates the conductive plug 21 from other first metal layers 12 except the first metal layer 12 electrically connected to the conductive plug 21. In the embodiment of the present disclosure, along a direction perpendicular to the plane of the first dielectric layer 11 and pointing from the first through-hole 181 to the first dielectric layer 11, the width of the lower portion of the first through-hole 181 gradually decreases, while the width of the isolation structure 14 whose sidewalls are exposed by the first through-hole 181 gradually increases. The distance between the conductive plug 21 and the other first metal layers 12 in a direction parallel to the plane of the first dielectric layer 11 gradually increases. In this way, the isolation effect of the isolation structure 14 can be enhanced, parasitic capacitance can be reduced, the withstand voltage characteristics of the conductive plug 21 can be improved, and leakage can be avoided or reduced.

[0094] In some embodiments, the ratio of the etching rate of the third dielectric layer 16 to the etching rate of the initial isolation structure 14 ′ ranges from 5:1 to 20:1, for example, 5:1, 10:1, 15:1, 20:1, etc. In this way, the etching consistency of the second dielectric layer 15 and the third dielectric layer 16 can be maintained, and the morphology quality of the first through hole 181 located in the second dielectric layer 15 and the third dielectric layer 16 can be improved.

[0095] In some embodiments, the materials of the isolation structure 14, the second dielectric layer 15, and the third dielectric layer 16 independently include at least one of silicon oxide, silicon carbonitride, silicon oxynitride, silicon oxycarbide, borophosphosilicate glass, and tetraethoxysilane. The total mass percentage of carbon and nitrogen in the second dielectric layer 15 is in the range of m2, and the total mass percentage of carbon and nitrogen in the third dielectric layer 16 is in the range of m3. m1 is greater than m2, and the difference between the two is in the range of 10% to 30% (including endpoint values, such as 10%, 15%, 20%, 30%, etc.); m1 is greater than m3, and the difference between the two is in the range of 10% to 30% (including endpoint values, such as 10%, 15%, 20%, 30%, etc.).

[0096] The values ​​of m2 and m3 may both be greater than or equal to 0; the mass percentage of carbon and / or the mass percentage of nitrogen in the second dielectric layer 15 may be greater than or equal to 0; and the mass percentage of carbon and / or the mass percentage of nitrogen in the third dielectric layer 16 may also be greater than or equal to 0. For example, the second dielectric layer 15 and the third dielectric layer 16 may be made of silicon oxide, and may contain no nitrogen or carbon. The isolation structure 14 may be made of silicon oxynitride, and the mass percentage of silicon, oxygen, and nitrogen in the isolation structure 14 may be 48.369%, 27.5417%, and 24.1114%.

[0097] In this way, by controlling the difference between m1 and m2, and the difference between m1 and m3 within the above range, the etching selectivity ratio of the second dielectric layer 15 and the isolation structure 14, and the etching selectivity ratio of the third dielectric layer 16 and the isolation structure 14 can be adjusted within the required range.

[0098] Next, execute step S106, as shown in FIG. Figure 13 As shown, a barrier layer 19 is formed, and the barrier layer 19 at least covers the sidewalls of the first through hole 181 but does not cover the bottom of the first through hole 181 .

[0099] In actual operation, the barrier layer 19 can be formed by one or more thin film processes such as chemical vapor deposition (CVD), plasma enhanced chemical vapor deposition (PECVD), physical vapor deposition (PVD), atomic layer deposition (ALD), electroplating, electroless plating, sputtering, evaporation, etc. The material of the barrier layer 19 can include titanium, tantalum, titanium nitride, tantalum nitride, and other materials with barrier properties.

[0100] During the formation of barrier layer 19, it is difficult for barrier layer 19 to nucleate on the surface of first initial self-assembled monolayer 13'. The material of barrier layer 19 has a weak bond with first initial self-assembled monolayer 13' at the bottom of first through-hole 181, and barrier layer 19 merely floats on the surface of first initial self-assembled monolayer 13'. In practice, after depositing barrier layer 19 material, a third cleaning process can be performed to remove barrier layer 19 material that is weakly bonded to second initial self-assembled monolayer 13". In this manner, after cleaning, barrier layer 19 will not be adsorbed and formed on the surface of first initial self-assembled monolayer 13'. Therefore, barrier layer 19 can be selectively formed, avoiding formation of barrier layer 19 at the bottom of first through-hole 181.

[0101] See again Figure 13 In some embodiments, the barrier layer 19 may further cover the sidewalls and a portion of the bottom surface of the trench structure 17. Here, the portion of the bottom surface of the trench structure 17 covered by the barrier layer 19 refers to the bottom surface of the trench structure 17 not penetrated by the first through hole 181.

[0102] See again Figure 13 In some embodiments, the barrier layer 19 may also cover the top surface of the third dielectric layer 16 .

[0103] Next, execute step S107, as shown in FIG. Figure 14 As shown, the exposed first initial self-assembled monolayer 13' is removed from the bottom of the first through hole 181 to form a second through hole 182, and the remaining first initial self-assembled monolayer 13' serves as the self-assembled monolayer 13. The second through hole 182 is located below the first through hole 181 and is connected to the first through hole 181, and the second through hole 182 exposes a portion of the top surface of the first metal layer 12 and a portion of the side wall of the self-assembled monolayer 13.

[0104] Here, the portion of the sidewall of the self-assembled monolayer 13 exposed by the second through hole 182 refers to the sidewall of the self-assembled monolayer 13 located on the surface of the first metal layer 12 and surrounding or partially surrounding the second through hole 182 .

[0105] like Figure 14 As shown, in some embodiments, during the process of removing the exposed first initial self-assembled monolayer 13' from the bottom of the first through hole 181, a portion of the first initial self-assembled monolayer 13' may be laterally etched to remove a portion of the first initial self-assembled monolayer 13' located on the sidewall of the isolation structure 14.

[0106] In actual operation, the exposed first initial self-assembled monolayer 13 ′ can be removed by a wet process or a dry process.

[0107] Next, execute step S108, as shown in FIG. Figure 1 As shown, a conductive plug 21 is formed. The conductive plug 21 covers the barrier layer 19 in the first through hole 181 and fills the first through hole 181 and the second through hole 182 . The conductive plug 21 is in direct contact with the first metal layer 12 .

[0108] See again Figure 1 In some embodiments, while forming the conductive plug 21 , the method further includes: simultaneously forming a second metal layer 22 , the second metal layer 22 covering the barrier layer 19 located in the trench structure 17 , filling the trench structure 17 and connecting to the conductive plug 21 .

[0109] In some embodiments, the top surface of the second metal layer 22 may be flush with the top surface of the barrier layer 19. In subsequent processes, a planarization process may be performed to remove the barrier layer 19 and the second metal layer 22 above the plane where the top surface of the third dielectric layer 16 is located.

[0110] In actual operation, conductive material can be filled in the first through hole 181, the second through hole 182 and the trench structure 17 by one or more thin film processes such as chemical vapor deposition (CVD), plasma enhanced chemical vapor deposition (PECVD), physical vapor deposition (PVD), atomic layer deposition (ALD), electroplating, chemical plating, sputtering, evaporation, etc. to form a conductive plug 21 and a second metal layer 22 respectively, and the second metal layer 22 is electrically connected to the first metal layer 12 through the conductive plug 21.

[0111] In actual operation, the materials of the conductive plug 21 and the second metal layer 22 may include tungsten (W), copper (Cu), titanium (Ti), tantalum (Ta), nickel (Ni), tin (Sn), chromium (Cr), gold (Au), silver (Ag), etc. or any other combination.

[0112] In the embodiment of the present disclosure, alignment of the first through hole 181 can be achieved by forming a first initial self-assembled monolayer 13' on the first metal layer 12, and the barrier layer 19 is not easily adsorbed on the surface of the first initial self-assembled monolayer 13', thereby avoiding the formation of the barrier layer 19 at the bottom of the first through hole 181 (after cleaning, the barrier layer 19 will not be adsorbed on the surface of the first initial self-assembled monolayer 13'), thereby avoiding the formation of the barrier layer 19 between the conductive plug 21 and the first metal layer 12. The conductive plug 21 is directly contacted and connected with the first metal layer 12, thereby reducing the RC resistance of the conductive plug 21 and improving the performance of the semiconductor structure.

[0113] Figures 11 to 14 as well as Figure 1 In the illustrated semiconductor structure, a trench structure 17 is formed in the third dielectric layer 16 before forming the first through hole 181. The first through hole 181 is located below the trench structure 17 and penetrates the second dielectric layer 15 and a portion of the third dielectric layer 16. However, the present invention is not limited thereto. In other embodiments of the present disclosure, the trench structure 17 may not be formed in the third dielectric layer 16, and the first through hole 181 may completely penetrate the second dielectric layer 15 and the third dielectric layer 16.

[0114] Specifically, such as Figure 15 As shown, a first through hole 181 is formed, which passes through the third dielectric layer 16 and the second dielectric layer 15 and exposes a portion of the first initial self-assembled monolayer 13 ′.

[0115] Then, if Figure 16 As shown, a barrier layer 19 is formed, and the barrier layer 19 covers the sidewalls of the first through hole 181 and the top surface of the third dielectric layer 16 , but does not cover the bottom of the first through hole 181 .

[0116] Next, if Figure 17 As shown, the exposed first initial self-assembled monolayer 13 ′ is removed from the bottom of the first through hole 181 to form a second through hole 182 .

[0117] Next, a conductive plug 21 is formed to cover the barrier layer 19 and fill the first through hole 181 and the second through hole 182. Figure 2 The structure shown.

[0118] In some embodiments, the top surface of the conductive plug 21 may be flush with the top surface of the barrier layer 19. In subsequent processes, a planarization process may be performed to remove the barrier layer 19 and the conductive plug 21 above the plane where the top surface of the third dielectric layer 16 is located.

[0119] The various technical features in the technical solutions described in the various embodiments may be arbitrarily combined unless they conflict. Those skilled in the art will be able to change the order of the steps in the above-mentioned formation method without departing from the scope of protection of this disclosure. The various steps in the embodiments of this disclosure may be performed simultaneously or sequentially unless they conflict.

[0120] The above description is merely a preferred embodiment of the present disclosure and is not intended to limit the scope of protection of the present disclosure. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of the present disclosure shall be included in the scope of protection of the present disclosure.

Claims

1. A semiconductor structure, characterized in that include: a first dielectric layer, and a first metal layer located within the first dielectric layer, wherein the first dielectric layer does not cover a top surface of the first metal layer; a self-assembled monolayer covering a portion of the top surface of the first metal layer; a second dielectric layer, located on the first dielectric layer and covering the self-assembled monolayer; a third dielectric layer, located on the second dielectric layer and bonded to the second dielectric layer; a first through hole, passing through the second dielectric layer and at least a portion of the third dielectric layer; a barrier layer, covering at least a sidewall of the first through hole and not covering a bottom of the first through hole; a second through hole, located below the first through hole and connected to the first through hole, the second through hole exposing a portion of the top surface of the first metal layer and a portion of the sidewall of the self-assembled monolayer; A conductive plug covers the barrier layer in the first through hole and fills the first through hole and the second through hole, wherein the conductive plug is in direct contact with the first metal layer.

2. The semiconductor structure according to claim 1, wherein: The semiconductor structure further includes an isolation structure located in the second dielectric layer and covering a top surface of the first dielectric layer surrounding the first metal layer, wherein a top surface of the isolation structure protrudes from a top surface of the self-assembled monolayer.

3. The semiconductor structure according to claim 2, wherein: The material of the isolation structure is doped with carbon and / or nitrogen. The total mass percentage of the carbon and nitrogen elements in the isolation structure is m1, and m1 is between 10% and 40%.

4. The semiconductor structure according to claim 3, wherein: The ratio of the etching rate of the second dielectric layer to the etching rate of the isolation structure is in a range of 5:1 to 20:1; and / or, The ratio of the etching rate of the third dielectric layer to the etching rate of the isolation structure ranges from 5:1 to 20:

1.

5. The semiconductor structure according to claim 3 or 4, characterized in that: The materials of the isolation structure, the second dielectric layer, and the third dielectric layer independently include at least one of silicon oxide, silicon carbon nitride, silicon oxynitride, silicon oxycarbide, borophosphosilicate glass, and tetraethoxysilane. The total mass percentage of carbon and nitrogen elements in the second dielectric layer is in the range of m2, and the total mass percentage of carbon and nitrogen elements in the third dielectric layer is in the range of m3. m1 is greater than m2, and the difference between the two is in the range of 10% to 30%; m1 is greater than m3, and the difference between the two is in the range of 10% to 30%.

6. The semiconductor structure according to claim 2, wherein: The lower sidewall of the first through hole exposes a portion of the sidewall of the isolation structure, and the exposed sidewall of the isolation structure is an inclined sidewall, so that the width of the portion of the first through hole that exposes the inclined sidewall of the isolation structure in a direction parallel to the plane of the first dielectric layer tends to decrease in a direction perpendicular to the plane of the first dielectric layer and from the first through hole to the first dielectric layer.

7. The semiconductor structure according to claim 1, wherein: The thickness of the self-assembled monolayer ranges from 1 nm to 3 nm.

8. The semiconductor structure according to claim 1, wherein: The first through hole penetrates the second dielectric layer and a portion of the third dielectric layer. The semiconductor structure further includes: a trench structure located in the third dielectric layer, wherein the first through hole is located below and communicates with the trench structure, and the barrier layer further covers a sidewall and a portion of a bottom surface of the trench structure; The second metal layer covers the barrier layer in the trench structure, fills the trench structure and is connected to the conductive plug.

9. A method for manufacturing a semiconductor structure, characterized in that: include: Providing a first dielectric layer, and forming a first metal layer in the first dielectric layer, wherein the first dielectric layer does not cover a top surface of the first metal layer; forming a first initial self-assembled monolayer on the first metal layer; forming a second dielectric layer on the first dielectric layer, wherein the second dielectric layer covers the first initial self-assembled monolayer; Providing a third dielectric layer, placing the third dielectric layer above the second dielectric layer and bonding the third dielectric layer to the second dielectric layer; forming a first through hole, wherein the first through hole penetrates the second dielectric layer and at least a portion of the third dielectric layer and exposes a portion of the first initial self-assembled monolayer; forming a barrier layer, wherein the barrier layer at least covers the sidewalls of the first through hole and does not cover the bottom of the first through hole; Removing the exposed first initial self-assembled monolayer from the bottom of the first through-hole to form a second through-hole, with the remaining first initial self-assembled monolayer serving as a self-assembled monolayer, wherein the second through-hole is located below and communicates with the first through-hole, and the second through-hole exposes a portion of the top surface of the first metal layer and a portion of the sidewall of the self-assembled monolayer; A conductive plug is formed, where the conductive plug covers the barrier layer in the first through hole and fills the first through hole and the second through hole, and the conductive plug is in direct contact with the first metal layer.

10. The manufacturing method according to claim 9, characterized in that: Before forming the second dielectric layer on the first dielectric layer, the method further includes: An initial isolation structure is formed, where the initial isolation structure covers a top surface of the first dielectric layer surrounding the first metal layer, and the second dielectric layer further covers the initial isolation structure.

11. The manufacturing method according to claim 10, characterized in that: Forming a first initial self-assembled monolayer on the first metal layer to form an initial isolation structure, comprising: forming a second initial self-assembled monolayer on the first metal layer; forming an initial isolation structure, wherein the initial isolation structure covers a top surface of the first dielectric layer located around the first metal layer; Part of the thickness of the second initial self-assembled monolayer is removed, and the remaining second initial self-assembled monolayer serves as the first initial self-assembled monolayer, the thickness of the first initial self-assembled monolayer ranges from 1 nm to 3 nm, and the top surface of the initial isolation structure protrudes from the top surface of the first initial self-assembled monolayer.

12. The manufacturing method according to claim 10 or 11, characterized in that: Forming a first through hole includes: The third dielectric layer, the second dielectric layer, and the initial isolation structure are etched to form the first through hole. The initial isolation structure remaining after etching serves as the isolation structure. The lower sidewall of the first through hole exposes a portion of the sidewall of the isolation structure, and the exposed sidewall of the isolation structure is an inclined sidewall. As the etching depth gradually increases, the width of the removed initial isolation structure in a direction parallel to the plane of the first dielectric layer decreases, so that the width of the portion of the first through hole that exposes the inclined sidewall of the isolation structure in a direction parallel to the plane of the first dielectric layer decreases in a direction perpendicular to the plane of the first dielectric layer and from the first through hole to the first dielectric layer.

13. The manufacturing method according to claim 12, characterized in that: The ratio of the etching rate of the second dielectric layer to the etching rate of the initial isolation structure is in a range of 5:1 to 20:1; and / or, The ratio of the etching rate of the third dielectric layer to the etching rate of the initial isolation structure ranges from 5:1 to 20:

1.

14. The manufacturing method according to claim 9, characterized in that The first through hole penetrates the second dielectric layer and a portion of the third dielectric layer. Before forming the first through hole, the method further includes: A trench structure is formed in the third dielectric layer, wherein the first through hole is located below the trench structure and communicates with the trench structure; the barrier layer also covers the sidewalls and a portion of the bottom surface of the trench structure; While forming the conductive plug, the method further includes: synchronously forming a second metal layer, wherein the second metal layer covers the barrier layer in the trench structure, fills the trench structure and is connected to the conductive plug.

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