Structure for laterally diffused metal oxide semiconductor transistor

Abstract

A structure for a laterally diffused metal oxide semiconductor device and a method of forming a structure for a laterally diffused metal oxide semiconductor device. The structure includes a drain and a source in a semiconductor substrate. The source includes a source region having a first terminal, a second terminal, and a length between the first terminal and the second terminal. The structure also includes a shallow trench isolation region in the semiconductor substrate. The shallow trench isolation region surrounds the drain. The structure also includes a gate surrounding the shallow trench isolation region and the drain. The gate has a side portion between the drain and source regions, the side portion of the gate having a width, and the gate having a length in a direction transverse to the width. A length of the source region is substantially equal to a length of the gate.

Description

Technical Field

[0001] The present disclosure relates generally to semiconductor devices and integrated circuit fabrication, and more particularly to structures for laterally diffused metal oxide semiconductor devices and methods of forming structures for laterally diffused metal oxide semiconductor devices. Background Art

[0002] For example, high-voltage integrated circuits used in power amplifiers typically require specialized device technologies capable of withstanding high voltages, such as voltages in the range of seven to fifty volts. Laterally diffused metal oxide semiconductor transistors are devices designed to handle such high voltages by incorporating additional transistor features that improve voltage handling capabilities, such as a drift well that provides an extended drain.

[0003] There is a need for improved structures for laterally diffused metal oxide semiconductor devices and methods of forming structures for laterally diffused metal oxide semiconductor devices. Summary of the Invention

[0004] In one embodiment, a structure for a laterally diffused metal oxide semiconductor transistor is provided. The structure includes: a semiconductor substrate; a drain located in the semiconductor substrate; and a source located in the semiconductor substrate. The source includes a source region having a first terminal, a second terminal, and a length between the first terminal and the second terminal. The structure also includes: a shallow trench isolation region located in the semiconductor substrate. The shallow trench isolation region surrounds the drain. The structure also includes: a gate surrounding the shallow trench isolation region and the drain. The gate has a side portion located between the drain and the source region, the side portion of the gate has a width, and the gate has a length in a direction transverse to the width. The length of the source region is substantially equal to the length of the gate.

[0005] In one embodiment, a method for forming a structure for a laterally diffused metal oxide semiconductor transistor is provided. The method includes forming a source, a drain, and a shallow trench isolation region in a semiconductor substrate. The source includes a source region having a first terminal, a second terminal, and a length between the first terminal and the second terminal. The shallow trench isolation region surrounds the drain. The method also includes forming a gate surrounding the shallow trench isolation region and the drain. The gate has a side portion located between the drain and the source region, the side portion of the gate having a width, and the gate having a length in a direction transverse to the width. The length of the source region is substantially equal to the length of the gate. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate various embodiments of the present invention and, together with the general description of the invention given above and the detailed description of the embodiments given below, serve to explain embodiments of the present invention. In the accompanying drawings, like reference numerals are used to indicate like features throughout the various views.

[0007] Figure 1 is a cross-sectional view of a structure according to an embodiment of the present invention.

[0008] Figure 2 It is roughly along Figure 1 A cross-sectional view taken along line 2-2 in FIG.

[0009] Figure 2A It is roughly along Figure 1 A cross-sectional view taken along line 2A-2A in FIG.

[0010] Figure 2B It is roughly along Figure 1 A cross-sectional view taken along line 2B-2B in FIG.

[0011] Figure 2C It is roughly along Figure 1 A cross-sectional view taken along line 2C-2C in FIG. DETAILED DESCRIPTION

[0012] refer to Figure 1 、 2 , 2A, 2B, 2C and according to an embodiment of the present invention, a device structure 10 for a laterally diffused metal oxide semiconductor transistor includes a semiconductor substrate 12, a high voltage well 14 located in the semiconductor substrate 12, a shallow trench isolation structure 16 located in the semiconductor substrate 12, and a shallow trench isolation region 18 located in the semiconductor substrate 12. The semiconductor substrate 12 can be composed of a semiconductor material such as single crystal silicon. In one embodiment, the high voltage well 14 can be lightly doped with a certain concentration of n-type dopant (for example, arsenic or phosphorus) so that the high voltage well 14 has n-type conductivity. The high voltage well 14 can be formed by implanting ions (such as ions including n-type dopant) using an implantation mask, wherein the implantation mask has an opening that defines a target location for the high voltage well 14 in the semiconductor substrate 12. Implantation conditions such as ion species, dose, and kinetic energy can be selected to adjust the electrical and physical properties of the high voltage well 14. The high voltage well 14 can form a pn junction with the semiconductor substrate 12, wherein the conductivity type changes across the pn junction.

[0013] The shallow trench isolation region 16 can be formed by patterning a shallow trench in the semiconductor substrate 12 using photolithography and etching processes, depositing a dielectric material such as silicon dioxide in the shallow trench, and recessing and / or planarizing the deposited dielectric material. The shallow trench isolation region 16 can extend from the top surface 13 of the semiconductor substrate 12 to a depth D1. The shallow trench isolation region 16 completely surrounds the device region in which the LDMOS transistor is located.

[0014] The shallow trench isolation region 18 can be formed by patterning a shallow trench in the semiconductor substrate 12 using a photolithography and etching process, depositing a dielectric material such as silicon dioxide in the shallow trench, and recessing and / or planarizing the deposited dielectric material. The shallow trench isolation region 18 is deposited inside the device region and is completely surrounded by the shallow trench isolation region 16. The shallow trench isolation region 18 can extend from the top surface 13 of the semiconductor substrate 12 to a depth D2 that is less than the depth D1 of the shallow trench isolation region 16. The shallow trench isolation region 18 has a closed shape that can be tapered at opposite ends. The shallow trench isolation region 18 includes an inner boundary that completely surrounds a portion of the semiconductor substrate 12, which can be located at the center of the active area.

[0015] The well 20 can be formed in a portion of the semiconductor substrate 12. The well 20 can be disposed within the high-voltage well 14, and the well 20 can form a pn junction with the high-voltage well 14 across which the conductivity type varies. The well 20 completely surrounds the device region. The outer portion of the well 20 adjacent to the outer edge of the device region can overlap with the shallow trench isolation region 16. In one embodiment, the well 20 can contain a certain concentration of p-type dopant (e.g., boron) to provide p-type conductivity. The well 20 can be formed by implanting ions (e.g., ions including n-type dopants) using an implantation mask, wherein the implantation mask has an opening defining a target location for the well 20 in the semiconductor substrate 12. Implantation conditions such as ion species, dose, and kinetic energy can be selected to adjust the electrical and physical properties of the well 20. The well 20 can provide a drain extension for a laterally diffused metal oxide semiconductor transistor.

[0016] Body well 22 may be formed in a portion of semiconductor substrate 12. Body well 22 may be disposed within well 20. Body well 22 may abut shallow trench isolation region 16, and body well 22 may extend to a depth less than the depth of shallow trench isolation region 16. Body well 22 may provide a body of a laterally diffused metal oxide semiconductor transistor. In one embodiment, body well 22 may contain a concentration of p-type dopant (e.g., boron) to provide p-type conductivity at a higher dopant concentration than well 20. Body well 22 may be formed by implanting ions (e.g., ions including p-type dopant) using an implantation mask having an opening in semiconductor substrate 12 that defines a target location for body well 22. Implantation conditions such as ion species, dose, and kinetic energy may be selected to adjust the electrical and physical properties of body well 22.

[0017] A drain well 24 may be formed in a portion of the semiconductor substrate 12 and disposed within the high-voltage well 14. The drain well 24 may extend to a depth greater than the depth D2 of the shallow trench isolation region 18. In one embodiment, the drain well 24 may abut the shallow trench isolation region 18. In an alternative embodiment, the drain well 24 may overlap the shallow trench isolation region 18. The drain well 24 has the same conductivity type as the high-voltage well 14. In one embodiment, the drain well 24 may include a concentration of n-type dopant (e.g., arsenic or phosphorus) to provide n-type conductivity with a higher dopant concentration than the high-voltage well 14. The drain well 24 may be formed by implanting ions (e.g., ions including an n-type dopant) using an implantation mask having an opening in the semiconductor substrate 12 that defines a target location for the drain well 24. Implantation conditions, such as ion species, dose, and kinetic energy, may be selected to adjust the electrical and physical properties of the drain well 24.

[0018] Doped regions 26, 28, 30, and doped region 32 are formed in corresponding portions of semiconductor substrate 12. Doped regions 26, 28, 30, and doped region 32 are located adjacent to top surface 13 of semiconductor substrate 12. Doped region 28, which is disposed in an upper portion of drain well 24 and between drain well 24 and top surface 13, is completely surrounded on all sides by the inner edges of shallow trench isolation region 18. Doped region 28 has the same conductivity type as drain well 24, but a higher dopant concentration. Doped region 26 and doped region 30 are disposed in corresponding upper portions of body well 22. Doped region 26 and doped region 30 have a conductivity type opposite to that of body well 22.

[0019] Doped region 32 is disposed in an upper portion of body well 22. Doped region 32 laterally surrounds a portion of semiconductor substrate 12 in which doped regions 26, 28, 30, drain well 24, and shallow trench isolation region 18 are disposed. A portion of doped region 32 may laterally abut doped region 26, while another portion of doped region 32 may laterally abut doped region 30. Doped region 32 has the same conductivity type as body well 22. Doped region 32 has an opposite conductivity type to doped regions 26, 28, 30.

[0020] In one embodiment, doped regions 26, 28, 30 may include a concentration of n-type dopant (e.g., arsenic or phosphorus) to provide n-type conductivity. Doped regions 26, 28, 30 may be formed by implanting ions (e.g., ions including n-type dopant) using an implantation mask having openings defining target locations for doped regions 26, 28, 30 in semiconductor substrate 12. The formation of doped region 28 may be self-aligned with drain well 24 through shallow trench isolation region 18. Implantation conditions such as ion species, dose, and kinetic energy may be selected to adjust the electrical and physical properties of doped regions 26, 28, 30, which may be heavily doped.

[0021] In one embodiment, doped region 32 may include a concentration of p-type dopant (e.g., boron) to provide p-type conductivity. Doped region 32 may be formed by implanting ions (e.g., ions including an n-type dopant) using an implantation mask having openings defining target locations for doped region 32 in semiconductor substrate 12. Implantation conditions such as ion species, dose, and kinetic energy may be selected to adjust the electrical and physical properties of doped region 32, which may be heavily doped.

[0022] The LDMOS transistor may include a source region formed by a source region provided by doped region 26 and a source region provided by doped region 30. Doped region 26 may have a straight outer boundary around a region at top surface 13 of semiconductor substrate 12 in a cross-sectional profile. Doped region 30 may also have a straight outer boundary around a region at top surface 13 of semiconductor substrate 12 in a cross-sectional profile. In one embodiment, the enclosing region associated with doped region 26 may be equal in size to the enclosing region associated with doped region 30.

[0023] Doped region 26 has a terminal 25 and a terminal 27 opposite terminal 25, and opposite ends 25 and 27 terminate at portions of doped region 32 and share a corresponding boundary with these portions. Doped region 26 has a length L1 that can be measured between terminal 25 and terminal 27. Doped region 30 has a terminal 29 and a terminal 31 opposite terminal 29, and opposite ends 29 and 31 terminate at portions of doped region 32 and share a corresponding boundary with these portions. Doped region 30 has a length L2 that can be measured between terminal 29 and terminal 31. Length L1 of doped region 26 can be substantially equal to length L2 of doped region 30. In one embodiment, length L1 of doped region 26 can be equal to length L2 of doped region 30.

[0024] Doped region 28 may provide a drain of the LDMOS transistor. In cross-sectional profile, doped region 28 may have a straight outer boundary surrounding a region at top surface 13 of semiconductor substrate 12 and surrounded by shallow trench isolation region 18. Doped region 28 may have a length L that is less than length L1 of doped region 26 or length L2 of doped region 30, such that the drain is shorter than either source region.

[0025] Gate 36 is formed on and above a portion of top surface 13 of semiconductor substrate 12. A gate dielectric layer 38, characterized by various thicknesses, is disposed between gate 36 and top surface 13 of semiconductor substrate 12. In one embodiment, gate 36 may be formed of a conductor such as doped polysilicon, and gate dielectric layer 38 may be formed of a dielectric material such as silicon dioxide. A thicker portion of gate dielectric layer 38, which may be formed by high-temperature oxidation, is disposed adjacent to doped region 28, which provides the drain of the LDMOS transistor. Gate 36 and gate dielectric layer 38 may overlap a portion of shallow trench isolation region 18 adjacent to doped region 28.

[0026] Gate 36 includes side subdivisions 40 and 42 disposed on opposite sides of doped region 28 and end subdivisions 44 and 46 connecting side subdivision 40 to side subdivision 42. Side subdivisions 40 and 42 and end subdivisions 44 and 46 of gate 36 collectively provide a closed shape surrounding shallow trench isolation region 18, doped regions 26 and 30 providing a source of the LDMOS transistor, and doped region 28 providing a drain of the LDMOS transistor.

[0027] Side subdivision 40 of gate 36 and ends 25, 27 of doped region 30 may be coextensive or substantially coextensive (i.e., share a boundary) with portions of doped region 32. In one embodiment, side subdivision 40 of gate 36 may have a length substantially equal to length L1 of doped region 26. In alternative embodiments, side subdivision 40 of gate 36 may have a length equal to length L1 of doped region 26. The length of side subdivision 40 of gate 36 may be greater than length L of doped region 28.

[0028] Side portion 42 of gate 36 and ends 29, 31 of doped region 26 may be coextensive or substantially coextensive (i.e., share a boundary) with a portion of doped region 32. In one embodiment, side portion 42 of gate 36 may have a length substantially equal to length L2 of doped region 30. In an alternative embodiment, side portion 42 of gate 36 may have a length equal to length L2 of doped region 30. The length of side portion 42 of gate 36 may be greater than length L of doped region 28.

[0029] Each of the side subdivisions 40, 42 has a width W in a direction transverse to its respective length, and the length of each of the side subdivisions 40, 42 can be greater than the width W, so that the gate 36 is elongated. The width W can be constant over the length L of the doped region 28, can widen adjacent to the tapered subdivision of the shallow trench isolation region 18, and can be wider at a location connected by the narrow end subdivisions 44, 46.

[0030] Doped region 32 disposed within body well 22 provides a body tap accessible at top surface 13 of semiconductor substrate 12. Body well 22 and doped region 32 within body well 22 completely surround the device region in a laterally direction. In this regard, body well 22 and doped region 32 within body well 22 completely surround a portion of semiconductor substrate 12 including shallow trench isolation region 18 and doped regions 26, 28, and 30, and also completely surround gate 36. Doped region 32 has a portion adjacent to doped region 26 along the length of gate 36, and doped region 32 has a portion adjacent to doped region 30 along the length of gate 36, with shallow trench isolation region 18, doped region 28, and gate 36 laterally disposed between these portions of doped region 32.

[0031] The LDMOS transistor has an isolation body provided by a body well 22. Termination of the shallow trench isolation region 18 and termination of the gate 36 can be used to improve device breakdown. The source of the LDMOS transistor (represented by the source region provided by doped region 26 adjacent to the side branch 40 of the gate 36 in combination with the source region provided by doped region 30 adjacent to the side branch 42 of the gate 36) does not completely surround the gate 36 of the LDMOS transistor. Instead, doped region 26 is disconnected from doped region 30, so that the source lacks regions adjacent to the end branches 44, 46 of the gate 36, and therefore lacks regions adjacent to the opposite ends of doped region 28. Thus, by dividing the source into disconnected source regions, current crowding at the drain terminal edge is reduced. In contrast to the source, the body well 22 providing the body of the LDMOS transistor completely surrounds the gate 36.

[0032] The above method is used to manufacture integrated circuit chips. The resulting integrated circuit chips can be distributed by the manufacturer in raw wafer form (e.g., as a single wafer with multiple unpackaged chips), as bare die, or in packaged form. The chips can be integrated with other chips, discrete circuit components, and / or other signal processing devices as part of an intermediate product or a final product. The final product can be any product that includes an integrated circuit chip, such as a computer product or a smartphone with a central processing unit.

[0033] References herein to terms modified by approximating language such as "about," "approximately," and "substantially" are not limited to the precise value or precise condition specified. In an embodiment, approximating language may indicate a + / - 10% range of the stated value or condition.

[0034] References herein to terms such as "vertical" and "horizontal" are made by way of example, not limitation, to establish a reference frame. As used herein, the term "horizontal" is defined as a plane parallel to the conventional plane of the semiconductor substrate, regardless of its actual three-dimensional spatial orientation. As just defined, the terms "vertical" and "normal" refer to directions perpendicular to the horizontal plane in the reference frame. The term "lateral" refers to a direction lying within the horizontal plane in the reference frame.

[0035] A feature that is “connected” or “coupled” to or “connected to” another feature may be directly connected or coupled to or “connected to” another feature, or one or more intervening features may be present. A feature may be “indirectly connected” or “indirectly coupled” to or “indirectly connected to” or “indirectly coupled to” another feature if no intervening features are present. A feature may be “indirectly connected” or “indirectly coupled” to or “indirectly connected to” or “indirectly coupled to” another feature if at least one intervening feature is present. A feature that is “located on” or “contacting” another feature may be directly located on or directly contacting another feature, or one or more intervening features may be present. A feature may be “directly located on” or “directly contacting” another feature if no intervening features are present. A feature may be “indirectly located on” or “indirectly contacting” another feature if at least one intervening feature is present. Different features may “overlap” if one feature extends over and covers a portion of another feature.

[0036] The description of various embodiments of the present invention has been given for the purpose of illustration, but is not intended to be exhaustive or limited to the disclosed embodiments. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the described embodiments. The terminology used herein is chosen to best explain the principles of the various embodiments, practical applications, or technical improvements over technologies found in the marketplace, or to enable others of ordinary skill in the art to understand the embodiments disclosed herein.

Claims

1. A structure for a laterally diffused metal oxide semiconductor transistor, the structure comprising: semiconductor substrates; a drain electrode located in the semiconductor substrate; a source located in the semiconductor substrate, the source comprising a first source region having a first terminal, a second terminal, and a length between the first terminal and the second terminal; A first shallow trench isolation region is located in the semiconductor substrate, and the first shallow trench isolation region surrounds the drain; as well as a gate surrounding the first shallow trench isolation region and the drain, the gate having a first side portion located between the drain and the first source region, the first side portion of the gate having a width, and the gate having a length in a direction transverse to the width, Wherein, the length of the first source region is substantially equal to the length of the gate.

2. The structure according to claim 1, wherein The source includes a second source region located in the semiconductor substrate, and the second source region has a first terminal, a second terminal, and a length located between the first terminal and the second terminal.

3. The structure according to claim 2, wherein: The gate is laterally disposed between the first source region and the second source region.

4. The structure according to claim 2, wherein The length of the second source region is substantially equal to the length of the gate.

5. The structure according to claim 2, wherein The length of the second source region is substantially equal to the length of the first source region.

6. The structure according to claim 2, wherein The drain is laterally disposed between the first source region and the second source region.

7. The structure according to claim 2, wherein: The gate has a second side portion located between the drain and the second source region, and the second side portion of the gate has the width.

8. The structure according to claim 2, wherein The drain is laterally disposed between the first source region and the second source region.

9. The structure according to claim 8, wherein The drain has a length, the length of the drain is less than the length of the first source region, and the length of the drain is less than the length of the second source region.

10. The structure according to claim 1, wherein The length of the gate is greater than the width of the first side portion of the gate.

11. The structure according to claim 1, wherein The first source region has a first linear outer boundary, the drain has a second linear outer boundary, and the drain has a length that is less than the length of the first source region.

12. The structure according to claim 1, further comprising: A second shallow trench isolation region is located in the semiconductor substrate, the second shallow trench isolation region surrounds the first shallow trench isolation region, the gate and the drain, and extends to a deeper depth than the first shallow trench isolation region.

13. The structure according to claim 12, further comprising: a well located in the semiconductor substrate, the well surrounding the drain, the gate and the first shallow trench isolation region, Wherein, the well overlaps with the second shallow trench isolation region.

14. The structure of claim 1, further comprising: a body well located in the semiconductor substrate, the body well surrounding the drain, the gate and the first shallow trench isolation region, Wherein, the first source region is arranged in the body well.

15. The structure of claim 14, further comprising: a doped region located in the body well, the doped region surrounding the drain, the gate and the first shallow trench isolation region, The doped region and the body well have the same conductivity type, and the doped region has a higher dopant concentration than the body well.

16. The structure according to claim 15, wherein The first source region is disposed in the body well and adjacent to the doped region, and the first source region has a conductivity type opposite to that of the doped region.

17. The structure of claim 1, wherein: The gate overlaps with a portion of the first shallow trench isolation region.

18. The structure of claim 1, wherein: The gate has a first end portion and a second end portion, and the drain is disposed longitudinally between the first end portion and the second end portion.

19. The structure of claim 1, further comprising: A gate dielectric layer is located under the gate, wherein the gate dielectric layer has a thicker portion adjacent to the drain, and the thicker portion overlaps the first shallow trench isolation region.

20. A method of forming a structure for a laterally diffused metal oxide semiconductor transistor, the method comprising: forming a source and a drain in a semiconductor substrate, wherein the source includes a source region having a first terminal, a second terminal, and a length between the first terminal and the second terminal; forming a shallow trench isolation region in the semiconductor substrate, wherein the shallow trench isolation region surrounds the drain; and forming a gate surrounding the shallow trench isolation region and the drain, wherein the gate has a side portion located between the drain and the source region, the side portion of the gate has a width, and the gate has a length in a direction transverse to the width, Wherein, the length of the source region is substantially equal to the length of the gate.

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