Low-temperature annealing ferroelectric capacitor device and preparation method thereof

Abstract

The invention relates to the technical field of microelectronics, in particular to a low-temperature annealing ferroelectric capacitor device and a preparation method thereof. The low-temperature annealing ferroelectric capacitor device comprises a lower electrode, a lower interface modification layer, a ferroelectric dielectric layer, an upper interface modification layer and an upper electrode which are sequentially deposited on a substrate layer. By growing the interface modification layer on the interface between the ferroelectric dielectric layer and the upper and lower electrodes, the annealing temperature required in the post-annealing stage in the preparation process of the ferroelectric capacitor can be effectively reduced, and the ferroelectric capacitor still has relatively high remanent polarization after annealing, so that the process cost required for large-scale preparation of the ferroelectric capacitor is reduced, and the production efficiency is improved. And the application scene of the ferroelectric memory device is expanded.

Description

Technical Field

[0001] The present invention relates to the field of microelectronic technology, in particular to a low-temperature annealing ferroelectric capacitor device and a preparation method thereof. Background Art

[0002] New ferroelectric materials based on HZO are potential contenders for next-generation memory devices due to their high speed, low power consumption, and compatibility with CMOS processes. Since the first report of ferroelectricity in Si-doped HfO2 thin films in 2011, research on exploring thin film ferroelectricity by varying doping and other fabrication processes has never ceased.

[0003] It is generally believed that the ferroelectricity exhibited by HfO2 films after doping is due to the transformation from the tetragonal phase to the non-centrosymmetric orthorhombic O phase, resulting in polarization. In this process, in order to overcome the kinetic barriers during the phase transition, a metal post-annealing process is generally required. Due to the different thermal expansion coefficients of the upper and lower electrodes and the dielectric layer, the tensile stress generated by the thermal expansion of the upper and lower electrode materials during the annealing process can promote the formation of O phase grains. The annealing temperature for traditional doped HfO2 materials needs to reach 400-1000℃.

[0004] Currently, by doping HfO2 with ZrO2 (HZO material), the annealing process temperature can be limited to 400-650°C. However, this temperature condition is unbearable for certain flexible substrates, such as polymer plastics. To reduce the annealing temperature during the process, related studies have tried inserting TiO2 films and using different upper and lower electrodes to reduce the annealing temperature, but the results have not been very ideal.

[0005] In view of this, the present invention is proposed. Summary of the Invention

[0006] The object of the present invention is to provide a low-temperature annealing ferroelectric capacitor device and a preparation method thereof, which can effectively reduce the annealing temperature required in the post-annealing stage during the device preparation process, and still have a large residual polarization intensity after annealing.

[0007] A first aspect of the present invention provides a low-temperature annealed ferroelectric capacitor device comprising: a lower electrode, a lower interface modification layer, a ferroelectric dielectric layer, an upper interface modification layer and an upper electrode sequentially deposited on a substrate layer.

[0008] Preferably, the ferroelectric dielectric layer is made of HZO, and has a thickness of 5-15 nm, for example, 5 nm, 10 nm, 15 nm, etc.

[0009] Preferably, the molar composition ratio of Hf and Zr in the ferroelectric dielectric layer is close to or equal to 1:1.

[0010] Preferably, the lower interface modification layer (Hf / Zr) and the upper interface modification layer (Hf / Zr) both comprise: multiple layers of Hf atoms and Zr atoms grown alternately and cyclically.

[0011] Preferably, the lower interface modification layer and the upper interface modification layer both comprise: 1-9 layers of Hf atoms and Zr atoms grown alternately and cyclically; more preferably 1 layer, 5 layers or 9 layers of Hf atoms and Zr atoms grown alternately.

[0012] In a specific embodiment, the lower interface modification layer and the upper interface modification layer both include: 9 layers of Hf atoms and 9 layers of Zr atoms.

[0013] Preferably, the substrate layer material is SiO2 / Si, wherein the thickness of the SiO2 layer is 100-500 nm, and the thickness of the Si layer is 300-600 μm.

[0014] Preferably, the lower electrode and the upper electrode are both made of TiN, with a thickness of 20-60 nm, preferably 30-40 nm, for example, 30 nm, 35 nm, 40 nm, etc.

[0015] A second aspect of the present invention provides a method for preparing a low-temperature annealed ferroelectric capacitor device, comprising the following steps:

[0016] S1. providing and cleaning a substrate layer;

[0017] S2. preparing a lower electrode on the substrate layer;

[0018] S3, preparing a lower interface modification layer on the lower electrode;

[0019] S4, preparing a ferroelectric dielectric layer on the lower interface modification layer;

[0020] S5, preparing an upper interface modification layer on the ferroelectric dielectric layer;

[0021] S6, applying photoresist on the upper interface modification layer, and performing exposure and development processing;

[0022] S7, preparing an upper electrode on the treated upper interface modification layer;

[0023] S8. Remove the photoresist and excess metal and perform post-annealing treatment.

[0024] Preferably, step S1 includes the following steps: soaking the substrate layer in acetone and anhydrous ethanol in sequence, cleaning, and drying, and then soaking, rinsing, and drying with deionized water.

[0025] Preferably, the substrate layer material is SiO2 / Si, wherein the thickness of the SiO2 layer is 100-500 nm, and the thickness of the Si layer is 300-600 μm.

[0026] Preferably, steps S3 and S5 both include the following steps: in an inert gas atmosphere, using an atomic layer deposition process to alternately grow Hf atoms and Zr atoms in a cycle, and generating multiple layers of alternately grown Hf atoms and Zr atoms after multiple cycles.

[0027] Preferably, the lower interface modification layer and the upper interface modification layer both comprise: multiple layers of Hf atoms and Zr atoms grown alternately and cyclically.

[0028] Preferably, the lower interface modification layer and the upper interface modification layer both comprise: 1-9 layers of Hf atoms and Zr atoms grown alternately and cyclically; more preferably 1 layer, 5 layers or 9 layers of Hf atoms and Zr atoms grown alternately.

[0029] In a specific embodiment, the lower interface modification layer and the upper interface modification layer both include: 9 layers of Hf atoms and 9 layers of Zr atoms.

[0030] Preferably, the inert gas is nitrogen (N2).

[0031] Preferably, step S4 includes the following steps: using an atomic layer deposition process to alternately cycle growing HfO2 and ZrO2, and generating a ferroelectric dielectric layer after multiple cycles.

[0032] Preferably, in step S4, tetrakis(ethylmethylamido)hafnium(IV) (Tetrakis(ethylmethylamido)hafnium(IV, TEMAH), chemical formula Hf(NCH3C2H5)4 is used as a precursor of Hf; tetrakis(ethylmethylamido)zirconium(IV) (Tetrakis(ethylmethylamido)zirconium(IV, TEMAZ), chemical formula Zr(NCH3CH5)4 is used as a precursor of Zr, and O3 is used as an oxygen source.

[0033] Preferably, in step S4, the deposition temperature of the ferroelectric dielectric layer is 250-300° C., the precursors of Hf and Zr are heated to 100-140° C., O3 is kept at room temperature, the carrier gas atmosphere is selected as N2, and the gas flow rate is 40-80 sccm.

[0034] Preferably, the ferroelectric dielectric layer is made of HZO, and has a thickness of 5-15 nm, for example, 5 nm, 10 nm, 15 nm, etc.

[0035] Preferably, the molar composition ratio of Hf and Zr in the ferroelectric dielectric layer is close to or equal to 1:1.

[0036] Preferably, in step S8, the annealing temperature is 300° C., the annealing time is 30 s, and the annealing atmosphere is N 2 .

[0037] Preferably, step S6 includes the following steps: coating a negative photoresist on the upper interface modification layer, pre-baking at 150°C for 1 minute, post-baking at 120°C for 1 minute after exposure, soaking in a developer for 30 seconds for development, rinsing with deionized water, and drying. Of course, a positive photoresist may also be used, in which case the hardening and exposure procedures will need to be adjusted accordingly.

[0038] Preferably, in steps S2 and S7, the preparation processes include but are not limited to: any one of the sputtering processes (ion beam sputtering, DC sputtering, reactive sputtering, etc.), atomic layer deposition (ALD), and electron beam evaporation processes. The applicable premise is an appropriate Ti / N ratio to ensure the conductivity of the electrode and the integrity of the electrode / dielectric interface, as well as the flatness of the electrode film (especially the lower electrode).

[0039] In a specific embodiment, an ion beam sputtering process is used to prepare the upper and lower electrodes, and the process parameters include: TiN target, beam voltage 700-900V, beam current 40-60mA, acceleration voltage 150-170V, gas is Ar / N2 mixed gas, and the flow rate is (7-9sccm) / (4-6sccm) respectively. Within this process range, a good film contrast can be obtained, which is conducive to the generation of ferroelectricity.

[0040] Preferably, the lower electrode and the upper electrode are both made of TiN, with a thickness of 20-60 nm, preferably 30-40 nm, for example, 30 nm, 35 nm, 40 nm, etc.

[0041] The present invention has the following beneficial effects:

[0042] (1) Before the present invention utilizes the atomic layer deposition process to grow a complete HZO thin film, separate Hf source and Zr source atoms are first alternately introduced to grow several layers of Hf / Zr alternatingly stacked single atomic layers on the lower electrode. Simultaneously, after the ferroelectric dielectric layer is grown, several layers of Hf / Zr alternatingly stacked single atomic layers are grown again, and then the upper electrode is grown. The addition of these two interface modification layers can achieve ferroelectricity in the HZO-based ferroelectric material under annealing conditions at 300°C, and the ferroelectric capacitor has a large residual polarization strength after annealing.

[0043] (2) By further reducing the annealing temperature of the HZO ferroelectric capacitor, the present invention can, on the one hand, expand the application of ferroelectric memory devices, especially for certain system materials that cannot withstand high temperatures; on the other hand, it can reduce the process difficulty in the preparation process and reduce the process cost required for large-scale preparation. BRIEF DESCRIPTION OF THE DRAWINGS

[0044] In order to more clearly illustrate the specific embodiments of the present invention or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the specific embodiments or the description of the prior art. Obviously, the drawings described below are some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0045] Figure 1 A schematic structural diagram of a low-temperature annealed ferroelectric capacitor device provided in Example 1 of the present invention;

[0046] Figure 2 A schematic structural diagram of a ferroelectric capacitor device provided in Comparative Example 1 of the present invention;

[0047] Figure 3 This is a comparison of the annealing results at 300° C. for the devices prepared in Example 1 of the present invention and Comparative Example 1;

[0048] Figure 4 A comparison diagram of the PV hysteresis loops of the devices prepared in Examples 1-3 of the present invention;

[0049] Figure 5 This is a comparison diagram of the CV butterfly curves of the devices prepared in Examples 1-3 of the present invention.

[0050] Explanation of the accompanying symbols: 1. substrate layer; 2. lower electrode; 3. lower interface modification layer; 4. ferroelectric dielectric layer; 5. upper interface modification layer; 6. upper electrode. DETAILED DESCRIPTION

[0051] It should be noted that the following detailed descriptions are illustrative and intended to provide further explanation of the present application. Unless otherwise specified, all technical and scientific terms used herein have the same meaning as commonly understood by those skilled in the art to which the present application belongs.

[0052] It should be noted that the terms used herein are only for describing specific embodiments and are not intended to limit the exemplary embodiments according to the present application. As used herein, unless the context clearly indicates otherwise, the singular also includes the plural. In addition, it should be understood that when the terms "comprise" and / or "include" are used in this specification, they indicate the presence of features, steps, operations, devices, components and / or combinations thereof.

[0053] The following will clearly and completely describe the technical solutions of the present invention in conjunction with the embodiments. Obviously, the embodiments described are only some embodiments of the present invention, not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of the present invention.

[0054] Example 1

[0055] like Figure 1 As shown, this embodiment provides a low-temperature annealed ferroelectric capacitor device, comprising: a lower electrode 2, a lower interface modification layer 3, a ferroelectric dielectric layer 4, an upper interface modification layer 5 and an upper electrode 6 sequentially deposited on a substrate layer 1.

[0056] In this embodiment, both the lower interface modification layer 3 and the upper interface modification layer 5 include: 9 layers of Hf atoms and Zr atoms grown in an alternating cycle, that is, 9 layers of Hf atoms and 9 layers of Zr atoms.

[0057] In this embodiment, the ferroelectric dielectric layer is made of HZO, has a thickness of 10 nm, and a molar composition ratio of Hf to Zr is close to or equal to 1:1.

[0058] In this embodiment, the substrate layer 1 is made of SiO 2 / Si and has a thickness of 300 nm / 450 μm.

[0059] In this embodiment, the lower electrode 2 and the upper electrode 6 are both made of TiN, with a thickness of 40 nm.

[0060] This embodiment also provides a method for preparing a low-temperature annealed ferroelectric capacitor device, comprising the following steps:

[0061] S1, soaking the substrate layer 1 in acetone and anhydrous ethanol, cleaning, and drying it, and then soaking, rinsing, and drying it in deionized water;

[0062] S2. A lower electrode 2 is formed on the substrate layer 1 by an ion beam sputtering process. The process parameters include: TiN target, beam voltage 700-900 V, beam current 40-60 mA, acceleration voltage 150-170 V, and Ar / N2 mixed gas with flow rates of (7-9 sccm) / (4-6 sccm) respectively;

[0063] S3. In an N2 atmosphere, an atomic layer deposition process is used to grow a layer of Zr atoms on the lower electrode 2, followed by a layer of Hf atoms. Two atomic layers constitute one cycle. During the cycle, no O-based gas is introduced to avoid the formation of ZrO2 and HfO2. After multiple cycles, nine layers of alternating Hf atoms and Zr atoms are generated, i.e., the lower interface modification layer 3.

[0064] S4, using an atomic layer deposition process, growing a layer of ZrO2 on the lower interface modification layer 3, then growing a layer of HfO2, and so on, and finally capping with a layer of ZrO2 to obtain a ferroelectric dielectric layer 4;

[0065] Among them, Hf(NCH3C2H5)4 is used as the precursor of Hf, Zr(NCH3CH5)4 is used as the precursor of Zr, and O3 is used as the oxygen source;

[0066] S5. In an N2 atmosphere, an atomic layer deposition process is used to grow a layer of Zr atoms on the ferroelectric dielectric layer 4, followed by a layer of Hf atoms. Two atomic layers constitute one cycle. During the cycle, no O-based gas is introduced to avoid the formation of ZrO2 and HfO2. After multiple cycles, nine layers of alternating Hf atoms and Zr atoms are generated, i.e., the upper interface modification layer 5.

[0067] S6. Coat a negative resist on the upper interface modification layer 5, pre-bake at 150°C for 1 minute, post-bake at 120°C for 1 minute after exposure, soak in a developer for 30 seconds for development, rinse with deionized water, and blow dry.

[0068] S7. An upper electrode 6 is prepared on the treated upper interface modification layer 5 by an ion beam sputtering process, wherein the process parameters include: TiN target, beam voltage 700-900 V, beam current 40-60 mA, acceleration voltage 150-170 V, gas is Ar / N2 mixed gas, and flow rates are (7-9 sccm) / (4-6 sccm) respectively;

[0069] S8, removing the photoresist and the excess metal of the upper electrode 6, and performing post-annealing treatment, with the annealing temperature being 300° C., the annealing time being 30 s, and the annealing atmosphere being N2.

[0070] Example 2

[0071] This embodiment is basically the same as the embodiment 1, except that both the lower interface modification layer 3 and the upper interface modification layer 5 include a layer of alternately grown Hf atoms and Zr atoms.

[0072] Example 3

[0073] This embodiment is basically the same as the embodiment 1, except that both the lower interface modification layer 3 and the upper interface modification layer 5 include five layers of alternately grown Hf atoms and Zr atoms.

[0074] Comparative Example 1

[0075] like Figure 2 As shown, this comparative example provides a ferroelectric capacitor device, comprising: a lower electrode 2, a ferroelectric dielectric layer 4 and an upper electrode 6 sequentially deposited on a substrate layer 1.

[0076] In this embodiment, the ferroelectric dielectric layer is made of HZO, has a thickness of 10 nm, and a molar composition ratio of Hf to Zr is close to or equal to 1:1.

[0077] In this comparative example, the material of the substrate layer 1 is SiO2 / Si, and the thickness is 300nm / 450μm.

[0078] In this comparative example, the lower electrode 2 and the upper electrode 6 are both made of TiN, with a thickness of 40 nm.

[0079] This comparative example also provides a method for preparing a ferroelectric capacitor device, comprising the following steps:

[0080] S1, soaking the substrate layer 1 in acetone and anhydrous ethanol, cleaning, and drying it, and then soaking, rinsing, and drying it in deionized water;

[0081] S2. A lower electrode 2 is formed on the substrate layer 1 by an ion beam sputtering process. The process parameters include: TiN target, beam voltage 700-900 V, beam current 40-60 mA, acceleration voltage 150-170 V, and Ar / N2 mixed gas with flow rates of (7-9 sccm) / (4-6 sccm) respectively;

[0082] S3, using an atomic layer deposition process, growing a layer of ZrO2 on the lower electrode 2, then growing a layer of HfO2, and so on, and finally capping it with a layer of ZrO2 to obtain a ferroelectric dielectric layer 4;

[0083] Among them, Hf(NCH3C2H5)4 is used as the precursor of Hf, Zr(NCH3CH5)4 is used as the precursor of Zr, and O3 is used as the oxygen source;

[0084] S4, coating a negative resist on the ferroelectric dielectric layer 4, pre-baking at 150° C. for 1 minute, post-baking at 120° C. for 1 minute after exposure, soaking in a developer for 30 seconds for development, rinsing with deionized water, and drying;

[0085] S5. An ion beam sputtering process is used to prepare an upper electrode 6 on the treated ferroelectric dielectric layer 4. The process parameters include: TiN target, beam voltage 700-900 V, beam current 40-60 mA, acceleration voltage 150-170 V, and Ar / N2 mixed gas with flow rates of (7-9 sccm) / (4-6 sccm) respectively.

[0086] S6, removing the photoresist and the excess metal of the upper electrode 6, and performing post-annealing treatment, with the annealing temperature being 300°C, the annealing time being 30s, and the annealing atmosphere being N2.

[0087] Test Example 1

[0088] Comparison of PV test results of hafnium-based ferroelectric capacitor devices prepared in Example 1 (with interface modification layer) and Comparative Example 1 (without interface modification layer) after annealing at 300°C Figure 3 As shown in the figure, it can be seen that for Example 1 using an interface modification layer with 9 Hf-Zr cycles, when the applied voltage is reset to 0V, the thermal conductivity is greater than 10μC / cm 2 In contrast, no obvious remnant polarization value was measured for comparative example 1 without interface treatment.

[0089] Test Example 2

[0090] The PV hysteresis loops of the hafnium-based ferroelectric capacitors prepared in Examples 1-3 are compared as follows: Figure 4 As can be seen from the figure: the ferroelectric properties of the hafnium-based ferroelectric capacitor device after interface treatment will change with the change of interface treatment conditions and show a certain trend, which further proves that the capacitor device after interface treatment has obtained better performance.

[0091] Test Example 3

[0092] The CV butterfly curves of the hafnium-based ferroelectric capacitors prepared in Examples 1-3 are compared. Figure 5 , it can be seen from the figure: Figure 4 The results confirm each other and the capacitor devices can obtain better performance after interface treatment.

[0093] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the above embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the above embodiments, or replace some or all of the technical features therein with equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A low-temperature annealed ferroelectric capacitor device, characterized in that: include: A lower electrode (2), a lower interface modification layer (3), a ferroelectric dielectric layer (4), an upper interface modification layer (5) and an upper electrode (6) are sequentially deposited on the substrate layer (1).

2. The low temperature annealing ferroelectric capacitor device according to claim 1, characterized in that: The material of the ferroelectric dielectric layer (4) is HZO.

3. The low temperature annealing ferroelectric capacitor device according to claim 1, characterized in that: The lower interface modification layer (3) and the upper interface modification layer (5) both comprise multiple layers of Hf atoms and Zr atoms that are alternately and cyclically grown.

4. The low temperature annealing ferroelectric capacitor device according to claim 1, characterized in that: The substrate layer (1) is made of SiO2 / Si, and the lower electrode (2) and upper electrode (6) are both made of TiN.

5. The method for preparing a low-temperature annealed ferroelectric capacitor device according to any one of claims 1 to 4, characterized in that: The following steps are involved: S1. providing and cleaning a substrate layer (1); S2, preparing a lower electrode (2) on the substrate layer (1); S3, preparing a lower interface modification layer (3) on the lower electrode (2); S4, preparing a ferroelectric dielectric layer (4) on the lower interface modification layer (3); S5, preparing an upper interface modification layer (5) on the ferroelectric dielectric layer (4); S6, applying photoresist, exposing and developing the upper interface modification layer (5); S7, preparing an upper electrode (6) on the treated upper interface modification layer (5); S8. Remove the photoresist and excess metal and perform post-annealing treatment.

6. The method for preparing a low-temperature annealed ferroelectric capacitor device according to claim 5, wherein: Steps S3 and S5 both include the following steps: In an inert gas atmosphere, an atomic layer deposition process is used to alternately grow Hf atoms and Zr atoms in a cycle. After multiple cycles, multiple layers of alternately grown Hf atoms and Zr atoms are generated.

7. The method for preparing a low-temperature annealed ferroelectric capacitor device according to claim 5, wherein: Step S4 includes the following steps: using an atomic layer deposition process to alternately cycle the growth of HfO2 and ZrO2, and generating a ferroelectric dielectric layer (4) after multiple cycles.

8. The method for preparing a low-temperature annealed ferroelectric capacitor device according to claim 7, wherein: In step S4, Hf(NCH3C2H5)4 is used as a precursor of Hf, Zr(NCH3CH5)4 is used as a precursor of Zr, and O3 is used as an oxygen source.

9. The method for preparing a low-temperature annealed ferroelectric capacitor device according to claim 5, wherein: In step S8, the annealing temperature is 300°C.

10. The method for preparing a low-temperature annealed ferroelectric capacitor device according to claim 5, characterized in that: In steps S2 and S7 , the preparation process includes: any one of a sputtering process, an atomic layer deposition process, and an electron beam evaporation process.

Images