A high-reliability power supply chip circuit fault detection system

Abstract

The application relates to the chip detection technical field and discloses a high-reliability power supply chip circuit fault detection system which comprises a built-in self-test architecture integrated in a low-dropout linear voltage regulator chip. The built-in self-test architecture is provided with a first test mode and a second test mode which are switched based on a mode switching control circuit to detect the key performance parameters of an error amplifier subcircuit in the low-dropout linear voltage regulator chip. The first test mode is used for measuring the direct current loop gain, the offset voltage, the common mode rejection ratio and the power supply ripple rejection ratio of the error amplifier. The second test mode is used for measuring the unit gain bandwidth of the error amplifier. According to the built-in self-test architecture and the two test modes, the application can identify abnormal states such as differential circuit imbalance and feedback loop failure in the bare chip stage, and can remove the chips with poor performance in advance, so that the LDO chip can reach the high-reliability standard of ppb.

Description

Technical Field

[0001] This application relates to the field of chip testing technology, specifically a high-reliability power chip circuit fault detection system. Background Technology

[0002] In recent years, with the rapid development of new energy vehicles and intelligent connected vehicles, vehicle functions have become increasingly diversified, and the number of chips in a single vehicle has steadily increased, highlighting the growing importance of automotive chips. In-vehicle systems such as autonomous driving, body control, and navigation are typically driven by PMICs (Power Management Integrated Circuits) such as DC-DC Buck circuits and LDO chips (Low Drop-Out regulators). Their reliability is crucial for safe driving and normal operation of the vehicle. Therefore, the automotive industry has extremely high reliability requirements for power management chips, represented by LDOs, typically requiring a failure rate in the ppb (parts per billion) range.

[0003] Parameter testing of LDO chips is a necessary means to verify their functionality and performance, and to detect faults or abnormal states. For example... Figure 4 As shown, the basic structure of an LDO chip includes a reference circuit, an EA (Error Amplifier), a power transistor, auxiliary circuits, and a feedback resistor network. The failure rate of the EA is closely related to the reliability of the LDO device. Imbalance in the differential circuit performance and the feedback loop of the power IC can lead to failure—comparators and operational amplifiers, as key components in many feedback loops, provide high performance and high power supply noise immunity, but imbalance in the differential circuit can cause performance degradation, leading to failure of the entire feedback loop, which is one of the main causes of LDO chip failure.

[0004] Current LDO functional performance parameter testing primarily relies on external input / output detection, with the basic method being testing V... INPUT (Input voltage), V GND (Ground voltage) and V OUTPUT Whether parameters such as (output voltage) meet the requirements. However, to adhere to the zero-defect reliability principle of automotive-grade chips, testing the performance of the internal sub-circuits of the power management chip is crucial. The aforementioned external testing methods have significant limitations: they cannot measure the performance characteristics of internal sub-circuits such as the EA, bandgap reference, and regulating transistor. This is because the internal nodes of an LDO are typically not directly testable, and the feedback loop has high loop gain (typically 60-100dB, composed of the EA gain, the inherent gain of the transfer transistor, and the sum of the feedback network gain). Weak sub-circuit performance is compensated for by the feedback loop, making it difficult for conventional external measurements to identify functional and performance abnormalities in the internal sub-circuits.

[0005] Therefore, there is an urgent need for a new LDO chip circuit detection technology. SUMMARY

[0006] The purpose of the present application is to provide a high-reliability power chip circuit fault detection system to solve the technical problems raised in the background art, improve the detection accuracy of the failure rate of automotive-grade power management chips, identify abnormal states of LDOs at the bare chip stage, reject chips with poor performance, improve manufacturing yield, and thus ensure quality reliability.

[0007] To achieve the above-mentioned purpose, the present application discloses the following technical solutions:

[0008] A high-reliability power chip circuit fault detection system, comprising a built-in self-test architecture integrated in a low-dropout linear regulator chip; the built-in self-test architecture comprises an auxiliary operational amplifier, an attenuator, an analog multiplexer, an oscillation element, and a mode switching control circuit; the built-in self-test architecture is provided with two test modes switched based on the mode switching control circuit to detect key performance parameters of an error amplifier subcircuit in the low-dropout linear regulator chip; the low-dropout linear regulator chip comprises a reference circuit, an error amplifier, a power tube, a compensation circuit, an auxiliary circuit, a charge pump, and a feedback resistor network, and the key performance parameters include DC loop gain, offset voltage, unit gain bandwidth, common-mode rejection ratio, and power supply ripple rejection ratio; the two test modes include a first test mode and a second test mode;

[0009] In the first test mode, the built-in self-test architecture activates the auxiliary operational amplifier and the attenuator through the mode switching control circuit to form a servo loop test platform for measuring the DC loop gain, offset voltage, common-mode rejection ratio, and power supply ripple rejection ratio of the error amplifier;

[0010] In the second test mode, the built-in self-test architecture mode switching control circuit drives the selection line of the analog multiplexer to convert the LDO core in the low-dropout linear regulator chip into an oscillation loop to measure the unit gain bandwidth of the error amplifier, and the LDO core comprises: an error amplifier, a power tube, a compensation circuit, an auxiliary circuit, a charge pump, and a feedback resistor network.

[0011] As a preferred, in the first test mode, the auxiliary operational amplifier is connected between the input end of the error amplifier and the control end of the power tube in the first test mode with a feedback servo loop, for forcibly generating a zero point at the input end of the error amplifier and stabilizing the DC operating point of the power tube and the error amplifier; the attenuator is connected to the inverting terminal of the auxiliary operational amplifier, and the output voltage of the low-dropout linear regulator is adjusted according to the DC reference voltage set value through negative feedback, so that the output voltage is equal to the DC reference voltage set value.

[0012] As a preference, in the first test mode, when reaching a balance state that the negative feedback makes the output voltage of the low dropout linear regulator equal to the DC reference voltage setting value and each node and current in the circuit do not change with time, the signal fed back to the input of the error amplifier is directly related to the output of the auxiliary operational amplifier, and the open loop DC gain of the error amplifier is determined by the ratio between the output of the auxiliary operational amplifier and the signal measured at the input of the error amplifier.

[0013] As a preference, the attenuator comprises a first resistor R1 and a second resistor R2, and the resistance of the second resistor R2 satisfies that the resistance of the second resistor R2 is approximately equal to the product between the open loop DC gain of the error amplifier and the resistance of the first resistor R1.

[0014] As a preference, the offset voltage test of the first test mode comprises the following steps:

[0015] Setting the voltage and the DC reference voltage setting value to an intermediate value between the power supply voltage and the ground voltage, and calculating the DC offset voltage based on the output of the device under test.

[0016] As a preference, the common mode rejection ratio test of the first test mode comprises the following steps:

[0017] Setting the same voltage signal applied to the non-inverting input and the inverting input of the error amplifier to a first common mode level and measuring the output of the auxiliary operational amplifier, and then setting the same voltage signal applied to the non-inverting input and the inverting input of the error amplifier to a second common mode level and measuring the output of the auxiliary operational amplifier again, calculating the common mode level change between the first common mode level and the second common mode level and the output change between the two outputs of the auxiliary operational amplifier, calculating the ratio between the common mode level change and the output change, and then calculating the product of the ratio and the attenuation ratio of the attenuator to obtain the common mode rejection ratio.

[0018] As a preference, the power supply ripple rejection ratio test of the first test mode comprises the following steps:

[0019] Setting the power supply voltage to a first power supply level and measuring the output of the auxiliary operational amplifier, and then setting the power supply voltage to a second power supply level and measuring the output of the auxiliary operational amplifier again, calculating the change between the first power supply level and the second power supply level as the power supply level change and the change between the two outputs of the auxiliary operational amplifier as the output change, calculating the ratio between the power supply level change and the output change, and then calculating the product of the ratio and the attenuation ratio of the attenuator to obtain the power supply ripple rejection ratio.

[0020] As preferred, the analog multiplexer is configured to: make the error amplifier, the power tube, the compensation circuit, the auxiliary circuit, the charge pump and the feedback resistance network form a closed oscillation loop after switching the connection in the second test mode, and the oscillation frequency of the oscillation loop is determined by the oscillation element and the unity gain bandwidth; in the second test mode, the LDO core is modeled as a single-pole system, and the frequency response characteristic is: at low frequency, the DC open-loop gain is stable, and as the frequency increases, the DC open-loop gain decreases due to the influence of the system main pole angular frequency.

[0021] As preferred, the unity gain bandwidth is the ratio of the product of the DC open-loop gain and the main pole angular frequency of the LDO core and 2p.

[0022] As preferred, the built-in self-test architecture is configured to: identify the abnormal state of the low-dropout linear voltage regulator in the bare die stage by designing the test nodes accessible in the low-dropout linear voltage regulator chip and the two test modes.

[0023] Beneficial effects: the high-reliability power chip circuit fault detection system of the application can directly measure the key performance parameters of the error amplifier through the built-in self-test architecture integrated in the LDO chip without external test vectors, and provides a direct basis for identifying core failure reasons such as differential circuit imbalance; secondly, through the design of two test modes, the servo loop test platform of the first test mode can stabilize the LDO DC operating point, measure the DC parameters of the error amplifier with high precision, and effectively capture subtle abnormalities caused by insufficient performance of the factor circuit; the oscillation loop design of the second test mode does not require additional test sources, and indirectly obtains the unity gain bandwidth through the oscillation frequency, which can evaluate the high-frequency performance and transient response of the error amplifier, and comprehensively cover the key characteristic detection of internal sub-circuits; and through the built-in self-test architecture and the two test modes, the abnormal state such as differential circuit imbalance and feedback loop failure can be identified in the bare die stage, and the chips with poor performance can be removed in advance to improve the manufacturing yield, and finally ensure that the LDO chip reaches the high-reliability standard of ppb level, and provides core support for the safe and stable operation of the vehicle power management system. BRIEF DESCRIPTION OF DRAWINGS

[0024] In order to more clearly illustrate the technical solutions in the embodiments of the application or the prior art, the following will briefly introduce the drawings needed to be used in the embodiment or prior art description. Obviously, the drawings in the following description are only some embodiments of the application, and other drawings can also be obtained by those skilled in the art without creative labor.

[0025] Figure 1 The structure schematic diagram of the high-reliability power chip circuit fault detection system provided by the embodiments of the application;

[0026] Figure 2 A first test mode servo loop test platform architecture schematic diagram provided for the embodiments of the present application;

[0027] Figure 3 A second test mode corresponding system simplified schematic diagram provided for the embodiments of the present application;

[0028] Figure 4 A LDO basic structure schematic diagram. DETAILED DESCRIPTION

[0029] The technical solutions in the embodiments of the present application will be described clearly and completely below. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative work fall within the scope of protection of the present application.

[0030] In this document, the term "comprising" is intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or further includes elements inherent to such a process, method, article or device. Without more limitations, the elements defined by the statement "comprising" do not exclude the presence of other identical elements in the process, method, article or device including the elements.

[0031] The embodiments disclose a high-reliability power supply chip circuit fault detection system as shown in Figure 1 The built-in self-test architecture includes an auxiliary operational amplifier (used as an integrator of the circuit), an attenuator, an analog multiplexer (MUX), an oscillation element (Rosc, Cosc), and a mode switching control circuit.

[0032] The built-in self-test architecture is provided with two test modes switched based on the mode switching control circuit, to detect key performance parameters of an error amplifier sub-circuit in a low-dropout linear voltage regulator (hereinafter referred to as LDO) chip. The LDO chip includes a reference circuit, an error amplifier (EA), a power tube, a compensation circuit, an auxiliary circuit, a charge pump, and a feedback resistor network, and the key performance parameters include a direct current loop gain (T), an offset voltage (VOS), a unit gain bandwidth (UGBW), a common-mode rejection ratio (PSRR), and a power supply ripple rejection ratio (PSRR).

[0033] The two test modes include a first test mode and a second test mode;

[0034] In the first test mode, the built-in self-test architecture activates an auxiliary operational amplifier and an attenuator through a mode switching control circuit to form a servo loop test platform for measuring the DC loop gain, offset voltage, common mode rejection ratio and power supply ripple rejection ratio of the error amplifier.

[0035] In the second test mode, the built-in self-test architecture mode switching control circuit drives the selection line of the analog multiplexer to convert the LDO core in the low dropout linear regulator chip into an oscillation loop to measure the unit gain bandwidth of the error amplifier, and the LDO core includes: an error amplifier, a power tube, a compensation circuit, an auxiliary circuit, a charge pump and a feedback resistance network.

[0036] As Figure 2 shown in the servo loop test platform architecture of the first test mode, in the first test mode, the auxiliary operational amplifier is connected between the input end of the error amplifier and the control end of the power tube in the feedback servo loop in the first test mode, for forcing to produce zero point at the input end of the error amplifier, and stabilizing the DC operating point of the power tube and the error amplifier; the attenuator is connected to the inverting end of the auxiliary operational amplifier, and the output voltage of the low dropout linear regulator is adjusted according to the DC reference voltage set value through negative feedback, so that the output voltage is equal to the DC reference voltage set value.

[0037] As Figure 2 shown, the DC gain of the to-be-tested operational amplifier (DUT is the measured device, i.e. LDO chip) is followed by an auxiliary operational amplifier Nulling Amplifier, and the attenuator used is as Figure 1 shown, which is composed of a first resistor R1 and a second resistor R2, and the attenuation ratio is (R1+R2) / R1.

[0038] In this embodiment, in the first test mode, when the balance state that the negative feedback makes the output voltage of the low dropout linear regulator equal to the DC reference voltage set value (V V SRC ) and each node and current in the circuit does not change with time is reached, the signal fed back to the input end of the error amplifier is directly related to the output of the auxiliary operational amplifier, and the open loop DC gain of the error amplifier is determined by the ratio between the output of the auxiliary operational amplifier and the signal measured at the input end of the error amplifier.

[0039] In detail, in the Figure 2 circuit shown, the negative feedback ensures that the output voltage of the LDO is forced to be adjusted to the required value according to the DC voltage set by V SRC , so that the output voltage of the LDO V LDO-out =V SRCIn this equilibrium state, the signal fed back to the input of the LDO error amplifier V IN-EA ( a correction voltage equal to the error magnitude) and the output of the auxiliary amplifier V O-NULL directly related, satisfying The open loop DC gain (T) of the error amplifier (EA) can be calculated by the following formula: .

[0040] Therefore, with the help of the servo loop test platform, the two required outputs can be forced to be generated, and then the tiny input that leads to the two outputs can be indirectly measured. Therefore, the extremely high loop gain of the LDO can be measured without applying a tiny voltage. In order to avoid the saturation of the auxiliary amplifier, the resistance value of the second resistor R2 satisfies: the resistance value of the second resistor R2 is approximately equal to the product between the open loop DC gain of the error amplifier and the resistance value of the first resistor R1, that is, R2≈T* R1.

[0041] In this embodiment, the offset voltage test of the first test mode includes the following steps:

[0042] The voltage and the DC reference voltage set value are set to an intermediate value between the power supply voltage and the ground voltage, and the DC offset voltage is calculated based on the output of the device under test.

[0043] That is, based on the setting of the auxiliary operational amplifier as shown in Figure 2 , the voltage V CM and V SRC in the figure can be set to an intermediate value between the power supply voltage V IN and the ground voltage to measure the input reference offset of the device under test (DUT). An ideal operational amplifier has zero offset, so its output voltage should also be an intermediate value between the power supply and the ground, but this is not the case for an actual operational amplifier. The input reference offset of an actual operational amplifier can be between several μV and several mV. For an LDO, the offset voltage will be directly amplified by the feedback factor, thereby introducing an error in the regulated output voltage. When V O-NULL the value of the amplifier gain multiplied by the offset, the output voltage of the LDO is V IN / 2 , the DC offset voltage V OS can be calculated by the following formula:

[0044]

[0045] In this embodiment, the common mode rejection ratio test of the first test mode includes the following steps:

[0046] The same voltage signal applied to the in-phase input and the anti-phase input of the error amplifier is set to a first common mode level, and the auxiliary operational amplifier output is measured, and the same voltage signal applied to the in-phase input and the anti-phase input of the error amplifier is set to a second common mode level, and the auxiliary operational amplifier output is measured again, and the common mode level change between the first common mode level and the second common mode level is calculated ΔV REF and the output change between the two auxiliary operational amplifier outputs ΔV O-NULL , and the ratio of ΔV REF and ΔV O-NULL is multiplied by the attenuation ratio of the attenuator to obtain the common mode rejection ratio CMRR, and the specific formula is:

[0047]

[0048] In the embodiment, the power supply ripple rejection ratio test of the first test mode includes the following steps:

[0049] The power supply voltage is set to a first power supply level, and the auxiliary operational amplifier output is measured, and the power supply voltage is set to a second power supply level, and the auxiliary operational amplifier output is measured again, and the change between the first power supply level and the second power supply level is calculated as the power supply level change ΔV IN and the change between the two auxiliary operational amplifier outputs is calculated as the output change ΔV O-NULL , and the ratio of ΔV IN and ΔV O-NULL is multiplied by the attenuation ratio of the attenuator to obtain the power supply ripple rejection ratio PSRR, and the specific formula is:

[0050]

[0051] The unit gain bandwidth (UGBW) is a factor that is negatively correlated with the gain, and a high bandwidth can improve the transient response time of the LDO, and at the same time, the effective range of the low-frequency PSRR can be maintained. Therefore, in the embodiment, the analog multiplexer is configured to: after switching the connection in the second test mode, the error amplifier, the power tube, the compensation circuit, the auxiliary circuit, the charge pump and the feedback resistance network form a closed oscillation loop, and the oscillation frequency f oscdetermined by the oscillation element (Rosc, Cosc) and the unity gain bandwidth; in the second test mode, the LDO core is modeled as a single-pole system, and the frequency response characteristic is: at low frequency, it has a stable DC open-loop gain, and as the frequency increases, the DC open-loop gain decreases due to the influence of the system main pole angular frequency; finally, the unity gain bandwidth is calculated by the ratio of the product of the DC open-loop gain and the main pole angular frequency of the LDO core to 2π, that is, .

[0052] In this embodiment, the transfer function of the LDO core is represented as:

[0053]

[0054] wherein, a v Gm is the DC open-loop gain of the LDO core, s s is a complex frequency variable, used to analyze the frequency and transient characteristics of the system by Laplace transform, w T ω is the unity gain bandwidth frequency, and both satisfy: a v ≈A EA (Assuming that the second stage (the subsequent circuit of the non-error amplifier) has a unity gain), A EA Gm_ea is the DC open-loop gain of the error amplifier (EA), w T =a v* w p1 , w p1 ω_p is the main pole angular frequency of the system, and the main pole is the pole closest to the origin of the complex plane, which determines the starting frequency of the gain drop.

[0055] In this embodiment, the built-in self-test architecture is configured to identify abnormal states of the low dropout linear regulator by designing accessible test nodes (such as error amplifier input, auxiliary operational amplifier output, and other internal nodes for measuring key parameters) within the low dropout linear regulator chip, and the two test modes, to identify abnormal states of the low dropout linear regulator at the bare chip stage (chip manufacturing stage without packaging). The abnormal state is a state caused by abnormal performance of the internal sub-circuit of the LDO, specifically including: performance degradation of the differential circuit (such as the differential input stage of the error amplifier) due to imbalance (device parameter mismatch, asymmetric bias, etc.), and feedback loop failure (such as insufficient loop gain, abnormal regulation function, etc.) caused by faults of sub-circuits such as error amplifiers, power tubes, and feedback networks.

[0056] In summary, the high-reliability power chip circuit fault detection system provided in the embodiment can directly measure the key performance parameters of the error amplifier without external test vectors through the built-in self-test architecture integrated in the LDO chip, solves the pain point that the existing external test cannot touch the performance of the internal sub-circuit, and provides a direct basis for identifying core failure reasons such as differential circuit imbalance; secondly, through the design of two test modes, the servo loop test platform of the first test mode can stabilize the LDO DC operating point, measure the DC parameters of the error amplifier with high precision, and effectively capture subtle abnormalities caused by insufficient performance of the factor circuit; the oscillation loop design of the second test mode does not require additional test sources, indirectly obtains the unit gain bandwidth through the oscillation frequency, can evaluate the high-frequency performance and transient response of the error amplifier, and comprehensively covers the key characteristic detection of the internal sub-circuit; and through the built-in self-test architecture and the two test modes, the differential circuit imbalance, feedback loop failure and other abnormal states can be identified at the bare chip stage, the chips with poor performance are removed in advance, the manufacturing yield is improved, and finally the LDO chip reaches the high-reliability standard of ppb level, providing core support for the safe and stable operation of the vehicle power management system.

[0057] In the embodiments provided in the present application, it should be understood that the embodiments described herein can be realized in hardware, software, firmware, middleware, code, or any appropriate combination thereof. For hardware implementation, the processor can be realized in one or more of the following units: application specific integrated circuit (ASIC), digital signal processor (DSP), digital signal processing device (DSPD), programmable logic device (PLD), field programmable gate array (FPGA), processor, controller, microcontroller, microprocessor, other electronic units designed to implement the functions described herein, or a combination thereof. For software implementation, part or all of the processes of the embodiments can be instructed by a computer program to relevant hardware. In implementation, the above program can be stored in a computer readable storage medium or transmitted as one or more instructions or codes on a computer readable storage medium. The computer readable storage medium includes computer storage medium and communication medium, wherein the communication medium includes any medium that facilitates the transmission of a computer program from one place to another. The storage medium can be any available medium that can be accessed by a computer. The computer readable storage medium can include but is not limited to RAM, ROM, EEPROM, CD-ROM or other optical disk storage, magnetic disk storage medium or other magnetic storage device, or any other medium that can be used to carry or store desired program codes in the form of instructions or data structures and can be accessed by a computer.

[0058] Finally, it should be noted that the above only describes the preferred embodiments of the present application and is not intended to limit the present application. Although the present application has been described in detail with reference to the foregoing embodiments, modifications or equivalent replacements of the technical solutions described in the foregoing embodiments can still be made by those skilled in the art, or some technical features can be replaced by equivalent features. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principle of the present application shall be included in the protection scope of the present application.

Claims

1. A high-reliability power supply chip circuit fault detection system, characterized by, The built-in self-test architecture includes an auxiliary operational amplifier, an attenuator, an analog multiplexer, an oscillation element, and a mode switching control circuit; the built-in self-test architecture is provided with two test modes switched based on the mode switching control circuit to detect key performance parameters of an error amplifier subcircuit in the low-dropout linear voltage regulator chip; the low-dropout linear voltage regulator chip includes a reference circuit, an error amplifier, a power tube, a compensation circuit, an auxiliary circuit, a charge pump, and a feedback resistor network, and the key performance parameters include a direct current loop gain, an offset voltage, a unit gain bandwidth, a common mode rejection ratio, and a power supply ripple rejection ratio; the two test modes include a first test mode and a second test mode; In the first test mode, the built-in self-test architecture activates the auxiliary operational amplifier and the attenuator through the mode switching control circuit to form a servo loop test platform for measuring the direct current loop gain, the offset voltage, the common mode rejection ratio, and the power supply ripple rejection ratio of the error amplifier. In the second test mode, the mode switching control circuit of the built-in self-test architecture drives the selection line of the analog multiplexer to convert the LDO core in the low-dropout linear voltage regulator chip into an oscillation loop to measure the unit gain bandwidth of the error amplifier, and the LDO core includes the error amplifier, the power tube, the compensation circuit, the auxiliary circuit, the charge pump, and the feedback resistor network.

2. The high reliability power supply chip circuit fault detection system of claim 1, wherein, In the first test mode, the auxiliary operational amplifier is connected between the input end of the error amplifier and the control end of the power tube in the first test mode in a feedback servo loop, for forcing a zero point at the input end of the error amplifier and stabilizing the direct current working point of the power tube and the error amplifier; the attenuator is connected to the inverting end of the auxiliary operational amplifier, and the output voltage of the low-dropout linear voltage regulator is adjusted according to the direct current reference voltage set value through negative feedback, so that the output voltage is equal to the direct current reference voltage set value.

3. The high-reliability power supply chip circuit fault detection system of claim 2, wherein, In the first test mode, when the balance state that the output voltage of the low-dropout linear voltage regulator is equal to the direct current reference voltage set value through negative feedback and each node and current in the circuit does not change with time is reached, the signal fed back to the input end of the error amplifier is directly related to the output of the auxiliary operational amplifier, and the open-loop direct current gain of the error amplifier is determined by the ratio between the output of the auxiliary operational amplifier and the signal measured at the input end of the error amplifier.

4. The high reliability power supply chip circuit fault detection system of claim 2, wherein, The attenuator includes a first resistor R1 and a second resistor R2, and the resistance value of the second resistor R2 is approximately equal to the product between the open-loop direct current gain of the error amplifier and the resistance value of the first resistor R1.

5. The high reliability power supply chip circuit fault detection system of claim 1, wherein, The offset voltage test of the first test mode includes the following steps: The voltage and the direct current reference voltage set value are set to an intermediate value between the power supply voltage and the ground voltage, and the direct current offset voltage is calculated based on the output of the device under test.

6. The high reliability power supply chip circuit fault detection system of claim 1, wherein, The common mode rejection ratio test of the first test mode includes the following steps: The same voltage signal applied to the in-phase input and the anti-phase input of the error amplifier is set to a first common mode level, and the auxiliary operational amplifier output is measured, and then the same voltage signal applied to the in-phase input and the anti-phase input of the error amplifier is set to a second common mode level, and the auxiliary operational amplifier output is measured again, the common mode level change between the first common mode level and the second common mode level and the output change between the two auxiliary operational amplifier outputs are calculated, the ratio between the common mode level change and the output change is calculated, and then the product of the ratio and the attenuation ratio of the attenuator is calculated to obtain the common mode rejection ratio.

7. The high reliability power supply chip circuit fault detection system of claim 1, wherein, The power supply ripple rejection ratio test of the first test mode comprises the following steps: The power supply voltage is set to a first power supply level, and the auxiliary operational amplifier output is measured, and then the power supply voltage is set to a second power supply level, and the auxiliary operational amplifier output is measured again, the change between the first power supply level and the second power supply level is calculated as the power supply level change, and the change between the two auxiliary operational amplifier outputs is calculated as the output change, the ratio between the power supply level change and the output change is calculated, and then the product of the ratio and the attenuation ratio of the attenuator is calculated to obtain the power supply ripple rejection ratio.

8. The high reliability power supply chip circuit fault detection system of claim 1, wherein, The analog multiplexer is configured to: after switching the connection in the second test mode, the error amplifier, the power tube, the compensation circuit, the auxiliary circuit, the charge pump and the feedback resistance network form a closed oscillation loop, and the oscillation frequency of the oscillation loop is determined by the oscillation element and the unit gain bandwidth; in the second test mode, the LDO core is modeled as a single pole system, and the frequency response characteristic is: at low frequency, it has stable direct current open loop gain, and as the frequency increases, the direct current open loop gain decreases due to the influence of the system main pole angular frequency.

9. The high-reliability power supply chip circuit fault detection system of claim 8, wherein, The unit gain bandwidth is the ratio of the product of the direct current open loop gain and the main pole angular frequency of the LDO core and 2π.

10. The high reliability power supply chip circuit fault detection system of claim 1, wherein, The built-in self-test architecture is configured to: by designing accessible test nodes in the low dropout linear voltage regulator chip, and through the two test modes, the abnormal state of the low dropout linear voltage regulator is identified when the chip is in the bare chip stage.

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