A device monitoring method and electronic device

Abstract

The application discloses a device monitoring method and electronic equipment, and relates to the technical field of device monitoring. The method comprises the following steps: in response to the power-on of an interconnection management device, a logic controller acquires a plurality of state detection signals related to the reset process of an interconnection controller; the logic controller generates a firmware loading flag signal based on the plurality of state detection signals, so as to be read by the management controller; in response to the fact that the firmware loading flag signal read by the management controller represents valid loading, the management controller accesses the interconnection controller to perform interconnection state monitoring after a preset waiting period. The application can take into account the differences in the architecture of the interconnection controller, control the access timing of the management controller to the interconnection controller, thereby avoiding the device monitoring method of the premature access of the management controller to the interconnection controller, and solving the problem that, in the related art, the premature access of the management controller to the interconnection controller leads to abnormal firmware loading of the interconnection manager, thereby leading to link training failure.

Description

Technical Field

[0001] This application relates to the field of device monitoring technology, and in particular to a device monitoring method and electronic device. Background Technology

[0002] In existing AI servers, an interconnect management device is typically used to host high-speed interconnect links, with the interconnect controller being the core component. To ensure the stability of high-speed interconnects, the management controller is needed to monitor the interconnect controller. However, due to differences in the architecture of different interconnect controllers, the management controller cannot accurately determine the firmware loading status of the interconnect controller at the initial power-on stage, which may lead to premature access to the interconnect controller, thereby interfering with firmware loading, causing link training failure, and reducing system stability. Traditional methods generally solve this problem by using fixed delays, but this is not compatible with interconnect controllers of different architectures and has poor reliability. Summary of the Invention

[0003] This application provides a device monitoring method that can take into account the architectural differences of interconnect controllers and control the timing of access to interconnect controllers by management controllers, thereby avoiding premature access to interconnect controllers by management controllers. This method aims to at least solve the problem in related technologies where premature access by management controllers leads to abnormal loading of interconnect manager firmware, resulting in link training failure.

[0004] This application provides a device monitoring method applied to an interconnect management device, the interconnect management device including at least a logic controller, an interconnect controller, and a management controller, the method comprising:

[0005] In response to the power-on of the interconnect management device, the logic controller acquires multiple status detection signals related to the reset process of the interconnect controller;

[0006] The logic controller generates a firmware loading flag signal based on multiple status detection signals for the management controller to read;

[0007] In response to the firmware loading flag signal read by the management controller indicating that loading is valid, the management controller accesses the interconnect controller to monitor the interconnect status after a preset waiting period.

[0008] This application also provides an electronic device, including: a memory for storing a computer program; and a processor for implementing any of the above-described device monitoring methods when executing the computer program.

[0009] By acquiring multiple status detection signals related to the interconnect controller reset process in the logic controller and generating a firmware loading flag signal based on these status detection signals, the manager can delay accessing the interconnect controller, thus preventing the management controller from accessing the interconnect controller prematurely before the firmware is fully loaded. Therefore, this solves the problem in the prior art where the management controller directly accesses the interconnect controller at the initial power-on, causing firmware loading interference and link training failure. This achieves effective protection during the firmware loading of the interconnect controller, avoiding the difficult-to-diagnose faults caused by premature access from the source, and improving the success rate of high-speed interconnect link training and the stability of system operation. Attached Figure Description

[0010] To more clearly illustrate the embodiments of this application, the accompanying drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0011] Figure 1 This is a schematic diagram of a device monitoring method provided in an embodiment of this application;

[0012] Figure 2 This is a schematic diagram of a device monitoring step provided in an embodiment of this application;

[0013] Figure 3 A schematic diagram of a trigger and an AND gate circuit structure provided in an embodiment of this application;

[0014] Figure 4 A structural diagram of an interconnect management device provided in an embodiment of this application;

[0015] Figure 5 A structural diagram of an interconnect management device including auxiliary circuitry is provided for an embodiment of this application;

[0016] Figure 6 A device monitoring flowchart provided in this application embodiment;

[0017] Figure 7 This is a schematic diagram of an electronic device provided in an embodiment of this application. Detailed Implementation

[0018] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the protection scope of this application.

[0019] It should be noted that, in the description of this application, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. The terms "first," "second," etc., in this application are used to distinguish similar objects and are not used to describe a specific order or sequence.

[0020] To enable those skilled in the art to better understand the present application, the present application will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0021] In one embodiment, such as Figure 1 As shown, this application provides a device monitoring method, including:

[0022] Step 101: In response to the power-on of the interconnect management device, the logic controller acquires multiple status detection signals related to the reset process of the interconnect controller;

[0023] Step 102: The logic controller generates a firmware loading flag signal based on multiple status detection signals for the management controller to read.

[0024] Step 103: In response to the firmware loading flag signal read by the management controller indicating that loading is valid, the management controller accesses the interconnect controller to monitor the interconnect status after a preset waiting period.

[0025] Specifically, this embodiment provides a device monitoring method that acquires multiple status detection signals related to the interconnect controller reset process in the logic controller and generates a firmware loading flag signal based on these status detection signals. This method controls the manager to delay accessing the interconnect controller, preventing the manager from accessing the interconnect controller prematurely before the firmware is fully loaded. This solves the problem in the prior art where the manager directly accesses the interconnect controller at the initial power-on stage, causing firmware loading interference and link training failure. Thus, it achieves effective protection during the firmware loading period of the interconnect controller, avoids the difficult-to-diagnose fault problems caused by premature access from the source, and improves the success rate of high-speed interconnect link training and the stability of system operation.

[0026] It is worth noting that, in one embodiment, the device monitoring method provided in this application is applied in an interconnect management device with a substrate as an example. After the device is powered on, the CPLD, which acts as a logic controller, receives the power status signal (RT_PWRGD) output by the power chip. The CPLD then sends an interconnect control signal (RT_RESET) to the Retimer to control its reset process. At the same time, it also transmits the link reset signal (RT_PERST) transmitted by the uplink board to the Retimer and OAM.

[0027] Specifically, this substrate is a substrate capable of mounting GPU modules. By mounting GPUs, a complete GPU platform is formed, enabling direct connection of GPU acceleration modules and providing a channel for high-speed data transmission and exchange. This facilitates multi-GPU collaboration to handle computationally intensive tasks in AI fields such as image recognition and machine learning. In some embodiments, this substrate can also provide power management and heat dissipation support for GPUs and other modules, ensuring stable operation of these modules. In some embodiments, this substrate is a UBB (Universal Baseboard) substrate, which can support multiple GPUs (such as 8 OAM modules) operating in various wiring and interconnect topologies.

[0028] Specifically, CPLD (Complex Programmable Logic Device), UBB board (Universal Base Board) is used to mount logic controllers, interconnect controllers, management controllers and accelerators to realize high-speed interconnection between CPU and OAM, OAM (OCP Accelerator Module) is used as an accelerator for the Open Computing Project to perform AI or other high-speed computing tasks, and Retimer is a PCIe retiming chip used as an interconnect controller for signal retiming and equalization to ensure signal integrity and stability of high-speed interconnect links;

[0029] During this process, due to the differences in the architecture design of different Retimer chips, the Retimer chip may start firmware loading at any time after reset. Unlike this application, in the prior art, the BMC, which acts as a management controller to monitor the Retimer, will start accessing the Retimer for monitoring as soon as the device is powered on. However, at this time, the BMC cannot determine whether the Retimer has completed firmware loading, which may lead to abnormal firmware loading in the Retimer, resulting in high-speed interconnect link training failure and exhibiting fault phenomena such as OAM card drop.

[0030] In one embodiment, such as Figure 2As shown, multiple status detection signals related to the reset process of the interconnect controller are acquired, including:

[0031] Step 201: Determine the reset process based on the architecture of the interconnect controller and obtain the corresponding reset completion time;

[0032] Step 202: Obtain the timing events associated with the logic controller, select the timing event that is at the same time as the reset completion time, and use the corresponding timing event signal as the status detection signal.

[0033] Specifically, in this embodiment, by combining the specific architectural features of the interconnect controller, the reset completion time is determined, and the corresponding timing event is selected from multiple timing events of the logic controller as the status detection signal. Therefore, the monitoring points can be flexibly adjusted according to the architecture of different interconnect controllers, avoiding the limitations of a single fixed timing judgment method. This ensures that the determination of the firmware loading status is more accurate, avoids the problem of inconsistent monitoring of the loading process due to architectural differences, and enhances the universality and stability of the method.

[0034] In one embodiment, a timing event that occurs at the same time as the reset completion time is selected, and the corresponding timing event signal is used as a state detection signal, including:

[0035] Acquire timing events associated with the logic controller, including at least power-on events, link reset events, and interconnect reset events;

[0036] Based on the power-on event, determine the power status signal received by the logic controller;

[0037] Based on the link reset event, determine the link reset signal received by the logic controller;

[0038] Based on the interconnect reset event, determine the interconnect reset control signal output by the logic controller;

[0039] One or more of the power status signal, link reset signal, and interconnect reset control signal are used as status detection signals.

[0040] Specifically, in this embodiment, by parsing the power-on event, link reset event, and interconnect reset event of the logic controller, the power status signal, link reset signal, and interconnect reset control signal are obtained and used as status detection signals. This enables comprehensive monitoring of the reset process from three dimensions: power, link, and interconnect, avoiding misjudgments caused by relying on a single signal, thereby enhancing the completeness and reliability of firmware loading status determination.

[0041] In one embodiment, the logic controller includes at least a logic judgment unit that generates a firmware loading flag signal based on multiple state detection signals, including:

[0042] Multiple state detection signals are input to the logic judgment unit so that the logic judgment unit can compare the input signal values ​​of the multiple state detection signals.

[0043] In response to multiple input signal values ​​being consistent with the corresponding preset valid state values, the logic judgment unit outputs the firmware loading flag signal to indicate that loading is valid.

[0044] In response to the existence of at least one input signal value that is inconsistent with the corresponding preset valid state value, the logic judgment unit outputs the firmware loading flag signal as indicating that loading is invalid.

[0045] Specifically, in this embodiment, a logic determination circuit is introduced into the logic controller. Multiple state detection signals are input to the determination circuit for comparison. Based on whether the input signal is consistent with the preset valid state value, a firmware loading flag signal indicating whether loading is valid or invalid is output. This embodiment completes the determination through hardware circuitry, avoiding the delay and burden caused by relying on software polling. It achieves fast and real-time determination of firmware loading status, improving the real-time performance and accuracy of system monitoring.

[0046] In one embodiment, the logic controller includes AND gates and flip-flops, and after using one or more of a power state signal, a link reset signal, and an interconnect reset control signal as state detection signals, it further includes:

[0047] When the logic controller starts up, the internal flags stored in the logic controller are initialized to invalid state values. The internal flags include the link reset first trigger flag and the firmware load flag.

[0048] Input the link reset signal and power status signal to the trigger;

[0049] If the input value of the power status signal is a valid status value, then the first rising edge of the link reset signal is obtained, and the first trigger flag of the link reset is set to a valid status value.

[0050] If the input value of the power status signal is an invalid status value, then both the link reset first trigger flag and the firmware load flag will remain invalid status values.

[0051] Input the link reset first trigger flag and the interconnect reset control signal into the AND gate circuit;

[0052] If both the input value of the interconnect reset control signal and the first trigger flag of the link reset are valid, then the firmware load flag is set to a valid value, and a firmware load flag signal indicating that the loading is valid is output.

[0053] If one or more of the input values ​​of the interconnect reset control signal and the link reset first trigger flag are invalid, the firmware load flag will be maintained as invalid, and a firmware load flag signal indicating invalid loading will be output.

[0054] Specifically, in this embodiment, by setting AND gate circuits and flip-flops in the logic controller and combining the power status signal, link reset signal, and interconnect reset control signal for judgment, it is possible to capture only the first rising edge of the link reset signal under the premise of stable power supply, so that the link reset first trigger flag is set under the correct timing conditions. Then, by inputting it and the interconnect reset control signal into the AND gate circuit, it is possible to ensure that the firmware loading flag is only set to be valid when both the link and interconnect reset are valid. This avoids misjudgment caused by unstable power supply or signal jitter, and ensures the accuracy and reliability of firmware loading flag generation. This effectively prevents link training failure and module card drop problems caused by abnormal firmware loading, and helps to improve the overall stability of the interconnect management device.

[0055] In one specific embodiment, such as Figure 3 As shown, the logic controller includes flip-flops and gate circuits. The flip-flops are preferably D flip-flops, and each flip-flop has multiple inputs, including a storage input, a preset input, a clear input, and a clock input. The output of the flip-flop is a trigger output, used to generate the first trigger flag for link reset.

[0056] When the logic controller starts up, the clear input is set to valid, the link reset first trigger flag bit of the trigger output is initialized to an invalid state value, and the firmware load flag bit is also set to an invalid state value.

[0057] When the input value of the current status signal is a valid status value, the logic controller inputs the signal to the storage input terminal and sets the preset input to valid, causing the flip-flop to enter the active state and begin waiting for the arrival of the link reset signal;

[0058] When the link reset signal arrives at the clock input and a rising edge appears for the first time, the trigger output of the flip-flop toggles to a valid state value, thereby generating the link reset first trigger flag bit;

[0059] The logic controller inputs the link reset first trigger flag and the interconnect reset control signal to the AND gate circuit. When both are valid, the firmware loading flag output by the AND gate circuit is set to a valid value and a firmware loading flag signal indicating that the loading is valid is generated. When either of them is invalid, the firmware loading flag remains invalid and a firmware loading flag signal indicating that the loading is invalid is output.

[0060] When the current status signal becomes invalid again, the trigger is reset through the clear input. The link reset first trigger flag and the firmware load flag are both restored to invalid values, thereby avoiding misjudgment caused by unstable power supply or link signal jitter.

[0061] Through the above design, the logic controller can rely on the storage input, preset input, clear input and clock input of the flip-flops to jointly determine the power status signal and the link reset signal, and combine the AND gate circuit to perform logical determination on the interconnect reset control signal, thereby generating an accurate firmware loading flag signal. The hardware circuit-based implementation not only ensures the reliability of firmware loading determination, but also enables fast response and improves the stability of the interconnect controller during operation.

[0062] In one embodiment, after setting the firmware load flag to a valid state value, the method further includes:

[0063] Continuously monitor power status signals and interconnect reset control signals;

[0064] If one or more of the input signal values ​​of the power status signal and the interconnect reset control signal change, the changed power status signal and / or interconnect reset control signal are re-inputted to the flip-flop and / or AND gate circuit.

[0065] If the input signal value in response to the power status signal is invalid, the trigger will be cleared, the firmware load flag and the link reset first trigger flag will be reset to invalid values, and the firmware load flag signal indicating invalid loading will be output again.

[0066] If the input signal value of the interconnect reset control signal is invalid, the original value of the link reset first trigger flag is maintained, and the firmware load flag is updated to an invalid value.

[0067] Specifically, in this embodiment, after the firmware loading flag is set to valid, the power status signal and interconnect reset signal are continuously monitored dynamically, and the judgment result is regenerated when the signal changes. This ensures the continuous validity of the firmware loading flag during operation, avoids the system stagnation problem caused by the firmware loading flag no longer being updated once it is output, and enables the system to detect abnormalities and correct the judgment state in a timely manner during operation, thereby improving the system's fault tolerance and operational safety.

[0068] In one embodiment, the logic controller further includes: an auxiliary input circuit connected to the interconnect controller, which combines a power status signal, a link reset signal, and an interconnect reset control signal to obtain multiple status detection signals, and further includes:

[0069] An auxiliary signal is obtained through the auxiliary input circuit to characterize the firmware loading completion status of the interconnect controller;

[0070] The corresponding auxiliary flag signal is generated based on the auxiliary signal, and the auxiliary flag signal is stored in the logic controller;

[0071] In response to receiving an interconnect controller status query request from the management controller, the stored auxiliary flag signal is sent to the management controller to provide auxiliary observation records for the management controller to determine the status changes of the interconnect controller.

[0072] Specifically, in this embodiment, an auxiliary input circuit is introduced into the logic controller to obtain the firmware loading completion status of the interconnect controller and generate an auxiliary flag signal for the management controller to call. This provides a verification mechanism that complements the logic judgment result, enabling the management controller to perform dual verification using both the logic controller's judgment signal and the interconnect controller's own signal. This avoids the problem of relying on only one side's signal and lacking cross-verification, further improving the accuracy of status judgment and adaptability to various architectures.

[0073] In one embodiment, in response to the firmware loading flag signal read by the management controller indicating that loading is valid, the management controller accesses the interconnect controller to perform interconnect status monitoring after a preset waiting period, including:

[0074] Based on the architecture and historical performance data of the interconnect controller, determine the minimum time required for the interconnect controller to complete internal initialization and the maximum time required to enter a stable operating state, and set the lower limit and upper limit of the waiting period threshold respectively.

[0075] The waiting period threshold is determined based on the lower limit and upper limit of the waiting period threshold, and a preset waiting period is selected.

[0076] Within a preset waiting period, the management controller continuously monitors whether the firmware loading flag signal output by the logic controller changes through the first bus connected to the logic controller.

[0077] If the preset waiting period ends and the firmware loading flag signal still indicates that loading is valid, the management controller will continuously access the interconnect controller through the second bus connected to the interconnect controller.

[0078] If the firmware loading flag signal changes within the preset waiting period and indicates that loading is invalid, the management controller will repeatedly reset the preset waiting period until the firmware loading flag signal indicates that loading is valid.

[0079] Specifically, in this embodiment, before the management controller accesses the interconnect controller, it sets upper and lower limits of the waiting period threshold based on the architecture and historical performance data of the interconnect controller. Within the preset waiting period, it listens for changes in the firmware loading flag and then decides whether to access the interconnect controller. This achieves accurate setting of the waiting time, avoids premature access that may cause firmware loading interference, and also avoids unnecessary long waiting times that may affect efficiency. It ensures reasonable control over the timing of access to the management controller, effectively balancing loading stability and access efficiency, thereby improving the success rate of link training and overall performance.

[0080] In one embodiment, if the preset waiting period ends and the firmware loading flag signal still indicates that loading is valid, the management controller continuously accesses the interconnect controller via a second bus connected to the interconnect controller, including:

[0081] Based on preset monitoring dimensions, the operating status information of the interconnected controller is continuously acquired through the second bus;

[0082] Based on the operating status information, the interconnect controller is monitored and evaluated for status.

[0083] During the access process, the firmware loading flag signal is continuously monitored via the first bus to see if it changes.

[0084] If a change in the firmware loading flag signal is detected and indicates that loading is invalid, the current access operation is aborted and an exception handling process is triggered. If the firmware loading flag signal does not change, access to the interconnect controller is maintained.

[0085] Specifically, in this embodiment, by continuously acquiring the running status register information during the process of the management controller accessing the interconnect controller, and simultaneously monitoring changes in the firmware loading flag, access is terminated and an exception handling process is triggered once an invalid loading flag is detected. This achieves synchronous operation monitoring and status determination, enabling timely identification and isolation of faults during the operation of the interconnect controller, thereby significantly improving the reliability and maintainability of the system operation.

[0086] In one optional embodiment, the interconnect management device includes multiple interconnect controllers that generate a firmware loading flag signal based on multiple status detection signals for the management controllers to read, including:

[0087] Each of the multiple interconnected controllers is assigned an independent status detection channel to store flag bits. The flag bits include at least: the sampling result of the power status signal, the first trigger flag bit of the link reset signal, and the firmware loading flag bit.

[0088] In response to device power-on, the interconnect reset control signals of the corresponding interconnect controllers are released sequentially based on the interconnect controller ports, and the link reset signals are synchronously distributed to the corresponding status detection channels, so that the reset processes of multiple interconnect controllers are staggered in time, avoiding the simultaneous triggering of each channel during the power-on phase and causing access congestion on the management side.

[0089] Based on the combination relationship between the power status signal and the link reset signal, firmware loading flag signals for multiple status detection channels are generated sequentially. The flag bits of multiple status detection channels are summarized and mapped to a set of consecutive register storage units to form a flag bit table and timestamp record arranged according to the interconnect controller port index. This allows the management controller to read and determine the access scheduling of multiple interconnect controllers based on the firmware loading flag signals of multiple status detection channels.

[0090] In one embodiment, the management controller reads and determines the access scheduling of multiple interconnect controllers based on firmware load flag signals from multiple status detection channels, including:

[0091] For a status detection channel marked as valid, the management controller accesses it in batches according to a preset waiting period table. Within the same batch, after the waiting period of each status detection channel expires, the management controller enters the status monitoring process of the corresponding interconnect controller through the interconnection access channel built on the second bus.

[0092] For state detection channels marked as invalid, the management controller does not initiate access, but only records the inspection results of the current round and re-evaluates them in the next round of scheduling;

[0093] Furthermore, the management controller limits the maximum number of parallel accesses within each access cycle and applies a small starting offset to the start time of the initial access, so that the access start points of multiple status detection channels within the batch are distributed in time, thereby reducing the disturbance of concurrent access to the internal firmware process of each interconnect controller.

[0094] Furthermore, during the access process, the management controller continuously monitors the changes in the flag table on the logic controller side. When any accessed status detection channel experiences a flag change from valid to invalid during operation, the management controller immediately terminates the current access to the corresponding status detection channel and moves it to the rollback queue. Access will resume in the next round after the logic controller regenerates a valid flag.

[0095] Optionally, in order to quickly locate anomalies in multi-channel scenarios, the logic controller configures an auxiliary input path for each status detection channel to receive auxiliary signals from the corresponding interconnect controller, and records the auxiliary flag bit and the time of the most recent change in the flag bit table; when the management controller reads the flag bit table, it dynamically adjusts the access priority in combination with the auxiliary flag bit: when the status detection channel shows an auxiliary flag indicating that it is in a debugging, rollback or loading incomplete state, even if the basic flag bit is valid, the management controller will also lower its priority or extend the waiting period to reduce interference with the internal process of the channel.

[0096] Specifically, through the aforementioned collaborative mechanism, the logic controller is responsible for providing accurate and de-concurrency-free status determination and timing arrangement under multi-channel conditions. The management controller then coordinates access for batching, rate limiting, rollback, and recovery. The two work together to achieve orderly supervision of multiple interconnected controllers without changing the single-channel determination logic. This avoids the disturbance to firmware loading caused by concentrated access during power-on and reset phases, and improves the overall stability and maintainability of the multi-channel system through continuous monitoring of flag bits and timely rollback during the operation phase.

[0097] In one embodiment, generating a firmware loading flag signal based on a plurality of the status detection signals for the management controller to read further includes:

[0098] The logic controller sets the firmware loading flag signal to a multi-bit signal that includes at least two bits of encoding, based on the bit width of the first bus.

[0099] In response to the first bus having a bit width greater than or equal to twice the number of interconnect controllers, the logic controller allocates fixed two-bit positions to multiple interconnect controllers sequentially based on the interconnect controller number sequence, stores the firmware loading status of the corresponding interconnect controller, and distributes it to the corresponding channel so that the management controller can collect data from all channels in one read. Optionally, 00 indicates that the firmware is not loaded, 01 indicates that the firmware is loading, 10 indicates that the firmware loading has failed, and 11 indicates that the firmware loading has been completed.

[0100] In response to the fact that the bit width of the first bus is less than twice the number of interconnect controllers, the logic controller outputs the firmware loading flag signals of multiple channels sequentially according to preset frames, and carries the channel index field and the check field in each frame so that the management controller can build the state view in multiple frame cycles.

[0101] Specifically, in this embodiment, by setting a multi-bit encoded firmware loading status signal, the management controller can synchronously or frame-by-frame collect the firmware loading status of multiple interconnect controllers under different bus bit widths, thereby realizing the construction of a unified view of multi-channel status and providing a reliable basis for subsequent access scheduling and parallel monitoring. Moreover, compared with using a single-bit flag signal, multi-bit encoding can carry more status information in a single read, such as distinguishing different stages such as loading, loading failure, or loading completion, thereby improving the precision of status collection and monitoring efficiency, while reducing the risk of bus congestion and access conflicts, and improving the management flexibility and reliability in multi-interconnect controller scenarios.

[0102] Through the above description of the embodiments, those skilled in the art can clearly understand that the methods according to the above embodiments can be implemented by means of software plus necessary general-purpose hardware platforms. Of course, they can also be implemented by hardware, but in many cases the former is a better implementation method.

[0103] like Figure 4 As shown, embodiments of this application also provide an interconnect management device, which is connected to an uplink management device. The interconnect management device includes a logic controller, an interconnect controller, and a management controller.

[0104] The logic controller is connected to the interconnect controller, the accelerator, and the management controller, respectively. The interconnect controller is connected to the accelerator, and the management controller is connected to the logic controller and the interconnect controller, respectively.

[0105] The logic controller receives power status signals and link reset signals, and generates interconnect reset signals and firmware loading flag signals. Specifically, the logic controller sends the interconnect reset signal to the interconnect controller, sends the firmware loading flag signal to the management controller, and forwards the link reset signal to the interconnect controller and the accelerator, respectively.

[0106] The interconnect controller performs a reset based on the received interconnect reset signal, and triggers the internal firmware loading and link training process when it receives the link reset signal. The interconnect controller is connected to the accelerator and provides a stable high-speed interconnect channel for data interaction between the accelerator and the uplink management device after completing the firmware loading and link training.

[0107] The management controller performs delayed access to the interconnect controller based on the received firmware loading flag signal. That is, it continuously accesses the interconnect controller and obtains the operating status information after a preset waiting period in order to realize the operation monitoring of the interconnect controller.

[0108] After receiving the link reset signal and completing the link training with the interconnect controller, the accelerator performs calculation processing and feeds back the calculation results to the interconnect controller through the high-speed channel, and then the interconnect controller forwards them to the uplink management device.

[0109] In one embodiment, the uplink management device is connected to the interconnect management device, and the uplink management device includes at least a central processing unit, main memory, an uplink interface control module, a system clock and reset module, a power management module, and an optional uplink board-level management controller.

[0110] The power management module is used to supply power to the uplink management device and the interconnect management device, and output a power status signal to the logic controller. The logic controller uses this signal as an important input for status detection to generate a firmware loading flag signal and control the reset timing of the interconnect controller.

[0111] The system clock and reset module is used to generate a link reset signal when the central processing unit initiates link initialization, and transmits it to the logic controller through the uplink interface control module. The logic controller distributes the link reset signal to the interconnect controller and the downlink accelerator, so that the interconnect link can start the training process under a unified reset reference.

[0112] The central processing unit (CPU), acting as the initiating unit for uplink data, establishes a high-speed data channel with the downlink accelerator via the uplink interface control module after the interconnect controller completes firmware loading and link training. This forms a high-speed channel signal. The interconnect controller processes and regenerates the high-speed channel signal before forwarding it to the accelerator to ensure signal integrity and link stability. Simultaneously, the accelerator's calculation results are returned to the interconnect controller via the high-speed channel signal and fed back to the CPU, achieving end-to-end data exchange.

[0113] Main memory provides support for task scheduling and data retrieval by the central processing unit;

[0114] The uplink board-level management controller interacts with the management controller in the interconnect management device via a low-speed management bus, receives firmware loading flag signals generated by the logic controller and interconnect controller operation status information fed back by the management controller, thereby realizing remote monitoring and management of the interconnect link operation.

[0115] like Figure 5 As shown, in one embodiment, this application also provides another interconnect management device, which, in addition to the structure of the interconnect management device described above, also provides an auxiliary circuit between the logic controller and the interconnect controller. The auxiliary circuit is preferably a general purpose input / output interface GPIO0.

[0116] Specifically, the logic controller acquires additional auxiliary signals from the interconnect controller through the GPIO0 interface, generates auxiliary flag signals, and stores them for subsequent management controllers to read and call.

[0117] Specifically, through this auxiliary circuit, the logic controller can obtain additional information such as the firmware loading completion status or debugging status of the interconnect controller, in addition to the conventional power status signal, link reset signal, and interconnect reset control signal. This allows for the generation of more accurate auxiliary flag signals, which are then fed back to the management controller. Simultaneously, when the management controller performs interconnect status monitoring, the auxiliary circuit can also provide additional observation channels, facilitating the rapid location of faulty components in the interconnect controller when firmware loading anomalies or link training failures occur, thereby improving the stability and maintainability of the system.

[0118] In one specific embodiment, the interconnect management device is located in a UBB board structure. This device includes a CPLD, a PCIeRetimer chip, a BMC, and an OAM, wherein:

[0119] The CPLD is connected to the PCIe Retimer chip, OAM, and BMC respectively; the Retimer is connected to the OAM; and the BMC is connected to the CPLD and the PCIe Retimer chip respectively.

[0120] The CPLD receives the power good signal (RT_PWRGD) and link reset signal (PERST) from the uplink CPU and power management chip, and generates the Retimer reset control signal (RT_RESET) and firmware loading flag signal accordingly. The power good signal is the power status signal, and the Retimer reset control signal is the interconnect control signal. The RT_RESET signal is sent to the PCIeRetimer chip, and the firmware loading flag signal is sent to the BMC. At the same time, the PERST signal is passed through by the CPLD to the PCIeRetimer chip and OAM to ensure that the link is trained under a unified reset benchmark.

[0121] Upon receiving the RT_RESET signal from the CPLD, the Retimer performs a reset operation and initiates the firmware loading and link training process upon receiving the PERST signal. After completing firmware loading and training, the Retimer provides retiming and signal equalization capabilities for the PCIeX16 high-speed link between the CPU and OAM, ensuring the stability and signal integrity of the link transmission.

[0122] Based on the firmware loading flag signal output by the CPLD, the BMC performs delayed access to the Retimer. That is, after a preset waiting period, it periodically accesses the Retimer through the I²C interface to read its operating status and working parameters such as temperature and voltage, thereby realizing the monitoring and management of the Retimer chip. In particular, the delayed access strategy avoids firmware loading abnormalities caused by premature access during the Retimer firmware loading process, thereby improving link stability.

[0123] After receiving the PERST signal transmitted by the CPLD and completing the link training with the Retimer, OAM performs AI training or inference tasks. The calculation results of OAM are returned to the Retimer chip through the PCIeX16 high-speed link, and then forwarded to the CPU by the Retimer, realizing end-to-end high-speed data exchange.

[0124] In a further embodiment, the uplink board includes a CPU, main memory, power management chip, system clock and reset module, and uplink interface control module:

[0125] The CPU, as the initiating unit of uplink data, sends the PCIeX16 signal to the Retimer via the uplink interface control module, and performs high-speed data interaction with OAM after the link is established.

[0126] The power management chip supplies power to the entire board and outputs the RT_PWRGD signal to the CPLD, which serves as an important input for the CPLD to determine the firmware loading flag.

[0127] The system clock and reset module generate a PERST signal, which is transmitted to the CPLD through the uplink interface control module. The CPLD then forwards the signal to the Retimer and OAM for unified reset control.

[0128] like Figure 6 As shown, in one embodiment, based on the interconnect management device provided in this application, the execution flow of the device monitoring method of this application includes:

[0129] On the logic controller side, firstly, after the interconnect management device is powered on, the logic controller initializes its internal flags, setting both the link reset first trigger flag and the firmware loading flag to an invalid state. Then, the logic controller receives the power status signal and determines whether its input value is a valid state value. If not, the power status signal is invalid, and the logic controller keeps all the aforementioned flags invalid and ends subsequent processing. If yes, the power status signal is valid, and the logic controller releases the interconnect reset control signal to the interconnect controller. Next, the logic controller detects the input status of the link reset signal. When the first rising edge of the link reset signal is detected, the logic controller sets the link reset first trigger flag to a valid state value and performs a logical determination together with the interconnect reset control signal. If both are valid state values, the logic controller sets the firmware loading flag to a valid state value and outputs a firmware loading flag signal indicating that loading is valid. If at least one of them is an invalid state value, the logic controller maintains the firmware loading flag as invalid and outputs a firmware loading flag signal indicating that loading is invalid.

[0130] On the management controller side, the management controller executes the corresponding access strategy based on the firmware loading flag signal generated by the logic controller. If the firmware loading flag signal indicates that the loading is invalid, the management controller will not access the interconnect controller, thereby avoiding interference with the firmware loading process due to premature access. If the firmware loading flag signal indicates that the loading is valid, the management controller will start accessing the interconnect controller after completing the preset waiting period, and continuously acquire the operating status information during the access process to achieve stable monitoring of the interconnect controller. During the access process, if the firmware loading flag bit changes to an invalid state value, access to the interconnect controller will stop.

[0131] Specifically, through the collaborative action of the logic controller and the management controller, this embodiment can dynamically identify the actual state of the interconnect controller during the firmware loading process and reasonably adjust the access timing of the management controller, thereby avoiding link training failure caused by firmware loading anomalies and ensuring the stability and reliability of the interconnect link.

[0132] like Figure 7 As shown, embodiments of this application also provide an electronic device, including a memory and a processor, wherein the memory stores a computer program and the processor is configured to run the computer program to perform the steps in any of the above-described device monitoring method embodiments.

[0133] Those skilled in the art will further recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of both. To clearly illustrate the interchangeability of hardware and software, the components and steps of the various examples have been generally described in terms of functionality in the foregoing description. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0134] The foregoing has provided a detailed description of a device monitoring method and electronic device provided in this application. Specific examples have been used to illustrate the principles and implementation methods of this application. The descriptions of the above embodiments are only intended to help understand the method and core ideas of this application. It should be noted that those skilled in the art can make various improvements and modifications to this application without departing from its principles, and these improvements and modifications also fall within the protection scope of this application.

Claims

1. A method of monitoring a device, characterized by, The application is applied to an interconnection management device, the interconnection management device at least includes a logic controller, an interconnection controller and a management controller, the logic controller at least includes a logic judging unit, the method includes: In response to power-on of the interconnection management device, the logic controller acquires a plurality of state detection signals related to a reset process of the interconnection controller, including: determining the reset process based on the architecture of the interconnection controller and obtaining the corresponding reset completion time, acquiring the timing event associated with the logic controller, and selecting the timing event at the same time as the reset completion time, and taking the corresponding timing event signal as the state detection signal; The logic controller generates a firmware loading flag signal based on a plurality of state detection signals for the management controller to read, including: inputting a plurality of state detection signals into the logic judging unit for the logic judging unit to compare according to the input signal values of a plurality of state detection signals, in response to a plurality of input signal values being consistent with the corresponding preset valid state value, the logic judging unit outputs the firmware loading flag signal as indicating loading valid, in response to at least one input signal value being inconsistent with the corresponding preset valid state value, the logic judging unit outputs the firmware loading flag signal as indicating loading invalid; In response to the firmware loading flag signal read by the management controller indicating loading valid, the management controller accesses the interconnection controller for interconnection state monitoring after a preset waiting period.

2. The device monitoring method according to claim 1, wherein The selection of the timing event at the same time as the reset completion time, taking the corresponding timing event signal as the state detection signal, includes: Acquiring the timing event associated with the logic controller, at least including power-on event, link reset event and interconnection reset event; Determine the power state signal received by the logic controller based on the power-on event; Determine the link reset signal received by the logic controller based on the link reset event; Determine the interconnection reset control signal output by the logic controller based on the interconnection reset event; One or more of the power state signal, the link reset signal and the interconnection reset control signal are taken as the state detection signal.

3. The device monitoring method according to claim 2, wherein The logic controller includes an AND gate circuit and a flip-flop, after the one or more of the power state signal, the link reset signal and the interconnection reset control signal are taken as the state detection signal, further including: When the logic controller starts, initialize the internal flag bit stored in the logic controller to an invalid state value, the internal flag bit includes a link reset first trigger flag bit and a firmware loading flag bit; Input the link reset signal and the power state signal into the flip-flop; If the input value of the power state signal is a valid state value, the first rising edge of the link reset signal is acquired, and the link reset first trigger flag bit is set to a valid state value; if the input value of the power state signal is an invalid state value, then the link reset first trigger flag and the firmware loading flag are both maintained as invalid state values; the link reset first trigger flag and the interconnection reset control signal are input into the AND gate circuit; if the input value of the interconnection reset control signal and the link reset first trigger flag are both valid state values, then the firmware loading flag is set as a valid state value, and the firmware loading flag signal representing a valid loading is output; if one or more of the input value of the interconnection reset control signal and the link reset first trigger flag is an invalid state value, then the firmware loading flag is maintained as an invalid state value, and the firmware loading flag signal representing an invalid loading is output.

4. The device monitoring method according to claim 3, wherein after the firmware loading flag is set as a valid state value, further comprising: continuously monitoring the power state signal and the interconnection reset control signal; in response to one or more of the input signal value of the power state signal and the input signal value of the interconnection reset control signal changing, then the changed power state signal and / or interconnection reset control signal are re-input into the flip-flop and / or the AND gate circuit; in response to the input signal value of the power state signal being an invalid state value, then the flip-flop is cleared, the firmware loading flag and the link reset first trigger flag are reset to invalid state values, and the firmware loading flag signal representing an invalid loading is re-output; in response to the input signal value of the interconnection reset control signal being an invalid state value, then the original value of the link reset first trigger flag is maintained, and the firmware loading flag is updated to an invalid state value.

5. The method of claim 2, wherein, The logic controller further comprises an auxiliary input circuit connected to the interconnection controller, and after the power state signal, the link reset signal and the interconnection reset control signal are combined to obtain a plurality of state detection signals, further comprising: through the auxiliary input circuit, an auxiliary signal is obtained for representing the firmware loading completion state of the interconnection controller; an auxiliary flag signal corresponding to the auxiliary signal is generated, and the auxiliary flag signal is stored in the logic controller; in response to receiving an interconnection controller state query request issued by the management controller, the stored auxiliary flag signal is sent to the management controller to provide auxiliary observation records for the management controller to judge the state change of the interconnection controller.

6. The method of claim 1, wherein, in response to the firmware loading flag signal read by the management controller representing a valid loading, the management controller accesses the interconnection controller for interconnection state monitoring after a preset waiting period, comprising: based on the architecture and historical performance data of the interconnection controller, the minimum time required for the interconnection controller to complete internal initialization and the maximum time to enter a stable running state are determined, and a waiting period threshold lower limit and a waiting period threshold upper limit are respectively set; determine the waiting period threshold according to the waiting period threshold lower limit and the waiting period threshold upper limit, and select the preset waiting period; In the preset waiting period, the management controller continuously monitors whether the firmware loading flag signal output by the logic controller changes through the first bus connected with the logic controller; If the firmware loading flag signal changes and represents invalid loading in the preset waiting period, the management controller resets the preset waiting period in a loop until the firmware loading flag signal represents valid loading; If the preset waiting period ends and the firmware loading flag signal still represents valid loading, the management controller continuously acquires the running state information of the interconnection controller based on preset monitoring dimensions through the second bus; According to the running state information, the interconnection controller is state-monitored and evaluated; In the access process, whether the firmware loading flag signal changes is continuously monitored through the first bus; if it is detected that the firmware loading flag signal changes and represents invalid loading, the current access operation is aborted and an exception processing procedure is triggered, and if the firmware loading flag signal does not change, the access to the interconnection controller is maintained.

7. The method of claim 1, wherein, The interconnection management device is provided with a plurality of interconnection controllers, and the firmware loading flag signal is generated based on a plurality of state detection signals for the management controller to read, which includes: Independent state detection channels are respectively arranged for a plurality of interconnection controllers to store flag bits, and the flag bits at least include: a sampling result of a power state signal, a first triggering flag bit of a link reset signal, and a firmware loading flag bit; In response to device power-on, the interconnection reset control signal of the corresponding interconnection controller is sequentially released based on the interconnection controller port order, and the link reset signal is synchronously distributed to the corresponding state detection channel, so that the reset processes of a plurality of interconnection controllers are staggered in time; According to the combination relationship of the power state signal and the link reset signal, the firmware loading flag signals of a plurality of state detection channels are sequentially generated, and the flag bits of a plurality of state detection channels are summarized and mapped to a group of continuous register storage units to form a flag bit table and a time stamp record arranged according to the interconnection controller port index, for the management controller to read and determine the access scheduling of a plurality of interconnection controllers according to the firmware loading flag signals of a plurality of state detection channels.

8. An electronic device, comprising: It includes: a memory for storing a computer program; a processor for executing the computer program to implement the device monitoring method according to any one of claims 1 to 6.

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