Chip verification system, verification method, device and medium

Abstract

The invention provides a chip verification system, verification method, device and medium, the system comprises a verification device and a to-be-tested chip, and the verification device comprises a test component, a verification model and a verification file; the test component is used for obtaining a reference test case and a to-be-input picture according to the identifier of the to-be-tested module; according to the dependency relationship of the to-be-tested module, determining an associated module having the dependency relationship with the to-be-tested module and obtaining an associated test case, and sequentially splicing the reference test case and the associated test case to obtain a first test linked list; obtaining a target test case, and sequentially splicing the reference test case, the associated test case and the target test case to obtain a second test linked list; and inputting the to-be-input picture and the first test linked list into the verification model, inputting the to-be-input picture and the second test linked list into the to-be-tested chip, and comparing output results of the to-be-input picture and the second test linked list to obtain a verification result. According to the scheme, the chip verification is accurate and reliable.

Description

TECHNICAL FIELD

[0001] The present application relates to the chip verification technical field, and particularly relates to a chip verification system, a verification method, equipment and a medium. BACKGROUND

[0002] With the rapid development of chip manufacturing technology and integrated circuit industry, more and more high-integration and complex-function chips are designed by technicians to meet the needs of different industries. Chip verification is a necessary step in the chip design process, which aims to ensure that the functions of the chip work normally according to the design requirements, and prevent functional defects or other problems caused by design errors.

[0003] Chip verification is to verify whether the chip design meets the requirements of the chip definition specification and whether all risks have been completely released before the chip is produced, and to find and correct all defects. When there are multiple modules in the chip that need to be combined for verification, there is no content for combined testing of multiple modules in the prior art, and more is to describe the verification platform and test the functions of a single module, which blurs the intermediate verification process and only embodies the functions of the verification platform. However, how to perform combined function verification on multiple modules is still a problem to be solved. SUMMARY

[0004] The present application provides a chip verification system, a verification method, equipment and a medium, which are flexible and have great expansibility, so that the chip verification is accurate and reliable.

[0005] In an aspect, the application provides a chip verification system, the chip verification system comprising a verification device and a chip under test, the verification device comprising a test component, a verification model and a verification file; the test component is configured to: obtain a reference test case from a test case set corresponding to a module under test according to an identifier of the module under test input by a user, and obtain a picture to be input, a parameter value of an image parameter of the picture to be input being the same as a parameter value of an image parameter in the reference test case; determine an associated module having a dependency relationship with the module under test according to a dependency relationship of the module under test in the verification file; obtain an associated test case from a test case set corresponding to the associated module, and sequentially splice the reference test case and the associated test case based on the dependency relationship of the module under test to obtain a first test chain table; and obtain a target test case from a test case set corresponding to all modules of the chip under test except the module under test and the associated module based on the dependency relationship of the module under test, and sequentially splice the reference test case, the associated test case and the target test case to obtain a second test chain table; the parameter values of the image parameters in the reference test case, the associated test case and the target test case are the same; input the picture to be input and the first test chain table into the verification model to obtain a first result output by the verification model; and input the picture to be input and the second test chain table into the chip under test to obtain a second result output by the chip under test, and compare the first result and the second result to obtain a verification result.

[0006] In a possible implementation, when the test component sequentially splices the reference test case and the associated test case based on the dependency relationship of the module under test to obtain the first test chain table, the test component is specifically configured to: determine a first running order of the module under test and the associated module based on the dependency relationship of the module under test; configure, according to the first running order, an input field content in a test case of a first module in the module under test and the associated module as an access path of the picture to be input; and sequentially configure, for each of other modules in the module under test and the associated module, an input field content in a test case of the module as an output field content in a test case of a previous module until the input field in the reference test case is configured, to obtain the first test chain table; when the test component sequentially splices the reference test case, the associated test case and the target test case to obtain the second test chain table, the test component is specifically configured to: determine a second running order of all modules of the chip under test including the module under test based on the dependency relationship of the module under test; configure, according to the second running order, an input field content in a test case of a first module of the chip under test as the access path of the picture to be input; and sequentially configure, for each of other modules of the chip under test, an input field content in a test case of the module as an output field content in a test case of a previous module until the input field in the reference test case is configured, to obtain the second test chain table.

[0007] In a possible implementation, the test case set corresponding to each module includes a list of regular parameters and a list of register parameters; the list of regular parameters is used to store image parameters and activation parameters of each test case in the test case set; the list of register parameters is used to store register parameters of each test case in the test case set; and the activation parameters in different states represent whether the corresponding module needs to be skipped.

[0008] In a possible implementation, when the test component obtains the associated test case from the test case set corresponding to the associated module, the test component is specifically configured to: randomly select, from the test case set corresponding to each associated module, a test case with the same parameter value of the image parameter in the reference test case as the associated test case of the module; and when the test component obtains the target test case from the test case set corresponding to each module other than the to-be-tested module and the associated module based on the dependency relationship of the to-be-tested module, the test component is specifically configured to: for each module other than the to-be-tested module and the associated module in the to-be-tested chip, select, from the test case set corresponding to the module, a test case with the same parameter value of the image parameter in the reference test case and with the activation parameter in the inactivation state as the target test case of the module.

[0009] In a possible implementation, the verification model is configured to: determine, according to the received first test chain table, a corresponding module in the verification model; run, according to each test case in the first test chain table, the module corresponding to the test case in the verification model in a first running order, and obtain a first result; and the to-be-tested chip is configured to: run, according to each test case in the received second test chain table, the to-be-tested module and the associated module of the to-be-tested chip in a second running order, and skip the modules other than the to-be-tested module and the associated module in the to-be-tested chip, and obtain a second result; and in the second test chain table, the activation parameters in the test cases of the to-be-tested module and the associated module are in the activation state, and the activation parameters in the test cases of other modules are in the inactivation state.

[0010] In a possible implementation, the activation parameter includes a skip parameter and an enable parameter; the activation parameter in the activation state includes the skip parameter being the inactivation value and the enable parameter being the activation value; and the activation parameter in the inactivation state includes the skip parameter being the activation value, the skip parameter being the inactivation value, and the enable parameter being the inactivation value.

[0011] In a possible implementation, the test component is further configured to: perform format conversion on the to-be-input picture to obtain a converted to-be-input picture before inputting the to-be-input picture and the second test chain table into the to-be-tested chip; and perform format conversion on the second result to obtain a converted second result before comparing the first result and the second result.

[0012] In a possible implementation, when the test component compares the first result and the second result to obtain the verification result, the first result and the second result are compared in the following manner: the results of the pixel points at the same positions in the first result and the converted second result are compared; if the results of the pixel points at the same positions in the first result and the converted second result are consistent, it is determined that the first result and the second result are consistent; otherwise, it is determined that the first result and the second result are inconsistent.

[0013] In a possible implementation, the test component is further configured to perform a cyclic redundancy check calculation on the first result to obtain a cyclic redundancy check value of the first result; the chip under test is further configured to output a cyclic redundancy check value of the second result according to the second result; and when the test component compares the first result and the second result to obtain the verification result, the first result and the second result are compared in the following manner: if the cyclic redundancy check value of the first result is the same as the cyclic redundancy check value of the second result, it is determined that the first result and the second result are consistent; otherwise, it is determined that the first result and the second result are inconsistent.

[0014] In a possible implementation, the test component is further configured to output a test report when the verification fails, the test report including a comparison record of the first result and the second result and a running state and related data of each test case used for the verification.

[0015] In another aspect, the present application provides a verification method based on a chip verification system, the chip verification system including a verification device and a chip under test, the verification device including a test component, a verification model, and a verification file; the method including: the test component obtaining a reference test case from a test case set corresponding to a module under test according to an identifier of the module under test input by a user, and obtaining a to-be-input image, a parameter value of an image parameter of the to-be-input image being the same as a parameter value of an image parameter in the reference test case; and determining an associated module having a dependency relationship with the module under test according to a dependency relationship of the module under test in the verification file; the test component obtaining an associated test case from a test case set corresponding to the associated module, and sequentially splicing the reference test case and the associated test case based on the dependency relationship of the module under test to obtain a first test linked list; and obtaining a target test case from a test case set corresponding to all modules of the chip under test except the module under test and the associated module based on the dependency relationship of the module under test, and sequentially splicing the reference test case, the associated test case, and the target test case to obtain a second test linked list; the parameter values of the image parameters in the reference test case, the associated test case, and the target test case being the same; the test component inputting the to-be-input image and the first test linked list into the verification model to obtain a first result output by the verification model; and inputting the to-be-input image and the second test linked list into the chip under test to obtain a second result output by the chip under test, and comparing the first result and the second result to obtain a verification result.

[0016] In yet another aspect, the present application provides an electronic device, comprising a processor, a memory connected with the processor, and the system as above.

[0017] In yet another aspect, the present application provides a computer readable storage medium, wherein the computer readable storage medium stores computer execution instructions, and the computer execution instructions comprise the system as above.

[0018] The chip verification system, verification method, device and medium provided by the present application, the chip verification system comprises a verification device and a chip to be tested, the verification device comprises a test component, a verification model and a verification file; the test component finds the reference test case corresponding to the to-be-tested module and the to-be-input picture according to the identification of the to-be-tested module input by a user; based on the dependency relationship of the to-be-tested module in the verification file, the dependency module corresponding to the to-be-tested module is found, and the associated test case corresponding to the dependency module is obtained, and the reference test case and the associated test case are sequentially spliced to obtain a first module linked list; based on the dependency relationship of the to-be-tested module in the verification file, the target test case corresponding to all modules of the chip to be tested except the to-be-tested module and the associated module is found, and the reference test case, the associated test case and the target test case are sequentially spliced to obtain a second module linked list; the first module linked list and the to-be-input picture are input into the verification model to obtain a first result, the second module linked list and the to-be-input picture are input into the chip to be tested to obtain a second result, and the first result and the second result are compared to obtain a verification result. The scheme of the present application provides a combined module test verification logic, the test case of the to-be-tested module and the to-be-input picture are found first, the modules having a dependency relationship are matched through the verification file, the test cases corresponding to the dependency modules and other modules are found, the test cases are spliced respectively, different module linked lists of the verification model and the chip to be tested are established, chip verification is realized, the method is flexible, and has high expansibility. Meanwhile, when the verification fails, a test report can also be output, error causes can be positioned and analyzed in time, problems can be reproduced and positioned, and the verification is more accurate and reliable. BRIEF DESCRIPTION OF DRAWINGS

[0019] The drawings incorporated into the specification and forming a part thereof, illustrate embodiments consistent with the present application and, together with the specification, serve to explain the principles of the present application.

[0020] Figure 1 FIG. 1 shows a structural schematic diagram of the chip verification system provided by the embodiment one of the present application;

[0021] Figure 2 FIG. 2 shows a schematic diagram of the to-be-tested chip connected with the computer host through the debugging tool;

[0022] Figure 3 FIG. 4 shows a schematic diagram of the pixel point comparison result;

[0023] Figure 4A cyclic redundancy check comparison diagram is shown in the figure;

[0024] Figure 5 The flowchart of the verification method based on the chip verification system provided by the second embodiment of the present application is shown in the figure;

[0025] Figure 6 The structural diagram of the electronic device provided by the third embodiment of the present application is shown in the figure.

[0026] The specific embodiments of the present application have been shown in the above figures, and will be described in more detail hereinafter. The figures and the description are not intended to limit the scope of the present application by any means, but to illustrate the concept of the present application to those skilled in the art by referring to specific embodiments. DETAILED DESCRIPTION

[0027] The exemplary embodiments will be described in detail herein with reference to the attached drawings. The same or similar components are denoted by the same reference numerals throughout the several views, unless otherwise indicated. The embodiments described in the following exemplary embodiments are not intended to represent all embodiments consistent with the present application. Instead, they are merely examples of apparatus and methods consistent with some aspects of the present application as detailed in the appended claims.

[0028] The terms "comprise" and "have" in the present application are used to represent an open-ended inclusion, and refer to the presence of additional elements / components / etc. in addition to the listed elements / components / etc.; the terms "first" and "second" are used only as labels or for distinguishing between the objects, and are not intended to represent the order or the number of the objects. In addition, the different elements and regions in the figures are only schematically shown, and thus are not limited to the size or distance shown in the figures. The technical solutions will be described in detail below with specific embodiments. The following specific embodiments can be combined with each other, and the same or similar concepts or processes can not be described again in some embodiments. The embodiments of the present application will be described below with reference to the drawings.

[0029] With the development of computer technology, the improvement of chip design level and the demand and promotion of application, the computer host framework developed by Python covers four connection modes of UART (universal asynchronous receiver / transmitter), SPI (synchronous serial bus), I2C (integrated circuit bus) and chip JTAG debugging and custom communication protocol, and tests and verifies the chip under test in the form of transparent instruction. At the same time, the programmable test equipment is automatically controlled by using program control, and the real-time data monitoring and collection of the chip are realized by combining the transparent instruction and the data collection algorithm. The chip verification system includes four main parts of computer, DUT, programmable test instrument and JTAG debugging channel. The computer is mainly used for overall process control and function integration, and sends test and program control instructions to the DUT and the programmable test instrument through the serial port and the program control interface, and receives test results and feedback information; the DUT and the chip under test are mainly used to receive instructions or feedback results through UART (universal asynchronous receiver / transmitter), SPI (synchronous serial bus) and I2C (integrated circuit bus) three connection modes; the programmable test instrument mainly receives control instructions from the computer through the program control interface, and is used for test data collection and excitation condition input of the chip under test; the JTAG debugging channel is mainly used for the computer to directly operate the chip under test at the register level through the JTAG interface, to test the basic functions of the chip from the bottom, and to return the debugging results to the computer through the JTAG interface.

[0030] However, the chip verification system mentioned above is generally compatible with only one or two devices, and its function is also limited by the instrument dynamic library function, which can only verify the function of a single module. When multiple modules in the chip need to be combined for verification, it is difficult to meet the expansion of custom functions, and the development cycle of adding new devices later is long and difficult to achieve in a short period. Therefore, the current verification scheme mainly collects test results, relies on programmable test instruments, establishes a real-time observation system externally, and does not have a reliable comparison system to compare the output picture or check code with the standard result of the algorithm. At the same time, the scalability is not high, and if new test content is added, the entire test framework needs to be modified. In the prior art, there is no system for combined testing of multiple modules, but a verification platform is embodied, and the function of a single module is tested, only the function of the verification platform is embodied, and the detailed process of multiple module function verification of the intermediate chip is not disclosed.

[0031] The technical content provided in the application aims to solve the above technical problems in the related art. In the embodiments of the application, the chip verification system includes a verification device and a chip to be tested, and the verification device includes a test component, a verification model, and a verification file. The test component finds a reference test case corresponding to a to-be-tested module and a to-be-input picture according to an identifier of the to-be-tested module input by a user. Based on a dependency relationship of the to-be-tested module in the verification file, the test component finds a dependent module corresponding to the to-be-tested module and obtains an associated test case corresponding to the dependent module, and sequentially splices the reference test case and the associated test case to obtain a first module linked list. Based on the dependency relationship of the to-be-tested module in the verification file, the test component finds target test cases corresponding to all modules of the chip to be tested except the to-be-tested module and the associated module, and sequentially splices the reference test case, the associated test case, and the target test cases to obtain a second module linked list. The first module linked list and the to-be-input picture are input into the verification model to obtain a first result, the second module linked list and the to-be-input picture are input into the chip to be tested to obtain a second result, and the first result and the second result are compared to obtain a verification result. The scheme of the application provides a combined module test verification logic, the test case of the to-be-tested module and the to-be-input picture are found first, the modules having the dependency relationship are matched through the verification file, the test cases corresponding to the dependent modules and other modules are found, the test cases are spliced respectively, different module linked lists are established for the verification model and the chip to be tested, chip verification is implemented, the method is flexible, and has high expansibility. Meanwhile, when the verification fails, a test report can also be output, the error cause can be positioned and analyzed in a timely manner, the positioning problem can be reproduced, and the verification is more accurate and reliable.

[0032] Some aspects of the examples of the application relate to the above considerations. The following describes the scheme by way of examples in combination with some examples.

[0033] Embodiment one

[0034] Figure 1 An example of the chip verification system provided in the embodiment one of the application is exemplarily shown in FIG. 1. As shown in FIG. 1, the system includes a verification device 11 and a chip to be tested 12, and the verification device 11 includes a test component 111, a verification model 112, and a verification file 113. Figure 1

[0035] According to the identifier of the to-be-tested module input by the user, the reference test case is obtained from the test case set corresponding to the to-be-tested module, and the to-be-input picture is obtained, the parameter value of the image parameter of the to-be-input picture being the same as the parameter value of the image parameter in the reference test case; and according to the dependency relationship of the to-be-tested module in the verification file 113, the associated module having the dependency relationship with the to-be-tested module is determined.

[0036] ​obtaining the associated test case from the test case set corresponding to the associated module, and based on the dependency relationship of the to-be-tested module, sequentially splicing the reference test case and the associated test case to obtain a first test chain table;

[0037] In addition, based on the dependency relationship of the to-be-tested module, obtaining a target test case from the test case set corresponding to all modules of the to-be-tested chip except the to-be-tested module and the associated module, and sequentially splicing the reference test case, the associated test case and the target test case to obtain a second test chain table; the parameter values of the image parameters in the reference test case, the associated test case and the target test case are the same;

[0038] inputting the to-be-input picture and the first test chain table into the verification model 112 to obtain a first result output by the verification model 112; and inputting the to-be-input picture and the second test chain table into the to-be-tested chip 12 to obtain a second result output by the to-be-tested chip 12, and comparing the first result and the second result to obtain a verification result.

[0039] In practical applications, there are various implementation manners of the chip verification system, for example, the chip verification system can be implemented through a computer program, for example, application software, etc.; or the chip verification system can also be implemented as a medium storing a related computer program, for example, a U disk, a cloud disk, etc.; or the chip verification system can also be implemented through an entity device integrated or installed with a related computer program.

[0040] Specifically, the chip verification system in the present example is to perform function verification on the combined modules in the chip. The function verification is to ensure the correctness of the chip design function, and the combined module is a module with a dependency relationship. The combined function verification is performed on the module A, the module B and the module C, wherein the module C depends on the module B, the module B depends on the module A, the verification of the module B depends on the function opening of the module A, and the verification of the module C depends on the function opening of the module B.

[0041] The chip verification system includes a verification device and a to-be-tested chip, and the to-be-tested chip is selected as an RTL hardware simulating the chip. The to-be-tested chip is connected with a computer host through a debugging tool, for example, Figure 2RTL (Register-Transfer Level) is an abstract model of synchronous digital circuits, which is determined according to the flow of digital signals between logical units such as hardware registers, memories, combinational logic devices and buses, and the logic algebraic operation mode thereof. The verification device includes a test component, a verification model and a verification file. The verification model selects a C Model model, which is a model written in C language to realize the function of a certain module and runs in a computer host. It is mainly an executable program provided by an algorithm team. The verification file is a json file, which is a lightweight data exchange format, uses a text format completely independent of programming languages to store and represent data, is easy for technical personnel to read and write, is also easy for machines to parse and generate, and effectively improves network transmission efficiency. The function of the RTL hardware design is checked to see whether the result of the RTL hardware output is consistent with the result of the verification model output. If they are consistent, it means that the verification is successful; if they are not consistent, it means that the verification fails.

[0042] In the present example, the test component obtains a reference test case and a to-be-input picture from the test case set corresponding to the to-be-tested module according to the identification of the to-be-tested module input by the user. The parameter value of the image parameter of the to-be-input picture is the same as that in the reference test case. The image parameters include but are not limited to size, bit width, format, exposure parameter, etc. The parameter value of the image parameter is the value under each parameter item. The size is taken as the first matching item to ensure that the image size meets the requirements; the bit width is taken as the second matching item to ensure the data bit width; the format is taken as the third matching item to ensure the image format; and the exposure parameter is taken as the fourth matching item to ensure the data source quantity. The identification of the to-be-tested module can be A, B and C corresponding to modules A, B and C, or 1, 2 and 3 corresponding to modules A, B and C, or other identifications, which are not limited herein, as long as one identification corresponds to one module. Each module corresponds to a test case set, and the test case sets corresponding to different modules are different, but each test case set includes image parameters.

[0043] In one example, the test case set corresponding to each module includes a general parameter list and a register parameter list; wherein the general parameter list is used to store image parameters and activation parameters of each test case in the test case set; and the register parameter list is used to store register parameters of each test case in the test case set; wherein the activation parameters in different states represent whether the corresponding module needs to be skipped for running. Specifically, the test case set corresponding to each module includes two parts, which are the general parameter list and the register parameter list. The general parameter list stores image parameters and activation parameters of each test case in the test case set. The image parameters include but are not limited to size, bit width, format, exposure parameter, etc. The activation parameters in different states represent whether the corresponding module needs to be skipped for running. The register parameter list stores register parameters of each test case in the test case set. It should be noted that the test case set corresponding to each module can be presented in the form of a table, or in other forms, which are not limited here. As shown in the following table, Table 1 is an example of a test case set of a certain module.

[0044] Table 1

[0045]

[0046]

[0047] In actual application, in order to effectively manage and use the test case set and the to-be-input picture, the test case set and the to-be-input picture are usually stored uniformly. For example, they are stored in a database. The test case set and the to-be-input picture are placed in different folders in the database and stored on a computer host. When actual operation is needed, these test case sets and to-be-input pictures can be obtained directly from the database. It should be noted that the above is only an example, and other ways of obtaining the test case set and the to-be-input picture are not excluded. The test component determines that the to-be-tested module is module C according to the identification C of the to-be-tested module input by the user, finds the test case set corresponding to module C in the folder of the test case set in the database, selects a test case in the test case set as a reference test case, and finds a picture with the same size, bit width, format, and exposure parameter value as the reference test case in the folder of the to-be-input picture in the database according to the size, bit width, format, and exposure parameter value in the reference test case, as the to-be-input picture.

[0048] Specifically, the verification file stores a piece of data corresponding to each module, and each piece of data includes 11 pieces of information, namely, target test module name, storage location of target module executable file, storage location of target module parameter file, storage location of target module input picture, storage location of target module output picture, storage location of target module other output file, target module other file, target module dependency 0, target module dependency 1, target module dependency N, and storage location of the verification file. According to the dependency relationship of the test module in the verification file, the associated modules having a dependency relationship with the test module are determined. The test module is module C, and according to the corresponding data of module C in the json file, it is known that the associated modules having a dependency relationship with module C are module B and module A. After the associated modules are found, the test cases corresponding to the associated modules are obtained from the test case set corresponding to the associated modules as the associated test cases, wherein the values of the size, bit width, format, and exposure parameter in the associated test cases are the same as the values of the size, bit width, format, and exposure parameter in the reference test cases. Based on the dependency relationship of the test module, the reference test cases and the associated test cases are sequentially spliced to obtain a first test chain table. The test module is module C, and the modules having a dependency relationship with module C are module B and module A, so the associated test cases corresponding to module A and the associated test cases corresponding to module B and the reference test cases corresponding to module C are sequentially spliced in the order of A-B-C to obtain a first module chain table. Still based on the dependency relationship of the test module, the test cases corresponding to all the modules except the test module and the associated modules in the test chip are obtained from the test case set corresponding to all the modules except the test module and the associated modules as target test cases, wherein the values of the size, bit width, format, and exposure parameter in the target test cases are the same as the values of the size, bit width, format, and exposure parameter in the reference test cases. The reference test cases, the associated test cases, and the target test cases are sequentially spliced to obtain a second test chain table. The test cases corresponding to modules D and E except the test module C and the associated modules A and B in the test chip are found as target test cases, and the reference test cases, the associated test cases, and the target test cases are spliced in the order of A-D-B-E-C to obtain a second test chain table.

[0049] Correspondingly, the obtained to-be-input picture and the first test chain table are input into the verification model to obtain a first result output by the verification model, the obtained to-be-input picture and the second test chain table are input into the test chip to obtain a second result output by the test chip, and the first result and the second result are compared to obtain a verification result.

[0050] In the foregoing example, a combination module test verification logic is provided, test cases of a to-be-tested module and input pictures are found first, modules with matching dependencies in a verification file are matched, and test cases corresponding to the dependent modules and other modules are found, the test cases are spliced respectively, different module linked lists of the verification model and the to-be-tested chip are established, chip verification is realized, and the method is flexible and has high expansibility.

[0051] On the basis of the foregoing example, when the test component sequentially splices the reference test case and the associated test case to obtain the first test linked list based on the dependency relationship of the to-be-tested module, the following is specifically used:

[0052] Based on the dependency relationship of the to-be-tested module, a first running order of the to-be-tested module and the associated module is determined.

[0053] According to the first running order, an input field content in a test case of a first module in the to-be-tested module and the associated module is configured as an access path of the input picture, and for each of other modules in the to-be-tested module and the associated module, an input field content in a test case of the module is configured as an output field content in a test case of a previous module until the input field in the reference test case is configured, and the first test linked list is obtained.

[0054] When the test component sequentially splices the reference test case, the associated test case, and the target test case to obtain the second test linked list, the following is specifically used:

[0055] Based on the dependency relationship of the to-be-tested module, a second running order of all modules including the to-be-tested module in the to-be-tested chip is determined.

[0056] According to the second running order, an input field content in a test case of a first module of the to-be-tested chip is configured as an access path of the input picture, and for each of other modules of the to-be-tested chip, an input field content in a test case of the module is configured as an output field content in a test case of a previous module until an input field in the reference test case is configured, and the second test linked list is obtained.

[0057] In the example, when the test component sequentially splices the reference test case and the associated test case to obtain the first test chain table, first, based on the dependency relationship of the to-be-tested module in the verification file, a first running order of the to-be-tested module and the associated module is determined, wherein the to-be-tested module is the last module in the first running order. Then, the input field content in the test case of the first module in the first running order is configured as the access path of the to-be-input picture, and the input field content in the test case of the other modules is sequentially configured as the output field content in the test case of the previous module according to the first running order, until the input field in the reference test case is configured, to obtain the first test chain table. The to-be-tested module is module C, the associated module is module B and module A, the first running order A-B-C is determined, the input field content in the test case corresponding to module A is configured as the access path of the to-be-input picture, the input field content in the test case corresponding to module B is configured as the output field content in the test case corresponding to module A, and the input field content in the test case corresponding to module C is configured as the output field content in the test case corresponding to module B, to obtain the first test chain table.

[0058] Correspondingly, when the test component sequentially splices the reference test case, the associated test case and the target test case to obtain the second test chain table, first, based on the dependency relationship of the to-be-tested module in the verification file, a second running order of all modules including the to-be-tested module in the to-be-tested chip is determined, wherein the to-be-tested module is the last module in the second running order. Then, the input field content in the test case of the first module in the second running order is configured as the access path of the to-be-input picture, and the input field content in the test case of the other modules is sequentially configured as the output field content in the test case of the previous module according to the second running order, until the input field in the reference test case is configured, to obtain the second test chain table. The to-be-tested module is module C, the associated module is module B and module A, the other modules are module D and module E, the second running order A-D-B-E-C is determined, the input field content in the test case corresponding to module A is configured as the access path of the to-be-input picture, the input field content in the test case corresponding to module D is configured as the output field content in the test case corresponding to module A, the input field content in the test case corresponding to module B is configured as the output field content in the test case corresponding to module D, the input field content in the test case corresponding to module E is configured as the output field content in the test case corresponding to module B, and the input field content in the test case corresponding to module C is configured as the output field content in the test case corresponding to module E, to obtain the second test chain table. In the above example, the test cases are spliced respectively, different module chain tables of the verification model and the to-be-tested chip are established, chip verification is implemented, and the method is flexible and has high expansibility.

[0059] In one example, when the test component obtains the associated test case from the test case set corresponding to the associated module, specifically for:

[0060] From the test case set corresponding to each associated module, a test case with the same parameter value of the image parameter in the reference test case is randomly selected as the associated test case of the associated module.

[0061] When the test component obtains the target test case from the test case set corresponding to all modules of the test chip except the test module and the associated module based on the dependency relationship of the test module, specifically for:

[0062] For each module in the test chip except the test module and the associated module, a test case with the same parameter value of the image parameter in the reference test case and the activation parameter in the inactive state is selected from the test case set corresponding to the module as the target test case of the module.

[0063] In this example, when the test component obtains the associated test case from the test case set corresponding to the associated module, in the test case set corresponding to the associated module, a test case with the same parameter value of the image parameter in the reference test case corresponding to the test module is randomly selected, that is, a test case with the same parameter value of the size, bit width, format, and exposure parameter in the reference test case as the associated test case of the associated module. In the test case set corresponding to all modules of the test chip except the test module and the associated module, a test case with the same parameter value of the image parameter in the reference test case corresponding to the test module is selected, that is, a test case with the same parameter value of the size, bit width, format, and exposure parameter in the reference test case and the activation parameter in the inactive state as the target test case of the module. Through the scheme of this example, chip verification can be realized, the method is flexible, and has high expansibility.

[0064] On the basis of the foregoing examples, the verification model is configured to determine the corresponding module in the verification model according to the received first test chain table; and run the module corresponding to each test case in the first test chain table in the verification model according to the first running order to obtain a first result.

[0065] The test chip is configured to run the test module and the associated module of the test chip according to each test case in the received second test chain table according to the second running order, and skip the modules in the test chip except the test module and the associated module to obtain a second result; wherein the activation parameter in the test case of the test module and the associated module in the second test chain table is in the active state, and the activation parameter in the test case of other modules is in the inactive state.

[0066] Specifically, the verification model determines the corresponding modules in the verification model according to the received first test chain table, and runs the modules corresponding to the test cases in the verification model in the first running order to obtain the first result. The verification model determines the corresponding modules in the verification model as module A, module B and module C according to the received first test chain table, and the first order is A-B-C, so the modules A, B and C in the verification model are run in turn to obtain the first result. Since the module positions in the to-be-tested chip are fixed, when running in the second running order, the to-be-tested module and the associated module are selected to run, and other modules except the to-be-tested module and the associated module are selected to skip, to obtain the second result. The activation parameters in the test cases of the to-be-tested module and the associated module in the second test chain table are in the activated state, and the activation parameters in the test cases of other modules are in the non-activated state. In an example, the activation parameters include a skip parameter and an enable parameter; wherein the activation parameters in the activated state include the skip parameter being a non-activated value and the enable parameter being an activated value; the activation parameters in the non-activated state include the skip parameter being an activated value, and the skip parameter being a non-activated value and the enable parameter being a non-activated value. Wherein the skip parameter is a bypass parameter, the enable parameter is an enable parameter, the non-activated value is 0, and the activated value is 1. When the bypass parameter is 0 and the enable parameter is 1, it is in the activated state; when the bypass parameter is 1 and the bypass parameter is 0 and the enable parameter is 0, it is in the non-activated state. The second running order is A-D-B-E-C, the to-be-tested module is module C, the associated module is module A and module B, and the other modules are module D and module E, so A enable-D bypass-B enable-E bypass-C enable, that is, module A is run, module D is skipped, module B is run, module E is skipped, and finally module C is run, to obtain the second result. Through the scheme of the example, the function verification of the chip module is more sufficient, and the obtained result is more accurate.

[0067] In an example, the test component is further configured to: perform format conversion on the to-be-input picture to obtain a converted to-be-input picture before inputting the to-be-input picture and the second test chain table into the to-be-tested chip; and perform format conversion on the second result to obtain a converted second result before comparing the first result and the second result.

[0068] Specifically, the format of the image to be input is jpeg format or raw format, and the verification model can directly read files in jpeg format or raw format, that is, the image to be input can be directly input into the verification model, but the chip to be tested can generally only read binary files. Therefore, before inputting the image to be input into the chip to be tested, the image to be input must be converted into a binary file, and the converted image to be input must be input into the chip to be tested, thereby ensuring that the content input into the verification model and the chip to be tested is consistent. Correspondingly, the format of the first result output by the verification model is txt format, and the format of the second result output by the chip to be tested is a binary file. In order to be able to compare the first result and the second result, it is necessary to convert the second result into a txt format file to obtain the converted second result, so as to compare the first result and the second result. Through the solution of this example, the result of chip verification is more accurate and reliable.

[0069] In one example, when the test component compares the first result and the second result to obtain a verification result, it is specifically used to: select the results of the pixel points at the same position in the first result and the converted second result for comparison; if the results of each pixel point at the same position in the first result and the converted second result are consistent, then the first result and the second result are determined to be consistent; otherwise, the first result and the second result are determined to be inconsistent.

[0070] Specifically, select several identical positions from the first result in txt format and the second result after conversion in txt format, and compare the results of the pixels at the identical positions. If the results of each pixel at the identical position are identical, the first result and the second result are determined to be identical, and the obtained verification result is verification passed; otherwise, the first result and the second result are determined to be inconsistent, and the obtained verification result is verification failed. Figure 3 As shown, pixels 1, 2, 3, and 4 are selected from the first result and the converted second result. The value of pixel 1 in the first result is 255, and the value in the converted second result is 255, indicating that the values ​​of pixel 1 in the first and second results are consistent. The value of pixel 2 in the first result is 254, and the value in the converted second result is 253, indicating that the values ​​of pixel 2 in the first and second results are inconsistent. Therefore, the verification result obtained is verification failure. Through the solution of this example, the chip verification results are more accurate and reliable.

[0071] Correspondingly, the first result and the second result can also be compared using the following scheme. In another example, the test component is further configured to perform a cyclic redundancy check calculation on the first result to obtain a cyclic redundancy check value of the first result; the chip under test is further configured to output a cyclic redundancy check value of the second result according to the second result; and when the test component compares the first result and the second result to obtain a verification result, the test component is specifically configured to: if the cyclic redundancy check value of the first result is the same as the cyclic redundancy check value of the second result, it is determined that the first result and the second result are consistent; otherwise, it is determined that the first result and the second result are inconsistent.

[0072] Specifically, different pixel points are selected in the first result, and a cyclic redundancy check calculation is performed on the value of each pixel point in the first result to obtain a cyclic redundancy check value of the first result. The chip under test provides a cyclic redundancy register, which can output a cyclic redundancy check value of the second result according to the second result. The cyclic redundancy check value of the first result and the cyclic redundancy check value of the second result are compared. If they are the same, it is determined that the first result and the second result are consistent; otherwise, it is determined that the first result and the second result are inconsistent. Figure 4 A cyclic redundancy check comparison diagram is shown. The specific method of performing a cyclic redundancy check calculation is the same as that of the prior art, and will not be described in detail here. Through the scheme of the present example, the first result and the second result can be quickly compared, the verification efficiency is improved, and the verification time is saved.

[0073] On the basis of any of the preceding examples, the test component is further configured to: when the verification fails, output a test report, the test report including a comparison record of the first result and the second result and a running state and related data of each test case used for verification.

[0074] Specifically, when the verification fails, the test component outputs a test report. By checking the test report, the output comparison results of each test case are recorded, the test case with inconsistent data can be accurately located, and then the configuration parameters and input sources of the verification model and the chip under test are found, respectively, and the log files and register information of each are found, and the causes of errors are analyzed. The CMM script of the debugging tool generated for the chip under test supports single-step execution, saves register information and input and output data, and can reproduce and locate problems. The log and bat scripts generated for the verification model can record the running state and input and output data of each test case. Through the scheme of the present example, problems existing in the verification process can be found in time, and the entire chip verification process can be improved.

[0075] The chip verification system provided by the embodiment comprises a verification device and a chip to be tested, the verification device comprises a test component, a verification model and a verification file; the test component finds a reference test case corresponding to the module to be tested and a picture to be input according to an identifier of the module to be tested input by a user; based on a dependency relationship of the module to be tested in the verification file, the test component finds a dependent module corresponding to the module to be tested and obtains an associated test case corresponding to the dependent module, and sequentially splices the reference test case and the associated test case to obtain a first module linked list; based on the dependency relationship of the module to be tested in the verification file, the test component finds target test cases corresponding to all modules of the chip to be tested except the module to be tested and the associated module, and sequentially splices the reference test case, the associated test case and the target test cases to obtain a second module linked list; the test component inputs the first module linked list and the picture to be input into the verification model to obtain a first result, inputs the second module linked list and the picture to be input into the chip to be tested to obtain a second result, and compares the first result and the second result to obtain a verification result. The scheme of the application provides a combined module test verification logic, the test case of the module to be tested and the picture to be input are found first, the modules having the dependency relationship are matched through the verification file, the test cases corresponding to the dependent module and other modules are found, the test cases are spliced respectively, different module linked lists are established for the verification model and the chip to be tested, chip verification is realized, the method is flexible and has high expansibility. Meanwhile, when the verification fails, a test report can be output, error causes can be positioned and analyzed in time, problems can be reproduced and positioned, and the verification is more accurate and reliable.

[0076] Embodiment two

[0077] Figure 5 The flowchart of the verification method based on the chip verification system provided by the embodiment two of the application is exemplarily shown, the execution subject of the example can be a chip verification system, the chip verification system comprises a verification device and a chip to be tested, the verification device comprises a test component, a verification model and a verification file, as shown in Figure 5 The method comprises the following steps.

[0078] In step 101, the test component obtains a reference test case and a picture to be input from a test case set corresponding to the module to be tested according to an identifier of the module to be tested input by a user, and determines an associated module having a dependency relationship with the module to be tested according to a dependency relationship of the module to be tested in the verification file.

[0079] In step 102, the test component obtains an associated test case from a test case set corresponding to the associated module, and sequentially splices the reference test case and the associated test case based on the dependency relationship of the module to be tested to obtain a first test linked list.

[0080] Step 103, based on the dependency relationship of the to-be-tested module, obtaining a target test case from a test case set corresponding to all modules of the to-be-tested chip except the to-be-tested module and the associated module, and sequentially splicing the reference test case, the associated test case and the target test case to obtain a second test chain table;

[0081] Step 104, the test component obtains the to-be-input picture, inputs the to-be-input picture and the first test chain table into the verification model, and obtains a first result output by the verification model;

[0082] Step 105, the test component inputs the to-be-input picture and the second test chain table into the to-be-tested chip, and obtains a second result output by the to-be-tested chip;

[0083] Step 106, comparing the first result and the second result to obtain a verification result.

[0084] In actual application, the execution subject of the method can be a chip verification system, and the implementation manner is various, for example, the chip verification system can be realized through a computer program, for example, application software, etc.; or, the chip verification system can also be realized as a medium storing a related computer program, for example, a U disk, a cloud disk, etc.; or, the chip verification system can also be realized through an entity device integrated or installed with a related computer program.

[0085] Specifically, the chip verification system in the example is to perform function verification on a combined module in a chip. The function verification is to ensure the correctness of the chip design function, and the combined module is a module with a dependency relationship, for example, performing combined function verification on a module A, a module B and a module C, wherein the module C depends on the module B, the module B depends on the module A, the verification of the module B depends on the function opening of the module A, and the verification of the module C depends on the function opening of the module B.

[0086] The chip verification system includes a verification device and a to-be-tested chip, and the to-be-tested chip selects an RTL hardware simulating the chip. The to-be-tested chip is connected with a computer host through a debugging tool, for example, a JTAG (Joint Test Action Group) debugging tool. Figure 2As shown. RTL (Register-Transfer Level) is an abstract model of synchronous digital circuits. This model is determined by the flow of digital signals between logic units such as hardware registers, memories, combinational logic devices, and buses, as well as their logical algebraic operation. Verification equipment includes test components, verification models, and verification files. The verification model uses the C Model model. The C Model model is a model written in C language that implements specific module functions and runs on a host computer. It is primarily an executable program provided by the algorithm team. The verification file is a JSON file, a lightweight data exchange format that uses a text format that is completely independent of the programming language to store and represent data. It is easy for technicians to read and write, as well as easy for machines to parse and generate, and effectively improves network transmission efficiency. The RTL hardware design is checked for functional correctness, that is, whether the results output by the RTL hardware are consistent with those output by the verification model. If they are consistent, verification is successful; if not, verification fails.

[0087] In this example, the test component obtains a reference test case and an input image from the test case set corresponding to the module under test based on the user-entered identifier of the module under test. The parameter values ​​of the image parameters of the input image are identical to those in the reference test case. Image parameters include, but are not limited to, size, bit width, format, and exposure parameters, and the values ​​of the image parameters are taken under each parameter item. For example, size is used as the first matching item to ensure that the image size meets the requirements; bit width is used as the second matching item to ensure the data bit width; format is used as the third matching item to ensure the image format; and exposure parameters are used as the fourth matching item to ensure the number of data sources. The identifier of the module under test can be A, B, or C, corresponding to modules A, B, and C; 1, 2, or 3, corresponding to modules A, B, and C; or other identifiers. This is not limited here; only one identifier is required for each module. Each module corresponds to a test case set. Different modules correspond to different test case sets, but each test case set includes image parameters.

[0088] In one example, the test case set corresponding to each module includes a general parameter list and a register parameter list; wherein the general parameter list is used to store image parameters and activation parameters of each test case in the test case set; the register parameter list is used to store register parameters of each test case in the test case set; wherein the activation parameters in different states represent whether the corresponding module needs to be skipped for running. Specifically, the test case set corresponding to each module includes two parts, which are the general parameter list and the register parameter list, wherein the general parameter list stores the image parameters and the activation parameters of each test case in the test case set, the image parameters include but are not limited to size, bit width, format, exposure parameter, etc., and the activation parameters in different states represent whether the corresponding module needs to be skipped for running. The register parameter list stores the register parameters of each test case in the test case set. It should be noted that the test case set corresponding to each module can be presented in the form of a table, or in other forms, which are not limited here.

[0089] In actual application, in order to effectively manage and use the test case set and the to-be-input picture, the test case set and the to-be-input picture are usually stored uniformly. For example, stored in a database. The test case set and the to-be-input picture are placed in different folders in the database and stored on a computer host. When actual operation is needed, these test case sets and to-be-input pictures can be obtained directly from the database. It should be noted that the above is only an example, and other ways of obtaining the test case set and the to-be-input picture are not excluded. For example, the test component determines that the to-be-tested module is module C according to the identification C of the to-be-tested module input by the user, finds the test case set corresponding to module C in the folder of the test case set in the database, selects a test case in the test case set as a reference test case, and finds a picture with the same size, bit width, format, and exposure parameter value as the reference test case in the folder of the to-be-input picture in the database according to the size, bit width, format, and exposure parameter value in the reference test case, as the to-be-input picture.

[0090] Specifically, the verification file stores a piece of data corresponding to each module, and each piece of data includes 11 pieces of information, namely, target test module name, storage location of target module executable file, storage location of target module parameter file, storage location of target module input picture, storage location of target module output picture, storage location of other output files of target module, other files of target module, dependency 0 of target module, dependency 1 of target module, dependency N of target module, and storage location of verification file. According to the dependency relationship of the to-be-tested module in the verification file, the associated modules having a dependency relationship with the to-be-tested module are determined. For example, the to-be-tested module is module C, and according to the data corresponding to module C in the json file, it is known that the associated modules having a dependency relationship with module C are module B and module A. After the associated modules are found, the test cases corresponding to the associated modules are obtained from the test case set corresponding to the associated modules as the associated test cases, wherein the values of the size, bit width, format, and exposure parameter in the associated test cases are the same as the values of the size, bit width, format, and exposure parameter in the reference test cases. Based on the dependency relationship of the to-be-tested module, the reference test cases and the associated test cases are sequentially spliced to obtain a first test chain table. For example, the to-be-tested module is module C, and the modules having a dependency relationship with module C are module B and module A, so the associated test cases corresponding to module A and the associated test cases corresponding to module B and the reference test cases corresponding to module C are sequentially spliced in the order of A-B-C to obtain a first module chain table. Still based on the dependency relationship of the to-be-tested module, the test cases corresponding to all the modules except the to-be-tested module and the associated modules in the to-be-tested chip are obtained from the test case set corresponding to all the modules except the to-be-tested module and the associated modules as target test cases, wherein the values of the size, bit width, format, and exposure parameter in the target test cases are the same as the values of the size, bit width, format, and exposure parameter in the reference test cases. The reference test cases, the associated test cases, and the target test cases are sequentially spliced to obtain a second test chain table. In combination with the foregoing example, the test cases corresponding to module D and module E except the to-be-tested module C and the associated modules A and B in the to-be-tested chip are found as target test cases, and the reference test cases, the associated test cases, and the target test cases are spliced in the order of A-D-B-E-C to obtain a second test chain table.

[0091] Correspondingly, the obtained to-be-input picture and the first test chain table are input into the verification model to obtain a first result output by the verification model, the obtained to-be-input picture and the second test chain table are input into the to-be-tested chip to obtain a second result output by the to-be-tested chip, and the first result and the second result are compared to obtain a verification result.

[0092] In the foregoing example, a combination module test verification logic is provided, test cases of a to-be-tested module and to-be-input pictures are found first, modules with matched dependencies are found through a verification file, and test cases corresponding to the dependent modules and other modules are found, the test cases are spliced respectively, different module linked lists of a verification model and a to-be-tested chip are established, and chip verification is implemented, the method is flexible and has high expansibility.

[0093] On the basis of the foregoing example, reference test cases and associated test cases are sequentially spliced based on a dependency relationship of a to-be-tested module to obtain a first test linked list, and the first test linked list specifically includes:

[0094] A first running order of the to-be-tested module and associated modules is determined based on a dependency relationship of the to-be-tested module.

[0095] According to the first running order, an input field content in a test case of a first module in the to-be-tested module and the associated modules is configured as an access path of the to-be-input pictures, and input field contents in test cases of other modules in the to-be-tested module and the associated modules are sequentially configured as output field contents in test cases of previous modules until the input field in the reference test case is configured, and the first test linked list is obtained.

[0096] Reference test cases, associated test cases and target test cases are sequentially spliced to obtain a second test linked list, and the second test linked list specifically includes:

[0097] A second running order of all modules including the to-be-tested module in a to-be-tested chip is determined based on a dependency relationship of the to-be-tested module.

[0098] According to the second running order, an input field content in a test case of a first module of the to-be-tested chip is configured as an access path of the to-be-input pictures, and input field contents in test cases of other modules of the to-be-tested chip are sequentially configured as output field contents in test cases of previous modules until the input field in the reference test case is configured, and the second test linked list is obtained.

[0099] In the present example, when the test component sequentially splices the reference test case and the associated test case to obtain the first test chain table, first, based on the dependency relationship of the to-be-tested module in the verification file, the first running order of the to-be-tested module and the associated module is determined, wherein the to-be-tested module is the last module in the first running order. Then, the input field content in the test case of the first module in the first running order is configured as the access path of the to-be-input picture obtained, and the input field content in the test case of the other modules is configured as the output field content in the test case of the previous module in turn according to the first running order, until the input field in the reference test case is configured, to obtain the first test chain table. For example, the to-be-tested module is module C, the associated module is module B and module A, the first running order A-B-C is determined, the input field content in the test case corresponding to module A is configured as the access path of the to-be-input picture, the input field content in the test case corresponding to module B is configured as the output field content in the test case corresponding to module A, and the input field content in the test case corresponding to module C is configured as the output field content in the test case corresponding to module B, to obtain the first test chain table.

[0100] Correspondingly, when the test component sequentially splices the reference test case, the associated test case and the target test case to obtain the second test chain table, first, based on the dependency relationship of the to-be-tested module in the verification file, the second running order of all modules including the to-be-tested module in the to-be-tested chip is determined, wherein the to-be-tested module is the last module in the second running order. Then, the input field content in the test case of the first module in the second running order is configured as the access path of the to-be-input picture obtained, and the input field content in the test case of the other modules is configured as the output field content in the test case of the previous module in turn according to the second running order, until the input field in the reference test case is configured, to obtain the second test chain table. For example, the to-be-tested module is module C, the associated module is module B and module A, the other modules are module D and module E, the second running order A-D-B-E-C is determined, the input field content in the test case corresponding to module A is configured as the access path of the to-be-input picture, the input field content in the test case corresponding to module D is configured as the output field content in the test case corresponding to module A, the input field content in the test case corresponding to module B is configured as the output field content in the test case corresponding to module D, the input field content in the test case corresponding to module E is configured as the output field content in the test case corresponding to module B, and the input field content in the test case corresponding to module C is configured as the output field content in the test case corresponding to module E, to obtain the second test chain table. In the above example, the test cases are spliced respectively to establish different module chain tables for the verification model and the to-be-tested chip, to realize chip verification, and the method is flexible and has high expansibility.

[0101] In one example, the associated test case is obtained from the test case set corresponding to the associated module, specifically including:

[0102] From the test case set corresponding to each associated module, a test case with the same parameter value of the image parameter in the reference test case is randomly selected as the associated test case of the associated module;

[0103] Based on the dependency relationship of the to-be-tested module, target test cases are obtained from the test case set corresponding to all modules of the to-be-tested chip except the to-be-tested module and the associated module, specifically including:

[0104] For each module in the to-be-tested chip except the to-be-tested module and the associated module, a test case with the same parameter value of the image parameter in the reference test case and the activation parameter in the non-activation state is selected from the test case set corresponding to the module as the target test case of the module.

[0105] In the present example, when the test assembly obtains the associated test case from the test case set corresponding to the associated module, in the test case set corresponding to the associated module, a test case with the same parameter value of the image parameter in the reference test case corresponding to the to-be-tested module is randomly selected, that is, a test case with the same parameter value of the size, bit width, format, and exposure parameter in the reference test case as the associated test case of the associated module; in the test case set corresponding to all modules in the to-be-tested chip except the to-be-tested module and the associated module, a test case with the same parameter value of the image parameter in the reference test case corresponding to the to-be-tested module is selected, that is, a test case with the same parameter value of the size, bit width, format, and exposure parameter in the reference test case and the activation parameter in the non-activation state as the target test case of the module. Through the scheme of the present example, chip verification can be realized, the method is flexible, and has high expansibility.

[0106] On the basis of the foregoing example, the method further includes: determining, by the verification model, corresponding modules in the verification model according to the received first test chain table; running, by the verification model, the modules corresponding to each test case in the first test chain table according to the first running order, to obtain a first result;

[0107] The to-be-tested chip runs the to-be-tested module and the associated module according to each test case in the received second test chain table according to the second running order, and skips the modules in the to-be-tested chip except the to-be-tested module and the associated module, to obtain a second result; in the second test chain table, the activation parameter in the test case of the to-be-tested module and the associated module is in the activation state, and the activation parameter in the test case of other modules is in the non-activation state.

[0108] Specifically, the verification model determines the corresponding modules in the verification model according to the received first test chain table, and runs the modules corresponding to the test cases in the verification model according to the first running order to obtain the first result. In combination with the foregoing example, the verification model determines the corresponding modules in the verification model as module A, module B and module C according to the received first test chain table, and the first order is A-B-C, so that module A, module B and module C in the verification model are run in sequence to obtain the first result. Since the module positions in the to-be-tested chip are fixed, when running according to the second running order, the to-be-tested module and the associated module are selected to run, and other modules except the to-be-tested module and the associated module are selected to skip, to obtain the second result. The activation parameters in the test cases of the to-be-tested module and the associated module in the second test chain table are in the activated state, and the activation parameters in the test cases of other modules are in the non-activated state. In an example, the activation parameters include a skip parameter and an enable parameter; wherein the activation parameters in the activated state include the skip parameter being a non-activated value and the enable parameter being an activated value; the activation parameters in the non-activated state include the skip parameter being an activated value, and the skip parameter being a non-activated value and the enable parameter being a non-activated value. The skip parameter is a bypass parameter, the enable parameter is an enable parameter, the non-activated value is 0, and the activated value is 1. When the bypass parameter is 0 and the enable parameter is 1, the activation parameters are in the activated state; when the bypass parameter is 1 and the bypass parameter is 0 and the enable parameter is 0, the activation parameters are in the non-activated state. In combination with the foregoing example, the second running order is A-D-B-E-C, the to-be-tested module is module C, the associated module is module A and module B, and the other modules are module D and module E, so that A enable-Dbypass-B enable-E bypass-C enable, that is, module A is run, module D is skipped, module B is run, module E is skipped, and finally module C is run to obtain the second result. Through the scheme of the example, the function verification of the chip module is more sufficient, and the obtained result is more accurate.

[0109] In an example, the method further comprises: before inputting the to-be-input picture and the second test chain table into the to-be-tested chip, performing format conversion on the to-be-input picture to obtain a converted to-be-input picture; and before comparing the first result and the second result, performing format conversion on the second result to obtain a converted second result.

[0110] Specifically, the format of the image to be input is jpeg format or raw format, and the verification model can directly read files in jpeg format or raw format, that is, the image to be input can be directly input into the verification model, but the chip to be tested can generally only read binary files. Therefore, before inputting the image to be input into the chip to be tested, the image to be input must be converted into a binary file, and the converted image to be input must be input into the chip to be tested, thereby ensuring that the content input into the verification model and the chip to be tested is consistent. Correspondingly, the format of the first result output by the verification model is txt format, and the format of the second result output by the chip to be tested is a binary file. In order to be able to compare the first result and the second result, it is necessary to convert the second result into a txt format file to obtain the converted second result, so as to compare the first result and the second result. Through the solution of this example, the result of chip verification is more accurate and reliable.

[0111] In one example, comparing the first result and the second result to obtain a verification result specifically includes: selecting the results of pixel points at the same position in the first result and the converted second result for comparison; if the results of each pixel point at the same position in the first result and the converted second result are consistent, then the first result and the second result are determined to be consistent; otherwise, the first result and the second result are determined to be inconsistent.

[0112] Specifically, select several identical positions from the first result in txt format and the second result after conversion in txt format, and compare the results of the pixels at the identical positions. If the results of the pixels at each identical position are identical, the first result and the second result are determined to be identical, and the obtained verification result is verification passed; otherwise, the first result and the second result are determined to be inconsistent, and the obtained verification result is verification failed. For example, if Figure 3 As shown, pixels 1, 2, 3, and 4 are selected from the first result and the converted second result. The value of pixel 1 in the first result is 255, and the value in the converted second result is 255, indicating that the values ​​of pixel 1 in the first and second results are consistent. The value of pixel 2 in the first result is 254, and the value in the converted second result is 253, indicating that the values ​​of pixel 2 in the first and second results are inconsistent. Therefore, the verification result obtained is verification failure. Through the solution of this example, the chip verification results are more accurate and reliable.

[0113] Correspondingly, the first result and the second result can also be compared using the following scheme. In another example, the method further includes: performing a cyclic redundancy check calculation on the first result to obtain a cyclic redundancy check value of the first result; outputting a cyclic redundancy check value of the second result according to the second result; and comparing the first result and the second result to obtain a verification result, specifically including: if the cyclic redundancy check value of the first result is the same as the cyclic redundancy check value of the second result, determining that the first result and the second result are consistent; otherwise, determining that the first result and the second result are inconsistent.

[0114] Specifically, different pixel points are selected in the first result, and a cyclic redundancy check calculation is performed on the value of each pixel point in the first result to obtain a cyclic redundancy check value of the first result. The cyclic redundancy register in the chip under test can output a cyclic redundancy check value of the second result according to the second result. The cyclic redundancy check value of the first result and the cyclic redundancy check value of the second result are compared. If they are the same, it is determined that the first result and the second result are consistent. Otherwise, it is determined that the first result and the second result are inconsistent. Figure 4 A cyclic redundancy check comparison diagram is shown. The specific method of performing a cyclic redundancy check calculation is the same as that of the prior art, and will not be described in detail here. Through the scheme of the present example, the first result and the second result can be quickly compared, the verification efficiency is improved, and the verification time is saved.

[0115] On the basis of any of the preceding examples, the method further includes: when the verification fails, outputting a test report, the test report including a comparison record of the first result and the second result and a running state and related data of each test case used for verification.

[0116] Specifically, when the verification fails, the test component outputs a test report. By checking the test report, the output comparison results of each test case are recorded, the test case with inconsistent data can be accurately located, and then the configuration parameters and input sources of the verification model and the chip under test are found, respectively, and the log files and register information of each are found, and the causes of errors are analyzed. The CMM script of the debugging tool generated for the chip under test supports single-step execution, saves register information and input and output data, and can reproduce and locate problems. The log and bat scripts generated for the verification model can record the running state and input and output data of each test case. Through the scheme of the present example, problems existing in the verification process can be found in time, and the entire chip verification process can be improved.

[0117] The verification method based on the chip verification system provided in the embodiment comprises a verification device and a chip to be tested, the verification device comprises a test component, a verification model and a verification file; the test component finds a reference test case corresponding to the to-be-tested module and a to-be-input picture according to an identifier of the to-be-tested module input by a user; based on a dependency relationship of the to-be-tested module in the verification file, a dependent module corresponding to the to-be-tested module is found, and an associated test case corresponding to the dependent module is obtained; the reference test case and the associated test case are sequentially spliced to obtain a first module linked list; based on the dependency relationship of the to-be-tested module in the verification file, target test cases corresponding to all modules of the chip to be tested except the to-be-tested module and the associated module are found; the reference test case, the associated test case and the target test cases are sequentially spliced to obtain a second module linked list; the first module linked list and the to-be-input picture are input into the verification model to obtain a first result, the second module linked list and the to-be-input picture are input into the chip to be tested to obtain a second result, and the first result and the second result are compared to obtain a verification result. The scheme of the application provides a combined module test verification logic, the test case of the to-be-tested module and the to-be-input picture are found first, the modules having the dependency relationship are matched through the verification file, the test cases corresponding to the dependent module and other modules are found, the test cases are spliced respectively, different module linked lists are established for the verification model and the chip to be tested, the chip verification is implemented, the method is flexible, and has high expansibility. Meanwhile, when the verification fails, a test report can be output, the error cause can be positioned and analyzed in a timely manner, the positioning problem can be reproduced, and the verification is more accurate and reliable.

[0118] Embodiment three

[0119] Figure 6 A structural schematic diagram of an electronic device provided in the embodiment three of the application is shown in FIG. 1, which comprises: Figure 6

[0120] A processor 291, the electronic device further comprises a memory 292; and can further comprise a communication interface 293 and a bus 294. The processor 291, the memory 292 and the communication interface 293 can complete mutual communication through the bus 294. The communication interface 293 can be used for information transmission. The processor 291 can call the logical instructions in the memory 292 to execute the method of the above examples.

[0121] In addition, the logical instructions in the memory 292 described above can be implemented in the form of a software functional unit and sold or used as an independent product, which can be stored in a computer readable storage medium.

[0122] ​The memory 292, as a computer readable storage medium, can be used to store software programs, computer executable programs, such as program instructions / modules corresponding to the method in the embodiments of the present application. The processor 291 performs function application and data processing, that is, implements the method in the method examples described above, by running the software programs, instructions and modules stored in the memory 292.

[0123] The memory 292 can include a program storage area and a data storage area, where the program storage area can store an operating system, at least one application required by a function; the data storage area can store data created according to the use of the terminal device, etc. In addition, the memory 292 can include a high-speed random access memory, and can also include a nonvolatile memory.

[0124] The embodiments of the present application also provide a computer readable storage medium, which stores computer execution instructions, and includes the system in any one of the preceding examples.

[0125] Other embodiments of the present application will be apparent to those skilled in the art from consideration of the specification and practice of the application disclosed herein. The application is intended to cover any variations, uses or adaptations of the application following the general principles thereof and including such departures from the present disclosure as come within known use or custom in the art. The specification and examples are to be regarded as illustrative only, and the true scope and spirit of the application is indicated by the appended claims.

[0126] It should be understood that the application is not limited to the precise construction that has been described above and shown in the accompanying drawings, and that various modifications and changes can be made by those skilled in the art without departing from the scope of the application. The scope of the application is limited only by the appended claims.

Claims

1. A chip verification system, characterized by, The verification device comprises a test component, a verification model and a verification file; the test component is used for: According to the identification of the to-be-tested module input by a user, a reference test case and a to-be-input picture are obtained from a test case set corresponding to the to-be-tested module; and according to a dependency relationship of the to-be-tested module in the verification file, an associated module having a dependency relationship with the to-be-tested module is determined; An associated test case is obtained from a test case set corresponding to the associated module, and the reference test case and the associated test case are sequentially spliced based on the dependency relationship of the to-be-tested module to obtain a first test chain table; And based on the dependency relationship of the to-be-tested module, a target test case is obtained from a test case set corresponding to all modules of the to-be-tested chip except the to-be-tested module and the associated module, and the reference test case, the associated test case and the target test case are sequentially spliced to obtain a second test chain table; The to-be-input picture is obtained, the to-be-input picture and the first test chain table are input into the verification model, and a first result output by the verification model is obtained; And the to-be-input picture and the second test chain table are input into the to-be-tested chip, a second result output by the to-be-tested chip is obtained, and a verification result is obtained by comparing the first result and the second result.

2. The system of claim 1, wherein, When the test component sequentially splices the reference test case and the associated test case based on the dependency relationship of the to-be-tested module to obtain the first test chain table, it is specifically used for: determining a first running order of the to-be-tested module and the associated module based on the dependency relationship of the to-be-tested module; configuring the input field content in the test case of the first module in the to-be-tested module and the associated module as the access path of the to-be-input picture according to the first running order; and for each of the other modules in the to-be-tested module and the associated module, configuring the input field content in the test case of the module as the output field content in the test case of the previous module until the input field configuration in the reference test case is completed, to obtain the first test chain table; wherein the parameter value of the image parameter of the to-be-input picture is the same as the parameter value of the image parameter in the reference test case, the associated test case and the target test case.

3. The system of claim 1, wherein, When the test component sequentially splices the reference test case, the associated test case and the target test case to obtain the second test chain table, it is specifically used for: determining a second running order of all modules including the to-be-tested module in the to-be-tested chip based on the dependency relationship of the to-be-tested module; According to the second operation sequence, for a first module of the to-be-tested chip, content of an input field in a test case of the module is configured as an access path of the to-be-input picture; and for each of other modules of the to-be-tested chip, content of an input field in a test case of the module is configured as content of an output field in a test case of a previous module, until configuration of the input field in the reference test case is completed, to obtain the second test chain table.

4. The system of claim 2, wherein, The test case set corresponding to each module includes a general parameter list and a register parameter list; the general parameter list is used to store image parameters and activation parameters of each test case in the test case set; and the register parameter list is used to store register parameters of each test case in the test case set; and the activation parameters in different states represent whether the corresponding module needs to be skipped.

5. The system of claim 4, wherein, When the test component obtains the associated test case from the test case set corresponding to the associated module, the test component is specifically configured to: randomly select, from the test case set corresponding to each associated module, a test case with the same parameter value of the image parameter in the reference test case as the associated test case of the associated module; When the test component obtains the target test case from the test case set corresponding to each module of the to-be-tested chip except the to-be-tested module and the associated module based on the dependency relationship of the to-be-tested module, the test component is specifically configured to: select, for each module of the to-be-tested chip except the to-be-tested module and the associated module, a test case with the same parameter value of the image parameter in the reference test case and in the non-activation state of the activation parameter from the test case set corresponding to the module as the target test case of the module.

6. The system of claim 5, wherein, The verification model is configured to determine a corresponding module in the verification model according to the received first test chain table, and run the module corresponding to each test case in the first test chain table according to the first operation sequence, to obtain the first result. The to-be-tested chip is configured to run the to-be-tested module and the associated module of the to-be-tested chip according to each test case in the received second test chain table according to the second operation sequence, and skip the modules of the to-be-tested chip except the to-be-tested module and the associated module, to obtain the second result; in the second test chain table, the activation parameters in the test cases of the to-be-tested module and the associated module are in the activation state, and the activation parameters in the test cases of other modules are in the non-activation state.

7. The system of claim 6, wherein, The activation parameters include a skip parameter and an enable parameter; when the activation parameters are in the activation state, the skip parameter is in the non-activation value and the enable parameter is in the activation value; and when the activation parameters are in the non-activation state, the skip parameter is in the activation value, the skip parameter is in the non-activation value, and the enable parameter is in the non-activation value.

8. The system of claim 1, wherein, The test component is further configured to: perform format conversion on the to-be-input picture before inputting the to-be-input picture and the second test chain table into the to-be-tested chip, to obtain a converted to-be-input picture. The second result is format-converted to obtain a converted second result before the first result and the second result are compared.

9. The system of claim 8, wherein, When the test component compares the first result and the second result to obtain a verification result, the test component is specifically configured to: select results of pixel points at the same positions in the first result and the converted second result for comparison; if the results of the pixel points at the same positions in the first result and the converted second result are consistent, determine that the first result and the second result are consistent; otherwise, determine that the first result and the second result are inconsistent.

10. The system of claim 1, wherein, The test component is further configured to perform a cyclic redundancy check calculation on the first result to obtain a cyclic redundancy check value of the first result. The chip under test is further configured to output a cyclic redundancy check value of the second result according to the second result. When the test component compares the first result and the second result to obtain a verification result, the test component is specifically configured to: if the cyclic redundancy check value of the first result is the same as the cyclic redundancy check value of the second result, determine that the first result and the second result are consistent; otherwise, determine that the first result and the second result are inconsistent. The test component is further configured to:

11. The system of any one of claims 1-10, wherein, output a test report when the verification fails, the test report including comparison records of the first result and the second result and running states and related data of each test case used for verification. The chip verification system includes a verification device and a chip under test, the verification device including a test component, a verification model, and a verification file; and the method includes:

12. A verification method of a chip verification system, characterized by, The test component obtains a reference test case and an input picture from a test case set corresponding to a module under test according to an identifier of the module under test input by a user; and determines an associated module having a dependency relationship with the module under test according to a dependency relationship of the module under test in the verification file. The test component obtains an associated test case from a test case set corresponding to the associated module, and sequentially splices the reference test case and the associated test case to obtain a first test linked list based on the dependency relationship of the module under test; and obtains a target test case from test case sets corresponding to all modules of the chip under test except the module under test and the associated module based on the dependency relationship of the module under test, and sequentially splices the reference test case, the associated test case, and the target test case to obtain a second test linked list. The test component inputs the input picture, the first test linked list, and the second test linked list into the verification model and the chip under test respectively to obtain a first result output by the verification model and a second result output by the chip under test, and compares the first result and the second result to obtain a verification result. The system includes:

13. An electronic device, comprising: a processor, a memory in communication connection with the processor, and the system according to any one of claims 1-11. The system includes: a processor, a memory in communication connection with the processor, and the system according to any one of claims 1-11.

14. A computer-readable storage medium, characterized in that, The computer readable storage medium has stored therein computer-executable instructions, comprising the system of any one of claims 1-11.

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