Low dropout regulator

Abstract

A low dropout regulator (LDO) includes a bias circuit including a first transistor, a second transistor, and a bias resistor, where a gate of the second transistor is coupled to a drain of the first transistor, and a difference between gate-source voltages of the first transistor and the second transistor generates a bias current on the bias resistor, the bias circuit is further configured to generate a first bias voltage based on the bias current; the output stage circuit comprises a power transistor and a feedback circuit, and the output voltage of the low dropout regulator is output from the drain electrode of the power transistor; the feedback circuit is coupled between the grid electrode and the drain electrode of the power transistor and is configured to change the grid electrode voltage of the power transistor in the same direction according to the change of the output voltage; and the feedback circuit receives the first bias voltage and generates an output voltage based on the first bias voltage. Therefore, stable power supply voltage can be provided at low cost.

Description

Technical Field

[0001] This disclosure relates to analog circuits, and more particularly to a low dropout voltage regulator. Background Technology

[0002] More and more functions are being integrated into chips, and many of these modules require dedicated low-dropout regulators (LDOs) for power. LDOs are typically used to reduce the external power supply voltage by a certain value and stabilize that reduced voltage as the power supply voltage required by some circuits.

[0003] Traditional LDOs require a bandgap reference circuit to provide a reference voltage, which increases the module area and thus the chip cost. In addition, some LDOs use operational amplifiers to provide bias voltage to generate the corresponding output voltage. During short-term switching of external power supply voltage values, the output voltage may fluctuate drastically, leading to malfunctions in some modules.

[0004] Therefore, an improved LDO circuit design is needed. Summary of the Invention

[0005] One technical problem this disclosure aims to solve is to provide an improved LDO circuit design that can provide a stable supply voltage at a lower cost.

[0006] According to a first aspect of this disclosure, a low-dropout regulator is provided, comprising: a bias circuit including a first transistor, a second transistor, and a bias resistor, wherein the gate of the second transistor is coupled to the drain of the first transistor, and a difference between the gate-source voltages of the first transistor and the second transistor generates a bias current across the bias resistor, and the bias circuit is further configured to generate a first bias voltage based on the bias current; and an output stage circuit including a power transistor and a feedback circuit, wherein an output voltage of the low-dropout regulator is output from the drain of the power transistor; the feedback circuit is coupled between the gate and drain of the power transistor and configured to change the gate voltage of the power transistor in the same direction according to a change in the output voltage; and the feedback circuit receives the first bias voltage and generates the output voltage based on the first bias voltage.

[0007] Optionally, the bias circuit further includes a first current mirror, wherein two branches of the first current mirror are respectively coupled to the first transistor and the second transistor, and the channel type is opposite to that of the transistor in the first current mirror; and the bias resistor is located between the gate or source of the first transistor and the second transistor, such that the voltage across the bias resistor is equal to the difference between the gate-source voltages of the first transistor and the second transistor, and the bias current generated on the bias resistor is the current of one branch of the first current mirror.

[0008] Optionally, the bias circuit further includes: a third transistor, which forms a current mirror with the transistor in the first current mirror to generate a first current proportional to the bias current; and a first clamping module, coupled to the drain of the third transistor and configured to clamp the voltage at the drain of the third transistor to the first bias voltage according to the first current.

[0009] Optionally, the first clamping module includes a fourth transistor, the gate and drain of which are both coupled to the drain of the third transistor, and the source of the fourth transistor is grounded.

[0010] Optionally, the first clamping module includes a first series unit, which includes a plurality of transistors connected in series. The gates of the plurality of transistors in the first series unit are all coupled to the drain of the third transistor. The drain of the first of the plurality of transistors in the first series unit is coupled to the drain of the third transistor. The source of the last of the plurality of transistors in the first series unit is grounded.

[0011] Optionally, the bias circuit further includes a first capacitor coupled between the drain of the third transistor and ground.

[0012] Optionally, the first capacitor is composed of a fifth transistor, the source and drain of which are both grounded and the gate is coupled to the drain of the third transistor.

[0013] Optionally, the bias circuit is configured to provide the gate-source voltage of the first transistor as the first bias voltage to the feedback circuit.

[0014] Optionally, the low-dropout regulator further includes: a startup circuit coupled to the gate of a transistor in the first current mirror, configured to provide a path from the gate of the transistor in the first current mirror to ground when the low-dropout regulator is turned on, such that all transistors in the first current mirror are turned on, and to turn off the path after the bias circuit starts operating.

[0015] Optionally, the startup circuit includes: a sixth transistor, with its drain coupled to the gate of the transistor in the first current mirror and its source coupled to ground; a seventh transistor, with its drain coupled to the gate of the sixth transistor, its source coupled to ground, and its gate coupled to the gate of the first transistor or the second transistor; and an eighth transistor or a second series unit; wherein the source of the eighth transistor is coupled to the input voltage of the low-dropout regulator, the drain of the eighth transistor is coupled to the gate of the sixth transistor, and the gate of the eighth transistor receives an enable signal; or, the second series unit includes a plurality of transistors connected in series, the gates of the plurality of transistors in the second series unit all receive an enable signal, the drain of the first of the plurality of transistors in the second series unit is coupled to the gate of the sixth transistor, and the source of the last of the plurality of transistors in the second series unit is coupled to the input voltage; wherein the enable signal is set to a first level when the low-dropout regulator is turned on, so that the eighth transistor or the plurality of transistors in the second series unit are turned on.

[0016] Optionally, the feedback circuit includes a ninth transistor, which is a PMOS transistor, with its source coupled to the drain of the power transistor and its gate receiving the first bias voltage or a voltage equal to the first bias voltage, such that the output voltage is the sum of the first bias voltage and the source-gate voltage of the ninth transistor, and the change in the output voltage is conducted from the source of the ninth transistor to the drain or gate of the ninth transistor, thereby changing the gate voltage of the power transistor in the same direction.

[0017] Optionally, the feedback circuit and the power transistor constitute an FVF structure.

[0018] Optionally, the gate of the ninth transistor receives the first bias voltage; the feedback circuit further includes: a tenth transistor, which is an NMOS transistor, whose gate receives a second bias voltage, whose source is coupled to the drain of the ninth transistor, and whose drain is coupled to the gate of the power transistor; a first current source coupled between the input voltage of the low-dropout regulator and the gate of the power transistor; and a second current source coupled between the drain of the ninth transistor and ground.

[0019] Optionally, the bias circuit further includes a first current mirror; wherein two branches in the first current mirror are respectively coupled to the first transistor and the second transistor, and the channel type is opposite to that of the transistor in the first current mirror; the bias resistor is located between the gate or source of the first transistor and the second transistor, such that the voltage across the bias resistor is equal to the difference between the gate-source voltages of the first transistor and the second transistor, and the bias current generated on the bias resistor is the current of one branch of the first current mirror; the first current source includes an eleventh transistor as a PMOS transistor, which, together with the transistor in the first current mirror, the first transistor, or the second transistor, forms a current mirror to generate a second current proportional to the bias current; the second current source includes a twelfth transistor as an NMOS transistor or a plurality of NMOS transistors connected in parallel, which, together with the transistor in the first current mirror, the first transistor, or the second transistor, forms a current mirror to generate a third current or a plurality of third currents proportional to the bias current.

[0020] Optionally, the bias circuit further includes: a thirteenth transistor, which forms a current mirror with the transistor in the first current mirror to generate a fourth current proportional to the bias current; and a second clamping module, coupled to the drain of the thirteenth transistor and the gate of the tenth transistor, and configured to clamp the voltage at the drain of the thirteenth transistor to the second bias voltage according to the fourth current.

[0021] Optionally, the second clamping module includes a fourteenth transistor, the gate and drain of which are both coupled to the drain of the thirteenth transistor, and the source of which is grounded.

[0022] Optionally, the second clamping module includes a third series unit, which includes a plurality of transistors connected in series. The gates of the plurality of transistors in the third series unit are all coupled to the drain of the thirteenth transistor. The drain of the first of the plurality of transistors in the third series unit is coupled to the drain of the thirteenth transistor. The source of the last of the plurality of transistors in the third series unit is grounded.

[0023] Optionally, the output stage circuit further includes a second resistor and a second capacitor connected in series between the source and gate of the power transistor, the second resistor and the second capacitor providing a zero point.

[0024] Optionally, the output stage circuit further includes a third capacitor for Miller compensation coupled between the source and drain of the ninth transistor.

[0025] Optionally, the gate of the ninth transistor is coupled to the drain of the ninth transistor; the feedback circuit further includes: an error amplifier, the non-inverting input of which is coupled to the gate of the ninth transistor, the inverting input of which receives the first bias voltage, and the output of which is coupled to the gate of the power transistor; and a third current source coupled between the drain of the ninth transistor and ground.

[0026] Optionally, the error amplifier includes: a first input transistor and a second input transistor, wherein the source of the first input transistor is coupled to the source of the second input transistor, the gate of the first input transistor receives the first bias voltage, and the gate of the second input transistor is coupled to the gate of the ninth transistor; a second current mirror, the reference branch of which is coupled to the drain of the first input transistor; a third current mirror, the reference branch of which is coupled to the drain of the second input transistor; a fourth current mirror, the reference branch of which is coupled to the output branch of the second current mirror, the output branch of which is coupled to the output branch of the third current mirror, and the coupling node of which is the output terminal of the error amplifier; and a tail current source, coupled between the input voltage of the low dropout regulator and the source of the first input transistor, providing a fifth current proportional to the bias current.

[0027] Optionally, the output stage circuit further includes a third resistor and a fourth capacitor connected in series between the gate and drain of the power transistor for Miller compensation.

[0028] Therefore, this disclosure generates a bias voltage using a simpler bias circuit structure and can quickly adjust and stabilize the output voltage using a feedback circuit when the output voltage fluctuates, thereby providing a stable supply voltage at a lower cost. Attached Figure Description

[0029] The above and other objects, features and advantages of this disclosure will become more apparent from the more detailed description of exemplary embodiments thereof taken in conjunction with the accompanying drawings, wherein like reference numerals generally denote like parts.

[0030] Figure 1 A system block diagram of an LDO according to some embodiments of the present disclosure is shown.

[0031] Figure 2a , Figure 2b and Figure 3 Schematic diagrams of the composition of the bias circuit in an LDO according to some embodiments of the present disclosure are shown.

[0032] Figure 4 A schematic diagram of the composition of the bias circuit and the startup circuit in an LDO according to some embodiments of the present disclosure is shown.

[0033] Figures 5 to 7 Schematic diagrams of the output stage circuitry in an LDO according to some embodiments of the present disclosure are shown.

[0034] Figure 8 and Figure 9 Schematic diagrams of LDO circuits according to some embodiments of the present disclosure are shown. Detailed Implementation

[0035] Preferred embodiments of the present disclosure will now be described in more detail with reference to the accompanying drawings. While preferred embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure may be implemented in various forms and should not be limited to the embodiments set forth herein. Rather, these embodiments are provided so that the present disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.

[0036] This disclosure presents a novel LDO circuit structure.

[0037] Figure 1 A system block diagram of an LDO according to some embodiments of the present disclosure is shown.

[0038] like Figure 1 As shown, the LDO 100 includes a bias circuit 110 and an output stage circuit 120. Although not explicitly shown in the figure, it should be understood that the LDO 100 can use the input voltage VIN as the power supply voltage for each circuit within it, and reduce the input power supply voltage VIN by a certain value to generate a stable output voltage VOUT, which can then be used as the power supply voltage required by other circuits.

[0039] The bias circuit 110 generates a bias current across the bias resistor using the difference between the gate-source voltages of the two transistors, and generates a first bias voltage Vb based on this bias current. The output stage circuit 120 receives the first bias voltage Vb and generates an output voltage VOUT based on the first bias voltage Vb. Specifically, as... Figure 2a and Figure 2b As shown, the bias circuit 110 includes a first transistor M1, a second transistor M2, and a bias resistor R1. The gate of the second transistor M2 is coupled to the drain of the first transistor M1, and the difference between the gate-source voltages of the first transistor M1 and the second transistor M2 generates a bias current I1 on the bias resistor R1. The bias circuit 110 also generates a first bias voltage Vb1 based on the bias current I1.

[0040] Therefore, the solution disclosed herein can provide a reliable bias voltage without using a bandgap reference circuit and an operational amplifier. Furthermore, compared to solutions that use a bandgap reference circuit and an operational amplifier, the solution disclosed herein saves circuit area and facilitates low-cost design.

[0041] Furthermore, as mentioned earlier, in conventional LDOs that use operational amplifiers to provide bias voltage, which is then regulated by the feedback loop of the output stage circuit to generate a stable output voltage, when the input voltage VIN (i.e., the power supply voltage) changes rapidly, the voltage at the output of the operational amplifier, which needs to be regulated through the loop containing the operational amplifier, cannot respond quickly enough to the input voltage VIN. This causes drastic fluctuations in the corresponding bias voltage, resulting in drastic fluctuations in the output voltage VOUT, leading to malfunctions in the circuit modules it powers. In contrast, the LDO disclosed in this invention does not require operational amplifiers to provide bias voltage, thus enabling a rapid response to large, short-term changes in the input voltage (i.e., the power supply voltage), keeping the output voltage stable. This reduces the impact of changes in the input power supply voltage on the output voltage, which is particularly advantageous for applications where the input power supply voltage changes frequently.

[0042] In some embodiments, such as the latter Figure 2a , Figure 2b and Figure 3 As will be detailed, the bias circuit 110 may further include a first current mirror (M3, M4), wherein the channel types of the first transistor M1 and the second transistor M2 are opposite to those of transistors M3 and M4 in the first current mirror. The first transistor M1 and the second transistor M2 are respectively coupled to two branches in the first current mirror (M3, M4), and a bias resistor R1 is located between the gates of the first transistor M1 and the second transistor M2. Figure 2a ) or between the source and the pole ( Figure 2b This makes the voltage across the bias resistor R1 equal to the difference between the gate-source voltages of the first transistor M1 and the second transistor M2, and the bias current I1 generated on the bias resistor R1 is the current of one branch of the first current mirror.

[0043] Return to reference Figure 1 The output stage circuit 120 includes a power transistor Mp and a feedback circuit 121.

[0044] The power transistor Mp is a PMOS transistor. Its source is coupled to the input voltage VIN (power supply voltage) of the LDO, and its drain can be connected to an external load, etc. (not shown in the figure). In other words, the output voltage VOUT of the LDO is output from the drain of the power transistor Mp.

[0045] Feedback circuit 121 is coupled between the gate and drain of power transistor Mp and configured to change the gate voltage of power transistor Mp in the same direction according to the change in output voltage VOUT. That is, when the output voltage VOUT fluctuates, for example due to load changes, the gate voltage of power transistor Mp increases as the output voltage VOUT increases and decreases as it decreases; the changes are in the same direction. The change in the gate voltage of power transistor Mp is also conducted in the reverse direction to the drain voltage, i.e., the output voltage VOUT, through the action of power transistor Mp; that is, when its gate voltage increases, its drain voltage, i.e., the output voltage VOUT, decreases, and when its gate voltage decreases, the output voltage VOUT increases. Therefore, feedback circuit 121 and power transistor Mp form a negative feedback loop, which can stabilize the output voltage VOUT at a specific value.

[0046] In some embodiments, such as the latter Figure 5 , Figure 6 and Figure 7 As shown, the feedback circuit 121 may include a ninth transistor as described in the summary section, whose source is coupled to the drain of the power transistor Mp, and whose gate receives a first bias voltage Vb or a voltage equal to the first bias voltage Vb, such that the output voltage VOUT is the sum of the first bias voltage Vb and the source-gate voltage of the ninth transistor (i.e., the voltage difference between the source and the gate, Vsg). In other words, the feedback circuit 121 can further boost the first bias voltage Vb generated by the bias circuit 110 by a voltage Vsg before outputting it as the output voltage, i.e., VOUT = Vb + Vsg. This is advantageous in some applications, for example, allowing for more flexible circuit design to achieve specific output voltage values.

[0047] In addition, the feedback circuit 121 can also conduct the change in output voltage VOUT from the source of the ninth transistor to the drain or gate of the ninth transistor, and correspondingly change the gate voltage of the power transistor Mp in the same direction, thereby forming a negative feedback loop together with the power transistor Mp to keep the output voltage stable.

[0048] In some embodiments, such as the latter Figure 5 As shown, the feedback circuit 121 and the power transistor Mp can form a flipped voltage follower (FVF) structure. Therefore, the LDO of this disclosure can quickly adjust the circuit state using this negative feedback loop when the output voltage fluctuates.

[0049] In some other embodiments, such as the following Figure 6 and Figure 7 As shown, the feedback circuit 121 can be implemented using an error amplifier (EA).

[0050] For example, feedback circuit 121 may include the aforementioned ninth transistor (such as a PMOS transistor), EA, and a third current source. The source of the ninth transistor is coupled to the drain of the power transistor Mp, and its gate is coupled to its drain. The third current source is coupled between the drain of the ninth transistor and ground, and can be used to provide quiescent current for the power transistor Mp and the ninth transistor. The non-inverting input of EA is coupled to the gate of the ninth transistor, the inverting input receives the first bias voltage Vb, and the output is coupled to the gate of the power transistor Mp. Due to the characteristics of EA, the voltage at the gate of the ninth transistor is equal to the first bias voltage Vb, and the fluctuation of the output voltage VOUT is conducted from the source of the ninth transistor to its gate in the same direction, amplified by EA, and output to the gate of the power transistor Mp, thereby changing the output voltage VOUT in the opposite direction. Thus, feedback circuit 121 and power transistor Mp together form a negative feedback loop, keeping the output voltage stable.

[0051] In some embodiments, such as the latter Figure 7 As shown, EA can include two-stage current mirrors.

[0052] For example, an EA includes: a first input transistor and a second input transistor, a second current mirror, a third current mirror, a fourth current mirror, and a tail current source. The source of the first input transistor is coupled to the source of the second input transistor, and the gate of the first input transistor receives a first bias voltage Vb. The gate of the second input transistor is coupled to the gate of a ninth transistor. The reference branch of the second current mirror is coupled to the drain of the first input transistor, the reference branch of the third current mirror is coupled to the drain of the second input transistor, the reference branch of the fourth current mirror is coupled to the output branch of the second current mirror, and the output branch of the fourth current mirror is coupled to the output branch of the third current mirror. The coupling node between these two current mirrors is the output terminal of the EA. The tail current source is coupled between the power supply voltage and the source of the first input transistor to provide current to the EA. For example, the reference branch of each current mirror can be a diode-connected transistor, whose drain current is the current in the reference branch, serving as a reference current. The output branch can be a transistor with a width-to-length ratio proportional to the transistor in the reference branch, used to proportionally replicate the current in the reference branch.

[0053] Additionally, in some cases, the bias circuit 110 may have a degenerate bias point, causing the circuit to stabilize in a turn-off state with zero current. In this case, additional circuitry such as... Figure 1The startup circuit 130 shown can be coupled to one or more nodes inside the bias circuit 110, such as the gate of one of the transistors, and provides a path from the internal node to the power supply voltage VIN or ground GND when the LDO is turned on, thereby changing the voltage at the internal node so that the transistor in the bias circuit 110 turns on. This allows the bias circuit 110 to escape its degenerate bias point and begin normal operation. After the bias circuit 110 starts operating, the startup circuit 130 closes this path to avoid affecting the voltage at the internal node.

[0054] The following will combine Figures 2a to 9 The specific circuit implementation of the LDO, either in whole or in part, is shown to illustrate the principles of this disclosure in more detail. Those skilled in the art will understand that... Figures 2a to 9 The specific implementations of the parts shown are merely exemplary and not restrictive. Those skilled in the art can make various modifications, alterations, or optimizations as needed, guided by the principles of this disclosure. Furthermore, the same reference numerals in the various figures of this disclosure indicate the same devices, but their device parameters, etc., can be changed according to the actual circuit requirements.

[0055] Figure 2a and Figure 2b A schematic diagram of the composition of the bias circuit in an LDO according to some embodiments of the present disclosure is shown.

[0056] like Figure 2a As shown, the bias circuit 210 includes a PMOS current mirror M4 / M3 (which is an example of the first current mirror as described above), NMOS transistors M1 and M2 (which are examples of the first transistor and the second transistor as described above, respectively), and a bias resistor R1.

[0057] In the PMOS current mirror, the width-to-length ratio of transistors M4 and M3 is 1:1. Therefore, during circuit operation, the current in both branches of the current mirror is equal, I1. M4 can be called the reference branch of the current mirror, and M3 is the output branch. NMOS transistors M1 and M2 are coupled to the output and reference branches of the current mirror, respectively. Specifically, the gate of M1 is coupled to the drain of M3, and the drain of M2 is coupled to the drain of M4. Furthermore, the sources of both M1 and M2 are grounded (GND), and the drain of M1 is coupled to the gate of M2. A bias resistor R1 is coupled between the gates of M1 and M2. Therefore, the voltage across the bias resistor R1 is equal to the difference between the gate-source voltages of M1 and M2, and the bias current generated across the bias resistor R1 by this voltage difference is the current I1 in one branch of the current mirror M4 / M3.

[0058] In other words, the bias current I1 generated by the bias circuit 210 is the ratio of the difference between the gate-source voltages (Vgs1-Vgs2) of NMOS transistors M1 and M2 to the resistance value of resistor R1. Furthermore, current I1 is also the drain current of NMOS transistors M1 and M2. Therefore, it can be deduced that:

[0059]

[0060] Where, μ n C represents the electron mobility. ox Let K be the gate oxide capacitance per unit area, and K be the width-to-length ratio of NMOS transistors M2 and M1 as shown in equation (2) below:

[0061]

[0062] It can be seen that the value of the bias current I1 generated by the bias circuit 210 depends only on the parameter values ​​of the components therein, and can be a fixed value, independent of the input voltage and other values.

[0063] In addition, such as Figure 2a As shown, a first bias voltage Vb1 can be derived from the gate of NMOS transistor M1. This first bias voltage Vb1 is equal to the gate-source voltage of M1, and is determined by the drain current of M1, i.e., the bias current I1, and the parameter values ​​of M1. Therefore, it can also be said that the first bias voltage Vb1 is generated based on the bias current I1. Furthermore, it should be understood that, although not shown, a first bias voltage Vb1 can also be derived from the gate of NMOS transistor M2, because the value of the bias current I1 also determines the value of the gate-source voltage of M2. Thus, it can also be said that a stable and reliable bias voltage is obtained based on the bias current I1.

[0064] Figure 2b Implementation examples and Figure 2a Similarly, and Figure 2a The difference lies in that the bias resistor R1 is coupled between the sources of M1 and M2, wherein the source of the first transistor M1 is coupled to ground and one end of the bias resistor R1, the source of the second transistor M2 is coupled to the other end of the bias resistor R1, and the drain of the first transistor M1 is coupled to its gate. Figure 2b In this context, the voltage across the bias resistor R1 is also equal to the difference between the gate-source voltages of M1 and M2, which can be compared with the aforementioned... Figure 2a Similarly, a bias current I1 is obtained. In one embodiment, Figure 2a and Figure 2b The bias circuits 210 and 210' are both configured to provide the gate-source voltage Vb1 of the first transistor M1 as the first bias voltage to the feedback circuit 121.

[0065] In some cases, the gate-source voltage (or gate voltage) of the first transistor M1 is insufficient to meet the requirement of the first bias voltage Vb1. Alternatively, to provide a more flexible bias voltage, or to provide a wider range or more bias voltages, one or more branches can be added to the bias circuit to generate one or more bias voltages based on the bias current I1. For example... Figure 3 As shown. It should be understood that "multiple" in this disclosure refers to two or more.

[0066] Therefore, in some embodiments, the bias circuit of this disclosure may further include a first branch formed by a third transistor and a first clamping module, wherein the third transistor may form a current mirror with the transistor in the first current mirror to generate a first current proportional to the bias current, and the first clamping module may be coupled to the drain of the third transistor and configured to clamp the voltage at the drain of the third transistor to the first bias voltage according to the first current.

[0067] For example, the first clamping module can be composed of a diode-connected transistor, whose gate and drain are both coupled to the drain of a third transistor, and whose source is grounded. Alternatively, the first clamping module can include a first series unit comprising multiple transistors connected in series, whose gates are all coupled to the drain of a third transistor, the drain of the first of these multiple series transistors is also coupled to the drain of the third transistor, and the source of the last of these multiple series transistors is grounded. It should be understood that multiple series transistors refer to multiple transistors whose gates are all connected together and whose source is sequentially connected to the drain of the next transistor. The diode-connected transistor or multiple series transistors can be equivalent to a resistor, through which a first current proportional to the bias current flows, generating a first bias voltage, or in other words, clamping the voltage at a first bias voltage. Using multiple series transistors as a clamping module facilitates circuit design or layout. The number of transistors connected in series can be selected according to needs (e.g., the magnitude of the bias voltage or circuit design considerations).

[0068] Additionally, in some embodiments, the bias circuit of this disclosure may further include one or more branches similar to the first branch, each consisting of a transistor constituting a current mirror to generate a current proportional to the bias current and a clamping module for clamping to a desired bias voltage value. This clamping module may be implemented in a manner similar to the foregoing example or in other different ways.

[0069] Figure 3 As an example, it is shown Figure 2a A variation of the bias circuit, the core part of which generates the bias current I1 is... Figure 2aThe difference is that two additional branches, one on the left and one on the right, are added to provide two bias voltages, Vb1 and Vb2, respectively. It should be understood that... Figure 3 The number of branches generating bias voltage in the diagram is merely an example and can be increased or decreased as needed; that is, only one branch can be retained, or other similar branches can be added. Additionally, [the following can be added]... Figure 2b The bias circuit similarly adds branches to obtain the same... Figure 3 A similar bias circuit configuration.

[0070] Figure 3 Zhongyu Figure 2a The same circuit parts and their working principles will not be repeated here. The following mainly describes the left and right branches that generate two bias voltages Vb1 and Vb2 based on the bias current I1 and their working principles.

[0071] like Figure 3 As shown, the bias circuit 310 further includes a first branch for generating a first bias voltage Vb1, which includes a PMOS transistor M7 and NMOS transistors M5 and M6 constituting a clamping module. M7 forms a current mirror with the reference transistor M4 in the aforementioned first current mirror, thereby generating a current I2 proportional to the bias current I1 (which is an example of the first current as described in the preceding summary section), the ratio of which is equal to the width-to-length ratio of M7 to M4. M5 and M6 are connected in series, that is, the gates of M5 and M6 are connected together and coupled to the drains of M7 and M5, the source of M5 is connected to the drain of M6, and the source of M6 is grounded. As previously described, M5 and M6 can be considered as resistors, clamping the voltage at the drain of M7 to the desired first bias voltage Vb1 based on the magnitude of the current I2 and the total equivalent resistance of M5 and M6.

[0072] It should be understood that Figure 3 The number of series-connected transistors shown is merely exemplary; depending on the required first bias voltage Vb1 and circuit design or layout considerations, M6 may be removed or one or more NMOS transistors may be added in series between M5 and M6.

[0073] In addition, such as Figure 3 As shown, the bias circuit 310 also includes a second branch for generating a second bias voltage Vb2. Its structure and working principle are similar to the first branch mentioned above, except that the design parameters of each transistor are different, so as to provide a second bias voltage Vb2 that is different from the first bias voltage Vb1.

[0074] In the bias circuit, such as Figure 3As shown, when the circuit includes a first branch and a second branch, or even more branches, that generate Vb1 and Vb2 respectively, multiple different bias voltages can be output as needed. This allows for more flexible configuration of the bias voltages and ensures that the transistors used as current sources in subsequent output stage circuits (e.g., Figure 8 The M18 and M19 shown can operate in the saturation region under various process temperature conditions, ensuring accurate current reproduction and excellent circuit performance. It should be understood that, in cases where the output bias voltage requirement is not high, only these two types of circuits may be retained. Figure 3 One branch in the circuit uses only Vb1 or Vb2 as the bias voltage required by the subsequent output stage circuit, saving power consumption and area.

[0075] Specifically, Figure 3 The second branch includes a PMOS transistor M9 and NMOS transistors M10 and M11 constituting a clamping module. M9 forms a current mirror with the reference transistor M4 in the aforementioned PMOS current mirror, thereby generating a third current I3 proportional to the bias current I1 (which serves as an example of a fourth current as described in the preceding description of the invention), the ratio of which is equal to the width-to-length ratio of M9 and M4. M10 and M11 are connected in series, i.e., the gates of M10 and M11 are connected together and coupled to the drains of M9 and M10, the source of M10 is connected to the drain of M11, and the source of M11 is grounded. As previously described, M10 and M11 can be considered as resistors, clamping the voltage at the drain of M9 to the desired second bias voltage Vb2 based on the magnitude of the current I3 and the total equivalent resistance of M10 and M11.

[0076] In addition, such as Figure 3 As shown, the bias circuit 310 may further include an NMOS transistor M8 coupled between the first bias voltage Vb1 and ground. The source and drain of M8 are both grounded, while its gate is coupled to the first bias voltage Vb1 (i.e., the drains of M5 and M7). This allows M8 to function as a capacitor to prevent the first bias voltage Vb1 from spikeing to excessively high levels during startup, which could affect circuit reliability. M8 can also be replaced with other capacitors (e.g., MIM (Metal-Insulator-Metal) capacitors or MOM (Metal-Oxide-Metal) capacitors). Although not shown in the figure, a similar capacitor can be provided between the second bias voltage Vb2 and ground as needed.

[0077] As mentioned earlier, in some cases, it is also necessary to provide Figure 2a , Figure 2b , Figure 3Or a similar bias circuit provides a corresponding startup circuit. For example, the startup circuit may be coupled to the gate of the transistor in the aforementioned first current mirror and configured to provide a path from the gate of the transistor in the aforementioned first current mirror to the power supply voltage VIN or ground when the LDO is turned on, so that all these transistors are turned on, and to turn off the path after the bias circuit starts operating.

[0078] Figure 4 Provided for Figure 2a A schematic diagram of the composition of an exemplary startup circuit for the bias circuit. Figure 4 The bias circuit 410 in the middle and Figure 2a The bias circuit 210 has the same structure, but as mentioned above, the bias circuit of the present invention is not limited to... Figure 2a or Figure 2b The specific implementation of the bias circuit is as follows. The startup circuit 430 is used to remove the bias circuit 410 from its degenerate bias point and enable it to begin normal operation when the LDO is turned on. It should be understood that... Figure 4 The startup circuit shown is not only applicable to Figure 2a or Figure 2b The bias circuit structure can also be applied to Figure 2a or Figure 2b Structural variations (e.g.) Figure 3 (etc.) or other bias circuits that use similar principles / constructions.

[0079] like Figure 4 As shown, the startup circuit 430 includes NMOS transistors M12 and M13, and PMOS transistors M14 and M15 connected in series. The drain of M12 is coupled to the gate of transistors M3 and M4 in the PMOS current mirror of the bias circuit 410 (the voltage here is labeled V1), the source of M12 is coupled to ground, and the gate of M12 is coupled to the drain of M13. The source of M13 is coupled to ground, and the gate of M13 is coupled to the gate of NMOS transistor M1 or M2 in the bias circuit 410. The PMOS transistors M14 and M15 connected in series can also be referred to as the second series unit. Their gates both receive the enable signal ENS. The drain of M14 is coupled to the gate of M12 and the drain of M13, the source of M14 is coupled to the drain of M15, and the source of M15 is coupled to the power supply voltage VIN.

[0080] The enable signal ENS is set to the first level (e.g., ground level, or the low level "0" of a digital signal) when the LDO is turned on, so that M14 and M15 are turned on. The turn-on of M14 and M15 pulls the gate voltage of M12 to approximately equal to VIN, causing M12 to turn on. This pulls the potential of V1 to ground level GND by M12, causing both M3 and M4 to turn on, breaking the degeneracy point of the bias circuit 410 and completing the circuit startup. In other words, when the LDO is turned on, M12 turns on, thus providing a path from the gates (at V1) of transistors M3 and M4 to ground, causing both transistors M3 and M4 to turn on, and the bias circuit 410 begins to operate. When the bias circuit 410 is operating stably, such as... Figure 4 As shown, transistors M1 to M4 in the bias circuit 410 are all turned on and generate bias current I1.

[0081] When the bias circuit 410 starts working, M12 is turned off, thereby closing the path from the gates (at V1) of transistors M3 and M4 to ground, preventing the potential of V1 from being affected by the startup circuit. M12 can be turned off in, for example, in the following two ways:

[0082] 1) Change the enable signal ENS to a second level higher than the first level (e.g., power supply voltage VIN) to turn off M14 and M15. Since the gate of M13 is coupled to the gate of M1, M13 is also turned on when M1 is turned on. The turn-on of M13 pulls the gate voltage of M12 to ground level GND, so that the gate-source voltage of M12 is lower than the threshold voltage, and M12 is turned off.

[0083] 2) M13 is designed with a large aspect ratio, which makes its pull-down capability greater than that of M14 and M15. Therefore, after M13 is turned on along with M1, even if M14 and M15 are turned on at the same time, the gate voltage of M12 will be pulled to ground level GND by M13, so that the gate-source voltage of M12 is lower than the threshold voltage, and M12 is turned off.

[0084] It should be understood that Figure 4 The number of PMOS transistors connected in series shown is merely exemplary; depending on the needs (e.g., circuit design or layout considerations), M14 can be removed or one or more PMOS transistors can be added between M14 and M15 in series. When M14 is removed, the source of M15 is coupled to VIN, and the drain is coupled to the gate of M12. The gate receives the enable signal ENS, and its operating principle is similar to that described above, so it will not be repeated here.

[0085] The following is combined with Figures 5 to 7 We will now discuss exemplary circuit implementations of the output stage circuitry in an LDO according to some embodiments of this disclosure.

[0086] Figure 5 An exemplary circuit implementation of an output stage circuit with an FVF structure is given.

[0087] like Figure 5 As shown, the output stage circuit 520 includes a power transistor Mp1, a PMOS transistor M16 (which is an example of the ninth transistor as described above), an NMOS transistor M17 (which is an example of the tenth transistor as described above), a current source Ib1 (which is an example of the first current source as described above), and current sources Ib2 and Ib3 (which are combined as an example of the second current source as described above).

[0088] The gate receiver of M16 is biased by a circuit (e.g., Figure 3 The first bias voltage Vb1 generated by the bias circuit 310 in the middle is source-coupled to the drain of the power transistor Mp1 (i.e., the output node at the output VOUT), and the drain is coupled to the current sources Ib2 and Ib3.

[0089] The gate receiver of M17 is biased by a circuit (e.g., Figure 3 The second bias voltage Vb2 generated by the bias circuit 310 in the middle is source-coupled to the drain of M16 and current sources Ib2 and Ib3, and drain-coupled to the gate of power transistor Mp1 and current source Ib1.

[0090] The fluctuation of the output voltage VOUT is detected and amplified by M16 and transmitted to the source terminal of M17. M17 adjusts the gate voltage of Mp1 accordingly based on the magnitude of the source voltage fluctuation, thereby regulating VOUT. Thus, M16, M17, and Mp1 form a negative feedback loop, which quickly adjusts the circuit state when the output voltage VOUT fluctuates, thereby stabilizing the output voltage.

[0091] The output voltage of the LDO is equal to the sum of the first bias voltage Vb1 and the source-gate voltage Vsg16 of M16, i.e.

[0092] VOUT = Vb1 + Vsg16

[0093] Additionally, current source Ib1 is coupled between the input voltage VIN (i.e., the power supply voltage) and the gate of power transistor Mp1 / drain of M17, while current sources Ib2 and Ib3 are coupled between the drain of M16 / source of M17 and ground GND, thereby providing the necessary current to power transistor Mp1, PMOS transistor M16, and NMOS transistor M17. It should be understood that... Figure 5 The current sources Ib2 and Ib3 in the diagram are two current sources connected in parallel, which are merely exemplary. Alternatively, they can be implemented by one current source or more than two current sources connected in parallel.

[0094] In some embodiments, such as the following Figure 8 As shown, current source Ib1 can be implemented by a PMOS transistor that forms a current mirror with the transistor in the first current mirror of the aforementioned bias circuit, generating a current Ib1 proportional to the bias current (as an example of a second current as described in the preceding description of the invention); while current sources Ib2 and Ib3 can be implemented by two NMOS transistors that form current mirrors with the transistor in the first current mirror of the aforementioned bias circuit, generating currents Ib2 and Ib3 proportional to the bias current (as an example of a plurality of third currents as described in the preceding description of the invention; it should be understood that "a plurality of third currents" in this document does not mean that these plurality of third currents have the same magnitude, but is determined according to the parameters of the respective NMOS transistors constituting the current sources, which may be the same or different from each other).

[0095] In addition, such as Figure 5 As shown, in some cases, to improve the stability of the output stage circuit, the output stage circuit 520 may also include a second resistor R2 and a second capacitor C2, which are connected in series between the source and gate of the power transistor Mp1 to provide a zero point. Additionally, in some cases, to further improve the stability of the output stage circuit, the output stage circuit 520 may also include a third capacitor C1 for Miller compensation, which is coupled between the source and drain of the transistor M16.

[0096] Figure 6 and Figure 7 An exemplary circuit implementation using an error amplifier and a power transistor is given, wherein... Figure 7 and Figure 6 The difference lies in giving Figure 6 An example of a specific implementation circuit for EA in the example.

[0097] like Figure 6 As shown, the output stage circuit 620 includes a power transistor Mp2, a PMOS transistor M18 (which is an example of a ninth transistor as described above), an error amplifier EA, and a current source Ib4 (which is an example of a third current source as described above).

[0098] The gate and drain of M18 are coupled together, and the source of M18 is coupled to the drain of power transistor Mp2 (i.e., the output node at output VOUT).

[0099] The non-inverting input of EA is coupled to the gate of M18, and the inverting input receives input from the bias circuit (e.g., Figure 2a , Figure 2b or Figure 3The first bias voltage Vb1 generated by the bias circuit in the circuit is coupled to the gate of the power transistor Mp2.

[0100] Fluctuations in the output voltage VOUT are transmitted to the non-inverting input of EA via M18, where they are amplified and output to the gate of Mp2, thus regulating VOUT. Therefore, M18, EA, and Mp2 form a negative feedback loop, adjusting the circuit state when the output voltage VOUT fluctuates, thereby stabilizing the output voltage.

[0101] The output voltage VOUT of the LDO is equal to the sum of the first bias voltage Vb1 and the source-gate voltage Vsg18 of M18, i.e.

[0102] VOUT = Vb1 + Vsg18

[0103] In addition, current source Ib4 is coupled between the drain of M18 and ground GND to provide quiescent current for PMOS transistors Mp2 and M18.

[0104] In some embodiments, such as the following Figure 9 As shown, the current source Ib4 can be implemented by an NMOS transistor that forms a current mirror with the transistor in the first current mirror of the aforementioned bias circuit, the first transistor or the second transistor, which generates a current Ib4 proportional to the bias current.

[0105] In addition, such as Figure 6 As shown, in some cases, in order to improve the stability of the output stage circuit, the output stage circuit 620 may also include a third resistor R3 and a fourth capacitor C3 for Miller compensation, which are connected in series between the gate and drain of the power transistor Mp2.

[0106] Figure 7 Given Figure 6 An example of a specific implementation circuit of EA in the example, such as Figure 7 The part shown in the dashed box.

[0107] like Figure 7 As shown, EA 726 includes: PMOS transistors M19 and M20 (as examples of the aforementioned first and second input transistors, respectively), NMOS current mirrors M22 / M21 (as examples of the aforementioned second current mirror), NMOS current mirrors M23 / M24 (as examples of the aforementioned third current mirror), PMOS current mirrors M25 / M26 (as examples of the aforementioned fourth current mirror), and current source Ib5 (as an example of the aforementioned tail current source).

[0108] The source of the first input transistor M19 is coupled to the source of the second input transistor M20, and the gate of the first input transistor M19 receives a bias circuit (e.g., ...). Figure 2a , Figure 2b or Figure 3 The first bias voltage Vb1 generated by the bias circuit in the middle is coupled to the gate of the second input transistor M20.

[0109] The drain of the first input transistor M19 is coupled to the reference branch of the NMOS current mirrors M22 / M21 (i.e., the drain and gate of M22), and the drain of the second input transistor M20 is coupled to the reference branch of the NMOS current mirrors M23 / M24 (i.e., the drain and gate of M23). The output branch of the NMOS current mirrors M22 / M21 is coupled to the reference branch of the PMOS current mirrors M25 / M26 (i.e., the drain and gate of M25), and the output branch of the NMOS current mirrors M23 / M24 is coupled to the output branch of the PMOS current mirrors M25 / M26 (i.e., the drain and gate of M26). The coupling node between the two (i.e., the drain terminals of M24 and M26) is the output terminal of EA 726.

[0110] Current source Ib5 is coupled as a tail current source between the input voltage VIN (i.e., the supply voltage) and the source of M19 or M20 to provide current to EA. In some embodiments, such as those described later... Figure 9 As shown, the current source Ib5 can be implemented by a PMOS transistor that forms a current mirror with the transistor in the first current mirror of the aforementioned bias circuit, the first transistor or the second transistor, which generates a current Ib5 proportional to the bias current (which is an example of a fifth current as described in the preceding summary of the invention section).

[0111] Figure 8 and Figure 9 Schematic diagrams of complete LDO circuits according to some embodiments of the present disclosure are shown.

[0112] Figure 8 The LDO 800 shown includes a startup circuit 830, a bias circuit 810, and an output stage circuit 820, wherein the startup circuit 830 has a... Figure 4 The startup circuit 430 has the same circuit structure as the bias circuit 810. Figure 3 The bias circuit 310 has the same circuit structure as the output stage circuit 820, and the output stage circuit 820 has the same circuit structure as the bias circuit 310. Figure 5 The output stage circuit 520 has the same circuit structure, except that the current source is implemented by transistors that form a current mirror.

[0113] Specifically, Figure 5 The current sources Ib1, Ib2, and Ib3 in the output stage circuit 520 shown are in Figure 8 The output stage circuit 820 shown is implemented using PMOS transistor M27, NMOS transistors M28 and M29, respectively. PMOS transistors M27 and M4 form a current mirror to generate a current Ib1 proportional to the bias current I1; NMOS transistors M28 and M1 form a current mirror to generate a current Ib2 proportional to the bias current I1; and NMOS transistors M29 and M1 form a current mirror to generate a current Ib3 proportional to the bias current I1. The remaining components of the LDO 800 are the same as those shown in the previous figures and will not be repeated here.

[0114] In some embodiments, the operation of the LDO 800 circuit can be as follows: When the LDO is turned on, the gate signal ENS of PMOS transistors M14 and M15 becomes 0 (low level), and M14 and M15 are turned on, making the gate voltage of M12 approximately equal to the input voltage VIN of the LDO (i.e., the power supply voltage). This causes M12 to turn on, pulling the potential of V1 towards GND, breaking the degeneracy point of the bias circuit 810, and completing the circuit startup. After the LDO circuit stabilizes, the bias circuit 810 generates a bias current I1 and replicates it to M7 and M9 through a current mirror according to the width-to-length ratio between the transistors. By designing parameters such as the current I2 of M7 (based on the width-to-length ratio of M7 to M4 and the magnitude of I1) and the width-to-length ratio of M5 and M6, the magnitude of the first bias voltage Vb1 to be provided to the gate of M16 is determined to provide a suitable output voltage value. By designing parameters such as the current I3 of M9 (based on the width-to-length ratio of M9 to M4 and the value of I1) and the width-to-length ratio of M10 and M11, the magnitude of the second bias voltage Vb2 to be supplied to the gate terminal of M17 is determined, ensuring that the gate voltage of M17 is high enough to guarantee that both M28 and M29 can operate in the saturation region. The current of the output stage circuit 820 is provided by the PMOS transistor M27, NMOS transistors M28 and M29, which respectively constitute current mirrors. The current Ib1 of M27 is determined by the width-to-length ratio of M27 to M4 and the bias current I1; the current Ib2 of M28 is determined by the width-to-length ratio of M28 to M1 and the bias current I1; and the current Ib3 of M29 is determined by the width-to-length ratio of M29 to M1 and the bias current I1. As mentioned earlier, the output stage circuit 820 using the FVF structure can quickly adjust the output voltage VOUT to stabilize it, and the value of the output voltage VOUT of the LDO 800 is equal to the sum of the first bias voltage Vb1 and the source-gate voltage Vsg16 of M16.

[0115] Therefore, the LDO according to the embodiments of this disclosure can provide a stable supply voltage for, for example, digital circuits using only a simple startup circuit, bias circuit, and FVF structure output stage circuit, without requiring a bandgap reference voltage and operational amplifier circuit, saving circuit area and facilitating low-cost design. Furthermore, since the LDO according to the embodiments of this disclosure does not use an operational amplifier to provide the bias voltage, it can respond quickly to large changes in the input power supply voltage value over a short period, avoiding excessive overshoot of the output voltage.

[0116] Figure 9 The LDO 900 shown includes a startup circuit 930, a bias circuit 910, and an output stage circuit 920, wherein the startup circuit 930 has a... Figure 4 The startup circuit 430 has the same circuit structure as the bias circuit 910. Figure 3 The bias circuit 310 has a partially identical circuit structure (the only difference being the removal of the rightmost branch used to generate the second bias voltage Vb2), and the output stage circuit 920 has the same... Figure 7 The output stage circuit 720 has the same circuit structure, except that the current source is implemented by transistors that form a current mirror.

[0117] Specifically, Figure 7 The current sources Ib4 and Ib5 in the output stage circuit 720 shown are in Figure 9 The output stage circuit 920 shown is implemented using NMOS transistor M31 and PMOS transistor M30, respectively. NMOS transistors M31 and M1 form a current mirror to generate a current Ib4 proportional to the bias current I1, and PMOS transistors M30 and M4 form a current mirror to generate a current Ib5 proportional to the bias current I1. The remaining components of the LDO 900 are the same as those shown in the previous figures and will not be repeated here.

[0118] Figure 9 The structure and operation of the startup circuit 930 and bias circuit 910 in the LDO900 shown are the same as those described above. Figure 8The output stage circuit 920 is identical to the previous one, except that it is now an error amplifier plus a power transistor. In the output stage circuit 920, the PMOS transistor M30, which forms a current mirror, provides the necessary current to the error amplifier EA, and the NMOS transistor M31, which also forms a current mirror, provides quiescent current to the PMOS transistors Mp2 and M18. The current Ib5 of M30 is determined by the width-to-length ratio of M30 to M4 and the bias current I1, while the current Ib4 of M31 is determined by the width-to-length ratio of M31 to M1 and the bias current I1. As mentioned earlier, by utilizing the error amplifier plus power transistor structure, the output stage circuit 920 can reliably regulate the output voltage VOUT, stabilizing it. Furthermore, the value of the LDO 900's output voltage VOUT is equal to the sum of the first bias voltage Vb1 and the source-gate voltage Vsg18 of M18. Additionally, even when the input power supply voltage VIN changes rapidly and significantly, the LDO 900 can respond quickly, preventing excessive fluctuations in the output voltage VOUT.

[0119] Therefore, the LDO according to the embodiments of this disclosure can provide a stable power supply voltage for, for example, digital circuits using only a simple startup circuit, bias circuit, and output stage circuit in the form of an EA, saving circuit area and facilitating low-cost design. Furthermore, the LDO according to the embodiments of this disclosure can quickly respond to large changes in the input power supply voltage value over a short period, avoiding excessive overshoot of the output voltage.

[0120] The various embodiments of this disclosure have been described above. These descriptions are exemplary and not exhaustive, nor are they limited to the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the described embodiments. The terminology used herein is chosen to best explain the principles, practical application, or improvement of the technology in the market, or to enable others skilled in the art to understand the embodiments disclosed herein.

Claims

1. A low-dropout voltage regulator, comprising: A bias circuit includes a first transistor, a second transistor, and a bias resistor, wherein the gate of the second transistor is coupled to the drain of the first transistor, and the difference between the gate-source voltages of the first transistor and the second transistor generates a bias current across the bias resistor, and the bias circuit is further configured to generate a first bias voltage based on the bias current. as well as The output stage circuitry includes power transistors and a feedback circuit. The output voltage of the low-dropout regulator is output from the drain of the power transistor. The feedback circuit is coupled between the gate and drain of the power transistor and is configured to change the gate voltage of the power transistor in the same direction according to the change in the output voltage; and The feedback circuit receives the first bias voltage and generates the output voltage based on the first bias voltage.

2. The low-dropout voltage regulator according to claim 1, wherein, The bias circuit also includes a first current mirror. The two branches in the first current mirror are respectively coupled to the first transistor and the second transistor, and the channel type is opposite to that of the transistor in the first current mirror; as well as The bias resistor is located between the gates or sources of the first transistor and the second transistor, such that the voltage across the bias resistor is equal to the difference between the gate-source voltages of the first transistor and the second transistor, and the bias current generated on the bias resistor is the current of one branch of the first current mirror.

3. The low-dropout voltage regulator according to claim 2, wherein, The bias circuit further includes: A third transistor, forming a current mirror with the transistor in the first current mirror to generate a first current proportional to the bias current; and A first clamping module is coupled to the drain of the third transistor and configured to clamp the voltage at the drain of the third transistor to the first bias voltage according to the first current.

4. The low-dropout voltage regulator according to claim 3, wherein, The first clamping module includes a fourth transistor, the gate and drain of which are both coupled to the drain of the third transistor, and the source of the fourth transistor is grounded; or The first clamping module includes a first series unit, which includes a plurality of transistors connected in series. The gates of the plurality of transistors in the first series unit are all coupled to the drain of the third transistor. The drain of the first of the plurality of transistors in the first series unit is coupled to the drain of the third transistor. The source of the last of the plurality of transistors in the first series unit is grounded.

5. The low-dropout voltage regulator according to claim 3, wherein, The bias circuit also includes a first capacitor coupled between the drain of the third transistor and ground. And / or, The first capacitor is composed of a fifth transistor, the source and drain of which are both grounded and the gate is coupled to the drain of the third transistor.

6. The low-dropout voltage regulator according to claim 1, wherein, The bias circuit is configured to provide the feedback circuit with the gate-source voltage of the first transistor as the first bias voltage.

7. The low-dropout voltage regulator according to claim 2 further includes: A startup circuit, coupled to the gate of a transistor in the first current mirror, is configured to provide a path from the gate of the transistor in the first current mirror to ground when the low-dropout regulator is turned on, such that all transistors in the first current mirror are turned on, and to turn off the path after the bias circuit starts operating.

8. The low-dropout voltage regulator according to claim 7, wherein, The startup circuit includes: The sixth transistor has its drain coupled to the gate of the transistor in the first current mirror, and its source coupled to ground. The seventh transistor has its drain coupled to the gate of the sixth transistor, its source coupled to ground, and its gate coupled to the gate of the first transistor or the second transistor; and The eighth transistor or the second series unit; The source of the eighth transistor is coupled to the input voltage of the low dropout regulator, the drain of the eighth transistor is coupled to the gate of the sixth transistor, and the gate of the eighth transistor receives an enable signal. Alternatively, the second series unit includes a plurality of transistors connected in series, the gates of the plurality of transistors in the second series unit all receive an enable signal, the drain of the first of the plurality of transistors in the second series unit is coupled to the gate of the sixth transistor, and the source of the last of the plurality of transistors in the second series unit is coupled to the input voltage. The enable signal is set to a first level when the low-dropout regulator is turned on, so that the eighth transistor or a plurality of series-connected transistors in the second series unit are turned on.

9. The low-dropout voltage regulator according to claim 1, wherein, The feedback circuit includes a ninth transistor, which is a PMOS transistor. Its source is coupled to the drain of the power transistor, and its gate receives the first bias voltage or a voltage equal to the first bias voltage. This makes the output voltage the sum of the first bias voltage and the source-gate voltage of the ninth transistor. The change in the output voltage is conducted from the source of the ninth transistor to the drain or gate of the ninth transistor, thereby changing the gate voltage of the power transistor in the same direction.

10. The low-dropout voltage regulator according to claim 9, wherein, The feedback circuit and the power transistor constitute an FVF structure.

11. The low-dropout regulator according to claim 10, wherein, The gate of the ninth transistor receives the first bias voltage; The feedback circuit also includes: The tenth transistor is an NMOS transistor, whose gate receives a second bias voltage, whose source is coupled to the drain of the ninth transistor, and whose drain is coupled to the gate of the power transistor. A first current source is coupled between the input voltage of the low-dropout regulator and the gate of the power transistor; and The second current source is coupled between the drain of the ninth transistor and ground.

12. The low-dropout voltage regulator according to claim 11, wherein, The bias circuit also includes a first current mirror; In this embodiment, the two branches in the first current mirror are respectively coupled to the first transistor and the second transistor, and the channel type is opposite to that of the transistor in the first current mirror. The bias resistor is located between the gate or source of the first transistor and the second transistor, such that the voltage across the bias resistor is equal to the difference between the gate-source voltages of the first transistor and the second transistor, and the bias current generated on the bias resistor is the current of one branch of the first current mirror. The first current source includes an eleventh transistor as a PMOS transistor, which, together with the transistor in the first current mirror, the first transistor, or the second transistor, forms a current mirror to generate a second current proportional to the bias current. The second current source includes a twelfth transistor or a plurality of NMOS transistors connected in parallel, which together with the transistors in the first current mirror, the first transistor, or the second transistor form a current mirror to generate a third current or a plurality of third currents proportional to the bias current.

13. The low-dropout voltage regulator according to claim 12, wherein, The bias circuit further includes: A thirteenth transistor, forming a current mirror with the transistor in the first current mirror to generate a fourth current proportional to the bias current; and The second clamping module is coupled to the drain of the thirteenth transistor and the gate of the tenth transistor, and is configured to clamp the voltage at the drain of the thirteenth transistor to the second bias voltage according to the fourth current.

14. The low-dropout regulator according to claim 13, wherein, The second clamping module includes a fourteenth transistor, the gate and drain of which are both coupled to the drain of the thirteenth transistor, and the source of the fourteenth transistor is grounded; or The second clamping module includes a third series unit, which includes a plurality of transistors connected in series. The gates of the plurality of transistors in the third series unit are all coupled to the drain of the thirteenth transistor. The drain of the first of the plurality of transistors in the third series unit is coupled to the drain of the thirteenth transistor. The source of the last of the plurality of transistors in the third series unit is grounded. And / or, The output stage circuit also includes a second resistor and a second capacitor connected in series between the source and gate of the power transistor, the second resistor and the second capacitor providing a zero point; And / or, The output stage circuit also includes a third capacitor for Miller compensation coupled between the source and drain of the ninth transistor.

15. The low-dropout voltage regulator according to claim 9, wherein, The gate of the ninth transistor is coupled to the drain of the ninth transistor; The feedback circuit also includes: An error amplifier, whose non-inverting input is coupled to the gate of the ninth transistor, whose inverting input receives the first bias voltage, and whose output is coupled to the gate of the power transistor. as well as The third current source is coupled between the drain of the ninth transistor and ground.

16. The low-dropout regulator according to claim 15, wherein, The error amplifier includes: A first input transistor and a second input transistor, wherein the source of the first input transistor is coupled to the source of the second input transistor, the gate of the first input transistor receives the first bias voltage, and the gate of the second input transistor is coupled to the gate of the ninth transistor. The second current mirror has its reference branch coupled to the drain of the first input transistor; The third current mirror, whose reference branch is coupled to the drain of the second input transistor; A fourth current mirror, whose reference branch is coupled to the output branch of the second current mirror, and whose output branch is coupled to the output branch of the third current mirror, with its coupling node being the output terminal of the error amplifier; and A tail current source, coupled between the input voltage of the low dropout regulator and the source of the first input transistor, provides a fifth current proportional to the bias current. And / or, The output stage circuit also includes a third resistor and a fourth capacitor connected in series between the gate and drain of the power transistor for Miller compensation.

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