Online upgrading system and method for domestic FT-C6748 DSP inertial navigation resolving software

Abstract

The invention relates to a domestic FT-C6748DSP inertial navigation resolving software online upgrading system and method, the system comprises a DSP chip, an FPGA chip, an NVSRAM FLASH chip and an SPI FLASH chip, the DSP chip is used for running an inertial navigation resolving scheme, the FPGA chip is used for collecting original pulses of an inertial navigation component and providing reset operation for the DSP chip, and the FPGA chip is used for providing reset operation for the DSP chip. The NVSRAM FLASH chip is used for storing calibration parameters and software programming control marks of a strapdown inertial navigation scheme, and the SPI FLASH chip is used for storing DSP inertial navigation resolving software. According to the method, the DSP resolving software and the inertial navigation parameters are respectively stored in the two independent chips by adopting the two FLASH, so that the effect of preventing the DSP inertial navigation resolving software from being accidentally erased and lost can be achieved, the DSP inertial navigation resolving software can be reliably started, and the reliability of the DSP inertial navigation resolving software is improved. By adopting the technical architecture designed by the invention, the problem of FLASH data loss caused by accidental power failure during FLASH erasing and writing of inertial navigation parameters can be avoided.

Description

Technical Field

[0001] This invention belongs to the field of embedded basic software platform technology, and in particular, it relates to an online upgrade system and method for domestically produced FT-C6748 DSP inertial navigation software. Background Technology

[0002] The RC5NS128K-PSO non-volatile static random access memory (NSRAM) produced by Hunan Rongchuang Microelectronics Co., Ltd. is a domestically produced NVSRAM flash memory chip with an SPI interface. In use, it can be considered a type of SRAM memory. Data to be stored is written to its SRAM using a standard SPI interface, just like RAM. After power failure or upon receiving an AutoStore or Software Store command, the chip utilizes its stored energy (capacitors) to complete at least one data erase and write operation. It supports automatic SORE operation upon power failure, ensuring that data written to the SRAM memory is always written to the FLASH memory, resulting in extremely high reliability and avoiding data loss due to accidental power loss during data erasure and writing in ordinary FLASH memory. This is its advantage. However, its disadvantage is also significant: a capacity of only 128KB, which generally cannot meet the ROM storage space requirements of embedded software. Therefore, this chip is an ideal flash memory chip for storing calibration parameters of strapdown inertial navigation systems.

[0003] The SM25QH16M flash memory chip, manufactured by Shenzhen Guowei Electronics Co., Ltd., is a domestically produced, non-volatile SPI interface flash memory chip. It supports a maximum read frequency of 104MHz and has a relatively large capacity of 2MB, making it a commonly used flash memory chip for storing strapdown inertial navigation system software.

[0004] The FT-C6748DSP chip, produced by Hunan Great Wall Galaxy Technology Co., Ltd., is a low-power, domestically produced floating-point DSP chip. Its main frequency reaches 460MHz, its floating-point operation capability reaches 2760MFLOPS@460MHz, its L2 RAM is 256KB, and its shared RAM is 4MB, making it the most powerful single-core DSP chip. Therefore, it is an ideal chip for strapdown inertial navigation system solutions requiring extensive digital computation.

[0005] The EG4X20BG256 Falcon System FPGA chip, manufactured by Shanghai Anlu Technology Co., Ltd., is a domestically produced chip. It features low power consumption and high performance. It is commonly used in strapdown inertial navigation systems for data acquisition, interface expansion, and signal enable control.

[0006] DSP software programming involves compiling the software into a *.out file, which cannot be directly programmed into the DSP's external program memory FLASH chip for loading and execution. Typically, conversion software is used to convert it to a *.bin file, which is then programmed directly into the program memory FLASH chip using an emulator or via online upgrade methods. For example, the file can be sent to the DSP software via serial port and then programmed into the program memory FLASH chip. Therefore, online DSP software updates essentially involve programming the *.bin file into the program memory FLASH chip.

[0007] DSP software programming is typically performed online using the Composer Code Studio integrated development environment. A significant drawback of this process is the need for a dedicated DSP chip emulator to connect the chip to the computer. Furthermore, it often requires disassembling DSP engineering equipment (such as inertial navigation systems), which presents considerable inconvenience for practical engineering applications.

[0008] Another method for DSP software programming generally requires users to develop secondary boot software. This allows for the programming and updating of DSP inertial navigation software without the need for a dedicated DSP chip emulator or disassembling DSP engineering equipment (such as inertial navigation equipment). However, this method has significant drawbacks. Firstly, in practical projects, it's common to use only one SPI FLASH or NORFLASH chip to store both the inertial navigation software and calibration parameters, thus lacking anti-burn-out functionality. Because the inertial parameters and programming software coexist on a single FLASH chip, there's a possibility of accidental overwriting during the inertial parameters erasure process. If this occurs, the DSP inertial navigation software will fail to boot after power-on, thus preventing the completion of normal inertial navigation computation tasks. Summary of the Invention

[0009] The purpose of this invention is to overcome the shortcomings of existing technologies and propose a domestically produced FT-C6748 DSP software online upgrade system and method. This system solves the problem of DSP inertial navigation software failing to boot due to accidental erasure of the software stored in FLASH memory; and utilizes a designed technical architecture to avoid the loss of inertial navigation parameters due to accidental power failure during FLASH chip updates. This improves the reliability of inertial navigation equipment.

[0010] The technical problem solved by this invention is achieved through the following technical solution:

[0011] A domestically produced FT-C6748 DSP inertial navigation software online upgrade system includes a DSP chip, an FPGA chip, an NVSRAM FLASH chip, and an SPI FLASH chip. The DSP chip is connected to an FPGA chip, an NVSRAM FLASH chip, and a general-purpose SPI FLASH chip. The DSP chip is used to run the inertial navigation solution, the FPGA chip is used for acquiring the original pulses of the inertial navigation components and providing reset operations for the DSP chip, the NVSRAM FLASH chip is used to store the calibration parameters of the strapdown inertial navigation solution and the software programming control flags, and the SPI FLASH chip is used to store the DSP inertial navigation solution software.

[0012] Furthermore, the DSP chip uses the FT-C6748 chip. The 256KB of L2 memory and the first 2MB of shared memory in the DSP chip are used to run the strapdown inertial navigation scheme calculations, while the remaining 2MB of shared memory is used as a temporary area to store software update data received from the outside as temporary storage.

[0013] Furthermore, the update software for the inertial navigation calculation software stored in the SPI FLASH chip adds a header of 0x7E7E, then adds four bytes of data length, adds a CRC16-bit checksum for software file verification and one byte at the end, and finally adds a data tail of 0xBF after the checksum.

[0014] Furthermore, the DSP chip adds a reset pin function, allowing the inertial navigation calculation software stored in the SPI FLASH chip to send commands to the FPGA chip as needed, thereby resetting the DSP software and restarting the boot process.

[0015] Furthermore, the NVSRAM FLASH chip used is the RC5NS128K-PSO chip.

[0016] An upgrade method for a domestically produced FT-C6748 DSP software online upgrade system is characterized by the following steps:

[0017] Step 1: Power on and run the secondary boot program;

[0018] Step 2: The DSP software receives the programming command and determines whether the programming control flag written to the NVSRAM FLASH is 0x6666. If it is, proceed to step 2; otherwise, the DSP works normally.

[0019] Step 3: Check if the header, footer, length, and checksum of the bin file in the ordinary SPI FLASH are correct. If correct, proceed to step 4; otherwise, prompt: you must reply Y to complete a normal programming process or do not accept N, and proceed to step 7.

[0020] Step 4: Ask if you want to write the FLASH. If the answer is "yes", proceed to step 5; otherwise, proceed to step 7.

[0021] Step 5: Clear the programming control flags in the NVSRAM FLASH chip;

[0022] Step 6: The FPGA chip resets the DSP chip by controlling the DSP pins, and the DSP chip continues to work normally.

[0023] Step 7: Receive external data and store it in a 2MB temporary area in the shared RAM;

[0024] Step 8: Check if the header, footer, length, and checksum of the bin file are correct. If yes, proceed to step 9; otherwise, issue a prompt and notify the FPGA to control the DSP reset pin to reset the DSP and return to step 2.

[0025] Step 9: Copy the data in the 2M temporary area of ​​the shared RAM to the ordinary SPI FLASH chip;

[0026] Step 10: Determine whether the data transfer (copying) is complete. If it is complete, proceed to step 11; otherwise, return to step 10.

[0027] Step 11: Clear the programming control flag in the NVSRAMFLASH and indicate success.

[0028] The advantages and positive effects of this invention are:

[0029] 1. In terms of technical architecture, this invention uses a DSP chip as the core, independently connected to an FPGA chip and two FLASH chips, uses the FPGA to control the DSP reset mechanism, and uses the DSP chip's own shared memory as a temporary storage area for software. This technical architecture is novel and highly reliable, as detailed below.

[0030] 2. This invention uses two separate FLASH chips to store the DSP calculation software and parameters, which essentially separates the two storage. This improves the success rate of the DSP inertial navigation calculation software to 100% (due to software reasons). It avoids the problem of accidentally erasing the DSP calculation software stored in the same FLASH chip when erasing parameters, and ensures that the DSP inertial navigation calculation software will start successfully when powered on (due to software reasons).

[0031] 3. The inertial navigation parameter storage FLASH chip selected in this invention is a non-volatile static random access memory (NVSRAM FLASH). Utilizing the inherent advantages of NVSRAM FLASH chips (automatic SORE operation upon power failure), the problem of FLASH data loss due to accidental power failure during FLASH erasure and writing can be avoided.

[0032] 4. This invention adds a software mechanism to the communication between the FPGA and DSP, enabling the DSP to reset its own reset mechanism by sending data packets to the FPGA chip. This allows for the programming and updating of the DSP inertial navigation software without repeatedly powering on the DSP chip (DSP inertial navigation device), making it highly practical in engineering applications.

[0033] 5. This invention utilizes the shared memory of the DSP as a temporary storage area when receiving DSP solution software files. After receiving and updating the files, the data is centrally verified and transferred (copied) to the SPI FLASH. This saves the space used for temporary storage of DSP solution software in the SPI FLASH, thereby achieving the effect of storing larger DSP inertial navigation solution software. Moreover, its operation speed is much faster than the SPI FLASH storage process.

[0034] 6. The implementation steps and prompts of this invention are quite practical in actual engineering. You can operate according to the prompts. You do not need to have an in-depth understanding of DSP and inertial navigation technology to complete the burning and updating of DSP inertial navigation calculation software. Moreover, you can repeat the operation repeatedly without burning out (DSP cannot start). Attached Figure Description

[0035] Figure 1 This is a structural diagram of the system;

[0036] Figure 2 This is a flowchart of the present invention. Detailed Implementation

[0037] The present invention will be further described in detail below with reference to the accompanying drawings.

[0038] To address this deficiency, this invention employs two FLASH chips to store the DSP calculation software and inertial navigation parameters on two separate chips. This prevents the DSP inertial navigation calculation software from being accidentally erased and lost, thus ensuring reliable startup and improving its reliability. Secondly, since the domestically produced 6748 DSP chip is newly introduced, there are few related supporting technologies. The software writing and updating technology of the imported TI 6748 DSP chip used in the past did not adopt the non-volatile static random access memory (NVSRAM) FLASH selected in this invention, resulting in the problem of FLASH data loss after accidental power failure during FLASH writing. Therefore, this technical architecture and chip selection are also a technical advantage of this invention.

[0039] A domestically developed online upgrade system for FT-C6748 DSP inertial navigation software, such as Figure 1As shown, it includes a DSP chip, an FPGA chip, an NVSRAM FLASH chip, and an SPI FLASH chip. The DSP chip is connected to an FPGA chip, an NVSRAM FLASH chip, and a regular SPI FLASH chip. The DSP chip is used to run the inertial navigation solution scheme, the FPGA chip is used to acquire the raw pulses of the inertial navigation components and provide reset operations for the DSP chip, the NVSRAM FLASH chip is used to store the calibration parameters of the strapdown inertial navigation scheme and the software programming control flags, and the SPI FLASH chip is used to store the DSP inertial navigation solution software.

[0040] The DSP chip used is the FT-C6748, the NVSRAM FLASH chip is the RC5NS128K-PSO, the FPGA chip is the EG4X20BG256, and the FLASH chip is the SM25QH16M. Specifically, the DSP chip's total L2 memory (256KB) and the first 2MB of shared memory are used for running the strapdown inertial navigation scheme calculations. The remaining 2MB of shared memory is used as a temporary area to store software update data received from external sources.

[0041] The pre-update software file for inertial navigation calculation software stored in the SPI FLASH chip is appended with a header of 0x7E7E, followed by four bytes of data length, and a 16-bit CRC checksum and one byte at the end. Finally, a data tail of 0xBF is appended after the checksum. The software program itself, received from an external serial port, CAN interface, or Ethernet interface, is temporarily stored in a shared memory temporary area. This area is used for header, tail, length, and checksum verification. Only when all four items are correct is the online pre-update software program considered correct and can it be written into the ordinary SPI FLASH chip.

[0042] The DSP chip adds a reset pin function, which allows the inertial navigation calculation software stored in the SPI FLASH chip to send commands to the FPGA chip as needed, and then reset the DSP software to restart and boot.

[0043] In the secondary boot software, software writing is performed when the software writing control flag is read as 0x6666; other values ​​indicate no writing. Therefore, the writing control command should only be cleared to 0xFFFF after the DSP software bin file has been completely written to the ordinary SPI FLASH chip. This ensures that the writing control command is cleared only when the writing is actually completed. Even if there is an unexpected power outage, the writing control command read by the secondary boot software will still be 0x6666 after power is restored, allowing the writing process to be completed again.

[0044] Simultaneously, prompts are provided: these prompts can guide the operator's actions and provide feedback on commands, making it easier for them to complete online software upgrade tasks.

[0045] a)Do you want to burn the flash? (y / n,Y / N)

[0046] b)Please transmit the bin file.

[0047] c)Copy the file,please wait...

[0048] d)The bin file has beenburn complete,restarting...

[0049] e) Checksum error,please transmit the bin file again.

[0050] f) Wrong command!

[0051] An upgrade method for a domestically developed FT-C6748 DSP software online upgrade system, such as... Figure 2 As shown, it includes the following steps:

[0052] Step 1: The DSP software receives the programming command, writes the programming control flag to 0x6666 in the NVSRAM FLASH, and notifies the FPGA to reset the DSP chip through the DSP's reset pin.

[0053] Step 2: After the DSP restarts, send the prompt a) Do you want to burn the flash? (y / n, Y / N);

[0054] Step 3: If n or N is received, the FPGA is notified to reset the DSP chip through the DSP's reset pin;

[0055] Step 4: If y or Y is received, send the prompt b) Please transmit the bin fi le.

[0056] Step 5: The secondary boot software receives the bin file sent from the outside and saves it in the temporary area of ​​the FT-C6748 shared RAM;

[0057] Step Six: After receiving the bin file in Step Five, perform checks on the data header, length, checksum, and end. If a check fails, send the message e) Checksum error, please transmit the bin file again. If the check passes, send the message c) Copy the file, please wait...;

[0058] Step 7: After the check in Step 6 passes, copy the temporary area bin file of the FT-C6748 shared RAM to the ordinary SPI FLASH for storage;

[0059] Step 8: After completing Step 7, re-verify the data header, length, checksum, and end of the new DSP bin file stored in the SPI FLASH. If the check fails, send the message e) Checksum error, please transmit the bin file again. If the check passes, clear the programming control flag in the NVSRAM and write it to 0xFFFF.

[0060] Step Nine: After clearing the programming control flag in Step Eight, send the prompt "d)The bin file has been burned complete, restarting..." and notify the FPGA to control the DSP chip's reset pin, causing the DSP chip to reboot, thus completing a reliable online program update process.

[0061] Based on the aforementioned domestically developed FT-C6748 DSP software online upgrade system and method, physical testing was conducted in the project to verify that the strapdown inertial navigation system DSP software did not experience any "burnout" issues. Specific test items are as follows:

[0062] 1) The DSP software's bin file header is incorrect; the software did not recognize the file header and did not proceed with the subsequent software programming process.

[0063] 2) The DSP software bin file has an incorrect length. The software detected the error and did not proceed with the subsequent software programming process.

[0064] 3) The DSP software bin file checksum was incorrect. The software detected the error and did not proceed with the subsequent software programming process.

[0065] 4) The DSP software's bin file has an error at the end. The software detected the error and did not proceed with the subsequent software programming process.

[0066] 5) If the device loses power during the reception of the DSP software bin file, the software does not perform verification or update the programming control flag. When the device is powered on again, the software sends the prompt a) Do you want to burn the flash?

[0067] 6) The DSP software receives the bin file normally and displays the message c) Copy the file, please wait... If the device loses power during this process, the software does not update the programming control flag. When the device is powered on again, the software sends the message a) Do you want to burn the flash?

[0068] 7) During normal DSP software programming, the final message sent is: d) The bin file has been burncomplete, restarting...;

[0069] 8) When sending N without programming, the DSP software automatically restarts and boots, and the software is not updated;

[0070] The above logic test covers the entire process logic, which can completely verify that the method of the present invention does not have the possibility of "burning out". It is a reliable online upgrade method for domestic FT-C6748 DSP software and can be extended to practical engineering applications.

[0071] It should be emphasized that the embodiments described in this invention are illustrative rather than limiting. Therefore, this invention includes, but is not limited to, the embodiments described in the specific implementation. Any other implementations derived by those skilled in the art based on the technical solutions of this invention are also within the scope of protection of this invention.

Claims

1. An online upgrade system for domestically produced FT-C6748 DSP inertial navigation software, characterized in that: It includes a DSP chip, an FPGA chip, an NVSRAM FLASH chip, and an SPI FLASH chip. The DSP chip is connected to an FPGA chip, an NVSRAM FLASH chip, and a regular SPI FLASH chip. The DSP chip is used to run the inertial navigation solution scheme, the FPGA chip is used to acquire the raw pulses of the inertial navigation components and provide reset operations for the DSP chip, the NVSRAM FLASH chip is used to store the calibration parameters of the strapdown inertial navigation scheme and the software programming control flags, and the SPI FLASH chip is used to store the DSP inertial navigation solution software.

2. The domestically produced FT-C6748 DSP software online upgrade system according to claim 1, characterized in that: The DSP chip is an FT-C6748 chip. The 256KB of L2 memory and the first 2MB of shared memory in the DSP chip are used to run the strapdown inertial navigation scheme calculation. The remaining 2MB of shared memory is used as a temporary area to store software update data received from the outside as temporary storage.

3. The online upgrade system for domestically produced FT-C6748 DSP inertial navigation software according to claim 1, characterized in that: The pre-update software file of the inertial navigation calculation software stored in the SPI FLASH chip is updated by adding a data header of 0x7E7E, then adding four bytes of data length, adding a CRC16-bit checksum and one byte at the end, and finally adding a data tail of 0xBF after the checksum.

4. The online upgrade system for domestically produced FT-C6748 DSP inertial navigation software according to claim 1, characterized in that: The DSP chip adds a reset pin function, which allows the inertial navigation calculation software stored in the SPI FLASH chip to send commands to the FPGA chip as needed, and then reset the DSP software to restart and boot.

5. The online upgrade system for domestically produced FT-C6748 DSP inertial navigation software according to claim 1, characterized in that: The NVSRAM FLASH chip used is the RC5NS128K-PSO chip.

6. An upgrade method for an online upgrade system of the domestically produced FT-C6748 DSP inertial navigation software as described in any one of claims 1 to 3, characterized in that: Includes the following steps: Step 1: Power on and run the secondary boot program; Step 2: The DSP software receives the programming command and determines whether the programming control flag written to the NVSRAM FLASH is 0x6666. If it is, proceed to step 2; otherwise, the DSP works normally. Step 3: Check if the header, footer, length, and checksum of the bin file in the ordinary SPI FLASH are correct. If correct, proceed to step 4; otherwise, prompt: you must reply Y to complete a normal programming process or do not accept N, and proceed to step 7. Step 4: Ask if you want to write the FLASH. If the answer is "yes", proceed to step 5; otherwise, proceed to step 7. Step 5: Clear the programming control flags in the NVSRAM FLASH chip; Step 6: The FPGA chip resets the DSP chip by controlling the DSP pins, and the DSP chip continues to work normally. Step 7: Receive external data and store it in a 2MB temporary area in the shared RAM; Step 8: Check if the header, footer, length, and checksum of the bin file are correct. If yes, proceed to step 9; otherwise, issue a prompt and notify the FPGA to control the DSP reset pin to reset the DSP and return to step 2. Step 9: Copy the data in the 2M temporary area of ​​the shared RAM to the ordinary SPI FLASH chip; Step 10: Determine if the data copy is complete. If complete, proceed to Step 11; otherwise, return to Step 10. Step 11: Clear the programming control flag in the NVSRAMFLASH and indicate success.

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