NAND type content addressable memory device and operation method thereof

Abstract

The invention belongs to the field of computer part manufacturing, and particularly discloses an NAND type content addressable memory circuit and an operation method. The circuit comprises an NAND type analog content addressable memory array, a pre-charging circuit and a comparator circuit. The input fixed-point number is compared with the stored fixed-point number bit by bit, a discharge path is formed according to a comparison result, and a word line load capacitor discharges through the path to obtain a corresponding word line voltage; and the voltage is input into the comparator circuit, and finally a data comparison result is output. According to the method, the size comparison of fixed-point numbers can be efficiently realized in parallel, the calculation complexity is greatly reduced, and the calculation rate is improved. In a big data or artificial intelligence application scene needing large-scale data comparison, a large amount of calculation overhead can be saved, and the calculation speed is improved.

Description

Technical Field

[0001] This application belongs to the field of computer component manufacturing, and more specifically, relates to a NAND type content-addressable memory device and its operation method. Background Art

[0002] Content-addressable memory (CAM) is a special type of memory circuit that can quickly and in parallel check whether input data matches stored data and return the matching result. However, in modern computing systems, in addition to checking whether data matches perfectly, there are many scenarios that require comparing the size or order of data, such as data sorting in search engines, threshold determination in decision trees, and sampling and filtering of point cloud data. These scenarios often require comparison of large amounts of data.

[0003] Patent CN2022101181545 discloses a Content Addressable Memory (CAM) device and its data search and comparison method. This technology is a traditional NOR-type CAM, which can achieve parallel data matching, but it can only check whether the data is completely consistent and cannot compare the size of the data. Patent US20050213360A1 discloses a CAM block including a CAM array with multiple rows and columns of 4-bit NAND-type CAM cells. This technology can achieve parallel data matching, but it can only check whether the data is completely consistent and cannot compare the size of the data. The document "CAMPER: Exploring the Potential of Content Addressable Memory for 3D Point Cloud Efficient Range Search" proposes a NAND-type CAM implemented through SRAM. It can compare the size of the data, but it requires 13 transistors, has a high area footprint, and has many input signals, making the operation method more complex and difficult to achieve high-efficiency data search function.

[0004] In summary, existing CAM designs are insufficient for data size comparison. Assigning these tasks to traditional processors would impose a significant computational burden. Therefore, a dedicated circuit structure is needed for these application scenarios to achieve fast and efficient data comparison. Summary of the Invention

[0005] In view of the shortcomings of the prior art, the purpose of this application is to provide a NAND type content-addressable memory device and its operation method, which aims to solve the problem that existing CAMs cannot achieve fast and efficient data comparison.

[0006] To achieve the above objectives, in a first aspect, this application provides a NAND-type content-addressable memory device, comprising: The NAND-type content-addressable memory array consists of several CAM sub-cells arranged in an m-row × n-column structure. The n CAM sub-cells in the same row are connected in series on a word line WL, and the m CAM sub-cells in the same column share the same pair of complementary bit lines. Each CAM sub-cell corresponds to 1 bit of the storage word. The NAND-type content-addressable memory array is used to store m n-bit storage words. When comparing data sizes, the n-bit input word is input to the corresponding n pairs of complementary bit lines. The input word and the storage word are compared bit by bit according to the configured comparison conditions. The comparison result of each bit determines the on / off state of the CAM sub-cell corresponding to its position. The pre-charge circuit is used to charge the word line WL; and forms a discharge path based on the comparison result of the NAND type content addressable memory array. The load capacitor discharges through the discharge path to obtain the corresponding word line voltage, the magnitude of which is determined by the length of the discharge path. The comparator circuit has two ports connected to the word lines WL of two content addressable memory arrays, respectively. It is used to compare the magnitude of the two word line voltages. When there is a difference in the input word line voltage, it outputs a high level, and when the voltages are the same, it outputs a low level. The output result indicates the size relationship between the input word and the stored word. The transmission gate is located between the precharge circuit and the NAND content-addressable memory array, and is used to control the connection / disconnection of the precharge circuit and the NAND content-addressable memory array; The drain of the discharge transistor is connected to the word line WL to set the word line voltage to zero. The two content-addressable memory arrays have the same input word and storage word, but are configured with different comparison conditions.

[0007] Preferably, the CAM subunit consists of four transistors and two memristors; The first transistor is a gate transistor, and its gate is connected to the control gate wire DL; the second transistor is a gate transistor, and its gate is connected to the control gate wire DLB; the sources of the first transistor and the second transistor are connected together, and their connection point is called point X. The third transistor is a write transistor. Its drain is connected to point X, its source is connected to the write signal line WR, and its gate is connected to the write control line WE, which is used to control data writing. The fourth transistor is a word line transistor. Its gate is connected to point X, its source is connected to the left word line WLL, and its drain is connected to the right word line WLR. The left word line WLL is connected to the WLR of the next CAM sub-unit, and the right word line WLR is connected to the WLL of the previous CAM sub-unit. It is used to determine whether the CAM sub-unit is turned on based on the comparison result between the input data and the stored data. The first memristor has its top electrode connected to the bit line BL and its bottom electrode connected to the drain of the first transistor; the second memristor has its top electrode connected to the complementary bit line BLB and its bottom electrode connected to the drain of the second transistor; the data stored in the first and second memristors are combined to form 1 bit of the corresponding stored word.

[0008] It should be noted that this application designs a CAM sub-unit structure that can realize the numerical comparison of fixed-point data in parallel. Compared with the existing CAM designs for data size comparison, this application only requires 4 transistors and 2 memristors, which greatly reduces the number of transistors and the complexity of operating signals, resulting in smaller area overhead and lower power consumption and computational efficiency.

[0009] Preferably, the CAM subunit is configured with any of the following comparison conditions: EQ, GE, LE; wherein, when the comparison condition is EQ, the CAM subunit is turned on when the input value and the stored value are the same; when the comparison condition is GE, the CAM subunit is turned on when the input value is greater than or equal to the stored value; and when the comparison condition is LE, the CAM subunit is turned on when the input value is less than or equal to the stored value.

[0010] Preferably, the most significant bit (MSB) of the storage word Q is stored in the CAM subcell closest to the pre-charge circuit, and the remaining data of the storage word are stored sequentially in the same row of CAM subcells in descending order.

[0011] Preferably, both the input word P and the storage word Q are n-bit fixed-point numbers.

[0012] Preferably, the input word is input to the NAND type content addressable memory array in the form of a voltage. For different comparison conditions, the voltage of the input word is encoded into different values, and the stored word is stored in the memristor in the form of conductance.

[0013] Preferably, the input word and the stored word together determine the voltage of node X:

[0014] The voltages input from BL and BLB are respectively... , The conductance values ​​of the stored word in the first memristor and the second memristor are respectively , .

[0015] Preferably, the pre-charge circuit includes a pre-charge transistor and a load capacitor, wherein the drain of the transistor and the load capacitor are connected in series, and the series connection point is connected to the word line WL through a transmission gate; the pre-charge transistor is used to charge the word line WL to a high level before the NAND content-addressable memory array performs a comparison; the load capacitor is used to discharge through the continuously conducting CAM sub-cell path on the word line WL during the comparison process of the NAND content-addressable memory array, and the word line voltage will reflect the comparison result according to the length of the discharge path.

[0016] To achieve the above objectives, in a second aspect, this application provides a method of operating a NAND-type content-addressable memory device as described in the first aspect, comprising: Data writing: Set DL and DLB to high level to select the corresponding CAM sub-cell, and then write the storage word Q to the memristor in the CAM sub-cell of the corresponding content addressable memory array A and content addressable memory array B simultaneously through BL and BLB. Pre-charge phase: The discharge transistor is turned on, the transmission gate is turned off, and the word line is charged through the pre-charge circuit. At this time, the word line voltage... Rise to high level; Sample and hold phase: Turn off the discharge transistor, set DL and DLB to high level, input word P is simultaneously input to the CAM sub-cells of the corresponding content addressable memory array A and content addressable memory array B through BL and BLB, open the transmission gate, the load capacitor on the pre-charge circuit will discharge through the conducting CAM sub-cells, if the continuously conducting CAM sub-cells form a discharge path, the charge on the load capacitor will be distributed to the CAM sub-cells on the path through this path until an unconducted CAM sub-cell is encountered, the discharge path will be interrupted; Comparison phase: Output voltage of array A and the output voltage of array B Simultaneously input to the comparator circuit, if Greater than If P and Q meet the comparison condition, the comparator circuit outputs a high level; otherwise, the comparator circuit outputs a low level, indicating that P and Q do not meet the comparison condition.

[0017] Preferably, It will satisfy the following formula:

[0018] in, This represents the length of the discharge path, i.e., the number of continuously conducting CAM sub-units. For load capacitance; Parasitic capacitance of the conductor; This represents the voltage value corresponding to a high level.

[0019] Overall, the technical solutions conceived in this application have the following beneficial effects compared with the prior art: (1) This application proposes a NAND-type content-addressable memory device. Data comparison is performed within the CAM sub-cell according to configured comparison conditions. A discharge path is formed based on the comparison result of the NAND-type content-addressable memory array. The load capacitor discharges through the discharge path to obtain the corresponding word line voltage, the magnitude of which is determined by the length of the discharge path. Therefore, efficient fixed-point number comparison can be achieved by detecting the word line voltages of two content-addressable memory arrays with the same input words and storage words but different configured comparison conditions. By sharing a word line among CAM sub-cells in the same column, data can be compared in parallel within the memory, significantly improving the computational speed. This application can not only detect whether data matches but also compare data sizes, saving significant computational overhead and latency in big data or artificial intelligence applications requiring large-scale data comparison.

[0020] (2) This application proposes an operation method for a NAND-type content-addressable memory device, which includes a data writing stage, a pre-charge stage, a sample-and-hold stage, and a comparison stage. Through the above method, data size comparison can be realized, and the comparison result can be output in the form of digital voltage, which can be well adapted to current digital processors. Attached Figure Description

[0021] Figure 1 This is a structural diagram of a NAND-type content-addressable memory device provided in an embodiment of this application.

[0022] Figure 2 This is a circuit diagram of the CAM subunit provided in the embodiments of this application.

[0023] Figure 3 This is a schematic diagram of the voltage and conductance encoding scheme provided in the embodiments of this application.

[0024] Figure 4 This is a schematic diagram of the comparison results provided in the embodiments of this application.

[0025] Figure 5 This is a circuit diagram of a NAND-type content-addressable memory device provided in an embodiment of this application.

[0026] Figure 6 This is a flowchart illustrating an operation method of a NAND-type content-addressable memory device provided in an embodiment of this application.

[0027] Figure 7This is a waveform diagram of the pre-charge and sample-and-hold phases provided in an embodiment of this application.

[0028] Figure 8 This is a schematic diagram illustrating an example of a comparison process 1 performed by a NAND-type content-addressable memory device according to an embodiment of this application.

[0029] Figure 9 This is a simulation waveform diagram of the comparison process 1 of the NAND type content addressable memory execution device provided in the embodiments of this application.

[0030] Figure 10 This is a schematic diagram illustrating an example of the comparison process 2 performed by a NAND-type content-addressable memory device according to an embodiment of this application.

[0031] Figure 11 This is a simulation waveform diagram of the NAND-type content-addressable memory device performing comparison process 2 according to the embodiments of this application.

[0032] In all the accompanying drawings, the same reference numerals are used to denote the same elements or structures, wherein: 10 is a NAND-type content-addressable memory array, 20 is a precharge circuit, 30 is a comparator circuit, 101 is the first transistor, 102 is the second transistor, 103 is the third transistor, 104 is the fourth transistor, 105 is the first memristor, and 106 is the second memristor. Detailed Implementation

[0033] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the scope of this application.

[0034] In this application, the term "and / or" describes the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent three cases: A existing alone, A and B existing simultaneously, and B existing alone. In this application, the symbol " / " indicates that the related objects are in an "or" relationship, for example, A / B means A or B.

[0035] In this application, the terms "first" and "second," etc., are used to distinguish different objects, not to describe a specific order of objects. For example, "first response message" and "second response message," etc., are used to distinguish different response messages, not to describe a specific order of response messages.

[0036] In this application, the term "electrical connection" can refer to a direct circuit connection or a signal transmission via a communication protocol.

[0037] In the embodiments of this application, the terms "exemplary" or "for example" are used to indicate that something is an example, illustration, or description. Any embodiment or design that is described as "exemplary" or "for example" in the embodiments of this application should not be construed as being more preferred or advantageous than other embodiments or designs. Specifically, the use of the terms "exemplary" or "for example" is intended to present the relevant concepts in a specific manner.

[0038] In the description of the embodiments of this application, unless otherwise stated, "multiple" means two or more, for example, multiple processing units means two or more processing units, multiple elements means two or more elements, etc.

[0039] The embodiments of this application are described below with reference to the accompanying drawings.

[0040] like Figure 1 As shown, this application provides a NAND-type content-addressable memory device, including a NAND-type content-addressable memory array 10, a precharge circuit 20, and a comparator circuit 30.

[0041] The NAND-type content-addressable memory array consists of several CAM sub-cells arranged in an m-row × n-column structure. The n CAM sub-cells in the same row are connected in series on a word line WL, and the m CAM sub-cells in the same column share the same pair of complementary bit lines. Each CAM sub-cell corresponds to 1 bit of the storage word. The NAND-type content-addressable memory array is used to store m n-bit storage words. When comparing data sizes, the n-bit input word is input to the corresponding n pairs of complementary bit lines. The input word and the storage word are compared bit by bit according to the configured comparison conditions. The comparison result of each bit determines the on / off state of the CAM sub-cell corresponding to its position.

[0042] The pre-charge circuit is used to pre-charge the word line WL. When the NAND type content addressable memory array is comparing, the voltage on WL will form a discharge path according to the comparison result of data P and Q. The load capacitor discharges through the discharge path to obtain the corresponding word line voltage, the magnitude of which is determined by the length of the discharge path.

[0043] The input ports of the comparator circuit are connected to the word lines of two NAND-type content-addressable memory arrays respectively, and are used to compare the voltages on the two word lines. When there is a difference in the input word line voltage, a high level is output, and when the voltages are the same, a low level is output. The comparison result indicates the size relationship between the input word and the stored word. The input word and the stored word of the two content-addressable memory arrays are the same, but the comparison conditions configured are different.

[0044] The device further includes: a transmission gate S1 located between the precharge circuit and the NAND content addressable memory array, used to control the connection / disconnection of the precharge circuit and the NAND content addressable memory array; and a discharge transistor T6 whose drain is connected to the word line WL, used to set the word line voltage to zero.

[0045] Preferably, the input word P and the storage words Q1, Q2, ..., Q are... m All are n-bit fixed-point numbers.

[0046] Preferably, the pre-charge circuit includes a pre-charge transistor and a capacitor; the pre-charge circuit is electrically connected to the NAND-type content-addressable memory array and the comparator circuit, and is used to charge the word line to a high level before the NAND-type content-addressable memory array performs a comparison; the capacitor connected to the word line WL is used to discharge through the continuously conducting CAM sub-cell path on the word line during the comparison process of the NAND-type content-addressable memory array, and the word line voltage will reflect the comparison result according to the discharge path length.

[0047] Preferably, the comparator circuit consists of a sense amplifier (SA). The SA has two input ports and one output port, used to compare the magnitude relationship between the voltages at the two input ports and reflect the result on the output level.

[0048] like Figure 2 As shown, the CAM subunit consists of four transistors 101, 102, 103, and 104 and two memristors 105 and 106. Specifically, the first transistor 101 is a selection transistor, with its gate connected to the control selection wire DL; the second transistor 102 is a selection transistor, with its gate connected to the control selection wire DLB; the sources of the first transistor 101 and the second transistor 102 are connected together, and this connection point is called point X; the third transistor 103 is a write transistor, with its drain connected to point X, its source connected to the write signal line WR, and its gate connected to the write control line WE, used to control data writing; the fourth transistor 104 is a word line transistor, with its gate connected to point X, its source connected to the left word line WLL, and its drain connected to the right word line W... LR, the left word line WLL is connected to the WLR of the next CAM subunit, and the right word line WLR is connected to the WLL of the previous CAM subunit, used to determine whether the CAM subunit is turned on based on the comparison result of the input data and the stored data; the first memristor 105 has its top electrode connected to the bit line BL and its bottom electrode connected to the drain of the first transistor 101; the second memristor 106 has its top electrode connected to the complementary bit line BLB and its bottom electrode connected to the drain of the second transistor 102; the data stored in the first memristor and the second memristor are combined to form 1 bit of the corresponding stored word.

[0049] Preferably, in this embodiment, the transistors of the CAM sub-unit are metal-semiconductor-oxide field-effect transistors, such as NMOS transistors.

[0050] Preferably, the input data is input from complementary bit lines BL and BLB in the form of voltage signals, and the input voltages are respectively , The stored data is stored in the form of conductance in the first memristor 105 and the second memristor 106, with conductance values ​​of respectively. , .

[0051] Specifically, the comparison process in the CAM sub-unit is as follows: DL and DLB are set to high level, and after selecting the sub-unit, input data is input from BL and BLB. At this time, R1 and R2 will act as a voltage divider, and the input data and stored data will jointly determine the voltage of node X.

[0052] Preferably, the CAM subunit can be configured with three comparison conditions: equal (EQ), greater than or equal to (GE), and less than or equal to (LE). These three conditions correspond to three different voltage encoding schemes. Specific voltage and conductance encoding schemes are as follows: Figure 3 As shown in the diagram. Here, voltages V1 and V2 represent the voltage values ​​input to BL and BLB, respectively, and data 1 and 0 refer to the binary data in the input data P and stored data Q. To search for voltage, A high conductivity value corresponds to the low resistance state of the memristor. A low conductivity value corresponds to the high resistance state of the memristor.

[0053] When the relationship between the input data P and the data stored in the CAM subunit satisfies the aforementioned configured comparison conditions, The voltage value is high voltage. Its voltage is higher than the threshold voltage of the fourth transistor 104, therefore the fourth transistor 104 will conduct; if the condition is not met, For low voltage If the voltage drops below the threshold voltage, the fourth transistor 104 will turn off. Specific comparison results are as follows: Figure 4 As shown. For example, when the setting condition is EQ, the input value and the stored value must be the same; therefore, Vx can only reach a high voltage when both the input and the stored value are 1. The CAM subunit is in a "pass" state (i.e., it is on) if it is in the "pass" state, otherwise it will be in a "no pass" state and cannot be on. Similarly, when the setting condition is GE, the input value must be greater than or equal to the stored value for the CAM subunit to be in the "pass" state; when the setting condition is LE, the input value must be less than or equal to the stored value for the CAM subunit to be in the "pass" state.

[0054] Furthermore, Figure 5 This demonstrates the circuit design of a NAND content-addressable memory array, a precharge circuit, and a sensitive amplifier. Specifically, n CAM sub-cells are connected in series on the word line WL, forming a row of CAM sub-cell arrays. Where C... L C1 is the parasitic capacitance of the conductor, S1 is the load capacitance, T5 is the transmission gate, T6 is the charging transistor, T6 is the discharging transistor, and SA is the sensitive amplifier. The stored word Q needs to be stored sequentially from the most significant bit (MSB) to the least significant bit (LSB) into the corresponding CAM sub-cells from right to left. To compare the magnitudes of the input word P and the stored word Q, the sensitive amplifier needs to be connected to two CAM arrays simultaneously: one end to array A and the other to array B. The input data P and the stored data Q are the same for arrays A and B, but A and B are configured with different comparison conditions; therefore, the input voltages of the two arrays will be different.

[0055] like Figure 6 As shown, this application provides an operation method for the aforementioned NAND-type content-addressable memory device, which consists of four stages: Data writing: Set DL and DLB to high level to select the corresponding CAM sub-cell, and then write the storage word Q into the memristor in the CAM sub-cell of the corresponding content addressable memory array A and content addressable memory array B through the programming signals of complementary bit lines BL and BLB.

[0056] Pre-charge phase: Pre-charge transistor T5 and discharge transistor T6 are turned on, transmission gate S1 is turned off, and load capacitor C1 is charged through pre-charge transistor T5. At this time, the word line voltage... Rise to high level VDD.

[0057] Sample and Hold Phase: The pre-charge transistor T5 and discharge transistor T6 are turned off. Then, DL and DLB are set high, and the input data P is input to the CAM sub-cell through BL and BLB. Then, transmission gate S1 is opened, and the load capacitor C1 discharges through the conducting CAM sub-cells. If consecutively conducting CAM sub-cells are connected, they form a discharge path, and the charge on C1 is distributed to the CAM sub-cells along this path until an unconducted CAM sub-cell is encountered, at which point the discharge path is interrupted. The number of consecutively conducting CAM sub-cells is called the discharge path length. , The larger the value, the greater the degree of discharge. The smaller it is, the less likely it is to be. It will satisfy the following formula:

[0058] Comparison phase: Output voltage of array A and the output voltage of array B Simultaneously input to the comparator circuit, if Greater than The comparator circuit outputs a high level, indicating that P and Q meet the comparison condition; if equal If the comparator circuit outputs a low level, it indicates that P and Q do not meet the comparison condition.

[0059] Figure 7 The waveform diagrams for the precharge and sample-and-hold phases are shown. During the precharge phase, the word line voltage... It will be charged to a high level VDD, and during the sample-and-hold phase, The charge will be discharged gradually according to the length of the discharge path. The longer the path, the lower the final discharge voltage.

[0060] This embodiment illustrates an example of the function of the NAND-type content-addressable memory provided in this application for detecting whether P is greater than Q.

[0061] like Figure 8 As shown, P and Q are both 8-bit fixed-point numbers. The input value P is 11010010, and the stored value Q is 11000110, at which point P > Q. Array A is configured with "EQ" condition, while array B is configured with "GE" condition. During comparison, from the most significant bit (MSB) to the least significant bit (LSB), CAM sub-cells that meet the conditions will be in the "pass" state, i.e., turned on. If any bit in the discharge path does not meet the conditions, the CAM sub-cell will be in the "no pass" state, and the charge discharge path will be interrupted. Array A is used to compare whether each bit of P and Q is equal, while array B is used to compare whether each bit of P is greater than or equal to Q. When P > Q, the lengths of the two discharge paths of array A and array B will be inconsistent; the path length of array B will be greater than that of array A. This makes... greater than SA's output SA OUT For high level, such as Figure 9 As shown.

[0062] like Figure 10As shown, if the input value P is 11010010 and the stored value Q is 11000110, then P < Q at this time. Array A is configured with the "EQ" condition, while array B is configured with the "GE" condition. When P ≤ Q, the discharge paths of array A and array B will be the same, and at this time will be equal to , and SA will output a low level, as Figure 11 shown.

[0063] It should be understood that the above device is used to execute the method in the above embodiment. For the corresponding program modules in the device, their implementation principles and technical effects are similar to those described in the above method. The working process of this device can refer to the corresponding process in the above method and will not be elaborated here.

[0064] Based on the method in the above embodiment, an embodiment of the present application provides an electronic device, which may include: a processor (Processor), a communication interface (Communications Interface), a memory (Memory), and a communication bus. Among them, the processor, the communication interface, and the memory complete mutual communication through the communication bus. The processor can call the logical instructions in the memory to execute the method in the above embodiment.

[0065] In addition, when the logical instructions in the above memory are implemented in the form of a software functional unit and sold or used as an independent product, they can be stored in a computer-readable storage medium. Based on such an understanding, the technical solution of the present application, in essence, or the part that contributes to the prior art, or a part of this technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions for causing a computer device (which may be a personal computer, a server, or a network device, etc.) to execute all or part of the steps of the methods described in various embodiments of the present application.

[0066] Based on the method in the above embodiment, an embodiment of the present application provides a computer-readable storage medium. The computer-readable storage medium stores a computer program. When the computer program runs on a processor, it causes the processor to execute the method in the above embodiment.

[0067] Based on the method in the above embodiment, an embodiment of the present application provides a computer program product. When the computer program product runs on a processor, it causes the processor to execute the method in the above embodiment.

[0068] It is understood that the processor in the embodiments of this application can be a central processing unit (CPU), or other general-purpose processors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), or other programmable logic devices, transistor logic devices, hardware components, or any combination thereof. A general-purpose processor can be a microprocessor or any conventional processor.

[0069] The method steps in this application embodiment can be implemented in hardware or by a processor executing software instructions. The software instructions can consist of corresponding software modules, which can be stored in random access memory (RAM), flash memory, read-only memory (ROM), programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), registers, hard disks, portable hard disks, CD-ROMs, or any other form of storage medium known in the art. An exemplary storage medium is coupled to the processor, enabling the processor to read information from and write information to the storage medium. Of course, the storage medium can also be a component of the processor. The processor and the storage medium can reside in an ASIC.

[0070] In the above embodiments, implementation can be achieved entirely or partially through software, hardware, firmware, or any combination thereof. When implemented using software, it can be implemented entirely or partially as a computer program product. The computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on a computer, all or part of the processes or functions described in the embodiments of this application are generated. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. The computer instructions can be stored in a computer-readable storage medium or transmitted through the computer-readable storage medium. The computer instructions can be transmitted from one website, computer, server, or data center to another website, computer, server, or data center via wired (e.g., coaxial cable, fiber optic, digital subscriber line (DSL)) or wireless (e.g., infrared, wireless, microwave, etc.) means. The computer-readable storage medium can be any available medium that a computer can access or a data storage device such as a server or data center that integrates one or more available media. The available medium can be a magnetic medium (e.g., floppy disk, hard disk, magnetic tape), an optical medium (e.g., DVD), or a semiconductor medium (e.g., solid-state disk (SSD)).

[0071] It is understood that the various numerical designations used in the embodiments of this application are merely for the convenience of description and are not intended to limit the scope of the embodiments of this application.

[0072] Those skilled in the art will readily understand that the above description is merely a preferred embodiment of this application and is not intended to limit this application. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this application should be included within the scope of protection of this application.

Claims

1. A NAND-type content-addressable memory device, characterized in that, include: The NAND-type content-addressable memory array consists of several CAM sub-cells arranged in an m-row × n-column structure. The n CAM sub-cells in the same row are connected in series on a word line WL, and the m CAM sub-cells in the same column share the same pair of complementary bit lines. Each CAM sub-cell corresponds to 1 bit of the storage word. The NAND-type content-addressable memory array is used to store m n-bit storage words. When comparing data sizes, the n-bit input word is input to the corresponding n pairs of complementary bit lines. The input word and the storage word are compared bit by bit according to the configured comparison conditions. The comparison result of each bit determines the on / off state of the CAM sub-cell corresponding to its position. The pre-charge circuit is used to charge the word line WL; and forms a discharge path based on the comparison result of the NAND type content addressable memory array. The load capacitor discharges through the discharge path to obtain the corresponding word line voltage, the magnitude of which is determined by the length of the discharge path. The comparator circuit has two ports connected to the word lines WL of two content addressable memory arrays, respectively. It is used to compare the magnitude of the two word line voltages. When there is a difference in the input word line voltage, it outputs a high level, and when the voltages are the same, it outputs a low level. The output result indicates the size relationship between the input word and the stored word. The transmission gate is located between the precharge circuit and the NAND content-addressable memory array, and is used to control the connection / disconnection of the precharge circuit and the NAND content-addressable memory array; The drain of the discharge transistor is connected to the word line WL to set the word line voltage to zero. The two content-addressable memory arrays have the same input word and storage word, but are configured with different comparison conditions.

2. The apparatus as claimed in claim 1, characterized in that, The CAM subunit consists of four transistors and two memristors; The first transistor (101) is a gate transistor, and its gate is connected to the control gate wire DL; the second transistor (102) is a gate transistor, and its gate is connected to the control gate wire DLB; the sources of the first transistor (101) and the second metal-oxide-semiconductor transistor (102) are connected together, and their connection point is called point X; The third transistor (103) is a write transistor. Its drain is connected to point X, its source is connected to the write signal line WR, and its gate is connected to the write control line WE. It is used to control data writing. The fourth transistor (104) is a word line transistor. Its gate is connected to point X, its source is connected to the left word line WLL, and its drain is connected to the right word line WLR. The left word line WLL is connected to the WLR of the next CAM sub-unit, and the right word line WLR is connected to the WLL of the previous CAM sub-unit. It is used to determine whether the CAM sub-unit is turned on based on the comparison result between the input data and the stored data. The first memristor (105) has its top electrode connected to the bit line BL and its bottom electrode connected to the drain of the first transistor (101); the second memristor (106) has its top electrode connected to the complementary bit line BLB and its bottom electrode connected to the drain of the second transistor (102); the data stored in the first memristor and the second memristor are combined to form 1 bit of the corresponding stored word.

3. The apparatus as described in claim 2, characterized in that, The CAM subunit is configured with any of the following comparison conditions: EQ, GE, LE; wherein, when the comparison condition is EQ, the CAM subunit is turned on when the input value and the stored value are the same; when the comparison condition is GE, the CAM subunit is turned on when the input value is greater than or equal to the stored value; and when the comparison condition is LE, the CAM subunit is turned on when the input value is less than or equal to the stored value.

4. The apparatus as claimed in claim 2, characterized in that, The most significant bit (MSB) of the storage word Q is stored in the CAM subcell closest to the precharge circuit, and the remaining data of the storage word is stored sequentially in the same row of CAM subcells from high to low.

5. The apparatus as described in claim 2, characterized in that, Both the input word P and the storage word Q are n-bit fixed-point numbers.

6. The apparatus as claimed in claim 2, characterized in that, The input word is input to the NAND type content addressable memory array in the form of voltage. For different comparison conditions, the voltage of the input word is encoded into different values, and the stored word is stored in the memristor in the form of conductance.

7. The apparatus as claimed in claim 6, characterized in that, The input word and the stored word together determine the voltage of node X: The voltages input from BL and BLB are respectively... , The conductance values ​​of the stored word in the first memristor and the second memristor are respectively , .

8. The apparatus as claimed in claim 2, characterized in that, The pre-charge circuit includes a pre-charge transistor (T5) and a load capacitor (C1). The drain of the transistor and the load capacitor are connected in series, and the series connection point is connected to the word line WL through a transmission gate (S1). The pre-charge transistor is used to charge the word line WL to a high level before the NAND content-addressable memory array performs a comparison. The load capacitor is used to discharge through the continuously conducting CAM sub-cell path on the word line WL during the comparison process of the NAND content-addressable memory array. The word line voltage will reflect the comparison result according to the length of the discharge path.

9. A method of operating a NAND-type content-addressable memory device as described in any one of claims 2 to 8, characterized in that, include: Data writing: Set DL and DLB to high level to select the corresponding CAM sub-cell, and then write the storage word Q to the memristor in the CAM sub-cell of the corresponding content addressable memory array A and content addressable memory array B simultaneously through BL and BLB. Pre-charge stage: Turn on the discharge transistor (T6), close the transmission gate (S1), and charge the word line through the pre-charge circuit. At this time, the word line voltage... Rise to high level; Sample and hold phase: Turn off the discharge transistor (T6), set DL and DLB to high level, input word P is simultaneously input to the CAM sub-cells of the corresponding content addressable memory array A and content addressable memory array B through BL and BLB, open the transmission gate (S1), the load capacitor on the pre-charge circuit will discharge through the conducting CAM sub-cells, if the continuously conducting CAM sub-cells will form a discharge path, the charge on the load capacitor will be distributed to the CAM sub-cells on the path through this path until an unconducted CAM sub-cell is encountered, the discharge path will be interrupted; Comparison phase: Output voltage of array A and the output voltage of array B Simultaneously input to the comparator circuit, if Greater than If the condition is met, the comparator circuit outputs a high level, indicating that P and Q meet the comparison condition; otherwise, the comparator circuit outputs a low level, indicating that P and Q do not meet the comparison condition.

10. The operating method as described in claim 9, characterized in that, It will satisfy the following formula: in, This represents the length of the discharge path, i.e., the number of continuously conducting CAM sub-units. For load capacitance; Parasitic capacitance of the conductor; This represents the voltage value corresponding to a high level.

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