Deep through silicon via preparation method, integrated chip preparation method and integrated chip

Abstract

The invention discloses a deep silicon through hole preparation method, an integrated chip preparation method and an integrated chip, and relates to the technical field of semiconductor manufacturing. The deep through silicon via preparation method comprises the following steps: depositing silicon oxide on the upper surface of a silicon interposer of a wafer to form a silicon oxide film; coating photoresist on the upper surface of the silicon oxide film, and exposing and developing the photoresist through a preset through hole mask to expose a through hole area; etching the silicon oxide thin film and the silicon interposer in the through hole region in the etching process cavity through a dry etching process to form a deep silicon through hole; and removing the residual photoresist and silicon oxide film in the etching process cavity through a dry etching process. Through the technical means, the photoresist and the silicon oxide film are directly removed in the etching process cavity by adopting the dry etching process after the through hole is etched, and a wafer does not need to be transferred to other process tables, so that the preparation process flow of the deep through silicon via is simplified, and the preparation efficiency of the deep through silicon via is improved.

Description

Technical Field

[0001] This application relates to the field of chip fabrication technology, and in particular to a method for fabricating deep silicon vias, a method for fabricating integrated chips, and an integrated chip. Background Technology

[0002] With the development of semiconductor processes and the limitations of Moore's Law, the cost of simply relying on process technology to improve performance has skyrocketed. Meanwhile, the development of technologies such as high-performance computing, artificial intelligence, and robotics has presented new challenges to chip integration density, bandwidth, and energy efficiency. Based on this, more companies are using advanced packaging technologies, namely heterogeneous integration technology. The core of heterogeneous integration technology is the introduction of silicon interpose (SIP) and through-silicon via (TSV) technology to achieve 2.5D stacking of multiple chips. TSV technology is a three-dimensional packaging technology in the field of integrated circuits, achieving efficient interconnection of multiple layers of chips through vertical through-holes in silicon wafers, significantly improving the performance of integrated circuits and reducing package size.

[0003] In existing technologies, deep silicon vias (TSVs) are etched into silicon wafers using photolithography and dry etching processes. Then, residual photoresist and hard mask on the wafer surface are removed sequentially using resist stripping and wet etching processes, thus completing the fabrication of the TSVs. Metal materials can then be filled into the TSVs to form metal interconnects connecting multilayer chips. Current TSV technologies involve hard mask deposition, photolithography, dry etching, resist stripping, and wet etching processes, making the entire process relatively complex and impacting the fabrication efficiency of TSVs. Summary of the Invention

[0004] This application provides a method for fabricating deep silicon vias, an integrated chip fabrication method, and an integrated chip. After etching the deep silicon vias, the photoresist and silicon oxide film can be removed directly in the etching process cavity using a dry etching process, smoothly removing the photoresist removal process and wet process. There is no need to transfer the wafer to other process stations, which simplifies the fabrication process of deep silicon vias and improves the fabrication efficiency of deep silicon vias.

[0005] In a first aspect, this application provides a method for fabricating deep silicon vias, comprising the following steps: Step 1: Deposit silicon oxide on the surface of the silicon interposer layer of the wafer to form a silicon oxide thin film; Step 2: Coat the surface of the silicon oxide film with photoresist, and expose and develop the photoresist through a preset through-hole mask to expose the through-hole area; Step 3: Etch the silicon oxide film and silicon interlayer in the via region using a dry etching process within the etching chamber to form a deep silicon via; Step 4: Remove the remaining photoresist and silicon oxide film using a dry etching process within the etching process chamber.

[0006] Optionally, the first process gas used in the dry etching process for removing the photoresist in step four includes oxygen, nitrogen trifluoride, helium, and argon.

[0007] Optionally, the flow rate of oxygen in the first process gas is 20~300 sccm, the flow rate of nitrogen trifluoride is 0~100 sccm, the flow rate of helium is 0~400 sccm, and the flow rate of argon is 10~150 sccm.

[0008] Optionally, the dry etching process for the photoresist in step four uses a cavity pressure of 5~100mT, a TCP upper electrode power of 200~1200W, a lower electrode bias voltage of 0~1500V, and a process time of 10~200s.

[0009] Optionally, the second process gas used in the dry etching process of the silicon oxide thin film in step four includes trifluoromethane, carbon tetrafluoride, nitrogen trifluoride, argon, helium, and difluoromethane.

[0010] Optionally, the ratio of the total flow rate of the trifluoromethane, the carbon tetrafluoride, and the nitrogen trifluoride to the flow rate of the helium is 1:1.

[0011] Optionally, the flow rate of trifluoromethane in the second process gas is 20~180 sccm, the flow rate of carbon tetrafluoride is 0~300 sccm, the flow rate of nitrogen trifluoride is 0~150 sccm, the flow rate of argon is 30~240 sccm, the flow rate of helium is 20~400 sccm, and the flow rate of difluoromethane is 50~200 sccm.

[0012] Optionally, the dry etching process for the silicon oxide thin film in step four uses a chamber pressure of 5~60mT, a TCP upper electrode power of 600~2000W, a lower electrode bias voltage of 40~350V, and a process time of 40~350s.

[0013] Secondly, this application provides an integrated chip fabrication method, including the deep silicon via fabrication method described in the first aspect.

[0014] Thirdly, this application provides an integrated chip, which is prepared using the integrated chip fabrication method described in the second aspect.

[0015] In this application, silicon oxide is deposited on the upper surface of a silicon interposer on a wafer to form a silicon oxide thin film; photoresist is coated on the upper surface of the silicon oxide thin film, and the photoresist is exposed and developed using a pre-set via mask to expose the via region; the silicon oxide thin film and silicon interposer in the via region are etched using a dry etching process within an etching chamber to form a deep silicon via; and the remaining photoresist and silicon oxide thin film are removed using a dry etching process within the etching chamber. Through the above technical means, after the deep silicon via etching is completed within the etching chamber, a process gas that can react with the photoresist and silicon oxide thin film can be directly introduced into the etching chamber to perform dry etching on the remaining photoresist and silicon oxide thin film. This achieves the removal of photoresist and silicon oxide thin film within the etching chamber, eliminating the need to transfer the wafer to other process stages, simplifying the deep silicon via fabrication process and improving the fabrication efficiency of deep silicon vias. Furthermore, the process gas contains fluoride ions, which can react with the silicon interlayer at a lower rate than the silicon oxide film. This allows the upper opening of the deep silicon via to be etched into a trumpet-shaped opening, expanding the upper cross-section of the via and facilitating subsequent filling with metal materials, thereby improving the filling efficiency of the metal materials. Attached Figure Description

[0016] Figure 1 This is a flowchart of a deep silicon through-hole fabrication method provided in an embodiment of this application; Figure 2 This is a schematic cross-sectional view of a wafer after silicon oxide deposition, provided in an embodiment of this application. Figure 3 This is a cross-sectional schematic diagram of the wafer coating and photoresist exposure and development process provided in the embodiments of this application; Figure 4 This is a schematic cross-sectional view of a wafer after etching deep silicon vias, provided in an embodiment of this application. Figure 5 This is a cross-sectional view of a wafer after the photoresist has been removed, as provided in an embodiment of this application. Figure 6 This is a schematic cross-sectional view of the wafer after the silicon oxide film has been removed, as provided in an embodiment of this application. Figure 7 This is a schematic diagram of the morphology of the deep silicon via provided in an embodiment of this application; Figure 8 This is a cross-sectional schematic diagram of two adjacent chip layers provided in an embodiment of this application; In the diagram, 10 is the first chip layer; 11 is the silicon interposer; 12 is the photoresist; 13 is the silicon oxide film; 14 is the opening; 15 is the deep silicon via; 16 is the metal wire; and 20 is the second chip layer. Detailed Implementation

[0017] To make the objectives, technical solutions, and advantages of this application clearer, specific embodiments of this application will be described in further detail below with reference to the accompanying drawings. It should be understood that the specific embodiments described herein are merely for explaining this application and not for limiting it. It should also be noted that, for ease of description, only the parts relevant to this application are shown in the drawings, not all of them. Before discussing exemplary embodiments in more detail, it should be mentioned that some exemplary embodiments are described as processes or methods depicted as flowcharts. Although the flowcharts describe operations (or steps) as sequential processes, many of these operations can be performed in parallel, concurrently, or simultaneously. Furthermore, the order of the operations can be rearranged. A process can be terminated when its operation is completed, but it may also have additional steps not included in the drawings. A process can correspond to a method, function, procedure, subroutine, subprogram, etc.

[0018] The terms "first," "second," and the like in the specification and claims of this application are used to distinguish similar objects, and are not used to describe a specific order or precedence. It should be understood that the terms used in this manner are interchangeable where appropriate, so that the embodiments of this application can be implemented in an order other than that illustrated or described herein, and that the objects distinguished by "first," "second," and the like are generally of the same type, and do not limit the number of objects; for example, the first object can be one or more. In addition, the term "and / or" in the specification and claims refers to at least one of the connected objects, and the character " / " generally indicates that the objects connected are in an "or" relationship.

[0019] In a common existing implementation, deep silicon vias are etched into the silicon wafer using photolithography and dry etching processes. Then, a wet photoresist removal process is used to remove residual photoresist from the silicon wafer surface. Specifically, the silicon wafer is placed in a reaction tank to utilize the sulfuric acid within the tank. ) and hydrogen peroxide ( The photoresist is removed using a mixed solution. After photoresist removal, a wet process is used to remove the residual silicon oxide hard mask on the silicon wafer surface. Similarly, the silicon wafer is placed in a reaction tank to remove the silicon oxide hard mask using a hydrofluoric acid (HF) solution within the tank. However, the preceding process for removing the photoresist and silicon oxide hard mask is etching deep silicon vias. That is, after etching deep silicon vias in the etching process chamber, the silicon wafer must be transferred to a solution containing sulfuric acid (HF). ) and hydrogen peroxide ( The photoresist is removed from the silicon wafer in a reaction tank containing a mixed solution. Because the chemical solutions for removing photoresist and silicon oxide are different, the removal processes cannot be completed in the same reaction tank. Therefore, after removing the photoresist, the silicon wafer must be transferred to a reaction tank containing hydrofluoric acid solution to remove the silicon oxide. In other words, after etching the vias, the silicon wafer must be transferred twice to remove both photoresist and silicon oxide before the deep silicon via fabrication is complete. This makes the deep silicon via process complex and affects its fabrication efficiency. Furthermore, if the integrated circuit requires multi-layer chip packaging, the deep silicon vias used to fill metal between every two chip layers must undergo the above process steps, which undoubtedly increases the complexity of integrated circuit fabrication and affects its overall fabrication efficiency.

[0020] To address the aforementioned issues, this embodiment provides a method for fabricating deep silicon vias (TSVs), an integrated chip fabrication method, and an integrated chip. This method allows for the direct removal of photoresist and silicon oxide films via a dry etching process within the etching chamber after etching the TSVs, smoothly eliminating the need for photoresist removal and wet etching processes. It also eliminates the need to transfer the wafer to other process stages, simplifying the TSV fabrication process and improving the fabrication efficiency of both TSVs and integrated chips.

[0021] Figure 1 A flowchart of a deep silicon via fabrication method provided in an embodiment of this application is given. Figure 1 As shown, the method for fabricating deep silicon vias includes: S110. Deposit silicon oxide on the surface of the silicon interposer layer of the wafer to form a silicon oxide thin film.

[0022] The silicon interposer 11 serves as the dielectric layer between multiple layers of chips in an integrated circuit, and this dielectric layer is made of silicon. A deep silicon via 15 is essentially formed by etching the silicon interposer 11 to connect the upper and lower chip layers. Subsequently, copper or other metal materials can be deposited within the deep silicon via 15 to form metal wires 16. These metal wires 16 connect the upper and lower chip layers to achieve conductive connections between the multiple chip layers in the integrated circuit. For example, silicon material can be deposited on the first chip 10 to form the silicon interposer 11, and then the upper surface of the silicon interposer 11 can be smoothed using a mechanical polishing process. Then, silicon oxide material is deposited on the smoothed surface of the silicon interposer 11 to form a silicon oxide film 13. The silicon oxide film 13 acts as a hard mask to protect non-via areas during the etching of the deep silicon via 15, improving the etching accuracy of the deep silicon via 15.

[0023] Optionally, silicon oxide can be deposited on the silicon interposer 11 using chemical vapor deposition (CVD) to form a silicon oxide thin film 13. Specifically, the wafer is placed in a CVD reaction chamber, and + / reaction gases are introduced to deposit silicon oxide at a relatively low temperature (300°C - 450°C). Although thermal oxidation can also be used to grow silicon oxide on the surface of the silicon interposer 11, thermal oxidation requires a high growth temperature, resulting in diffused doping impurities in the silicon wafer. Moreover, thermal oxidation has a low growth rate and high process complexity, and the resulting silicon oxide has a high structural density that is not easy to remove later. Therefore, chemical vapor deposition can rapidly deposit the silicon oxide thin film 13, improving the deposition efficiency of the silicon oxide thin film 13 while simplifying the subsequent removal operation, which helps to improve the preparation efficiency of deep vias.

[0024] Figure 2 This is a schematic cross-sectional view of a wafer after silicon oxide deposition, as provided in an embodiment of this application. Figure 2 As shown, after forming a silicon interposer 11 on the first chip 10, silicon oxide is deposited on the upper surface of the silicon interposer 11 to form a silicon oxide thin film 13.

[0025] S120. Photoresist is coated on the surface of a silicon oxide film, and the photoresist is exposed and developed through a preset through-hole mask to expose the through-hole area.

[0026] For example, a positive photoresist 12 is coated on the entire upper surface of the silicon oxide thin film 13. After aligning the wafer with the via mask, ultraviolet light is irradiated onto the photoresist 12 through the via mask. The photoresist 12 located in the via region on the wafer becomes soluble. After dissolving the soluble photoresist 12 with a chemical solution, the via region of the wafer is exposed. The via region is the area on the upper surface of the wafer where the deep silicon vias 15 are to be etched. Since the photoresist 12 is a positive photoresist that becomes soluble upon exposure, the light-transmitting pattern on the via mask is the pattern of the via region.

[0027] For example, Figure 3 This is a cross-sectional schematic diagram of the wafer coating and photoresist exposure and development process 12 provided in the embodiments of this application. Figure 3 As shown in (a) and (b), a layer of photoresist 12 is coated on the upper surface of the silicon oxide film 13, and then the photoresist 12 is exposed and dissolved through a via mask. The photoresist 12 in the via region is removed to form an opening 14, so that the silicon oxide film 13 in the via region is exposed on the wafer surface.

[0028] S130. The silicon oxide film and silicon interlayer in the via region are etched by a dry etching process within the etching process chamber to form a deep silicon via.

[0029] For example, after dissolving the exposed photoresist 12 on the wafer using a chemical solution, the wafer exposes the underlying silicon oxide film 13 in the via region. The wafer is then placed in an etching chamber, where a reactive gas is introduced. The reactive gas reacts with the silicon oxide and silicon to etch the silicon oxide film 13 and the silicon interposer 11 not covered by the photoresist 12. The process duration of the dry etching process is controlled so that the silicon interposer 11 is etched through to form a deep silicon via 15 that contacts the bottom of the first chip 10.

[0030] Figure 4 This is a schematic cross-sectional view of the wafer after etching the deep silicon via 15, as provided in an embodiment of this application. Figure 4 As shown, during the process of etching the deep silicon via 15 using a dry etching process, the silicon oxide thin film 13 and silicon interposer 11 under the opening 14 of the wafer are vertically etched, and a vertical structure is formed at the opening 14 and contacts the deep silicon via 15 of the first layer chip 10.

[0031] S140. Remove the remaining photoresist and silicon oxide film using a dry etching process within the etching process chamber.

[0032] refer to Figure 4 After etching the deep silicon via 15, photoresist 12 and silicon oxide film 13 remain on the wafer surface. The fabrication process of the deep silicon via 15 is only complete after removing the photoresist 12 and silicon oxide film. To simplify the fabrication process of the deep silicon via 15, the remaining photoresist 12 and silicon oxide film 13 can be removed directly within the etching process chamber of the deep silicon via 15 using a dry etching process.

[0033] For example, a first process gas that can react with the photoresist 12 can be introduced into the etching process chamber to remove the residual photoresist 12 on the wafer surface. Figure 5 This is a cross-sectional view of the wafer after the photoresist 12 has been removed, as provided in an embodiment of this application. Figure 5 As shown, after removing the residual photoresist 12 on the wafer surface, the upper surface of the wafer is covered with a silicon oxide film 13, and the remaining silicon oxide film 13 can then be removed by a dry etching process in the etching process chamber.

[0034] Optionally, the first process gas used in the dry etching process for removing photoresist 12 in S140 includes ( Nitrogen trifluoride ( ), helium ( ) and argon ( Oxygen is the main gas that reacts chemically with photoresist 12. The main components of photoresist 12 include resin, solvent, and photoinitiator, and it is primarily composed of organic matter, with C, H, and O as its main components. Oxygen is excited in the plasma generator to produce high-energy oxygen plasma. This high-energy oxygen plasma reacts with the organic materials in photoresist 12, oxidizing and decomposing it into carbon monoxide (CO), carbon dioxide (C), and water vapor (O). Finally, a vacuum system extracts the product from the etching chamber to avoid contaminating the chip and interfering with subsequent processes. Helium, argon, and nitrogen trifluoride serve as auxiliary gases and do not directly participate in the chemical reaction of etching photoresist 12. Argon focuses on physical bombardment to enhance the chemical activity of the reactant gases, while helium focuses on thermal conduction to improve etching uniformity. Nitrogen trifluoride generates active fluorine radicals through plasma dissociation, which efficiently remove carbon-based or carbon-based deposits accumulated in the reaction chamber.

[0035] Furthermore, the flow rates of oxygen, nitrogen trifluoride, helium, and argon in the first process gas are 20-300 sccm, 0-100 sccm, 0-400 sccm, and 10-150 sccm, respectively. That is, oxygen, as the primary gas reacting chemically with photoresist 12, must have a flow rate greater than or equal to 20 sccm. A higher oxygen flow rate results in a faster removal rate of photoresist 12, and the oxygen flow rate can be set according to actual needs. Nitrogen trifluoride and helium serve for cleaning and heat conduction, and are not the preferred choice for photoresist 12 removal; photoresist 12 can be removed normally even without introducing nitrogen trifluoride and helium. The physical bombardment brought by the introduced argon gas selectively etches the photoresist 12; therefore, at least 10 sccm of argon gas is introduced.

[0036] In the dry etching process for removing photoresist 12 in S140, the chamber pressure is 5~100mT, the upper electrode power of the TCP is 200~1200W, the lower electrode bias voltage is 0~1500V, and the process time is 10~200s. In this dry etching process, a first process gas is injected into the etching process chamber via a plasma generator. The chamber pressure is maintained at 5~100mT, the upper electrode power of the plasma generator is maintained at 200~1200W, the lower electrode bias voltage is maintained at 0~1500V, and the process time for removing photoresist 12 is maintained at 10~200s.

[0037] Secondly, after removing the photoresist 12, the chemical gas generated in the etching process chamber after removing the photoresist 12 is vented to avoid the chemical gas affecting the subsequent removal process of the silicon oxide film 13. Then, a second process gas that can react with silicon oxide is introduced into the etching process chamber to remove the residual silicon oxide film 13 on the wafer surface. Figure 6 This is a cross-sectional view of the wafer after the silicon oxide film 13 has been removed, as provided in an embodiment of this application. Figure 6 As shown, after removing the residual silicon oxide film 13 on the wafer surface, the upper surface of the wafer is a silicon interposer 11 for forming deep silicon vias 15.

[0038] Optionally, the second process gas used in the dry etching process for removing the silicon oxide film 13 in S140 includes trifluoromethane ( Carbon tetrafluoride () Nitrogen trifluoride ( ), argon, helium and difluoromethane ( In this process, carbon tetrafluoride and trifluoromethane are excited to produce fluoride ions in the plasma generator. These fluoride ions react chemically with silicon oxide to generate silicon fluoride and oxygen. Trifluoromethane is excited to produce hydrogen ions in the plasma generator, which combine with the fluoride ions to generate hydrogen fluoride, thereby suppressing the concentration of fluoride free radicals and controlling the effect on the silicon oxide thin film 13. The etching rate of the silicon interposer 11 (Si) is adjusted to avoid over-etching of the silicon interposer 11 when removing the silicon oxide film 13. The remaining nitrogen trifluoride, argon, helium and difluoromethane serve as auxiliary gases, providing cleaning, physical bombardment, thermal conduction and polymer protection, respectively.

[0039] Furthermore, the total flow rate of trifluoromethane, carbon tetrafluoride, and nitrogen trifluoride is in a 1:1 ratio to the flow rate of helium. + + When the ratio is 1:1, The choice of Si is relatively high to avoid over-etching the underlying silicon interposer 11 when etching the silicon oxide film. It should be noted that fluoride ions will still react with silicon ions in the silicon interposer 11. Therefore, when etching the silicon oxide film 13, the sidewalls at the upper end of the deep silicon via 15 are etched because they are not covered by silicon oxide. However, hydrogen ions inhibit the reaction between silicon and fluoride ions, thereby reducing the etching rate of the sidewalls at the upper end of the deep silicon via 15. This results in only the sidewalls at the upper end of the deep silicon via 15 being etched from a vertical structure to an inclined structure after the silicon oxide film 13 is completely removed. Figure 7 This is a schematic diagram of the morphology of a deep silicon via provided in an embodiment of this application. (Reference) Figure 6 and Figure 7 During the etching of the silicon oxide thin film 13, the sidewall at the upper end of the deep silicon via 15 is etched by fluorine ions to form a slope, and the upper end of the deep silicon via 15 forms a trumpet opening 14, which expands the upper cross-section of the deep via. This improves the convenience of subsequent filling with metal materials without affecting the overall structure of the deep via, and helps to improve the filling efficiency of metal materials.

[0040] The flow rates of trifluoromethane in the second process gas are 20-180 sccm, carbon tetrafluoride is 0-300 sccm, nitrogen trifluoride is 0-150 sccm, argon is 30-240 sccm, helium is 20-400 sccm, and difluoromethane is 50-200 sccm. It is understandable that, since trifluoromethane can decompose into fluoride and hydrogen ions, it can be used as the main gas for removing the silicon oxide thin film 13, and at least 20 sccm should be introduced into the etching process chamber. With the introduction of trifluoromethane, carbon tetrafluoride also provides fluoride ions, and its introduction or non-introduction can be selected according to actual needs. Nitrogen trifluoride, as a cleaning gas, can also be introduced or not. Because... + + =1:1, therefore in + + The minimum flow rate of the mixed gas is 20 sccm, so helium must be introduced at least 20 sccm. Argon, as the gas that performs physical bombardment, must be introduced at least 30 sccm, and difluoromethane, as the gas that protects the polymer, must be introduced at least 50 sccm.

[0041] In the dry etching process of the silicon oxide thin film 13 in S140, the chamber pressure is 5~60mT, the upper electrode power of the TCP is 600~2000W, the lower electrode bias voltage is 40~350V, and the process time is 40~350s. In the dry etching process for removing the silicon oxide thin film 13, a second process gas is injected into the etching process chamber through a plasma generator. The chamber pressure of the etching process chamber is maintained at 5~60mT, the upper electrode power of the plasma generator is maintained at 600~2000W, the lower electrode bias voltage is maintained at 40~350V, and the process time for removing the photoresist 12 is maintained at 40~350s.

[0042] Based on the above embodiments, this application also provides an integrated chip fabrication method, which includes the deep silicon via (TSV) 15 fabrication method described in the above embodiments. For example, when fabricating an integrated chip composed of multiple stacked chips, a silicon interposer 11 can be deposited on the lower chip. A TSV 15 is then fabricated on the silicon interposer 11 using the aforementioned TSV 15 fabrication method. Metal material is then filled into the TSV 15 to form metal wires 16 connecting the upper and lower chips. After the upper surface of the metal wires 16 is smoothed using a mechanical polishing process, the upper chip is fabricated on the silicon interposer 11. This process can be repeated to fabricate an integrated chip composed of multiple chip layers and silicon interposers 11 stacked alternately. Figure 8 This is a cross-sectional schematic diagram of two adjacent chip layers provided in an embodiment of this application. For example... Figure 8As shown, after removing the residual silicon oxide film 13 on the surface of the silicon interposer 11 above the first chip 10, metal material is filled into the deep silicon via 15 to form metal wires 16, and the second chip 20 is then fabricated above the silicon interposer 11. The fabrication process of the integrated chip involves multiple deep silicon via 15 fabrication processes. In this embodiment, by using a dry etching process within the etching chamber to remove the photoresist 12 and silicon oxide film 13, the fabrication efficiency of each deep silicon via 15 can be improved, thereby significantly increasing the fabrication efficiency of the integrated chip.

[0043] Based on the above embodiments, this application also provides an integrated chip, which is fabricated using the integrated chip fabrication method described in the above embodiments. (Reference) Figure 8 In an integrated chip, there is a silicon interposer 11 between any two adjacent chips, and the metal wires 16 in the silicon interposer 11 connect the chips of the upper and lower layers.

[0044] In summary, the deep silicon via 15 fabrication method, integrated chip fabrication method, and integrated chip provided in this application embodiment can be achieved by depositing silicon oxide on the upper surface of the silicon interposer 11 of a wafer to form a silicon oxide thin film 13; coating photoresist 12 on the upper surface of the silicon oxide thin film 13; exposing and developing the photoresist 12 through a preset via mask to expose the via area; etching the silicon oxide thin film 13 and the silicon interposer 11 in the via area using a dry etching process in an etching chamber to form the deep silicon via 15; and removing the remaining photoresist 12 and silicon oxide thin film 13 using a dry etching process in an etching chamber. Using the aforementioned techniques, after etching the deep silicon via 15 within the etching process chamber, a process gas capable of reacting with the photoresist 12 and silicon oxide film 13 can be directly introduced into the etching process chamber. This process gas is then used to dry-etch the remaining photoresist 12 and silicon oxide film 13, enabling the removal of the photoresist 12 and silicon oxide film 13 within the etching process chamber. This eliminates the need to transfer the wafer to other process stages, simplifying the fabrication process of the deep silicon via 15 and improving its fabrication efficiency. Furthermore, the process gas contains fluoride ions, which react with the silicon interposer 11 at a lower rate than the silicon oxide film 13. This allows the upper opening 14 of the deep silicon via 15 to be etched into a trumpet-shaped opening 14, expanding the upper cross-section of the via and facilitating subsequent metal material filling, thus improving the metal material filling efficiency.

[0045] The above description is merely a preferred embodiment and the technical principles employed in this application. This application is not limited to the specific embodiments described herein, and various obvious changes, readjustments, and substitutions that can be made by those skilled in the art will not depart from the scope of protection of this application. Therefore, although this application has been described in detail through the above embodiments, this application is not limited to the above embodiments, and may include many other equivalent embodiments without departing from the concept of this application. The scope of this application is determined by the scope of the claims.

Claims

1. A method for fabricating deep silicon through-holes, characterized in that, Includes the following steps: Step 1: Deposit silicon oxide on the surface of the silicon interposer layer of the wafer to form a silicon oxide thin film; Step 2: Coat the surface of the silicon oxide film with photoresist, and expose and develop the photoresist through a preset through-hole mask to expose the through-hole area; Step 3: Etch the silicon oxide film and silicon interlayer in the via region using a dry etching process within the etching chamber to form a deep silicon via; Step 4: Remove the remaining photoresist and silicon oxide film using a dry etching process within the etching process chamber.

2. The method for preparing deep silicon through-holes according to claim 1, characterized in that, The first process gas used in the dry etching process for removing the photoresist in step four includes oxygen, nitrogen trifluoride, helium, and argon.

3. The method for preparing deep silicon through-holes according to claim 2, characterized in that, The flow rate of oxygen in the first process gas is 20~300 sccm, the flow rate of nitrogen trifluoride is 0~100 sccm, the flow rate of helium is 0~400 sccm, and the flow rate of argon is 10~150 sccm.

4. The method for preparing deep silicon through-holes according to claim 1, characterized in that, In step four, the dry etching process for removing the photoresist uses a chamber pressure of 5~100mT, a TCP upper electrode power of 200~1200W, a lower electrode bias voltage of 0~1500V, and a process time of 10~200s.

5. The method for preparing deep silicon through-holes according to claim 1, characterized in that, The second process gas used in the dry etching process for removing the silicon oxide film in step four includes trifluoromethane, carbon tetrafluoride, nitrogen trifluoride, argon, helium, and difluoromethane.

6. The method for preparing deep silicon through-holes according to claim 5, characterized in that, The ratio of the total flow rate of trifluoromethane, carbon tetrafluoride, and nitrogen trifluoride to the flow rate of helium is 1:

1.

7. The method for preparing deep silicon through-holes according to claim 5, characterized in that, The flow rates of trifluoromethane, carbon tetrafluoride, nitrogen trifluoride, argon, helium, and difluoromethane in the second process gas are 20-180 sccm, 0-300 sccm, 0-150 sccm, 30-240 sccm, 20-400 sccm, and 50-200 sccm, respectively.

8. The method for preparing deep silicon through-holes according to claim 1, characterized in that, The dry etching process for the silicon oxide thin film in step four uses a chamber pressure of 5~60mT, a TCP upper electrode power of 600~2000W, a lower electrode bias voltage of 40~350V, and a process time of 40~350s.

9. A method for fabricating an integrated chip, characterized in that, This includes the deep silicon through-hole fabrication method as described in any one of claims 1-8.

10. An integrated chip, characterized in that, It was prepared using the integrated chip fabrication method as described in claim 9.

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