Wafer structure cutting method and cutting system based on silicon interposer

Abstract

The invention provides a wafer structure cutting method and cutting system based on a silicon interposer. The silicon interposer wafer structure sequentially comprises a silicon substrate, a functional layer and a connecting substrate, the cutting method comprises the following steps: S1, adopting a V-shaped blade to carry out two times of V-shaped cutting with preset dislocation offset on a silicon substrate, and forming a splicing groove in the silicon substrate; s2, a laser ablation technology is adopted, the functional layer below the splicing groove is removed through the splicing groove, and the surface of the connecting substrate is exposed; and S3, cutting along the cutting path formed in the steps S1 and S2 by using a cutting blade, and cutting through the connecting substrate to realize separation of the wafer structure. According to the cutting method disclosed by the invention, through an innovative mechanical-laser-mechanical cutting synergistic process, cracks are effectively prevented from extending downwards from the brittle dielectric layer or collapsing from the surface of the silicon substrate, the integrity of a cutting interface is greatly improved, high-quality cutting of heterogeneous materials is realized, and the synergistic effect of mechanical cutting and laser processing is exerted.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor manufacturing technology, and in particular relates to a wafer structure dicing method and dicing system based on a silicon interposer. Background Technology

[0002] In the field of advanced semiconductor packaging, especially in 2.5D integration technology, ultra-thin silicon interposer (UTI) wafer structures have become a key carrier for achieving heterogeneous integration of high-bandwidth, high-performance chips (such as CPUs, GPUs, and HBMs). These wafers typically exhibit a multi-layered heterogeneous structure: from top to bottom, they consist of an ultra-thin silicon substrate layer (e.g., approximately 50 μm thick), a low-k layer, a metal layer, and a thick interconnect substrate (e.g., approximately 600 μm thick). The silicon substrate layer contains high-density through-silicon vias (TSVs) and wiring, while the low-k layer and metal layer together form a fine interconnect network to enable high-speed signal transmission between chips. The interconnect substrate provides support and connection.

[0003] However, this unique structure—thin on top and thick on the bottom—with vastly different material properties (e.g., brittle silicon versus low-dielectric-constant materials, tough metals, and rigid substrates) presents a significant challenge to the final wafer dicing process. Currently, the industry commonly uses a single traditional blade for a single cut, which has inherent limitations when dealing with this structure. During dicing, immense mechanical stress is concentrated at the contact point between the blade edge and the material. This highly concentrated stress first induces long, strip-like chipping and cracks at the cut of the silicon substrate layer, which has extremely low mechanical strength. More seriously, this stress is transmitted downwards to the more mechanically fragile and poorly adhered low-dielectric-constant layer and the interface between the Low-k layer and the metal layer, causing the Low-k layer to fracture or the interface to delaminate. These defects not only significantly reduce yield but can also become hidden reliability risks, severely impacting the performance and lifespan of the final chip product. Currently, there is a lack of an efficient dicing solution that can simultaneously maintain the surface integrity of the ultra-thin silicon substrate layer and protect the interfaces of the internal brittle functional layers.

[0004] Therefore, there is a need to provide an improved technical solution that addresses the shortcomings of the existing technology. Summary of the Invention

[0005] In view of the shortcomings of the prior art described above, the purpose of this invention is to provide a wafer structure cutting method and cutting system based on silicon interposer, which solves the problem of cracks and long strip-shaped edge breakage caused by stress concentration when cutting ultrathin silicon interposer wafers with traditional tools in a single cutting operation.

[0006] To achieve the above and other related objectives, the present invention provides a method for dicing a wafer structure based on a silicon interposer, wherein the silicon interposer wafer structure sequentially comprises a silicon substrate, a functional layer, and a connection substrate; the dicing method includes the following steps:

[0007] S1. The silicon substrate is cut twice with a preset offset using a V-shaped blade to form a splicing groove on the silicon substrate, which is formed by splicing two V-shaped cuts.

[0008] S2. Using laser ablation technology, the functional layer beneath the splicing groove is removed, exposing the surface of the connecting substrate;

[0009] S3. Using a cutting blade, cut along the cutting path formed by steps S1 and S2 to cut through the connecting substrate and achieve separation of the wafer structure.

[0010] Preferably, the thickness of the silicon substrate is 50μm to 80μm.

[0011] Preferably, the functional layer is composed of alternating dielectric and metal layers, and the thickness of the functional layer is 5μm~20μm.

[0012] Preferably, the dielectric layer is made of a material with a low dielectric constant.

[0013] Preferably, the thickness of the connecting substrate is 400~800μm.

[0014] Preferably, the included angle of the V-shaped blade in step S1 is 40°~60°.

[0015] Preferably, the preset misalignment offset in step S1 is 40~80μm.

[0016] Preferably, the depth of the splicing groove in step S1 is 20% to 30% of the thickness of the silicon substrate.

[0017] Preferably, the cutting blade in step S3 is a rectangular blade.

[0018] The present invention also provides a cutting system for implementing the above-described cutting method, the cutting system comprising:

[0019] The first cutting module is used to perform two V-shaped cuts with preset misalignment offsets;

[0020] The laser processing module is used to perform laser ablation on the functional layers;

[0021] The second cutting module is used to complete the final separation of the wafer structure;

[0022] The control unit is used to control the first cutting module, the laser processing module, and the second cutting module to work together in sequence.

[0023] As described above, the wafer dicing method and dicing system based on silicon interposer of the present invention have the following beneficial effects:

[0024] The cutting method in this invention, through an innovative mechanical-laser-mechanical cutting synergistic process, effectively prevents cracks from propagating downwards from the brittle dielectric layer or causing chipping from the silicon substrate surface, greatly improving the integrity of the cutting interface, achieving high-quality cutting of heterogeneous materials, and leveraging the synergistic effect of mechanical cutting and laser processing. This invention employs a V-shaped blade for two-stage offset cutting, effectively dispersing the traditional single-point concentrated cutting stress into a wider V-shaped region, improving the uniformity of stress distribution during cutting, and solving the problems of cracks and long strip-shaped edge chipping caused by stress concentration, resulting in smooth and intact chip edges after cutting. Furthermore, the non-contact, selective removal of the fragile dielectric and metal layers using laser ablation technology completely avoids the shearing effect of mechanical stress on the interface between the dielectric and metal layers, fundamentally eliminating the risk of delamination and hidden cracks caused by stress concentration at this interface, thereby significantly improving chip yield and long-term reliability. Attached Figure Description

[0025] Figure 1 The diagram shown is a schematic diagram of the silicon interposer wafer structure in Embodiment 1 of the present invention.

[0026] Figure 2 The diagram shown is a cutting schematic corresponding to step S1 of the cutting method in Embodiment 1 of the present invention.

[0027] Figure 3 The diagram shown is a cutting schematic corresponding to step S2 of the cutting method in Embodiment 1 of the present invention.

[0028] Figure 4 The diagram shown is a cutting schematic corresponding to step S3 of the cutting method in Embodiment 1 of the present invention.

[0029] Figure 5 The image shown is a front view of a physical cutting path formed using the cutting method described in Embodiment 1 of the present invention.

[0030] Component designation explanation

[0031] 10 silicon substrate 20 Functional layer 21 dielectric layer 22 Metal layer 40 Connecting substrate 50 splicing groove 60 Laser processing module 70 Second cutting module Detailed Implementation

[0032] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0033] Before further describing specific embodiments of the present invention, it should be understood that the scope of protection of the present invention is not limited to the specific embodiments described below; it should also be understood that the terminology used in the embodiments of the present invention is for describing specific embodiments and not for limiting the scope of protection of the present invention. Test methods in the following embodiments that do not specify specific conditions are generally performed under conventional conditions or as recommended by the respective manufacturers.

[0034] When numerical ranges are given in the embodiments, it should be understood that, unless otherwise stated in the present invention, both endpoints of each numerical range and any value between the two endpoints may be selected. Unless otherwise defined, all technical and scientific terms used in this invention have the same meaning as commonly understood by one of ordinary skill in the art. In addition to the specific methods, apparatus, and materials used in the embodiments, based on the knowledge of the prior art possessed by one of ordinary skill in the art and the description of this invention, any prior art methods, apparatus, and materials similar to or equivalent to those described, apparatus, and materials in the embodiments of this invention may be used to implement the present invention.

[0035] This invention relates to a wafer dicing method and corresponding dicing system based on a silicon interposer, aiming to solve the problems in existing technologies where the silicon interposer wafer structure is prone to defects such as edge chipping, cracking, delamination, metal layer tearing, and heat-affected zone diffusion during dicing due to the large differences in mechanical properties, thin thickness, and high brittleness of the multilayer materials, leading to decreased chip yield and reliability. This invention introduces a three-step collaborative process of "V-shaped pre-cutting—laser ablation—final dicing," combined with specific geometric parameters and tool selection, to achieve low-damage, high-precision, and high-efficiency wafer separation.

[0036] The technical solution of the present invention will now be described in detail with reference to the accompanying drawings. Please refer to the accompanying drawings. Figures 1-5 It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of the present invention. Therefore, the drawings only show the components related to the present invention and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.

[0037] Example 1

[0038] This embodiment provides a wafer dicing method based on a silicon interposer layer. The silicon interposer layer wafer structure sequentially includes a silicon substrate 10, a functional layer 20, and a connection substrate 40. The dicing method includes the following steps:

[0039] S1. The silicon substrate 10 is cut twice with a preset offset using a V-shaped blade to form a splicing groove 50 on the silicon substrate 10, which is formed by splicing two V-shaped grooves.

[0040] S2. Using laser ablation technology, the functional layer 20 beneath the splicing groove 50 is removed, exposing the surface of the connecting substrate 40.

[0041] S3. Using a cutting blade, cut along the cutting path formed by steps S1 and S2 to cut through the connecting substrate 40 and achieve separation of the wafer structure.

[0042] For details, please refer to Figure 1 The silicon interposer wafer structure to be cut includes, from top to bottom, a silicon substrate 10, a functional layer 20, and a connecting substrate 40.

[0043] As an example, the thickness of the silicon substrate 10 is 50 μm to 80 μm.

[0044] Specifically, the thickness of the silicon substrate 10 can be any value within the range of 50μm, 60μm, 70μm, 80μm, etc., and can be adjusted according to actual needs.

[0045] As an example, the functional layer 20 is formed by alternating layers of dielectric layer 21 and metal layer 22, and the thickness of the functional layer 20 is 5μm~20μm.

[0046] Specifically, the thickness of the functional layer 20 can include any value within the range of 5μm, 12μm, 15μm, 18μm, 20μm, etc.

[0047] As an example, the dielectric layer 21 is made of a low dielectric constant material.

[0048] As an example, the thickness of the connecting substrate 40 is 400~800μm.

[0049] Specifically, the thickness of the connecting substrate 40 may include any value within the range of 400μm, 500μm, 600μm, 700μm, 800μm, etc., and can be adjusted according to actual needs; the connecting substrate plays a supporting and connecting role, and in a specific embodiment, the connecting substrate is a composite resin material.

[0050] See Figures 1-5The following describes in detail the wafer dicing method based on silicon interposer. It should be noted that these embodiments are merely descriptive and do not limit the invention in any way.

[0051] In this embodiment, a pre-cutting step with a V-shaped blade is added before laser processing. The cutting sequence is crucial. First, the V-shaped blade creates a splicing groove 50 with optimized stress distribution in the silicon substrate 10. This cutting method has a low stress transmission path, which reduces potential microstructure damage and improves the stability of the wafer in subsequent packaging, transportation and reliability testing. Then, a combination of laser ablation technology and final cutting process is used to reduce the participation of the dielectric layer 21 and metal layer 22 in fracture propagation, effectively improving the verticality of the cut and edge integrity.

[0052] See Figure 1 In this embodiment, the silicon interposer wafer structure to be cut includes, from top to bottom, a silicon substrate 10, a functional layer 20, and a connecting substrate 40. The silicon substrate 10 has a thickness of 50 μm. The functional layer 20 includes a dielectric layer 21 and a metal layer 22. The dielectric layer 21 has a thickness of 1 μm, the metal layer 22 has a thickness of 11 μm, and the connecting substrate 40 has a thickness of 600 μm.

[0053] First, step S1 is performed, in which a V-shaped blade is used to make two V-shaped cuts with a preset offset amount, forming a splicing groove 50 on the silicon substrate 10 by splicing two V-shaped cuts.

[0054] For details, please refer to Figure 2 The silicon substrate 10 is cut twice using a V-shaped blade. First, a first cut is made along the predetermined cut path centerline. Then, the V-shaped blade is horizontally offset relative to the centerline of the first cut path, i.e., a second cut is made according to a preset offset. The depth of the two cuts is controlled to be consistent, thus forming a partially overlapping W-shaped splicing groove 50 on the silicon substrate 10. This splicing groove 50 is formed by splicing two V-shaped grooves and has a certain overlap. This new cutting method allows the offset to independently bear a portion of the cutting stress, thereby dispersing the stress point originally concentrated at the cut center and reducing the probability of long cracks and edge damage found during DPA polishing or EMC unpacking.

[0055] As an example, the included angle of the V-shaped blade in step S1 is 40°~60°.

[0056] Specifically, the included angle of the V-shaped blade in step S1 can be any value within a range such as 40°, 45°, 50°, 55°, 60°, etc., and can be adjusted according to actual needs; in addition, diamond is preferred as the material of the V-shaped blade, but there is no restriction here, and it can be selected according to actual needs.

[0057] As an example, the preset misalignment offset in step S1 is 40~80μm.

[0058] Specifically, the V-shaped blade's offset splicing cut is not a one-time vertical cut, but rather a wider splicing groove 50 formed by two V-shaped cuts with preset offset amounts, which directly solves the core problem of single-point stress concentration.

[0059] In addition, the preset misalignment offset is based on the horizontal misalignment distance between the center line of the first cutting path and the center line of the second cutting path, which is preset according to the wafer structure to be cut; in a specific embodiment of the present invention, the preset misalignment offset may include any value in the range of 40μm, 50μm, 60μm, 70μm, 80μm, etc., and can be adjusted according to the actual situation; more preferably, the preset misalignment offset in this embodiment is 60μm.

[0060] As an example, the depth of the splicing groove 50 in step S1 is 20% to 30% of the thickness of the silicon substrate 10.

[0061] Specifically, the depth of the splicing groove 50 is the deepest part of the W-shaped splicing groove 50, and the depth of the splicing groove 50 is any value within a range such as 20%, 22%, 24%, 25%, 26%, 28%, 30% of the thickness of the silicon substrate 10.

[0062] Next, in step S2, laser ablation technology is used to remove the functional layer 20 beneath the splicing groove 50 and expose the surface of the connecting substrate 40.

[0063] Specifically, laser ablation is a processing method that uses a high-energy pulsed laser beam to irradiate the surface of a material, causing the surface material to melt, vaporize, ionize, or have its chemical bonds broken in a very short time, thereby precisely removing microscopic or macroscopic amounts of material. See also Figure 3 Infrared laser ablation (wavelength 1064nm) is used. The laser beam is focused on the bottom of the splicing groove 50 formed in step S1 and scanned along the cutting path. The laser energy can effectively penetrate the cutting gap of the silicon substrate 10, selectively ablate and completely remove the dielectric layer 21 and metal layer 22 directly below it, forming a clean channel, thereby exposing the surface of the underlying connecting substrate 40. By controlling the laser scanning speed and the number of scans, it is ensured that the functional layer 20 is completely removed. In the specific embodiment of the present invention, the parameters selected in the laser ablation technology are not overly restricted, as long as they can meet the actual needs to completely remove the functional layer 20 below the splicing groove 50 and expose the surface of the connecting substrate 40.

[0064] Specifically, the present invention innovatively adds a pre-cutting step of V-shaped blade before laser ablation. This sequence is crucial. First, the V-shaped blade creates a splicing groove 50 with optimized stress distribution in the silicon substrate 10. Then, the silicon substrate 10 and functional layer 20 are removed by laser ablation technology. This not only avoids the laser heat-affected zone directly acting on the complete silicon substrate 10, but also avoids the traditional blade directly impacting the silicon substrate 10.

[0065] Finally, in step S3, a cutting blade is used to cut along the cutting path formed by steps S1 and S2, cutting through the connecting substrate 40 to achieve separation of the wafer structure.

[0066] As an example, the cutting blade mentioned in step S3 is a rectangular blade.

[0067] For details, please refer to Figure 4 A rectangular blade is used to make the final cut along the splicing groove 50 and the laser ablation channel. The rectangular blade can easily cut through the exposed connecting substrate 40, thereby completing the separation of the entire wafer structure.

[0068] See Figure 5 This is a front view of the actual cut path. After cutting using the method described in this embodiment, the chip edge shows no visible elongated chipping on the top of the silicon substrate 10, no cracks extending to the functional layer 20, and a clear and complete interface between the dielectric layer 21 and the metal layer 22 without delamination. Compared to traditional single-blade cutting methods, this significantly improves the integrity of the cutting interface. If a traditional blade were used to cut through the entire wafer structure in one go, the enormous stress would first damage the most vulnerable top silicon substrate 10. If only the 600μm connecting substrate 40 were cut with a laser, it would be inefficient and could potentially cause thermal damage to the functional layer 20. Therefore, this embodiment, through an innovative mechanical-laser-mechanical cutting synergistic process, effectively prevents cracks from extending downwards from the brittle dielectric layer 21 or from chipping on the surface of the silicon substrate 10, greatly improving the integrity of the cutting interface, achieving high-quality cutting, and leveraging the synergistic effect of mechanical cutting and laser processing.

[0069] Example 2

[0070] This embodiment provides a cutting system for implementing the cutting method in Embodiment 1 above. The cutting system includes:

[0071] The first cutting module is used to perform two V-shaped cuts with preset misalignment offsets;

[0072] Laser processing module 60 is used to perform laser ablation on functional layer 20;

[0073] The second cutting module 70 is used to complete the final separation of the wafer structure;

[0074] The control unit is used to control the first cutting module, the laser processing module 60, and the second cutting module 70 to work together in sequence.

[0075] Specifically, the first cutting module is equipped with a V-shaped blade, which can precisely perform two V-shaped cuts with a preset misalignment offset under the command of the control unit; the laser processing module 60 integrates a laser source and a beam focusing scanning system for precise laser ablation of the splicing groove 50; the second cutting module 70 is equipped with a rectangular blade for performing the final separation cut; the control unit, as the core of the system, has a built-in control program for coordinating and controlling the first cutting module, the laser processing module 60, and the second cutting module 70 to work automatically and collaboratively in the order of steps S1, S2, and S3, ensuring seamless connection of each step.

[0076] In summary, the cutting method of this invention, through an innovative mechanical-laser-mechanical cutting synergistic process, effectively prevents cracks from propagating downwards from brittle surfaces or causing chipping on the silicon substrate surface, greatly improving the integrity of the cutting interface, achieving high-quality cutting of heterogeneous materials, and leveraging the synergistic effect of mechanical cutting and laser processing. This invention employs a V-shaped blade for two-stage offset cutting, effectively dispersing the traditional single-point concentrated cutting stress into a wider V-shaped region, improving the uniformity of stress distribution during cutting, and solving the problems of cracks and long strip-shaped edge chipping caused by stress concentration, resulting in smooth and intact chip edges after cutting. Furthermore, the non-contact, selective removal of fragile dielectric and metal layers using laser ablation technology completely avoids the shearing effect of mechanical stress on the dielectric-metal interface, fundamentally eliminating the risk of delamination and hidden cracks caused by stress concentration at this interface, thereby significantly improving chip yield and long-term reliability. Therefore, this invention effectively overcomes the various shortcomings of existing technologies and has high industrial application value.

[0077] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.

Claims

1. A wafer dicing method based on a silicon interposer, characterized in that, The silicon interposer wafer structure sequentially comprises a silicon substrate, a functional layer, and a connection substrate; the dicing method includes the following steps: S1. The silicon substrate is cut twice with a preset offset using a V-shaped blade to form a splicing groove on the silicon substrate, which is formed by splicing two V-shaped cuts. S2. Using laser ablation technology, the functional layer beneath the splicing groove is removed, exposing the surface of the connecting substrate; S3. Using a cutting blade, cut along the cutting path formed by steps S1 and S2 to cut through the connecting substrate and achieve separation of the wafer structure.

2. The wafer dicing method based on a silicon interposer layer according to claim 1, characterized in that: The thickness of the silicon substrate is 50μm~80μm.

3. The wafer dicing method based on a silicon interposer layer according to claim 1, characterized in that: The functional layer is composed of alternating dielectric and metal layers, and the thickness of the functional layer is 5μm~20μm.

4. The wafer dicing method based on a silicon interposer layer according to claim 3, characterized in that: The dielectric layer is made of a low dielectric constant material.

5. The wafer dicing method based on a silicon interposer layer according to claim 1, characterized in that: The thickness of the connecting substrate is 400~800μm.

6. The wafer dicing method based on a silicon interposer layer according to claim 1, characterized in that: The included angle of the V-shaped blade in step S1 is 40°~60°.

7. The wafer dicing method based on a silicon interposer layer according to claim 1, characterized in that: The preset misalignment offset in step S1 is 40~80μm.

8. The wafer dicing method based on a silicon interposer layer according to claim 1, characterized in that: The depth of the splicing groove in step S1 is 20% to 30% of the thickness of the silicon substrate.

9. The wafer dicing method based on a silicon interposer according to claim 1, characterized in that: The cutting blade mentioned in step S3 is a rectangular blade.

10. A cutting system, characterized in that: The cutting system is used to implement the cutting method according to any one of claims 1 to 9, and the cutting system comprises: The first cutting module is used to perform two V-shaped cuts with preset misalignment offsets; The laser processing module is used to perform laser ablation on the functional layers; The second cutting module is used to complete the final separation of the wafer structure; The control unit is used to control the first cutting module, the laser processing module, and the second cutting module to work together in sequence.

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