Method and system for controlling charging time based on load end capacitance value

Abstract

The invention provides a method and system for controlling charging time based on a load end capacitance value, and relates to the technical field of new energy. The method comprises the following steps: establishing a corresponding simulation model in a dynamic system modeling tool according to a solid-state power control unit circuit, and determining a fitting curve through the simulation model; controlling a current limiting branch in the solid state power control unit circuit to be switched on and switched off so as to generate a current response signal and a voltage signal at a load end, and processing the current response signal and the voltage signal in sequence by using a sampling circuit, Fourier transform, an FPGA and a fitting curve so as to obtain a capacitance value of the load end; and according to the maximum value of the plurality of preset capacitance value ranges, the resistance of the current limiting branch and the capacitance value of the load end, determining the turn-on time of the current limiting branch, and according to the turn-on time, controlling the current limiting branch to be turned on so as to enable the capacitor of the load end to complete charging. Therefore, the switching-on time of the current limiting branch is dynamically adjusted by utilizing the capacitance value of the load end, and the efficiency and the reliability of the system can be improved.

Description

Technical Field

[0001] This invention relates to the field of new energy technology, and in particular to a method and system for controlling charging time based on load-side capacity. Background Technology

[0002] The rapid development of new energy vehicles has significantly advanced the electrification and intelligentization of electric vehicles. Traditional 12V systems are no longer sufficient to meet the higher power requirements of modern electric vehicles; therefore, 48V systems are becoming the future trend. In 48V system scenarios, traditional low-voltage circuit breakers and fuses in automobiles are insufficient to meet the demands of increasingly complex circuits. To meet the performance indicators of the power distribution system, solid-state power control units are used to replace low-voltage circuit breakers and fuses. However, with the development of new energy vehicle power systems, the types and capacities of their loads are constantly increasing. New energy vehicle power systems include motor drive systems, on-board chargers, DC-DC converters, and high-power infotainment systems. New energy vehicle power systems contain many capacitive loads. Due to the charge conservation characteristics of capacitive loads, their voltage cannot change abruptly, resulting in a large current surge at the moment of switching on, which can easily cause the failure of switching devices. Especially for high-power capacitive loads, the use of solid-state power control units faces a significant current surge during startup.

[0003] Currently, to handle the significant current surge during startup of solid-state power control units, a current-limiting branch is typically used. For example, a current-limiting resistor is connected in series with a current-limiting power transistor. During startup, the current-limiting branch is activated to charge the capacitive load. After a certain time, the main branch is activated. Since the equivalent impedance of the main branch is much smaller than that of the current-limiting branch, the current-limiting branch can be short-circuited, thus achieving current limiting during startup. However, because the capacitive impedance of the load is unknown and the startup time of the current-limiting branch is fixed, power loss is high, the heat capacity of the current-limiting branch is wasted, and device damage may occur, resulting in low reliability. Furthermore, the fixed startup time of the current-limiting branch leads to additional power loss, thereby reducing system efficiency. Summary of the Invention

[0004] The purpose of this invention is to provide a method and system for controlling charging time based on the load-side capacitance value, so as to solve the problems of low system efficiency and reliability in the prior art.

[0005] To address the aforementioned technical problems, the embodiments of the present invention provide the following technical solutions: The first aspect of this invention provides a method for controlling charging time based on load capacitance, comprising: Based on the solid-state power control unit circuit, a corresponding simulation model is established in the dynamic system modeling tool, and the fitting curve is determined through the simulation model. The fitting curve is used to indicate the relationship between the ratio of the preset real part of the load terminal and the capacitance value at different angular frequencies. The solid-state power control unit circuit is connected to the sampling circuit, the field-programmable gate array (FPGA), and the load terminal. The current-limiting branch in the solid-state power control unit circuit is turned on and off to generate current response signals and voltage signals at the load end. The current response signals and voltage signals are processed sequentially using sampling circuit, Fourier transform, FPGA and fitting curve to obtain the capacitance value at the load end. Based on the maximum value of multiple preset capacitance ranges, the resistance of the current-limiting branch, and the capacitance of the load, the turn-on time of the current-limiting branch is determined, and the turn-on time is controlled to enable the current-limiting branch to be turned on so that the capacitor at the load end can be fully charged.

[0006] A second aspect of the present invention provides a system for controlling charging time based on load-side capacitance, comprising: A module is established to create a corresponding simulation model in a dynamic system modeling tool based on the solid-state power control unit circuit, and to determine the fitting curve through the simulation model. The fitting curve is used to indicate the relationship between the ratio of the preset real part of the load terminal and the capacitance value at different angular frequencies. The solid-state power control unit circuit is connected to the sampling circuit, FPGA and load terminal. The processing module is used to control the opening and closing of the current-limiting branch in the solid-state power control unit circuit to generate current response signals and voltage signals at the load end. The current response signals and voltage signals are processed sequentially using sampling circuit, Fourier transform, FPGA and fitting curve to obtain the capacitance value at the load end. The control module is used to determine the turn-on time of the current-limiting branch based on the maximum value of multiple preset capacitance ranges, the resistance of the current-limiting branch, and the capacitance of the load end, and to control the turn-on of the current-limiting branch according to the turn-on time so that the capacitor at the load end can be charged.

[0007] A third aspect of the present invention provides an electronic device, the electronic device comprising: at least one processor; and at least one memory and a bus connected to the processor; wherein the processor and the memory communicate with each other via the bus; the processor is configured to call program instructions in the memory to execute the method for controlling charging time based on load capacity of the first aspect or any optional embodiment of the first aspect described above.

[0008] Compared to existing technologies, the method and system for controlling charging time based on load-side capacitance provided by this invention establishes a corresponding simulation model in a dynamic system modeling tool based on the solid-state power control unit circuit, and determines a fitting curve through the simulation model. The fitting curve is used to indicate the relationship between the ratio of the preset real part of the load-side circuit and the capacitance value at different angular frequencies. The current-limiting branch in the solid-state power control unit circuit is controlled to turn on and off to generate current response signals and voltage signals at the load-side. The current response signals and voltage signals are processed sequentially using a sampling circuit, Fourier transform, FPGA, and fitting curve to obtain the capacitance value at the load-side. The on-time of the current-limiting branch is determined based on the maximum value of multiple preset capacitance ranges, the resistance of the current-limiting branch, and the capacitance value at the load-side. The on-time of the current-limiting branch is controlled to turn on according to the on-time, so that the capacitor at the load-side can be fully charged. In this way, by controlling the opening and closing of the current-limiting branch in the solid-state power control unit circuit, current response signals and voltage signals are acquired. Based on the existing solid-state power control unit circuit, without adding any additional circuits, the capacitance value at the load end is obtained by using sampling circuit, Fourier transform, FPGA and fitting curve. The opening time of the current-limiting branch is dynamically adjusted by using the capacitance value at the load end. This can effectively suppress the surge current during the opening process, improve the system efficiency, avoid additional power loss, reduce the heat capacity generated, and improve the reliability of the system. Attached Figure Description

[0009] The above and other objects, features, and advantages of exemplary embodiments of the present invention will become readily apparent upon reading the following detailed description with reference to the accompanying drawings. In the drawings, several embodiments of the invention are illustrated by way of example and not limitation, with the same or corresponding reference numerals denoteing the same or corresponding parts, wherein: Figure 1 A flowchart illustrating a method for controlling charging time based on load-side capacitance is shown schematically. Figure 2 A schematic diagram of the equivalent circuit model of the load terminal is shown. Figure 3 The fitted curves corresponding to the ratios of the preset real parts under different capacitance values ​​are schematically shown. Figure 4 An impedance measurement circuit diagram is shown schematically. Figure 5 A schematic diagram illustrating the magnitude of the surge current when a 940uF load with unlimited current branch is turned on; Figure 6 This diagram schematically illustrates the magnitude of the surge current when a load with a capacitance of 1670uF is turned on in an infinite current branch. Figure 7 A schematic diagram illustrating the magnitude of the surge current when a load with a capacitance of 2400uF is opened in an infinite current branch; Figure 8 A schematic diagram illustrating the magnitude of the surge current when a load with a capacitance of 2870uF is turned on in an infinite current branch; Figure 9 A schematic diagram illustrating the magnitude of the surge current when a load with a capacitance of 3560uF is turned on in an infinite current branch; Figure 10 A schematic diagram illustrating the magnitude of the surge current when a load with a capacitance of 4500uF is opened in an infinite current branch; Figure 11 The diagram illustrates the surge current of a 940uF capacitive load under a current limiting strategy. Figure 12 The diagram illustrates the surge current of a 1670uF capacitive load under a current limiting strategy. Figure 13 The diagram illustrates the surge current of a 2400uF capacitive load under a current limiting strategy. Figure 14 The diagram illustrates the surge current of a 2870uF capacitive load under a current limiting strategy. Figure 15 The diagram illustrates the surge current of a 3560uF capacitive load under a current limiting strategy. Figure 16 The diagram illustrates the surge current of a 4500uF capacitive load under a current limiting strategy. Figure 17 A schematic diagram of power loss at a capacitance of 940uF is shown. Figure 18 A schematic diagram of power loss at a capacitance of 1670uF is shown. Figure 19 A schematic diagram of power loss at a capacitance of 2400uF is shown. Figure 20 A schematic diagram of power loss at a capacitance of 2870uF is shown. Figure 21 A schematic diagram of power loss at a capacitance of 3560uF is shown. Figure 22 A schematic diagram of power loss at a capacitance of 4500uF is shown. Figure 23 A schematic diagram of a system for controlling charging time based on load capacitance is shown. Figure 24 A schematic diagram of the electronic device is shown. Detailed Implementation

[0010] Exemplary embodiments of the invention will now be described in more detail with reference to the accompanying drawings. While exemplary embodiments of the invention are shown in the drawings, it should be understood that the invention can be implemented in various forms and should not be limited to the embodiments set forth herein. Rather, these embodiments are provided to enable a more thorough understanding of the invention and to fully convey the scope of the invention to those skilled in the art.

[0011] It should be noted that, unless otherwise stated, the technical or scientific terms used in this invention should have the ordinary meaning as understood by those skilled in the art.

[0012] The methods described in the embodiments of the present invention will be explained in detail below.

[0013] Figure 1 A flowchart illustrating a method for controlling charging time based on load-side capacitance value in an embodiment of the present invention is shown schematically. See also... Figure 1 As shown, the method for controlling charging time based on load capacitance can include: S101. Based on the solid-state power control unit circuit, establish the corresponding simulation model in the dynamic system modeling tool, and determine the fitting curve through the simulation model.

[0014] The fitted curve indicates the relationship between the ratio of the preset real part of the load terminal and the capacitance value at different angular frequencies. The solid-state power control unit circuit is connected to the sampling circuit, FPGA, and load terminal.

[0015] Specifically, establish an equivalent model for the load side. Figure 2 A schematic diagram of the equivalent circuit model at the load end is shown below. Figure 2 As shown, the equivalent model of the load includes the equivalent resistance. Equivalent capacitance and equivalent inductance Equivalent capacitance One end and equivalent resistance One end is connected, equivalent capacitance The other end is connected to the equivalent inductance One end is connected, equivalent resistance The other end is connected to the equivalent inductance The other end is connected. Based on the equivalent model of the load end, the internal impedance of the load end can be determined. The expression is: ; in, Pre-determine the real part for the load side. Pre-determine the imaginary part for the load side. The imaginary unit, ω is the angular frequency.

[0016] The internal impedance of the above load terminal Simplifying the expression, we obtain the load-side preset real part and load-side preset imaginary part as follows: ; Based on the expressions for the preset real and imaginary parts of the load terminal, it can be seen that under the condition that the load terminal remains unchanged, i.e., the magnitude of the internal impedance of the load terminal is constant, when the angular frequency... As the load-side preset real and imaginary parts change, a regular pattern emerges. Based on the expressions for the load-side preset real and imaginary parts, the relationship between the load-side preset real and equivalent resistance can be determined. Equivalent capacitance Equivalent inductance angular frequency The relationship in equivalent resistance Equivalent inductance Changing the angular frequency while keeping it constant This allows us to obtain the preset real part values ​​of the load at different angular frequencies. Therefore, based on the solid-state power control unit circuit, a corresponding simulation model can be established in the dynamic system modeling tool, and the fitting curve can be determined through the simulation model.

[0017] Dynamic system modeling tools can include Simulink and Matlab.

[0018] For example, the simulation model uses typical industrial control parameters for electric vehicles: the total capacitance range of the load is set to 0-5000uF, and the inductance range is set to 0-500uH. Simultaneously, based on the actual situation where multiple loads in parallel in an electric vehicle cause a decrease in equivalent resistance, the resistance parameter is fixed at 84Ω to simulate typical resistance control in an electric vehicle. By changing the inductance and capacitance values ​​in the typical resistance control of an electric vehicle, the ratio of the preset real parts under different capacitance values ​​can be obtained. Based on the simulation model, the fitting curve between the ratio of the preset real parts of the load and the capacitance value at different angular frequencies can be determined. Figure 3 The fitted curves corresponding to the ratios of the preset real parts for different capacitance values ​​are schematically shown. (See attached image) Figure 3 As shown, the vertical axis represents the capacitance value, and the horizontal axis represents the ratio of the preset real part of the load at different angular frequencies. Figure 3There are five curves with different inductance values: curves with circles, curves with squares, curves with asterisks, curves with inverted triangles, and curves with crosses. The inductance value of the curve with circles is 100uH, the inductance value of the curve with squares is 200uH, the inductance value of the curve with asterisks is 300uH, the inductance value of the curve with inverted triangles is 400uH, and the inductance value of the curve with crosses is 500uH. From these five curves with different inductance values, it can be seen that changing the value of the load-side capacitance, although the inductance values ​​are different, the ratio between the preset real parts of the load-side capacitance is similar. Therefore, in actual solid-state power control unit circuits, by changing the angular frequency, the preset real and imaginary parts of the load-side capacitance can be obtained at different angular frequencies. Based on the ratio of the preset real parts of the load-side capacitance at different angular frequencies, the value of the load-side capacitance can be determined.

[0019] S102. Control the current limiting branch in the solid-state power control unit circuit to turn on and off, so as to generate current response signal and voltage signal at the load end. Then, use sampling circuit, Fourier transform, FPGA and fitting curve to process the current response signal and voltage signal in sequence to obtain the capacitance value at the load end.

[0020] Figure 4 An impedance measurement circuit diagram is schematically shown; see [link / reference]. Figure 4 As shown, the impedance measurement circuit includes a solid-state power control unit circuit, a sampling circuit, an FPGA, a load terminal, a power supply, and an inductor. The sampling circuit includes a current sampling circuit and a voltage sampling circuit. The positive terminal of the power supply, one end of the inductor, and one end of the current sampling circuit are all connected. The negative terminal of the power supply, one end of the load terminal, and one end of the voltage sampling circuit are all connected. The other end of the inductor, the other end of the current sampling circuit, and one end of the solid-state power control unit circuit are all connected. One end of the FPGA is connected to the other ends of the current sampling circuit and the solid-state power control unit circuit. The other end of the voltage sampling circuit, the other end of the FPGA, the other end of the load terminal, and the other end of the solid-state power control unit circuit are all connected. The solid-state power control unit circuit includes a first resistor, a first capacitor, a first freewheeling diode, a first MOSFET, a second capacitor, a second freewheeling diode, and a second MOSFET. One end of the first resistor, the other end of the current sampling circuit, the other end of the inductor, one end of the second capacitor, the cathode of the second freewheeling diode, and the drain of the second MOSFET are all connected. The other end of the first resistor, one end of the first capacitor, the cathode of the first freewheeling diode, and the drain of the first MOSFET are all connected. The other end of the first capacitor, the anode of the first freewheeling diode, the source of the first MOSFET, the other end of the second capacitor, the anode of the second freewheeling diode, the anode of the second MOSFET, the other end of the load terminal, the other end of the voltage sampling circuit, and the other end of the FPGA are all connected. One end of the FPGA, the gate of the first MOSFET, and the gate of the second MOSFET are all connected.

[0021] The solid-state power control unit circuit includes two branches: a current-limiting branch and a main branch. A first resistor, a first capacitor, a first freewheeling diode, and a first MOSFET form the current-limiting branch, while a second capacitor, a second freewheeling diode, and a second MOSFET form the main branch. The MOSFET device includes a first capacitor, a first freewheeling diode, a first MOSFET, a second capacitor, a second freewheeling diode, and a second MOSFET.

[0022] Specifically, step S102 includes: Step A1: Control the MOSFET devices in the current-limiting branch to turn on and off, so as to generate current response signals and voltage signals at the load end.

[0023] Dividing the voltage signal by the current response signal yields the angular frequency. The impedance corresponding to the load terminal below is: ; in, Angular frequency The impedance corresponding to the load terminal below, Angular frequency The voltage signal below, Angular frequency The current response signal under the given conditions.

[0024] Specifically, step A1 includes: Step A11: Control the MOSFET devices in the current-limiting branch to turn on and off, generating a square wave signal.

[0025] Specifically, before activating the main branch of the solid-state power control unit, the MOSFET devices in the current-limiting branch are controlled to turn on and off, generating an angular frequency of... The square wave signal.

[0026] Step A12: Control the square wave signal to flow through the load terminal to generate corresponding current response signal and voltage signal at the load terminal.

[0027] Step A2: Use a sampling circuit to sample the current response signal and voltage signal to obtain discrete current response signal and discrete voltage signal.

[0028] Step A3: Perform Fourier transform on the discrete current response signal and the discrete voltage signal to obtain the transformed current response signal and the transformed voltage signal.

[0029] Since FPGAs can only process discrete current response signals and discrete voltage signals, it is necessary to discretize the current response signals and voltage signals to obtain discrete current response signals and discrete voltage signals. In other words, it is necessary to discretize the aforementioned angular frequency signals. The expression for the impedance corresponding to the load terminal is transformed into a discrete form, and Fourier transforms are performed on the discrete current response signal and the discrete voltage signal. For example, for the signal... Discretization and Fourier transform are performed on the signal. It can be a current response signal or a voltage signal, to For the sampling period of the signal Sampling was performed to obtain a length of Discrete time series And perform a Fourier transform on the sampled signal: ; in, The transformed signal is either the transformed current response signal or the transformed voltage signal. This is the frequency index of the discrete spectrum corresponding to the discrete-time series, used to determine specific frequencies in the signal for calculating the transformed signal. The length of the discrete time series corresponding to the discrete signal. The sampling period is The first corresponding to the discrete signal A discrete time series.

[0030] Step A4: Determine the discrete impedance expression based on the transformed current response signal and the transformed voltage signal.

[0031] Specifically, the discrete impedance expression is as follows: ; in, For discrete impedances, For discrete voltage signals, the discrete time series is... The voltage signal corresponding to the first A discrete time series The sampling period is Let be the length of the discrete-time sequence corresponding to the discrete voltage signal. This is the discrete-time sequence corresponding to the discrete current response signal. The first corresponding to the discrete current response signal A discrete time series Let be the length of the discrete time series corresponding to the discrete current response signal. The imaginary unit. The length of the discrete-time sequence corresponding to the discrete voltage signal. The length of the discrete time series corresponding to the discrete current response signal. They are the same.

[0032] Step A5 uses an FPGA with discrete impedance expressions and multiple angular frequencies to determine the ratio of the target real part of the load at different angular frequencies.

[0033] Among them, several angular frequencies are different.

[0034] Specifically, step A5 includes: Step A51: Using an FPGA with discrete impedance expressions, determine the real part of the load at the target angular frequency.

[0035] The target angular frequency is different from multiple angular frequencies.

[0036] The target angular frequency can be Multiple angular frequencies can be , wait.

[0037] Step A52: Determine the target real part of the load at different angular frequencies based on the real part of the load at the target angular frequency and multiple angular frequencies.

[0038] For example, will Change to and , respectively obtained and The real and imaginary parts of the target at the load end at angular frequency.

[0039] Step A53: Determine the ratio of the target real parts of the load at different angular frequencies based on the target real parts of the load at different angular frequencies.

[0040] Step A6: Substitute the ratio of the real part of the target at the load end at different angular frequencies into the fitted curve to obtain the capacitance value at the load end.

[0041] S103. Determine the turn-on time of the current-limiting branch based on the maximum value of multiple preset capacitance ranges, the resistance of the current-limiting branch, and the capacitance of the load end, and control the turn-on of the current-limiting branch according to the turn-on time so that the capacitor at the load end can complete charging.

[0042] After the current-limiting branch is activated, the power supply will first charge the capacitor at the load end through the current-limiting branch. At this time, the voltage and current across the load end are: ; ; in, The voltage across the load terminals. The voltage across the DC power supply. For the opening time, It is a time constant. , The resistor of the current-limiting branch, This is the capacitance value at the load end. This represents the current across the load terminals.

[0043] Differentiating the expressions for the voltage and current across the load terminals, we can derive the voltage transformation rate and current transformation rate corresponding to the capacitance at the load terminals: ; ; in, The voltage transformation rate corresponds to the capacitor at the load end. This is the current conversion rate corresponding to the capacitor at the load end.

[0044] When the time At this point, using the expressions for the voltage and current transformation rates corresponding to the capacitor at the load end, it can be determined that the voltage and current transformation rates at both ends of the load are zero. Therefore, there will be no surge current in the impedance measurement circuit. However, in practice, the turn-on time of the current-limiting branch cannot be infinitely long. Therefore, the following expression for the voltage transformation rate at the load end is used for judgment. When the voltage transformation rate at the load end is less than the parameter... When this happens, it is determined that the capacitor at the load end is fully charged. ; in, The voltage transformation rate at the load end. This is the voltage sample value at the load end. ,when At this time, the voltage across the capacitor at the load end is approximately 95% of the power supply voltage, confirming that the capacitor at the load end is fully charged. Therefore, the current-limiting branch can be controlled to turn on during the turn-on time, allowing the capacitor at the load end to fully charge.

[0045] Specifically, step S103 includes: Step B1: Determine multiple turn-on times corresponding to multiple preset capacitance ranges based on the maximum value of multiple preset capacitance ranges and the resistance of the current-limiting branch.

[0046] Multiple preset capacitance ranges can be 6 preset capacitance ranges. The load-side capacitance range is 0-5000uF, which can be divided into 6 preset capacitance ranges: 0-1400uF, 1400-2000uF, 2000-2600uF, 2600-3200uF, 3200-4000uF, and 4000-5000uF.

[0047] Specifically, step B1 includes: Step B11: Determine the corresponding time constants based on the maximum value of multiple preset capacitance ranges and the resistance of the current-limiting branch.

[0048] Based on the maximum values ​​of the six preset capacitance ranges, namely 1400uF, 2000uF, 2600uF, 3200uF, 4000uF, and 5000uF, the six time constants corresponding to the maximum values ​​of the six preset capacitance ranges are determined by multiplying them by the resistance of the current-limiting branch.

[0049] Step B12: Determine multiple activation times based on multiple time constants and preset values.

[0050] The preset value is set to 3. By multiplying the six time constants determined in step B11 by the preset value 3, the corresponding six turn-on times are obtained. The six turn-on times are 42.24ms, 60.48ms, 78.62ms, 96.77ms, 120.96ms, and 151.20ms. Using the formula for calculating turn-on losses in existing technology, the corresponding six turn-on losses are determined to be 1.6087W, 2.298W, 2.9878W, 3.677W, 4.5966W, and 5.7457W, respectively.

[0051] Step B2: Establish a correspondence table between multiple preset tolerance ranges and multiple activation times.

[0052] Based on six preset capacitance ranges and six determined activation times, a correspondence table is established between the six preset capacitance ranges and the six activation times. Table 1 shows the activation time and activation loss under different capacitance conditions. Table 1 contains the correspondence between the six preset capacitance ranges, six activation times, the ratio of the six preset real parts, the six capacitance conditions, and the six activation losses. Among them, the ratios of the six preset real parts are the ratios of the preset real parts of the load end at different angular frequencies in step S101. The preset real part ratios are 1:2, 2:3, 3:4, 4:5, 5:6 and 6:8, respectively, and the capacitance values ​​are Case 1, Case 2, Case 3, Case 4, Case 5 and Case 6. Case 1 is the case where the preset capacitance value range is 0-1400uF, Case 2 is the case where the preset capacitance value range is 1400-2000uF, Case 3 is the case where the preset capacitance value range is 2000-2600uF, Case 4 is the case where the preset capacitance value range is 2600-3200uF, Case 5 is the case where the preset capacitance value range is 3200-4000uF, and Case 6 is the case where the preset capacitance value range is 4000-5000uF.

[0053] Table 1. Turn-on time and turn-on loss under different capacitance values

[0054] Step B3: Determine the target preset capacitance range corresponding to the capacitance value of the load end.

[0055] Among them, multiple preset tolerance ranges include the target preset tolerance range.

[0056] For example, when the capacitance value at the load end is 1500uF, the target preset capacitance value range corresponding to 1500uF can be determined to be 1400-2000uF.

[0057] Step B4: In the corresponding relationship table, find the activation time corresponding to the target preset tolerance range.

[0058] Following the example in step B3, the activation time for 1400-2000uF is 60.48ms.

[0059] Step B5: Control the current-limiting branch to turn on according to the turn-on time so that the capacitor at the load end can be fully charged.

[0060] Following the example in step B4, the current-limiting branch is turned on based on an on-time of 60.48ms to allow the capacitor at the load end to complete charging.

[0061] The effectiveness of the method for controlling charging time by the load-side capacitance proposed in this invention is verified through the following simulation experiments.

[0062] Figure 5 This diagram schematically illustrates the magnitude of the surge current when a 940uF load with unlimited current branch is applied. Figure 6 This diagram schematically illustrates the magnitude of the surge current when a 1670uF load with unlimited current branch is applied. Figure 7 This diagram schematically illustrates the magnitude of the surge current when a 2400uF load with unlimited current branch is applied. Figure 8 This diagram schematically illustrates the magnitude of the surge current when a 2870uF load with unlimited current branch is applied. Figure 9 This diagram schematically illustrates the magnitude of the surge current when a 3560uF load with unlimited current branch is applied. Figure 10 This diagram schematically illustrates the surge current magnitude of a 4500uF capacitance load when an infinite current branch is connected. See also... Figures 5 to 10 As shown, the horizontal axis represents turn-on time, and the vertical axis represents current amplitude. Capacitors of 940uF, 1670uF, 2400uF, 2870uF, 3560uF, and 4500uF were turned on in the unlimited current branch. With the increase in the capacitance at the load end, the amplitude and oscillation degree of the surge current also increase, reaching a maximum turn-on surge current of 76A. Such excessively large surge currents can cause significant impact on the components in the solid-state power control unit circuit, leading to component breakdown and subsequent current damage, severely affecting the reliability and stability of the system.

[0063] Figure 11 The diagram illustrates the surge current magnitude of a 940uF capacitive load under a current-limiting strategy. Figure 12 The diagram illustrates the surge current of a 1670uF capacitive load under a current-limiting strategy. Figure 13 The diagram illustrates the surge current magnitude of a 2400uF capacitive load under a current-limiting strategy. Figure 14 The diagram illustrates the surge current magnitude of a 2870uF capacitive load under a current-limiting strategy. Figure 15 The diagram illustrates the surge current of a 3560uF capacitive load under a current-limiting strategy. Figure 16 This diagram schematically illustrates the surge current magnitude of a 4500uF capacitive load under a current-limiting strategy. (See also...) Figures 11 to 16 As shown, the horizontal axis represents turn-on time, and the vertical axis represents current amplitude. Under the current limiting strategy, the inrush current was significantly suppressed when capacitors of 940uF, 1670uF, 2400uF, 2870uF, 3560uF, and 4500uF were turned on. By precisely controlling the turn-on time of the current-limiting branch, the maximum inrush current was successfully limited to within 13A, reducing the inrush current amplitude by 83%. Compared to not using this current limiting strategy, the current oscillation amplitude was significantly reduced after adopting the current limiting strategy, effectively avoiding damage to the solid-state power control unit circuit components caused by excessive inrush current.

[0064] Figure 17 The diagram schematically illustrates the power loss at a capacitance of 940uF. Figure 18 The diagram schematically illustrates the power loss at a capacitance of 1670uF. Figure 19 The diagram schematically illustrates the power loss at a capacitance of 2400uF. Figure 20 The diagram schematically illustrates the power loss at a capacitance of 2870uF. Figure 21 The diagram schematically illustrates the power loss at a capacitance of 3560uF. Figure 22 A schematic diagram illustrating power loss at a capacitance of 4500uF is shown. See also Figures 17 to 22 As shown, the horizontal axis represents turn-on time, and the vertical axis represents turn-on power. The power loss using a current-limiting strategy is shown for capacitance values ​​of 940uF, 1670uF, 2400uF, 2870uF, 3560uF, and 4500uF. Before the surge current occurs, all values ​​represent the power loss of the current-limiting branch. The longer the turn-on time of the current-limiting branch, the greater the corresponding power loss. From... Figures 17 to 22As shown in Table 1, under different capacitance ranges compared to the preset capacitance range of 4000-5000uF, the turn-on losses were reduced by 72%, 60%, 48%, 36%, and 20%, respectively. This significantly improved the overall efficiency of the circuit and optimized the performance of the solid-state power control unit.

[0065] Based on the above Figure 1 As can be seen from the implementation method, the embodiments of the present invention establish a corresponding simulation model in a dynamic system modeling tool based on the solid-state power control unit circuit, and determine the fitting curve through the simulation model. The fitting curve is used to indicate the relationship between the ratio of the preset real part of the load end and the capacitance value at different angular frequencies. The current limiting branch in the solid-state power control unit circuit is controlled to turn on and off to generate current response signals and voltage signals at the load end. The current response signals and voltage signals are processed sequentially using sampling circuit, Fourier transform, FPGA and fitting curve to obtain the capacitance value at the load end. The turn-on time of the current limiting branch is determined according to the maximum value of multiple preset capacitance value ranges, the resistance of the current limiting branch and the capacitance value at the load end, and the turn-on time of the current limiting branch is controlled according to the turn-on time to enable the capacitor at the load end to complete charging. In this way, by controlling the opening and closing of the current-limiting branch in the solid-state power control unit circuit, current response signals and voltage signals are acquired. Based on the existing solid-state power control unit circuit, without adding any additional circuits, the capacitance value at the load end is obtained by using sampling circuit, Fourier transform, FPGA and fitting curve. The opening time of the current-limiting branch is dynamically adjusted by using the capacitance value at the load end. This can effectively suppress the surge current during the opening process, improve the system efficiency, avoid additional power loss, reduce the heat capacity generated, and improve the reliability of the system.

[0066] Based on the same inventive concept, as an implementation of the above-mentioned method for controlling charging time based on load end capacity, this embodiment of the invention also provides a system for controlling charging time based on load end capacity. Figure 23 This is a structural diagram of the system for controlling charging time based on load-side capacitance in an embodiment of the present invention. See also... Figure 23 As shown, the system for controlling charging time based on load-side capacitance may include: Module 2301 is established to create a corresponding simulation model in the dynamic system modeling tool based on the solid-state power control unit circuit, and to determine the fitting curve through the simulation model. The fitting curve is used to indicate the relationship between the ratio of the preset real part of the load terminal and the capacitance value at different angular frequencies. The solid-state power control unit circuit is connected to the sampling circuit, FPGA and load terminal. The processing module 2302 is used to control the opening and closing of the current limiting branch in the solid-state power control unit circuit to generate current response signals and voltage signals at the load end. The current response signals and voltage signals are processed sequentially using sampling circuit, Fourier transform, FPGA and fitting curve to obtain the capacitance value at the load end. The control module 2303 is used to determine the turn-on time of the current-limiting branch based on the maximum value of multiple preset capacitance ranges, the resistance of the current-limiting branch and the capacitance of the load end, and to control the turn-on of the current-limiting branch according to the turn-on time so that the capacitor at the load end can be charged.

[0067] Processing module 2302 is specifically used to control the switching on and off of MOSFET devices in the current-limiting branch to generate current response signals and voltage signals at the load end; it uses a sampling circuit to sample the current response signals and voltage signals to obtain discrete current response signals and discrete voltage signals; it performs Fourier transform on the discrete current response signals and discrete voltage signals to obtain transformed current response signals and transformed voltage signals; it determines discrete impedance expressions based on the transformed current response signals and transformed voltage signals; it uses an FPGA with discrete impedance expressions and multiple angular frequencies to determine the ratio of the target real part at the load end at different angular frequencies, and the multiple angular frequencies are all different; it substitutes the ratio of the target real part at the load end at different angular frequencies into the fitting curve to obtain the capacitance value at the load end.

[0068] The processing module 2302 controls the MOSFET devices in the current-limiting branch to turn on and off, so as to generate current response signals and voltage signals at the load end, including: controlling the MOSFET devices in the current-limiting branch to turn on and off, generating a square wave signal; controlling the square wave signal to flow through the load end, so as to generate corresponding current response signals and voltage signals at the load end.

[0069] Processing module 2302 uses an FPGA with discrete impedance expressions and multiple angular frequencies to determine the ratio of the target real parts of the load at different angular frequencies. This includes: using the FPGA with discrete impedance expressions to determine the real part of the load at the target angular frequency, where the target angular frequency is different from the multiple angular frequencies; determining the target real parts of the load at different angular frequencies based on the real part of the load at the target angular frequency and the multiple angular frequencies; and determining the ratio of the target real parts of the load at different angular frequencies based on the target real parts of the load at different angular frequencies.

[0070] Processing module 2302, the discrete impedance expression is: ; in, For discrete impedances, For discrete voltage signals, the discrete time series is... The voltage signal corresponding to the first A discrete time series The sampling period is Let be the length of the discrete-time sequence corresponding to the discrete voltage signal. This is the discrete-time sequence corresponding to the discrete current response signal. The first corresponding to the discrete current response signal A discrete time series Let be the length of the discrete time series corresponding to the discrete current response signal. It is the imaginary unit.

[0071] The control module 2303 is specifically used to determine multiple turn-on times corresponding to multiple preset capacitance ranges based on the maximum value of multiple preset capacitance ranges and the resistance of the current-limiting branch; establish a correspondence table between multiple preset capacitance ranges and multiple turn-on times; determine the target preset capacitance range corresponding to the capacitance value of the load, where the multiple preset capacitance ranges include the target preset capacitance range; look up the turn-on time corresponding to the target preset capacitance range in the correspondence table; and control the current-limiting branch to turn on according to the turn-on time so that the capacitor at the load end can complete charging.

[0072] The control module 2303 determines multiple turn-on times corresponding to multiple preset capacitance ranges based on the maximum value of multiple preset capacitance ranges and the resistance of the current limiting branch, including: determining multiple time constants based on the maximum value of multiple preset capacitance ranges and the resistance of the current limiting branch; and determining multiple turn-on times based on multiple time constants and preset values.

[0073] Based on the same inventive concept, embodiments of the present invention also provide an electronic device. Figure 24 This is a structural diagram of the electronic device in an embodiment of the present invention. See also... Figure 24 As shown, the electronic device 240 may include: at least one processor 2401; and at least one memory 2402 and bus 2403 connected to the processor 2401; wherein the processor 2401 and the memory 2402 communicate with each other through the bus 2403; the processor 2401 is used to call program instructions in the memory 2402 to execute the method of controlling charging time based on load end capacity in one or more of the above embodiments.

[0074] It should be noted that the above description of the system embodiment for controlling charging time based on load-side capacitance is similar to the description of the method embodiment for controlling charging time based on load-side capacitance, and has similar beneficial effects. For any technical details not disclosed in the system embodiment of the present invention, please refer to the description of the method embodiment for controlling charging time based on load-side capacitance.

[0075] The above are merely specific embodiments of the present invention, but the scope of protection of the present invention is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in the present invention should be included within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.

Claims

1. A method for controlling charging time based on load capacitance, characterized in that, include: Based on the solid-state power control unit circuit, a corresponding simulation model is established in the dynamic system modeling tool, and a fitting curve is determined through the simulation model. The fitting curve is used to indicate the relationship between the ratio of the preset real part of the load terminal and the capacitance value at different angular frequencies. The solid-state power control unit circuit is connected to the sampling circuit, FPGA, and load terminal. The current-limiting branch in the solid-state power control unit circuit is turned on and off to generate a current response signal and a voltage signal at the load terminal. The current response signal and the voltage signal are processed sequentially using the sampling circuit, Fourier transform, the FPGA, and the fitting curve to obtain the capacitance value at the load terminal. Based on the maximum value of multiple preset capacitance ranges, the resistance of the current-limiting branch, and the capacitance of the load terminal, the turn-on time of the current-limiting branch is determined, and the current-limiting branch is turned on according to the turn-on time so that the capacitor at the load terminal can be fully charged.

2. The method for controlling charging time based on load-side capacitance as described in claim 1, characterized in that, The circuit controls the switching on and off of the current-limiting branch in the solid-state power control unit to generate a current response signal and a voltage signal at the load terminal. The current response signal and the voltage signal are then processed sequentially using the sampling circuit, Fourier transform, the FPGA, and the fitted curve to obtain the capacitance value at the load terminal, including: Control the MOSFET device in the current-limiting branch to turn on and off, so as to generate the current response signal and the voltage signal at the load terminal; The sampling circuit is used to sample the current response signal and the voltage signal to obtain discrete current response signals and discrete voltage signals. Perform Fourier transform on the discrete current response signal and the discrete voltage signal to obtain the transformed current response signal and the transformed voltage signal; Based on the transformed current response signal and the transformed voltage signal, determine the discrete impedance expression; Using an FPGA with the discrete impedance expression set and multiple angular frequencies, the ratio of the target real part of the load at different angular frequencies is determined; The ratio of the target real part of the load at different angular frequencies is substituted into the fitted curve to obtain the capacitance value of the load.

3. The method for controlling charging time based on load-side capacitance as described in claim 2, characterized in that, The control of turning the MOSFET device in the current-limiting branch on and off to generate the current response signal and the voltage signal at the load terminal includes: The MOSFET device in the current-limiting branch is controlled to turn on and off, generating a square wave signal; The square wave signal is controlled to flow through the load terminal to generate the corresponding current response signal and voltage signal at the load terminal.

4. The method for controlling charging time based on load-side capacitance as described in claim 2, characterized in that, The step of determining the ratio of the target real part of the load at different angular frequencies using an FPGA with the discrete impedance expression and multiple angular frequencies includes: Using an FPGA with the discrete impedance expressions configured, the real part of the load terminal at the target angular frequency is determined, where the target angular frequency is different from all of the plurality of angular frequencies. Based on the real part of the load terminal at the target angular frequency and the plurality of angular frequencies, determine the target real part of the load terminal at different angular frequencies; Based on the target real part of the load at different angular frequencies, determine the ratio of the target real parts of the load at different angular frequencies.

5. The method for controlling charging time based on load-side capacitance according to claim 2, characterized in that, The discrete impedance expression is as follows: ； in, For the discrete impedance, This refers to the discrete time series corresponding to the discrete voltage signal. The voltage signal corresponding to the first A discrete time series The sampling period is The length of the discrete time series corresponding to the discrete voltage signal is given. This refers to the discrete time series corresponding to the discrete current response signal. The first corresponding to the discrete current response signal A discrete time series The length of the discrete time series corresponding to the discrete current response signal is given. It is the imaginary unit.

6. The method for controlling charging time based on load-side capacitance as described in claim 1, characterized in that, The step of determining the activation time of the current-limiting branch based on the maximum value of multiple preset capacitance ranges, the resistance of the current-limiting branch, and the capacitance of the load terminal, and controlling the activation of the current-limiting branch according to the activation time to enable the capacitor at the load terminal to complete charging, includes: Based on the maximum value of the plurality of preset capacitance ranges and the resistance of the current-limiting branch, determine the plurality of turn-on times corresponding to the plurality of preset capacitance ranges; Establish a correspondence table between the multiple preset tolerance ranges and the multiple activation times; Determine the target preset capacitance range corresponding to the capacitance value of the load end, wherein the plurality of preset capacitance ranges include the target preset capacitance range; In the corresponding relationship table, find the activation time corresponding to the target preset tolerance range; The current-limiting branch is activated according to the activation time so that the capacitor at the load end can be fully charged.

7. The method for controlling charging time based on load-side capacitance as described in claim 6, characterized in that, The step of determining multiple turn-on times corresponding to the multiple preset capacitance ranges based on the maximum value of the multiple preset capacitance ranges and the resistance of the current-limiting branch includes: Based on the maximum value of the multiple preset capacitance ranges and the resistance of the current-limiting branch, determine the corresponding multiple time constants; The multiple activation times are determined based on the multiple time constants and preset values.

8. A system for controlling charging time based on load capacitance, characterized in that, include: A module is established to create a corresponding simulation model in a dynamic system modeling tool based on the solid-state power control unit circuit, and to determine a fitting curve through the simulation model. The fitting curve is used to indicate the relationship between the ratio of the preset real part of the load terminal and the capacitance value at different angular frequencies. The solid-state power control unit circuit is connected to the sampling circuit, the FPGA, and the load terminal. The processing module is used to control the opening and closing of the current-limiting branch in the solid-state power control unit circuit to generate a current response signal and a voltage signal at the load terminal, and to process the current response signal and the voltage signal sequentially using the sampling circuit, Fourier transform, the FPGA and the fitting curve to obtain the capacitance value at the load terminal. The control module is used to determine the turn-on time of the current-limiting branch based on the maximum value of multiple preset capacitance ranges, the resistance of the current-limiting branch and the capacitance of the load terminal, and to control the current-limiting branch to turn on according to the turn-on time so that the capacitor of the load terminal can be charged.

9. The system for controlling charging time based on load-side capacitance as described in claim 8, characterized in that, The processing module is specifically used to control the MOSFET devices in the current-limiting branch to turn on and off, thereby generating the current response signal and the voltage signal at the load terminal; to sample the current response signal and the voltage signal using the sampling circuit to obtain discrete current response signals and discrete voltage signals; to perform Fourier transform on the discrete current response signals and discrete voltage signals to obtain transformed current response signals and transformed voltage signals; to determine discrete impedance expressions based on the transformed current response signals and transformed voltage signals; to determine the ratio of the target real parts of the load terminal at different angular frequencies using an FPGA configured with the discrete impedance expressions and multiple angular frequencies, wherein the multiple angular frequencies are all different; and to substitute the ratio of the target real parts of the load terminal at different angular frequencies into the fitting curve to obtain the capacitance value of the load terminal.

10. An electronic device, characterized in that, The electronic device includes: At least one processor; and at least one memory and bus connected to the processor; The processor and the memory communicate with each other through the bus; the processor is used to call program instructions in the memory to execute the method of controlling charging time based on load capacity as described in any one of claims 1 to 7.

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