Improved hybrid clamping three-level structure and loss suppression method thereof

Abstract

The invention discloses an improved hybrid clamping three-level structure and a loss suppression method, and aims to suppress surge current and reduce switching loss by introducing a buffer inductor between a DC bus capacitor and the midpoint of a clamping diode, and maintain the inherent voltage self-balancing capability of the topology at the same time. Experimental verification shows that the surge current can be reduced to the level close to the load current, the turn-on loss is averagely reduced by 23%, and the reliability and efficiency of the series-connected SiC MOSFETs in medium-voltage direct-current application are remarkably improved.

Description

Technical Field

[0001] This invention relates to the technical field of power electronic conversion, and in particular to an improved hybrid clamp three-level structure and its loss suppression method. Background Technology

[0002] With the rapid development of applications such as renewable energy grid connection, industrial frequency conversion drives, and medium-voltage DC (MVDC) power distribution, the demand for high-voltage, large-capacity, high-efficiency, and high-power-density converters in power electronic systems is becoming increasingly urgent. Traditional two-level topologies, limited by device withstand voltage bottlenecks and switching losses, cannot directly meet the application requirements of bus voltages above 3.3kV. Multilevel technology, through device series connection or capacitor voltage division, reduces the voltage stress on individual devices while improving output waveform quality and system efficiency, and has become the mainstream solution for medium- and high-voltage applications.

[0003] Among various multilevel topologies, diode-clamped (NPC) and flying capacitor (FC) topologies have been widely studied due to their relatively simple structure and high degree of modularity. In recent years, a hybrid-clamped three-level topology has emerged, combining the advantages of both types: on the one hand, it utilizes clamping diodes to achieve voltage clamping of devices on the inner side of the bridge arm; on the other hand, it achieves midpoint potential self-balancing through dynamic energy exchange between the flying capacitor and the DC bus capacitor. This topology exhibits significant advantages in applications such as wind power converters, photovoltaic inverters, and medium-voltage DC transformers.

[0004] However, existing hybrid clamp three-level topologies still have problems in practical applications, such as excessive surge current and increased turn-on losses caused by the switched capacitor loop under quasi-two-level (Q2L) modulation. Summary of the Invention

[0005] The purpose of this invention is to overcome the shortcomings of the prior art and provide an improved hybrid clamp three-level structure and loss suppression method.

[0006] To achieve the above objectives, the technical solutions provided by the present invention are:

[0007] An improved hybrid clamping three-level structure includes a main power bridge arm, a clamping circuit, DC bus capacitors C1 and C2, a buffer inductor L, and an output inductor L. L Output filter capacitor C L Load R L ;

[0008] The main power bridge arm includes SiC MOSFETs S1, S2, S3, and S4 connected in series. The drain of S1 is connected to the high-potential end of the DC bus, the source of S1 is connected to the drain of S2, the source of S2 is connected to the drain of S3, the source of S3 is connected to the drain of S4, and the source of S4 is connected to the low-potential end of the DC bus.

[0009] The clamping circuit includes clamping diodes D1 and D2 and flying capacitor C3; clamping diodes D1 and D2 are connected in series and in parallel with C3; the cathode of clamping diode D1 and one end of C3 are connected between S1 and S2; the anode of clamping diode D2 and the other end of C3 are connected between S3 and S4.

[0010] The DC bus capacitors C1 and C2 are connected in series, and their two ends are connected to the drain of S1 and the source of S4, respectively.

[0011] One end of the buffer inductor L is connected to the DC bus capacitors C1 and C2, and the other end of the buffer inductor L is connected to the clamping diodes D1 and D2.

[0012] Output inductor L L One end is connected to S2 and S3;

[0013] Output filter capacitor C L and load R L Connected in parallel, one end of each is connected to the output inductor L L The other end is connected, and the other end of both is connected to the source of S4.

[0014] Furthermore, the present invention also provides a loss suppression method for the above-mentioned improved hybrid clamp three-level structure, comprising:

[0015] A quasi-two-level modulation strategy is used to control the switching states of SiC MOSFETs S1, S2, S3, and S4, so that the topology output voltage V... M DC bus voltage V i Intermediate level V i Switching between / 2 and zero levels, with the duration ΔT of the intermediate level being hundreds of nanoseconds, ensures that the clamping circuit only participates in operation for a short time;

[0016] The surge current in the switched capacitor loop is suppressed by the buffer inductor L, reducing the turn-on loss of SiC MOSFET S1. At the same time, the voltage self-balance of each device is maintained by the synergistic effect of the clamping circuit and the switched capacitor loop.

[0017] The switched capacitor loop includes SiC MOSFETs S1, S2, S3, and S4, and DC bus capacitors C1 and C2.

[0018] Furthermore, the inductance value of the buffer inductor L satisfies:

[0019]

[0020] Among them, I o1 , I o2ΔT is the load current component, ΔT is the duration of the intermediate level, C3' is the capacitance of the flying capacitor C3, and L_max is the maximum inductance value to avoid increasing the size of the converter and introducing additional losses.

[0021] Furthermore, when S1 and S2 are on and S3 and S4 are off, the topology output voltage V M For V i When S1 is off and S2 is on, the flying capacitor C3 discharges through the clamping diode D2. The buffer inductor L limits the discharge current slope, and the topology output voltage V... M For V i / 2; When S1 and S2 are off, the topology output voltage V M The value is 0, and the intermediate level V is... i The duration ΔT of / 2 is set to several hundred nanoseconds; when S1 is turned on, the buffer inductor L suppresses the surge current of the DC bus capacitor C1 charging the flying capacitor C3, shortening the drain-source voltage V of S1. DS The fall time reduces the overlap loss between voltage and current.

[0022] Furthermore, when the switched capacitor loop is formed, the buffer inductor L limits the rate of change of the loop current, reducing the peak surge current to near the load current.

[0023] Furthermore, during voltage self-balancing, the charging and discharging process of the switched capacitor loop causes the power supply of the flyaway capacitor C3 to... Maintain at V i Around / 2;

[0024] In continuous conduction mode, the discharge of the flying capacitor C3 in the intermediate state prevents its voltage from becoming too high, ultimately causing...

[0025] Compared with existing technologies, the principles and advantages of this technical solution are as follows:

[0026] 1. Reduced losses: The buffer inductor reduces the overlap time between surge current and voltage, resulting in an average reduction of 23% in turn-on losses.

[0027] 2. Reduced current stress: Surge current is suppressed to near the load current level, reducing the risk of device damage.

[0028] 3. Maintain self-balancing: It does not rely on additional closed-loop control, but maintains voltage balance through the inherent mechanism of the topology, simplifying system design.

[0029] 4. Strong compatibility: Suitable for medium-voltage DC-DC conversion scenarios, compatible with the high-frequency characteristics of SiC MOSFETs, and improves power density. Attached Figure Description

[0030] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the services required in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings in the following description are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0031] Figure 1 This is a schematic diagram of an improved hybrid clamping three-level structure according to the present invention;

[0032] Figure 2 Waveform diagram of the quasi-two-level modulation strategy for the existing hybrid clamp three-level structure;

[0033] Figure 3 The waveform diagram shows a quasi-two-level modulation strategy for an improved hybrid clamping three-level structure according to the present invention.

[0034] Figure 4 This is a schematic diagram of the operation of the switched capacitor loop in an improved hybrid clamping three-level structure of the present invention;

[0035] Figure 5 The waveform comparison diagram is shown for the double pulse test (a represents the unbuffered inductor, and b represents the buffered inductor). Detailed Implementation

[0036] The present invention will be further described below in conjunction with specific embodiments:

[0037] like Figure 1 As shown in the figure, the improved hybrid clamping three-level structure described in this embodiment includes a main power bridge arm, a clamping circuit, DC bus capacitors C1 and C2, a buffer inductor L, and an output inductor L. L Output filter capacitor C L Load R L ;

[0038] The main power bridge arm includes SiC MOSFETs S1, S2, S3, and S4 connected in series. The drain of S1 is connected to the high-potential end of the DC bus, the source of S1 is connected to the drain of S2, the source of S2 is connected to the drain of S3, the source of S3 is connected to the drain of S4, and the source of S4 is connected to the low-potential end of the DC bus.

[0039] The clamping circuit includes clamping diodes D1 and D2 and flying capacitor C3; clamping diodes D1 and D2 are connected in series and in parallel with C3; the cathode of clamping diode D1 and one end of C3 are connected between S1 and S2; the anode of clamping diode D2 and the other end of C3 are connected between S3 and S4.

[0040] The DC bus capacitors C1 and C2 are connected in series, and their two ends are connected to the drain of S1 and the source of S4, respectively.

[0041] One end of the buffer inductor L is connected to the DC bus capacitors C1 and C2, and the other end of the buffer inductor L is connected to the clamping diodes D1 and D2.

[0042] Output inductor L L One end is connected to S2 and S3;

[0043] Output filter capacitor C L and load R L Connected in parallel, one end of each is connected to the output inductor L L The other end is connected, and the other end of both is connected to the source of S4.

[0044] In the above structure, the SiC MOSFETs are selected as 1700V devices (such as ASC800N1700MED), and four are connected in series to withstand a 2000V bus voltage.

[0045] Capacitor parameters: C1 and C2 are 10μF (DC bus support), C3 is 100nF (flying capacitor to ensure controllable voltage ripple);

[0046] Buffer inductor L: 800nH, satisfying... Among them, I o1 , I o2 ΔT is the load current component, ΔT is the duration of the intermediate level, C′3 is the capacitance of the flying capacitor C3, and L_max is the maximum inductance value to avoid increasing the size of the converter and introducing additional losses.

[0047] Clamping diodes D1 and D2: High-frequency SiC diodes (such as C4D20120A) are selected, capable of withstanding V i / 2 voltage.

[0048] The improved loss suppression method for the hybrid clamp three-level structure mentioned above includes:

[0049] A quasi-two-level modulation strategy is used to control the switching states of SiC MOSFETs S1, S2, S3, and S4, so that the topology output voltage V... M DC bus voltage V i Intermediate level V i Switching between / 2 and zero levels, with the duration ΔT of the intermediate level being hundreds of nanoseconds, ensures that the clamping circuit only participates in operation for a short time;

[0050] The surge current in the switched capacitor loop is suppressed by the buffer inductor L, reducing the turn-on loss of SiC MOSFET S1. At the same time, the voltage self-balance of each device is maintained by the synergistic effect of the clamping circuit and the switched capacitor loop.

[0051] The switched capacitor loop includes SiC MOSFETs 1, S2, S3, and S4, DC bus capacitors C1 and C2, clamping diodes D1 and D2, and flying capacitor C3.

[0052] In the quasi-two-level modulation strategy, when S1 and S2 are on and S3 and S4 are off, the topology output voltage V M For V i When S1 is off and S2 is on, the flying capacitor C3 discharges through the clamping diode D2. The buffer inductor L limits the discharge current slope, and the topology output voltage V... M For V i / 2; When S1 and S2 are off, the topology output voltage V M The value is 0, and the intermediate level V is... i The duration ΔT of / 2 is set to several hundred nanoseconds; when S1 is turned on, the buffer inductor L suppresses the surge current of the DC bus capacitor C1 charging the flying capacitor C3, shortening the drain-source voltage V of S1. DS The fall time reduces the overlap loss between voltage and current.

[0053] When the switched capacitor loop is formed, the buffer inductor L limits the rate of change of the loop current, reducing the peak surge current to close to the load current.

[0054] During voltage self-balancing, the charging and discharging process of the switched capacitor loop causes the power supply V across capacitor C3 to... C3 Maintain at V i Around / 2;

[0055] In continuous conduction mode, the discharge of the flying capacitor C3 in the intermediate state prevents its voltage from becoming too high, ultimately causing...

[0056] Experimental verification

[0057] Double Pulse Test (DPT): Under a bus voltage of 2000V and a load current of 20-60A, compare the results with and without a buffer inductor.

[0058] Surge current: decreased from 129.5A (without surge current) to 80.7A (with surge current), a decrease of 37.7%;

[0059] Turn-on loss: decreased from 9.12 mJ (without L) to 6.94 mJ (with L), an average reduction of 23%.

[0060] Continuous operation test: under 1000V / 20A conditions, The voltage was stabilized at 500V±18.5V to verify its self-balancing capability.

[0061] This invention addresses the inrush current and additional turn-on losses caused by the switched capacitor loop in an improved hybrid clamped three-level topology employing a quasi-two-level modulation strategy. To mitigate these issues, a buffer inductor is introduced between the DC bus capacitor and the midpoint of the clamping diode. This reduces inrush current and switching losses while maintaining the topology's inherent voltage self-balancing capability. Experimental results demonstrate that the method described in this invention can reduce inrush current to near-load current levels and lower turn-on losses by an average of 23%, significantly improving the reliability and efficiency of series-connected SiC MOSFETs in medium-voltage DC applications.

[0062] The embodiments described above are only preferred embodiments of the present invention and are not intended to limit the scope of implementation of the present invention. Therefore, any changes made based on the shape and principle of the present invention should be included in the scope of protection of the present invention.

Claims

1. An improved hybrid clamping three-level structure, characterized in that, Includes the main power bridge arm, clamping circuit, DC bus capacitors C1 and C2, buffer inductor L, and output inductor L. L Output filter capacitor C L Load R L ; The main power bridge arm includes SiC MOSFETs S1, S2, S3, and S4 connected in series. The drain of S1 is connected to the high-potential end of the DC bus, the source of S1 is connected to the drain of S2, the source of S2 is connected to the drain of S3, the source of S3 is connected to the drain of S4, and the source of S4 is connected to the low-potential end of the DC bus. The clamping circuit includes clamping diodes D1 and D2 and flying capacitor C3; clamping diodes D1 and D2 are connected in series and in parallel with C3; the cathode of clamping diode D1 and one end of C3 are connected between S1 and S2; the anode of clamping diode D2 and the other end of C3 are connected between S3 and S4. The DC bus capacitors C1 and C2 are connected in series, and their two ends are connected to the drain of S1 and the source of S4, respectively. One end of the buffer inductor L is connected to the DC bus capacitors C1 and C2, and the other end of the buffer inductor L is connected to the clamping diodes D1 and D2. Output inductor L L One end is connected to S2 and S3; Output filter capacitor C L and load R L Connected in parallel, one end of each is connected to the output inductor L. L The other end is connected, and the other end of both is connected to the source of S4.

2. A loss suppression method for the improved hybrid clamp three-level structure as described in claim 1, characterized in that, include: A quasi-two-level modulation strategy is used to control the switching states of SiC MOSFETs S1, S2, S3, and S4, so that the topology output voltage V... M DC bus voltage V i Intermediate level V i Switching between / 2 and zero levels, with the duration ΔT of the intermediate level being hundreds of nanoseconds, ensures that the clamping circuit only participates in operation for a short time; The surge current in the switched capacitor loop is suppressed by the buffer inductor L, reducing the turn-on loss of SiC MOSFET S1. At the same time, the voltage self-balance of each device is maintained by the synergistic effect of the clamping circuit and the switched capacitor loop. The switched capacitor loop includes SiC MOSFETs S1, S2, S3, and S4, DC bus capacitors C1 and C2, clamping diodes D1 and D2, and flying capacitor C3.

3. The loss suppression method according to claim 2, characterized in that, The inductance value of the buffer inductor L satisfies: Among them, I o1 I o2 ΔT is the load current component, ΔT is the duration of the intermediate level, C′3 is the capacitance of the flying capacitor C3, and L_max is the maximum inductance value to avoid increasing the size of the converter and introducing additional losses.

4. The loss suppression method according to claim 2, characterized in that, In the quasi-two-level modulation strategy, when S1 and S2 are on and S3 and S4 are off, the topology output voltage V M For V i When S1 is off and S2 is on, the flying capacitor C3 discharges through the clamping diode D2. The buffer inductor L limits the discharge current slope, and the topology output voltage V... M For V i / 2; When S1 and S2 are off, the topology output voltage V M The value is 0, and the intermediate level V is... i The duration ΔT of / 2 is set to several hundred nanoseconds; when S1 is turned on, the buffer inductor L suppresses the surge current of the DC bus capacitor C1 charging the flying capacitor C3, shortening the drain-source voltage V of S1. DS The fall time reduces the overlap loss between voltage and current.

5. The loss suppression method according to claim 2, characterized in that, When the switched capacitor loop is formed, the buffer inductor L limits the rate of change of the loop current, reducing the peak surge current to close to the load current.

6. The loss suppression method according to claim 2, characterized in that, During voltage self-balancing, the charging and discharging process of the switched capacitor loop causes the power supply of the flyaway capacitor C3 to... Maintain at V i Around / 2; In continuous conduction mode, the discharge of the flying capacitor C3 in the intermediate state prevents its voltage from becoming too high, ultimately causing...

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