Filter circuit and MCU
By designing a filter circuit that includes rising edge and falling edge filtering units, the problem of not being able to filter rising edge and falling edge glitches simultaneously in the prior art is solved, achieving a stable signal filtering effect and improving the accuracy of the chip's logic calculation.
Patent Information
- Application Number
- CN202511003528.9
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-07-21
- Publication Date
- 2025-10-28
AI Technical Summary
Existing filtering circuits cannot effectively filter glitch signals on both the rising and falling edges, resulting in chip logic calculation errors.
Design a filter circuit that includes a rising edge filter unit and a falling edge filter unit, which are used to filter glitches on the rising and falling edges respectively, and restore the output signal through a signal output unit, thereby achieving simultaneous filtering of rising and falling edge glitches.
It achieves simultaneous filtering of rising and falling edge glitches, improving the accuracy of the chip's logic calculation. The filtering time is adjustable and is unaffected by external temperature and voltage.
Smart Images
Figure CN120856100A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of signal filtering technology, specifically to a filtering circuit and an MCU. Background Technology
[0002] During chip use, due to factors such as power supply jitter and electromagnetic interference in the environment, glitches may occur in the signals inside the chip. Although the glitches are very short, often ranging from tens of picoseconds to tens of nanoseconds, if they are not dealt with, they will cause timing errors in the CPU part of the chip, which in turn will lead to errors in the chip's logic calculations.
[0003] To avoid the impact of glitches on the chip, the chip often has an internal filter to filter the glitches. Since the glitches may be erroneous rising edge signals or erroneous falling edge signals, existing filtering circuits can often only filter rising edge glitches or falling edge glitches, and cannot filter both rising edge glitches and falling edge glitches at the same time. Summary of the Invention
[0004] In view of the shortcomings of the prior art, the present invention provides a filtering circuit and an MCU for simultaneously filtering glitches on rising and falling edges.
[0005] To solve the above technical problems, in a first aspect, the present invention provides the following technical solution: a filtering circuit, comprising a rising edge filtering unit, a falling edge filtering unit, and a signal output unit; the signal input terminal of the rising edge filtering unit and the signal input terminal of the falling edge filtering unit are electrically connected; The rising edge filtering unit is used to filter out the high-level signal within a first preset time T1 when the signal input at the signal input terminal changes from low level to high level, and output the first filtered signal. The falling edge filtering unit is used to filter out the low-level signal within the second preset time T2 when the signal input at the signal input terminal changes from high level to low level, and output the second filtered signal. The signal output unit is electrically connected to the rising edge filtering unit and the falling edge filtering unit respectively, and outputs a third filtering signal based on the first filtering signal and the second filtering signal. When the high-level time of the signal is greater than the first preset time T1, the rising edge of the third filtered signal lags behind the rising edge of the signal by the first preset time T1, and the falling edge of the third filtered signal lags behind the falling edge of the signal by the second preset time T2.
[0006] In one embodiment of the first aspect, the rising edge filtering unit includes an inverter INV10, a MOSFET P10, a MOSFET N10, a capacitor C10, a comparator CMP10, and an AND gate AND10; The input terminal of the inverter INV10 is the signal input terminal of the rising edge filter unit, used to input the signal. The output terminal of the inverter INV10 is electrically connected to the gate of MOSFET P10 and the gate of MOSFET N10, respectively. The source of MOSFET P10 is used to input the bias current I2. The drain of MOSFET P10 is electrically connected to the drain of MOSFET N10, one end of capacitor C10, and the positive input terminal of comparator CMP10, respectively. The other end of capacitor C10 and the source of MOSFET N10 are both grounded. The negative input terminal of comparator CMP10 is used to input the first reference voltage. The output terminal of comparator CMP10 is electrically connected to one input terminal of AND gate AND10. The other input terminal of AND gate AND10 is electrically connected to the signal input terminal. The output terminal of AND gate AND10 outputs the first filtered signal.
[0007] In one embodiment of the first aspect, the falling edge filtering unit includes a MOSFET P20, a MOSFET N20, a capacitor C20, a comparator CMP20, an inverter INV20, and an OR gate OR20; The gate of MOSFET P20 is electrically connected to the gate of MOSFET N20, serving as the signal input terminal of the falling edge filter unit. The source of MOSFET P20 is used to input the bias current I3. The drain of MOSFET P20 is electrically connected to the drain of MOSFET N20, one end of capacitor C20, and the positive input terminal of comparator CMP20. The source of MOSFET N20 and the other end of capacitor C20 are both grounded. The negative input terminal of comparator CMP20 is used to input the second reference voltage. The output terminal of comparator CMP20 is electrically connected to the input terminal of inverter IN20. The output terminal of inverter INV20 is electrically connected to one input terminal of OR gate OR20. The other input terminal of OR gate OR20 is electrically connected to the signal input terminal. The output terminal of OR gate OR20 outputs the second filtered signal.
[0008] In one embodiment of the first aspect, the first reference voltage and the second reference voltage are of the same magnitude.
[0009] In one embodiment of the first aspect, the invention further includes a reference unit for generating the first reference voltage, bias current I2, and bias current I3.
[0010] In one embodiment of the first aspect, the reference unit includes a voltage divider circuit, an operational amplifier OP, a resistor R3, a MOSFET P1, a MOSFET P2, and a MOSFET P3; The input terminal of the voltage divider circuit, the source of MOSFET P1, the source of MOSFET P2, and the source of MOSFET P3 are used to connect to the power supply voltage VDD. One voltage divider node of the voltage divider circuit is electrically connected to the positive input terminal of the operational amplifier OP. The output terminal of the operational amplifier OP is electrically connected to the gate of MOSFET P1, the drain of MOSFET P1, the gate of MOSFET P2, and the gate of MOSFET P3, respectively. The drain of MOSFET P1 is grounded through resistor R3 and electrically connected to the negative input terminal of the operational amplifier OP. The voltage across resistor R3 is the first reference voltage. The drain of MOSFET P2 is used to output the bias current I2, and the drain of MOSFET P3 is used to output the bias current I3.
[0011] In one embodiment of the first aspect, the bias current I2 and the bias current I3 are of the same magnitude, and the capacitance values of capacitor C10 and capacitor C20 are the same.
[0012] In one embodiment of the first aspect, the voltage divider circuit includes resistors R1 and R2, one end of resistor R1 is used to connect to the power supply voltage VDD, the other end of resistor R1 is the voltage divider node, and is grounded through resistor R2.
[0013] In one embodiment of the first aspect, the signal output unit includes an XOR gate XOR30, an inverter INV30, and a latch LATCH. The two input terminals of the XOR gate XOR30 are used to input a first filtered signal and a second filtered signal, respectively. The output terminal of the XOR gate XOR30 is electrically connected to the input terminal of the inverter INV30. The output terminal of the inverter INV30 is electrically connected to the clock input terminal CLK of the latch LATCH. The D input terminal of the latch LATCH is used to input the second filtered signal, and the Q output terminal of the latch LATCH is used to output a third filtered signal.
[0014] Secondly, the present invention also provides an MCU, wherein the MCU is provided with the above-mentioned filtering circuit.
[0015] The beneficial effects of this invention compared with the prior art are as follows: In actual use, this invention filters the rising edge glitch signal through the rising edge filtering unit to filter out the high-level signal within the first preset time T1, filters the falling edge glitch signal through the falling edge filtering unit to filter out the low-level signal within the second preset time T2, and restores the output signal through the signal output unit, thereby enabling simultaneous filtering of rising edge glitch and falling edge glitch signals. Attached Figure Description
[0016] Figure 1 This is a schematic diagram of the filter circuit in Example 1; Figure 2This is a circuit diagram of the rising edge filtering unit in Example 1; Figure 3 The circuit diagram is shown for the falling edge filtering unit in Embodiment 1. Figure 4 This is a circuit diagram of the reference unit in Embodiment 1; Figure 5 This is a circuit diagram of the signal output unit in Embodiment 1; Figure 6 for Figure 2 The circuit shown has relevant waveforms when in use. Figure 7 for Figure 2 The circuit shown presents the relevant waveforms when filtering rising edge glitches. Figure 8 for Figure 3 The circuit shown has relevant waveforms when in use. Figure 9 for Figure 3 The circuit shown is used for filtering rising edge glitches. Figure 10 for Figure 5 The circuit shown has relevant waveforms when in use. Detailed Implementation
[0017] The present invention will now be described in further detail with reference to the accompanying drawings. These drawings are simplified schematic diagrams, illustrating only the basic structure of the invention, and therefore only show the components relevant to the invention.
[0018] Example 1 like Figure 1 As shown, the filtering circuit provided in this embodiment includes a rising edge filtering unit 1, a falling edge filtering unit 2, and a signal output unit 3; the signal input terminal of the rising edge filtering unit 1 and the signal input terminal of the falling edge filtering unit 2 are electrically connected. The rising edge filtering unit 1 is used to filter out the high-level signal within the first preset time T1 when the signal IN input at the signal input terminal changes from low level to high level, and output the first filtered signal OUT1. The falling edge filtering unit 2 is used to filter out the low-level signal within the second preset time T2 when the signal IN input at the signal input terminal changes from high level to low level, and output the second filtered signal OUT2. Signal output unit 3 is electrically connected to rising edge filter unit 1 and falling edge filter unit 2 respectively, and outputs third filter signal OUT based on first filter signal OUT1 and second filter signal OUT2. When the high-level time of signal IN is greater than the first preset time T1, the rising edge of the third filter signal OUT lags behind the rising edge of signal IN by the first preset time T1, and the falling edge of the third filter signal OUT lags behind the falling edge of signal IN by the second preset time T2.
[0019] In practical use, the present invention filters the rising edge glitch signal through the rising edge filtering unit 1 to filter out the high-level signal within the first preset time T1, filters the falling edge glitch signal through the falling edge filtering unit 2 to filter out the low-level signal within the second preset time T2, and restores the output signal through the signal output unit 3, thereby enabling simultaneous filtering of rising edge glitch and falling edge glitch signals.
[0020] Currently, the two commonly used filtering methods are as follows: 1. Filtering using a digital filter with a high-frequency clock signal. The advantage of this structure is that the filtering time is fixed, typically an integer period of the high-frequency clock. The disadvantage is that it requires a very high-speed clock signal, and the filtering time must be adjusted as a multiple of the high-speed clock signal's period, making the filtering time setting inflexible. 2. Filtering using an analog filter, specifically by inserting capacitors into the signal transmission channel. The advantage of this structure is its low cost, requiring only the addition of capacitors. The disadvantage is that the filtering time is unstable, greatly affected by temperature and voltage. At high and low temperatures, the filtering time can differ by two to three times, requiring a very large window in timing design, resulting in significant resource waste.
[0021] Existing filtering methods lack flexibility in filtering time and are significantly affected by external temperature and voltage. To make the filtering time adjustable and increase filtering reliability, such as... Figure 2 As shown, this embodiment provides The rising edge filter unit 2 includes an inverter INV10, a MOSFET P10, a MOSFET N10, a capacitor C10, a comparator CMP10, and an AND gate AND10; The input terminal of inverter INV10 is the signal input terminal of rising edge filter unit 1, used to input signal IN. The output terminal of inverter INV10 is electrically connected to the gate of MOSFET P10 and the gate of MOSFET N10 respectively. The source of MOSFET P10 is used to input bias current I2. The drain of MOSFET P10 is electrically connected to the drain of MOSFET N10, one end of capacitor C10 and the positive input terminal of comparator CMP10 respectively. The other end of capacitor C10 and the source of MOSFET N10 are both grounded. The negative input terminal of comparator CMP10 is used to input the first reference voltage. The output terminal of comparator CMP10 is electrically connected to one input terminal of AND gate AND10. The other input terminal of AND gate AND10 is electrically connected to the signal input terminal. The output terminal of AND gate AND10 outputs the first filtered signal OUT2.
[0022] for Figure 2 The timing diagram of the circuit shown is as follows when it performs filtering. Figure 6 As shown, when a rising edge arrives on signal IN, signal A1 goes low. At this time, the bias current I2 charges capacitor C10, and the voltage of signal A2 begins to rise. When the voltage of signal A2 rises to the first reference voltage, signal A3 changes from 0 to a high level. Since signal IN is already at a high level, the first filter signal OUT1 is also at a high level. If a falling edge arrives on signal IN, the first filter signal OUT1 will be directly pulled low by signal IN without any delay.
[0023] When a glitch occurs at signal IN, if the glitch width is less than the first preset time T1, it will be directly filtered out. The relevant timing diagram is as follows: Figure 7 As shown, from Figure 7 It can be seen that the first two burrs with a width less than T1 and the last three burrs with a width less than T1 are all filtered out.
[0024] Furthermore, if the magnitude of the first reference voltage is set to VREF, then T1 = C10 * VREF / I2. The magnitude of the first preset time T1 can be adjusted by adjusting the values of capacitor C10, VREF, and I2.
[0025] Similarly, in this embodiment, the second preset time T2 of the falling edge filtering unit 2 is also adjustable, and its circuit is as follows: Figure 3 As shown, it includes MOSFET P20, MOSFET N20, capacitor C20, comparator CMP20, inverter INV20 and OR gate OR20; The gate of MOSFET P20 is electrically connected to the gate of MOSFET N20, serving as the signal input terminal of falling edge filter unit 2. The source of MOSFET P20 is used to input bias current I3. The drain of MOSFET P20 is electrically connected to the drain of MOSFET N20, one end of capacitor C20, and the positive input terminal of comparator CMP20. The source of MOSFET N20 and the other end of capacitor C20 are both grounded. The negative input terminal of comparator CMP20 is used to input the second reference voltage. The output terminal of comparator CMP20 is electrically connected to the input terminal of inverter IN20. The output terminal of inverter INV20 is electrically connected to one input terminal of OR gate OR20. The other input terminal of OR gate OR20 is electrically connected to the signal input terminal. The output terminal of OR gate OR20 outputs the second filtered signal.
[0026] In practical applications, the timing diagram for processing the IN signal is as follows: Figure 8 As shown, from Figure 8 As can be seen, when a falling edge arrives with signal IN, the voltage of signal A4 slowly rises. During this time, the bias current I3 charges capacitor C20. When signal A4 rises above the second reference voltage, signal A5 changes from a low level to a high level, and signal A6 changes from a high level to a low level. The second filter signal OUT2 also changes from a high level to a low level. When a rising edge arrives with signal IN, the second filter signal OUT2 directly follows signal IN to a high level, without filtering. Therefore, this circuit only filters falling edges.
[0027] When a falling edge glitch occurs at the IN signal, if the glitch width is less than the second preset time T2, it will be directly filtered out. The relevant timing diagram is as follows. Figure 9 As shown, from Figure 9 It can be seen that the first two burrs with a width less than T2 and the last three burrs with a width less than T2 are all filtered out.
[0028] Furthermore, if the magnitude of the second reference voltage is set to VREF, then T2 = C20 * VREF / I3. By adjusting the values of capacitor C20, VREF, and I3, the magnitude of the first preset time T1 can be adjusted. Moreover, when adjusting the value of T1 using the reference circuit described below, no intermediate parameters such as voltage and current are involved, making the adjustment simple and straightforward.
[0029] In this embodiment, in order to make the first preset time T1 and the second preset time T2 the same, the first reference voltage and the second reference voltage have the same magnitude, the bias current I2 and the bias current I3 have the same magnitude, and the capacitance values of capacitor C10 and capacitor C20 have the same value.
[0030] In addition, in this embodiment, in Figure 1In addition, the present invention also includes a reference unit 4, which is used to generate a first reference voltage, a bias current I2 and a bias current I3, wherein the first reference voltage is...
[0031] In addition, in this embodiment, the circuit of the reference unit 4 is as follows: Figure 4 As shown, it includes a voltage divider circuit, operational amplifier OP, resistor R3, MOSFET P1, MOSFET P2 and MOSFET P3; The input terminal of the voltage divider circuit, the source of MOSFET P1, the source of MOSFET P2, and the source of MOSFET P3 are connected to the power supply voltage VDD. One voltage divider node of the voltage divider circuit is electrically connected to the positive input terminal of the operational amplifier OP. The output terminal of the operational amplifier OP is electrically connected to the gate of MOSFET P1, the drain of MOSFET P1, the gate of MOSFET P2, and the gate of MOSFET P3, respectively. The drain of MOSFET P1 is grounded through resistor R3 and electrically connected to the negative input terminal of the operational amplifier OP. The voltage across resistor R3 is the first reference voltage. The drain of MOSFET P2 is used to output the bias current I2, and the drain of MOSFET P3 is used to output the bias current I3.
[0032] In this embodiment, the voltage divider circuit includes resistors R1 and R2. One end of resistor R1 is used to connect to the power supply voltage VDD, and the other end of resistor R1 is the voltage divider node and is grounded through resistor R2.
[0033] for Figure 4 In the circuit shown, the operational amplifier OP uses a negative feedback connection. In this case, VREF and V1 are the same, and the bias current I1 is VREF / R3. MOSFETs P1, P2, and P3 are connected as a current mirror structure. When MOSFETs P1, P2, and P3 are the same, the bias currents I1, I2, and I3 are all the same, which are VREF / R3 respectively. Substituting this calculation formula into the calculation formulas for the first preset time T1 and the second preset time T2, we can obtain T1=R3*C10 and T2=R2*C20. From these two formulas, we can see that the filtering time is independent of the reference voltage and only related to the three parameters: resistor R3, capacitor C10, and capacitor C20. These three parameters are designed resistor and capacitor values and have a very weak correlation with the power supply and temperature, so the filtering time will be very stable.
[0034] Furthermore, for the circuit of this invention, the values of T1 and T2 can be adjusted simultaneously by adjusting resistor R3. T1 and T2 can be made the same by making the first reference voltage and the second reference voltage the same, I2 and I3 the same, and C10 and C20 the same. Ultimately, the pulse width of the third filter signal OUT is consistent with the pulse width of the signal IN, which will not affect the duty cycle.
[0035] In this embodiment, the circuit of the signal output unit 3 is as follows: Figure 5 As shown, the circuit includes an XOR gate XOR30, an inverter INV30, and a latch LATCH. The two inputs of the XOR gate XOR30 are used to input the first filtered signal OUT1 and the second filtered signal OUT2, respectively. The output of the XOR gate XOR30 is electrically connected to the input of the inverter INV30. The output of the inverter INV30 is electrically connected to the clock input CLK of the latch LATCH. The D input of the latch LATCH is used to input the second filtered signal OUT2, and the Q output of the latch LATCH is used to output the third filtered signal OUT.
[0036] In practical use, during the filtering phase, the values of the first filter signal OUT1 and the second filter signal OUT2 are opposite, the XOR gate XOR30 outputs high, and signal A7 is in a low-level state. At this time, the latch LATCH will not transmit the value of the second filter signal OUT2, and the third filter signal OUT will not change with the second filter signal OUT2. When the first filter signal OUT1 and the second filter signal OUT2 are in phase, it means that filtering is over, and signal A7 goes high. At this time, the output of the latch, the third filter signal OUT, will be equal to the value of the second filter signal OUT2. The relevant timing diagram is as follows: Figure 10 As shown, from Figure 10 The relationship between the third filter signal OUT and the signal IN can be obtained from this. That is, when the high level time of the signal IN is greater than the first preset time T1, the rising edge of the third filter signal OUT lags behind the rising edge of the signal IN by the first preset time T1, and the falling edge of the third filter signal OUT lags behind the falling edge of the signal IN by the second preset time T2.
[0037] Example 2 This embodiment also provides an MCU, which is equipped with a filtering circuit as described in Embodiment 1. Based on the above description, those skilled in the art can make various changes and modifications without departing from the technical concept of this invention. The technical scope of this invention is not limited to the contents of the specification, but must be determined according to the scope of the claims.
Claims
1. A filter circuit, characterized in that, It includes a rising edge filtering unit, a falling edge filtering unit, and a signal output unit; the signal input terminal of the rising edge filtering unit and the signal input terminal of the falling edge filtering unit are electrically connected; The rising edge filtering unit is used to filter out the high-level signal within a first preset time T1 when the signal input at the signal input terminal changes from low level to high level, and output the first filtered signal. The falling edge filtering unit is used to filter out the low-level signal within the second preset time T2 when the signal input at the signal input terminal changes from high level to low level, and output the second filtered signal. The signal output unit is electrically connected to the rising edge filtering unit and the falling edge filtering unit respectively, and outputs a third filtering signal based on the first filtering signal and the second filtering signal. When the high-level time of the signal is greater than the first preset time T1, the rising edge of the third filtered signal lags behind the rising edge of the signal by the first preset time T1, and the falling edge of the third filtered signal lags behind the falling edge of the signal by the second preset time T2.
2. The filter circuit according to claim 1, characterized in that, The rising edge filtering unit includes an inverter INV10, a MOSFET P10, a MOSFET N10, a capacitor C10, a comparator CMP10, and an AND gate AND10; The input terminal of the inverter INV10 is the signal input terminal of the rising edge filter unit, used to input the signal. The output terminal of the inverter INV10 is electrically connected to the gate of MOSFET P10 and the gate of MOSFET N10, respectively. The source of MOSFET P10 is used to input the bias current I2. The drain of MOSFET P10 is electrically connected to the drain of MOSFET N10, one end of capacitor C10, and the positive input terminal of comparator CMP10, respectively. The other end of capacitor C10 and the source of MOSFET N10 are both grounded. The negative input terminal of comparator CMP10 is used to input the first reference voltage. The output terminal of comparator CMP10 is electrically connected to one input terminal of AND gate AND10. The other input terminal of AND gate AND10 is electrically connected to the signal input terminal. The output terminal of AND gate AND10 outputs the first filtered signal.
3. A filter circuit according to claim 2, characterized in that, The falling edge filtering unit includes a MOSFET P20, a MOSFET N20, a capacitor C20, a comparator CMP20, an inverter INV20, and an OR gate OR20; The gate of MOSFET P20 is electrically connected to the gate of MOSFET N20, serving as the signal input terminal of the falling edge filter unit. The source of MOSFET P20 is used to input the bias current I3. The drain of MOSFET P20 is electrically connected to the drain of MOSFET N20, one end of capacitor C20, and the positive input terminal of comparator CMP20. The source of MOSFET N20 and the other end of capacitor C20 are both grounded. The negative input terminal of comparator CMP20 is used to input the second reference voltage. The output terminal of comparator CMP20 is electrically connected to the input terminal of inverter IN20. The output terminal of inverter INV20 is electrically connected to one input terminal of OR gate OR20. The other input terminal of OR gate OR20 is electrically connected to the signal input terminal. The output terminal of OR gate OR20 outputs the second filtered signal.
4. A filter circuit according to claim 3, characterized in that, The first reference voltage and the second reference voltage are the same.
5. A filter circuit according to claim 4, characterized in that, It also includes a reference unit, which is used to generate the first reference voltage, bias current I2 and bias current I3.
6. A filter circuit according to claim 5, characterized in that, The reference unit includes a voltage divider circuit, an operational amplifier OP, a resistor R3, a MOSFET P1, a MOSFET P2, and a MOSFET P3; The input terminal of the voltage divider circuit, the source of MOSFET P1, the source of MOSFET P2, and the source of MOSFET P3 are used to connect to the power supply voltage VDD. One voltage divider node of the voltage divider circuit is electrically connected to the positive input terminal of the operational amplifier OP. The output terminal of the operational amplifier OP is electrically connected to the gate of MOSFET P1, the drain of MOSFET P1, the gate of MOSFET P2, and the gate of MOSFET P3, respectively. The drain of MOSFET P1 is grounded through resistor R3 and electrically connected to the negative input terminal of the operational amplifier OP. The voltage across resistor R3 is the first reference voltage. The drain of MOSFET P2 is used to output the bias current I2, and the drain of MOSFET P3 is used to output the bias current I3.
7. A filter circuit according to claim 6, characterized in that, The bias currents I2 and I3 are of the same magnitude, and the capacitances of capacitors C10 and C20 are of the same value.
8. A filter circuit according to claim 6, characterized in that, The voltage divider circuit includes resistors R1 and R2. One end of resistor R1 is used to connect to the power supply voltage VDD, and the other end of resistor R1 is the voltage divider node, and is grounded through resistor R2.
9. A filter circuit according to claim 1, characterized in that, The signal output unit includes an XOR gate (XOR30), an inverter (INV30), and a latch (LATCH). The two inputs of the XOR gate (XOR30) are used to input the first filtered signal and the second filtered signal, respectively. The output of the XOR gate (XOR30) is electrically connected to the input of the inverter (INV30). The output of the inverter (INV30) is electrically connected to the clock input (CLK) of the latch (LATCH). The D input of the latch (LATCH) is used to input the second filtered signal, and the Q output of the latch (LATCH) is used to output the third filtered signal.
10. An MCU, characterized in that, The MCU is equipped with a filtering circuit as described in any one of claims 1-9.