Level shifter, chip, and electronic device
By performing pulse coding and multi-branch level shifting on the level shifter of the half-bridge driver chip, the problems of anti-interference and miniaturization of the level shifter under external interference were solved, and a circuit design with high reliability and low power consumption was achieved.
Patent Information
- Application Number
- CN202411932059.4
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-12-25
- Publication Date
- 2025-10-28
AI Technical Summary
The level shifter of the existing half-bridge driver chip is prone to causing the high voltage IGBT to conduct directly to ground when faced with external interference, resulting in high current damage. In addition, the circuit area is large, making it difficult to meet the requirements of high reliability and miniaturization.
A pulse encoding circuit is used to encode the rising and falling edge information of the control signal, and the signal is shifted from the low voltage domain to the high voltage domain through a level shift circuit with multiple branches. The control signal is restored through a pulse decoding circuit, and a narrow pulse signal is used to reduce circuit power consumption and anti-interference ability.
The anti-interference capability of the level shifter is improved, the circuit area is reduced, the power consumption is reduced, and the requirements of high reliability and miniaturization are met.
Smart Images
Figure CN120856128A_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of circuit technology, and more specifically to a level shifter, chip, and electronic device. Background Technology
[0002] Half-bridge driver chips play a crucial role in modern power electronics, widely used in motor drives, display drivers, automotive electronics, and many other fields. These chips provide the necessary voltage and current to effectively control high-power semiconductor switches, such as Metal-Oxide-Semiconductor Field-Effect Transistors (MOSFETs) and Insulated-Gate Bipolar Transistors (IGBTs). With increasing emphasis on energy conservation and emission reduction, half-bridge driver chips have become particularly critical for achieving efficient motor drive. They not only need high reliability and low cost but also support intelligent functions to meet ever-increasing performance requirements. With the rapid development of electronic technology, especially in power electronics, increasingly higher demands are being placed on the accuracy and stability of current control.
[0003] In half-bridge driver chips, level shifters are a crucial component. They shift control signals from the microcontroller or other control circuits from a low-voltage domain to a high-voltage domain, or vice versa, achieving signal level shifting. Typically, during level shifting, it's essential to prevent external signals from interfering with the control signal. For example, in IGBT applications, significant interference in the circuit can cause the external high-voltage IGBT to conduct directly to ground, triggering a large current and causing irreversible and severe damage to the circuit. Therefore, enhancing the interference immunity of level shifters is of paramount importance. Summary of the Invention
[0004] This application is made to address the aforementioned problems. According to one aspect of this application, a level shifter is provided, the level shifter comprising:
[0005] A pulse coding circuit is used to encode the rising edge information and falling edge information of a first control signal in a first voltage domain to obtain a first set of pulse signals, wherein at least two pulse signals in the first set of pulse signals include the rising edge information and falling edge information of the first control signal.
[0006] A level shifting circuit is used to shift the first group of pulse signals from the first voltage domain to the second voltage domain to obtain a second group of pulse signals, wherein one of the first voltage domain and the second voltage domain is a low voltage domain and the other is a high voltage domain;
[0007] A pulse decoding circuit is used to decode the second set of pulse signals to obtain a second control signal in the second voltage domain.
[0008] The above technical solution has the following technical effects: it can encode the rising and falling edge information of the control signal to be level shifted into a set of pulse signals, wherein each pulse signal in at least two pulse signals contains the rising edge information and falling edge information of the control signal, and has a strong anti-interference capability.
[0009] In one embodiment of this application, the first group of pulse signals includes a first encoded signal, a second encoded signal, and a first reset signal, and the pulse encoding circuit includes:
[0010] The first encoding circuit is used to generate the first encoded signal based on the rising edge information and falling edge information of the first control signal;
[0011] The second encoding circuit is used to generate the second encoded signal based on the rising edge information and falling edge information of the first control signal, wherein the second encoded signal is a delayed signal of the first encoded signal;
[0012] The third encoding circuit is used to generate the first reset signal based on the rising edge information of the first control signal.
[0013] The above technical solution has the following technical effects: the upper and lower edge information of the first control signal are encoded twice, which not only improves the anti-interference ability of the level shifter, but also reduces the amount of calculation and can be implemented with a simple structure, thus avoiding a large circuit area and facilitating device miniaturization.
[0014] In one embodiment of this application, the first encoding circuit includes:
[0015] A first delay unit, wherein the first control signal is input to the input terminal of the first delay unit, and the output terminal of the first delay unit is connected to the input terminal of the first inverter and the first input terminal of the first XNOR gate;
[0016] The first inverter, the output of which is connected to the input of the second delay unit;
[0017] The second delay unit, the output of which is connected to the second input of the first XOR gate;
[0018] The first XOR gate outputs the first encoded signal.
[0019] The above technical solution has the following technical effects: by passing the first control signal after delay and the first control signal after delay, inversion, and further delay through an XNOR gate, the first encoded signal is obtained.
[0020] In one embodiment of this application, the second encoding circuit includes:
[0021] The third delay unit receives the first control signal at its input terminal and its output terminal is connected to the second inverter.
[0022] The output of the second inverter is connected to the input of the third inverter and the first input of the second XNOR gate;
[0023] The output of the third inverter is connected to the input of the fourth delay unit;
[0024] The output of the fourth delay unit is connected to the second input of the second XOR gate;
[0025] The second XOR gate outputs the second encoded signal.
[0026] The above technical solution has the following technical effects: by passing the first control signal after delay and inversion and the first control signal after delay, inversion, re-inversion and further delay through an XNOR gate, a second encoded signal is obtained.
[0027] In one embodiment of this application, the third encoding circuit includes:
[0028] The fifth delay unit receives the first control signal at its input terminal and its output terminal is connected to the first input terminal of the fourth inverter and the first AND gate.
[0029] The output of the fourth inverter is connected to the input of the sixth delay unit;
[0030] The output of the sixth delay unit is connected to the second input of the first AND gate;
[0031] The first AND gate outputs the first reset signal.
[0032] The above technical solution has the following technical effects: by passing the first control signal after delay and the first control signal after delay, inversion, and further delay through an AND gate, a first reset signal is obtained.
[0033] In one embodiment of this application, the second group of pulse signals includes a second reset signal, a third encoded signal, and a fourth encoded signal, and the level shifting circuit includes:
[0034] A first shift circuit is used to shift the first reset signal from the first voltage domain to the second voltage domain to obtain the second reset signal;
[0035] The second shift circuit is used to shift the first encoded signal from the first voltage domain to the second voltage domain to obtain the third encoded signal;
[0036] A third shift circuit is used to shift the second encoded signal from the first voltage domain to the second voltage domain to obtain the fourth encoded signal.
[0037] The above technical solution has the following technical effects: by using three branches to shift the three pulse signals from the first voltage domain to the second voltage domain respectively, the signals do not interfere with each other, the structure is not complicated, the circuit area is not large, and it is conducive to the miniaturization of the device.
[0038] In one embodiment of this application, the first shift circuit includes:
[0039] A first resistor, the first end of which is connected to the voltage source of the second voltage domain and the output terminal of the first Zener diode, and the second end of which is connected to the input terminal of the first Zener diode and the drain of the first transistor;
[0040] The first Zener diode, the input terminal of the first Zener diode and the second terminal of the first resistor are connected to the input terminal of the first driver;
[0041] The first transistor has its gate connected to the first reset signal and its source grounded.
[0042] The first driver outputs the second reset signal from its output terminal.
[0043] The above technical solution has the following technical effects: the first reset signal controls the conduction state of the first transistor, thereby affecting the breakdown state of the first Zener diode, and then the first driver outputs the result after voltage domain conversion.
[0044] In one embodiment of this application, the second shift circuit includes:
[0045] The second resistor has its first end connected to the voltage source of the second voltage domain and the output terminal of the second Zener diode, and its second end connected to the input terminal of the second Zener diode and the drain of the second transistor.
[0046] The second Zener diode, the input terminal of the second Zener diode and the second terminal of the second resistor are connected to the input terminal of the second driver;
[0047] The second transistor has its gate connected to the first encoded signal and its source grounded.
[0048] The second driver outputs the third encoded signal.
[0049] The above technical solution has the following technical effects: the first encoded signal controls the conduction state of the second transistor, thereby affecting the breakdown state of the second Zener diode, and then the second driver outputs the result after voltage domain conversion.
[0050] In one embodiment of this application, the third shift circuit includes:
[0051] The third resistor has its first end connected to the voltage source of the second voltage domain and the output terminal of the third Zener diode, and its second end connected to the input terminal of the third Zener diode and the drain of the third transistor.
[0052] The third Zener diode, the input terminal of the third Zener diode and the second terminal of the third resistor are connected to the input terminal of the third driver;
[0053] The third transistor has its gate connected to the second encoded signal and its source grounded.
[0054] The third driver outputs the fourth encoded signal at its output terminal.
[0055] The above technical solution has the following technical effects: the conduction state of the third transistor is controlled by the second encoded signal, which in turn affects the breakdown state of the third Zener diode, and then the result is output by the third driver after voltage domain conversion.
[0056] In one embodiment of this application, the pulse decoding circuit includes:
[0057] A fourth driver, the input of which is connected to the third encoded signal, and the output of which is connected to the first input of the second AND gate;
[0058] The fifth driver has its input connected to the fourth encoded signal and its output connected to the second input of the second AND gate.
[0059] The second AND gate, the output of which is connected to the clock signal input of the D flip-flop;
[0060] The D flip-flop has the second reset signal input at its reset signal input terminal and the second control signal output at its output terminal.
[0061] The above technical solution has the following technical effects: by shaping the second set of pulse signals with the upper and lower edge information of the first control signal through the driver and then passing them through the AND gate, the second control signal can be obtained. The structure is simple and conducive to the miniaturization of the device.
[0062] In one embodiment of this application, both the first group of pulse signals and the second group of pulse signals are narrow pulse signals.
[0063] The above technical solution has the following technical effects: the duty cycle of the narrow pulse signal is very small and the pulse interval time is long, which makes the energy of the narrow pulse signal mainly concentrated in a short time during the same period of time, thereby reducing the average power consumption of the circuit.
[0064] According to another aspect of this application, a chip is also provided, the chip including the level shifter described above.
[0065] According to another aspect of this application, an electronic device is also provided, the electronic device comprising the above-described chip.
[0066] The level shifter, chip, and electronic device according to the embodiments of this application encode the rising and falling edge information of the control signal to be level shifted into a set of pulse signals, wherein each of at least two pulse signals contains the rising edge information and falling edge information of the control signal, and has strong anti-interference capability. Attached Figure Description
[0067] The above and other objects, features, and advantages of this application will become more apparent from the more detailed description of the embodiments of this application in conjunction with the accompanying drawings. The accompanying drawings are used to provide a further understanding of the embodiments of this application and form part of the specification. They are used together with the embodiments of this application to explain this application and do not constitute a limitation thereof. In the accompanying drawings, the same reference numerals generally represent the same components or steps.
[0068] Figure 1 A schematic block diagram of a level shifter according to an embodiment of this application is shown.
[0069] Figure 2 A schematic circuit diagram of a pulse coding circuit in a level shifter according to an embodiment of this application is shown.
[0070] Figure 3 A timing diagram of the pulse code circuit in a level shifter according to an embodiment of this application is shown.
[0071] Figure 4 A schematic circuit diagram of a level shifting circuit in a level shifter according to an embodiment of this application is shown.
[0072] Figure 5 A timing diagram of a level shifting circuit in a level shifter according to an embodiment of this application is shown.
[0073] Figure 6 A schematic circuit diagram of a pulse decoding circuit in a level shifter according to an embodiment of this application is shown.
[0074] Figure 7 A timing diagram of the pulse decoding circuit in a level shifter according to an embodiment of this application is shown. Detailed Implementation
[0075] To make the objectives, technical solutions, and advantages of this application more apparent, exemplary embodiments according to this application will be described in detail below with reference to the accompanying drawings. Obviously, the described embodiments are merely a part of the embodiments of this application, and not all of the embodiments of this application. It should be understood that this application is not limited to the exemplary embodiments described herein. Based on the embodiments of this application described herein, all other embodiments obtained by those skilled in the art without inventive effort should fall within the protection scope of this application.
[0076] As mentioned earlier, half-bridge driver chips, such as high-voltage half-bridge driver chips, play a crucial role in modern power electronics, widely used in motor drives, display drives, automotive electronics, and many other fields. These chips provide the necessary voltage and current to effectively control high-power semiconductor switches, such as MOSFETs and IGBTs. With the increasing importance of energy conservation and emission reduction, high-voltage half-bridge driver chips have become particularly critical for achieving efficient motor drive. They not only need to possess high reliability and low cost but also support intelligent functions to adapt to ever-increasing performance requirements.
[0077] The circuit composition of a high-voltage half-bridge driver chip mainly includes the following six key components: a pulse generator, which generates pulse signals on the rising and falling edges of the input signal to drive the switching action of power semiconductor devices; a level shifting circuit, which converts the low-voltage control signal from the microcontroller or other control circuits into a signal that matches the high-voltage side, realizing signal level shifting; a buffer, which amplifies the input signal to ensure the strength and stability of the signal during transmission, in order to drive high-power semiconductor switches such as power MOSFETs or IGBTs; a bootstrap diode, which charges the bootstrap capacitor when the low-side IGBT is turned on, generating the floating source required by the high-side circuit to support the switching action of the high-side IGBT; an undervoltage lockout protection device, which does not output a signal when the power supply voltage VDD is lower than the undervoltage protection threshold, in order to protect the gate driver itself and the connected semiconductor devices; and a high-side drive circuit, which serves as the last stage output of the signal and is mainly responsible for controlling the power transistor connected to the high-voltage side.
[0078] Among the aforementioned components, the high-voltage level-shift circuit is the core part of the high-voltage IGBT gate driver chip. Without it, the circuit cannot output control for the high-side power transistor. Its normal operation determines the success or failure of the driver circuit design. The system's stability, power consumption, and anti-interference performance are all closely related to it; therefore, it is one of the most critical circuits in the entire power circuit system. Typically, during level-shifting, constant attention must be paid to preventing external signals from interfering with the control signal. If significant interference is introduced into the circuit, it may cause the external high-voltage IGBT to conduct directly to ground, triggering a large current and causing irreversible and severe damage to the circuit. Therefore, enhancing the anti-interference capability of the high-voltage level-shift circuit is of paramount importance.
[0079] Based on this, this application provides a level shifter with strong anti-interference capability, which can be used not only to shift from a low voltage domain to a high voltage domain, but also to shift from a high voltage domain to a low voltage domain. For the sake of brevity, the following description primarily uses shifting from a low voltage domain to a high voltage domain as an example. Those skilled in the art can understand the similar principle of shifting from a high voltage domain to a low voltage domain in conjunction with the following description.
[0080] Figure 1 A schematic structural block diagram of a level shifter 1 according to an embodiment of this application is shown. Figure 1As shown, the level shifter 1 may include a pulse encoding circuit 11, a level shifting circuit 12, and a pulse decoding circuit 13. The pulse encoding circuit 11 encodes the rising and falling edge information of a first control signal in a first voltage domain to obtain a first set of pulse signals, where at least two pulse signals in the first set include both rising and falling edge information of the first control signal. The level shifting circuit 12 shifts the first set of pulse signals from the first voltage domain to a second voltage domain to obtain a second set of pulse signals. The pulse decoding circuit 13 decodes the second set of pulse signals to obtain a second control signal in the second voltage domain. One of the first and second voltage domains is a low voltage domain, and the other is a high voltage domain. For example, when the first voltage domain is a low voltage domain, the second voltage domain is a high voltage domain; conversely, when the first voltage domain is a high voltage domain, the second voltage domain is a low voltage domain.
[0081] In the embodiments of this application, the pulse encoding circuit 11 in the level shifter 1 can encode the rising and falling edge information of the control signal to be level shifted (referred to as the first control signal in this application) to obtain a set of pulse signals (referred to as the first set of pulse signals in this application). In the first set of pulse signals, each of at least two pulse signals contains both the rising and falling edge information of the first control signal. That is, the pulse encoding circuit 11 can encode the rising edge information of the first control signal into at least two pulse signals, and simultaneously, the pulse encoding circuit 11 can encode the falling edge information of the first control signal into at least two pulse signals. This means that when the level shifter 1 is interfered with, at least all pulse signals (at least two pulse signals) containing the rising edge information of the first control signal and at least all pulse signals (at least two pulse signals) containing the falling edge information of the first control signal need to be interfered with (at least four pulse signals need to be interfered with in total) to destroy the rising and falling edge information of the first control signal and produce an incorrect level shift result. Therefore, the level shifter 1 has a strong anti-interference capability.
[0082] In the embodiments of this application, the first set of pulse signals described above can be narrow pulse signals. Narrow pulse signals have a very small duty cycle, meaning the pulse duration is short (e.g., a few microseconds, a few nanoseconds, or even shorter), while the pulse interval is long. This means that within the same time frame, the energy of the narrow pulse signal is mainly concentrated and released in a shorter period, thereby reducing the average power consumption of the circuit. Because the small duty cycle of the narrow pulse signal means that the circuit is in a non-operating state most of the time, only operating when the pulse appears, this significantly reduces the average power consumption of the circuit. Furthermore, the energy of the narrow pulse signal is concentrated and released in a shorter period, allowing the circuit to enter a low-power mode during non-operating periods, further saving energy.
[0083] In embodiments of this application, the first set of pulse signals may include a first encoded signal, a second encoded signal, and a first reset signal. Correspondingly, the pulse encoding circuit 11 may include a first encoding circuit, a second encoding circuit, and a third encoding circuit. The first encoding circuit generates the first encoded signal based on the rising and falling edge information of the first control signal. The second encoding circuit generates the second encoded signal based on the rising and falling edge information of the first control signal; the second encoded signal is a delayed version of the first encoded signal. The third encoding circuit generates the first reset signal based on the rising edge information of the first control signal.
[0084] In this embodiment, the rising and falling edge information of the first control signal is encoded into a set of pulse signals comprising three pulse signals. Specifically, the first encoding circuit samples the rising and falling edge information of the first control signal to obtain a first encoded signal. The second encoding circuit samples the rising and falling edge information of the first control signal to obtain a second encoded signal. Therefore, both the first and second encoded signals contain the rising and falling edge information of the first control signal; the difference is that the second encoded signal has a time delay relative to the first encoded signal. The third encoding circuit samples the rising edge of the first control signal, and the resulting signal is used to reset the D flip-flop in the pulse decoding circuit 13 described later; therefore, it is called the reset signal (referred to as the first reset signal to distinguish it from the level-shifted reset signal). In this embodiment, the rising and falling edge information of the first control signal is encoded twice, which not only improves the anti-interference capability of the level shifter 1 but also reduces the computational load, allowing for a simple structure and miniaturization of the device without increasing the circuit area.
[0085] In embodiments of this application, the first encoding circuit described above may include: a first delay unit, a first inverter, a second delay unit, and a first XNOR gate. The first delay unit receives a first control signal at its input terminal; its output terminal is connected to the input terminal of the first inverter and the first input terminal of the first XNOR gate; the output terminal of the first inverter is connected to the input terminal of the second delay unit; the output terminal of the second delay unit is connected to the second input terminal of the first XNOR gate; and the output terminal of the first XNOR gate outputs a first encoded signal. In this embodiment, the first encoded signal is obtained by passing the delayed first control signal and the delayed-inverted and then further delayed first control signal through an XNOR gate.
[0086] In embodiments of this application, the second encoding circuit described above may include a third delay, a second inverter, a fourth delay, and a second XNOR gate. The input terminal of the third delay receives a first control signal, and its output terminal is connected to the second inverter. The output terminal of the second inverter is connected to the input terminal of the third inverter and the first input terminal of the second XNOR gate. The output terminal of the third inverter is connected to the input terminal of the fourth delay. The output terminal of the fourth delay is connected to the second input terminal of the second XNOR gate. The output terminal of the second XNOR gate outputs the second encoded signal. In this embodiment, the second encoded signal is obtained by passing the first control signal (delayed and inverted) and the first control signal (delayed, inverted, and then delayed again) through an XNOR gate.
[0087] In embodiments of this application, the aforementioned third encoding circuit may include: a fifth delay unit, a fourth inverter, a sixth delay unit, and a first AND gate. The fifth delay unit receives a first control signal at its input terminal, and its output terminal is connected to the first input terminals of the fourth inverter and the first AND gate. The output terminal of the fourth inverter is connected to the input terminal of the sixth delay unit. The output terminal of the sixth delay unit is connected to the second input terminal of the first AND gate. The first AND gate outputs a first reset signal. In this embodiment, the first reset signal is obtained by passing the delayed first control signal and the delayed, inverted, and then further delayed first control signal through an AND gate.
[0088] The following is combined with Figure 2 Describe an example of a pulse-code circuit. It should be understood that any implementation is acceptable. Figure 1 The pulse code circuit shown in the diagram has the function of various pulse code circuit structures and can be used.
[0089] like Figure 2As shown, the pulse coding circuit includes a first coding circuit, a second coding circuit, and a third coding circuit. The first coding circuit includes a delay unit, an inverter, another delay unit, and an XNOR gate connected in sequence. The first control signal PWM is converted into signal A by the delay unit. Signal A is converted into signal B by the inverter. Signal B is converted into signal C by the delay unit. Signal C and signal A are input to the XNOR gate to obtain the first encoded signal CODE1. The second coding circuit includes a delay unit, an inverter, another inverter, another delay unit, and an XNOR gate connected in sequence. The first control signal PWM is converted into signal A by the delay unit. Signal A is converted into signal B by the inverter. Signal B is converted into signal E by the inverter. Signal E is converted into signal F by the delay unit. Signal F and signal A are input to the XNOR gate to obtain the second encoded signal CODE2. The third coding circuit includes a delay unit, an inverter, another delay unit, and an AND gate connected in sequence. The first control signal PWM is converted into signal A by the delay unit. Signal A is converted into signal B by the inverter. Signal B is converted into signal C by the delay unit. Signal C and signal A are input into the AND gate to obtain the first reset signal RST.
[0090] Figure 2 The timing diagram of the signal shown is as follows Figure 3 As shown. By Figure 3 As shown in the timing diagram, the edge information of the first control signal PWM is encoded when both CODE1 and CODE2 pulse signals are at a high level. As long as the interference does not cause both CODE1 and CODE2 pulse signals to become high, the output control signal of level shifter 1 will not change. Therefore, the anti-interference capability of level shifter 1 is greatly enhanced.
[0091] Now continue with the reference. Figure 1 In the embodiments of this application, based on the first set of pulse signals described in the above examples, the second set of pulse signals may correspondingly include a second reset signal, a third encoded signal, and a fourth encoded signal. Correspondingly, the level shifting circuit 12 may include a first shifting circuit, a second shifting circuit, and a third shifting circuit, wherein the first shifting circuit is used to shift the first reset signal from a first voltage domain to a second voltage domain to obtain a second reset signal; the second shifting circuit is used to shift the first encoded signal from the first voltage domain to the second voltage domain to obtain a third encoded signal; and the third shifting circuit is used to shift the second encoded signal from the first voltage domain to the second voltage domain to obtain a fourth encoded signal.
[0092] In this embodiment, the level shifting circuit 12 shifts the three pulse signals from the first voltage domain to the second voltage domain through three branches. The signals do not interfere with each other, the structure is not complicated, and the circuit area is not large, which is conducive to the miniaturization of the device.
[0093] In embodiments of this application, the first shift circuit described above may include a first resistor, a first Zener diode, a first transistor, and a first driver. Specifically, the first terminal of the first resistor is connected to the voltage source of the second voltage domain and the output terminal of the first Zener diode; the second terminal of the first resistor is connected to the input terminal of the first Zener diode and the drain of the first transistor; the input terminal of the first Zener diode and the second terminal of the first resistor are connected to the input terminal of the first driver; the gate of the first transistor is connected to a first reset signal, and the source of the first transistor is grounded; the output terminal of the first driver outputs a second reset signal. In this embodiment, the first reset signal controls the conduction state of the first transistor, thereby affecting the breakdown state of the first Zener diode, and the first driver outputs the result after voltage domain conversion.
[0094] In embodiments of this application, the second shift circuit described above may include: a second resistor, a second Zener diode, a second transistor, and a second driver. The first terminal of the second resistor is connected to the voltage source of the second voltage domain and the output terminal of the second Zener diode; the second terminal of the second resistor is connected to the input terminal of the second Zener diode and the drain of the second transistor; the input terminal of the second Zener diode and the second terminal of the second resistor are connected to the input terminal of the second driver; the gate of the second transistor is connected to a first encoded signal, and the source of the second transistor is grounded; the output terminal of the second driver outputs a third encoded signal. In this embodiment, the first encoded signal controls the conduction state of the second transistor, thereby affecting the breakdown state of the second Zener diode, and the second driver outputs the voltage domain conversion result.
[0095] In embodiments of this application, the aforementioned third shift circuit may include: a third resistor, a third Zener diode, a third transistor, and a third driver. The first terminal of the third resistor is connected to the voltage source of the second voltage domain and the output terminal of the third Zener diode; the second terminal of the third resistor is connected to the input terminal of the third Zener diode and the drain of the third transistor; the input terminal of the third Zener diode and the second terminal of the third resistor are connected to the input terminal of the third driver; the gate of the third transistor is connected to a second encoded signal, and the source of the third transistor is grounded; the output terminal of the third driver outputs a fourth encoded signal. In this embodiment, the conduction state of the third transistor is controlled by the second encoded signal, thereby affecting the breakdown state of the third Zener diode, and the result after voltage domain conversion is output by the third driver.
[0096] The following is combined with Figure 4 Describe an example of a level shifting circuit. It should be understood that any implementation is acceptable. Figure 1 The level shift circuit shown in the diagram demonstrates its function; level shift circuits of various structures can be used.
[0097] like Figure 4As shown, the level shifting circuit includes a first shift circuit, a second shift circuit, and a third shift circuit. The first shift circuit may include a first resistor R1, a first Zener diode Z1, a first transistor HM1, and a first driver that takes the N1 node voltage as input. The control signal for HM1 is a first reset signal RST, which in this example is a low-voltage domain signal. When the input RST is high, the high-voltage NMOS transistor HM1 is turned on, and the N1 node voltage drops to the point where the Zener diode D1 breaks down. The voltage of the second reset signal RST_H, outputting from the high-voltage domain driver (which is connected to power supplies VDDH and VSSH, where VDDH is equivalent to HVDD and VSSH is equivalent to HVSS), is HVDD. Conversely, when the input RST is low, the high-voltage NMOS transistor HM1 is turned off, and the N1 node outputs a high voltage, HVDD. The voltage of the second reset signal RST_H, outputting from the high-voltage domain driver, is HVSS.
[0098] The second shift circuit may include a second resistor R2, a second Zener diode Z2, a second transistor HM2, and a second driver that takes the N2 node voltage as input. The control signal for HM2 is the first encoded signal CODE1, which in this example is a low-voltage domain signal. When the input CODE1 is high, the high-voltage NMOS transistor HM2 is turned on, and the N2 node voltage drops to the point where the Zener diode D2 breaks down. After passing through the high-voltage domain driver, the voltage of the third encoded signal CODE1_H in the high-voltage domain is HVDD. Conversely, when the input CODE1 is low, the high-voltage NMOS transistor HM2 is turned off, and the N2 node outputs a high voltage, HVDD. After passing through the high-voltage domain driver, the voltage of the third encoded signal CODE1_H in the high-voltage domain is HVSS.
[0099] The third shift circuit may include a third resistor R3, a third Zener diode Z3, a third transistor HM3, and a third driver that takes the N3 node voltage as input. The control signal for HM3 is the second encoded signal CODE2, which in this example is a low-voltage domain signal. When the input CODE2 is high, the high-voltage NMOS transistor HM3 is turned on, and the N3 node voltage drops to the point where the Zener diode D3 breaks down. After passing through the high-voltage domain driver, the output voltage of the fourth encoded signal CODE2_H in the high-voltage domain is HVDD. Conversely, when the input CODE2 is low, the high-voltage NMOS transistor HM3 is turned off, and the N3 node outputs a high voltage, HVDD. After passing through the high-voltage domain driver, the output voltage of the fourth encoded signal CODE2_H in the high-voltage domain is HVSS.
[0100] Figure 4 The timing diagram of the signal shown is as follows Figure 5 As shown. By Figure 5 As shown in the timing diagram, the narrow pulse signals CODE1, CODE2 and RST with the edge information of the first control signal PWM can be shifted from the low voltage domain to the high voltage domain by the level shifting circuit, so as to obtain the corresponding CODE1_H, CODE2_H and RST_H.
[0101] Now continue with the reference. Figure 1 In embodiments of this application, the pulse decoding circuit 13 may include a fourth driver, a fifth driver, a second AND gate, and a D flip-flop. The input of the fourth driver is connected to the third encoded signal, and the output of the fourth driver is connected to the first input of the second AND gate. The input of the fifth driver is connected to the fourth encoded signal, and the output of the fifth driver is connected to the second input of the second AND gate. The output of the second AND gate is connected to the clock signal input of the D flip-flop. The reset signal input of the D flip-flop receives a second reset signal, and the output of the D flip-flop outputs a second control signal.
[0102] In this embodiment, the pulse decoding circuit 13 obtains the second control signal by shaping the second set of pulse signals with the rising and falling edge information of the first control signal through a driver and then passing them through an AND gate. The structure is simple and conducive to device miniaturization.
[0103] The following is combined with Figure 6 Describe an example of a pulse decoding circuit. It should be understood that any implementation is acceptable. Figure 1 The pulse decoding circuit shown in the diagram has the function of various pulse decoding circuit structures and can be used.
[0104] like Figure 6 As shown, the pulse decoding circuit includes two drivers, an AND gate, and a D flip-flop. The inputs to the two drivers are the aforementioned third encoded signal CODE1_H and fourth encoded signal CODE2_H, respectively. Each of the third encoded signal CODE1_H and fourth encoded signal CODE2_H is shaped by a driver and then passed through an AND gate to obtain the PULSE node signal. The PULSE node signal is the edge information of the first control signal PWM. The PULSE node signal is input to the clock signal input port (CK port) of the D flip-flop with falling edge control. When the falling edge of the PULSE node is encountered, the output Q of the D flip-flop toggles once. The second reset signal RST_H is enabled when it is high (HVDD), that is, when RST_H is high, D is set to high. The data input D of the D flip-flop is connected to the inverting input of its output. Connected. When the first falling edge of the PULSE signal occurs, the D signal is transmitted to Q, meaning that VOUT_H output is high at this time. When D is low (HVSS), the D signal is transmitted to Q when the second falling edge of PULSE arrives, meaning VOUT_H is low at this time. D is at a high level. Then RST_H will send another high-level reset signal, setting D high, thus completing one cycle.
[0105] Figure 6 The timing diagram of the signal shown is as follows Figure 7 As shown. By Figure 7 As shown in the timing diagram, the pulse decoding circuit can decode the second control signal VOUT_H, which is in the high voltage domain and contains the PWM edge information of the first control signal, from the narrow pulse signal in the high voltage domain.
[0106] The level shifter 1 according to an embodiment of this application has been described in detail above. Based on the above description, the level shifter 1 according to an embodiment of this application can encode the rising and falling edge information of the control signal to be level shifted into a set of pulse signals, wherein each of at least two pulse signals contains the rising edge information and falling edge information of the control signal, and has strong anti-interference capability.
[0107] According to another aspect of this application, a chip is also provided, which includes the level shifter described above according to the embodiments of this application.
[0108] According to another aspect of this application, an electronic device is also provided, which includes the aforementioned chip.
[0109] Although exemplary embodiments have been described herein with reference to the accompanying drawings, it should be understood that the above exemplary embodiments are merely illustrative and are not intended to limit the scope of this application. Various changes and modifications can be made therein by those skilled in the art without departing from the scope and spirit of this application. All such changes and modifications are intended to be included within the scope of this application as claimed in the appended claims.
[0110] Those skilled in the art will recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.
[0111] In the several embodiments provided in this application, it should be understood that the disclosed devices and methods can be implemented in other ways. For example, the device embodiments described above are merely illustrative. For instance, the division of units is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another device, or some features may be ignored or not executed.
[0112] Numerous specific details are set forth in the specification provided herein. However, it will be understood that embodiments of this application may be practiced without these specific details. In some instances, well-known methods, structures, and techniques have not been shown in detail so as not to obscure the understanding of this specification.
[0113] Similarly, it should be understood that, for the purpose of simplification and aiding understanding of one or more aspects of this application, various features of this application may sometimes be grouped together in a single embodiment, figure, or description thereof in the description of exemplary embodiments of this application. However, the approach of this application should not be construed as reflecting an intention that the claimed application requires more features than are expressly recited in each claim. Rather, as reflected in the corresponding claims, its inventive point lies in solving the corresponding technical problem with fewer features than all features of a single disclosed embodiment. Therefore, the claims following the detailed description are hereby expressly incorporated into that detailed description, wherein each claim itself is a separate embodiment of this application.
[0114] Those skilled in the art will understand that, apart from the mutual exclusion of features, all features disclosed in this specification (including the accompanying claims, abstract, and drawings) and all processes or units of any method or apparatus so disclosed can be combined in any combination. Unless otherwise expressly stated, each feature disclosed in this specification (including the accompanying claims, abstract, and drawings) may be replaced by an alternative feature that serves the same, equivalent, or similar purpose.
[0115] Furthermore, those skilled in the art will understand that although some embodiments herein include certain features but not others included in other embodiments, combinations of features from different embodiments are intended to be within the scope of this application and form different embodiments. For example, in the claims, any one of the claimed embodiments can be used in any combination.
[0116] The various component embodiments of this application can be implemented in hardware, or as software modules running on one or more processors, or a combination thereof. Those skilled in the art will understand that microprocessors or digital signal processors (DSPs) can be used in practice to implement some or all of the functions of some modules in the article analysis device according to the embodiments of this application. This application can also be implemented as an apparatus program (e.g., a computer program and computer program product) for performing part or all of the methods described herein. Such an implementation of this application can be stored on a computer-readable medium, or can be in the form of one or more signals. Such signals can be downloaded from an Internet website, provided on a carrier signal, or provided in any other form.
[0117] It should be noted that the above embodiments are illustrative of this application and not restrictive, and that those skilled in the art can devise alternative embodiments without departing from the scope of the appended claims. In the claims, any reference signs placed between parentheses should not be construed as limiting the claims. The word "comprising" does not exclude the presence of elements or steps not listed in the claims. The word "a" or "an" preceding an element does not exclude the presence of a plurality of such elements. This application can be implemented by means of hardware comprising several different elements and by means of a suitably programmed computer. In the unit claims enumerating several means, several of these means may be embodied by the same item of hardware. The use of the words first, second, and third, etc., does not indicate any order. These words can be interpreted as names.
[0118] The above are merely specific embodiments or descriptions of specific embodiments of this application. The scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. The scope of protection of this application shall be determined by the scope of the claims.
Claims
1. A level shifter, characterized in that, The level shifter includes: A pulse coding circuit is used to encode the rising edge information and falling edge information of a first control signal in a first voltage domain to obtain a first set of pulse signals, wherein at least two pulse signals in the first set of pulse signals include the rising edge information and falling edge information of the first control signal. A level shifting circuit is used to shift the first group of pulse signals from the first voltage domain to the second voltage domain to obtain a second group of pulse signals, wherein one of the first voltage domain and the second voltage domain is a low voltage domain and the other is a high voltage domain; A pulse decoding circuit is used to decode the second set of pulse signals to obtain a second control signal in the second voltage domain.
2. The level shifter according to claim 1, characterized in that, The first group of pulse signals includes a first encoded signal, a second encoded signal, and a first reset signal. The pulse encoding circuit includes: The first encoding circuit is used to generate the first encoded signal based on the rising edge information and falling edge information of the first control signal; The second encoding circuit is used to generate the second encoded signal based on the rising edge information and falling edge information of the first control signal, wherein the second encoded signal is a delayed signal of the first encoded signal; The third encoding circuit is used to generate the first reset signal based on the rising edge information of the first control signal.
3. The level shifter according to claim 2, characterized in that, The first encoding circuit includes: A first delay unit, wherein the first control signal is input to the input terminal of the first delay unit, and the output terminal of the first delay unit is connected to the input terminal of the first inverter and the first input terminal of the first XNOR gate; The first inverter, the output of which is connected to the input of the second delay unit; The second delay unit, the output of which is connected to the second input of the first XOR gate; The first XOR gate outputs the first encoded signal.
4. The level shifter according to claim 2, characterized in that, The second encoding circuit includes: The third delay unit receives the first control signal at its input terminal and its output terminal is connected to the second inverter. The output of the second inverter is connected to the input of the third inverter and the first input of the second XNOR gate; The output of the third inverter is connected to the input of the fourth delay unit; The output of the fourth delay unit is connected to the second input of the second XOR gate; The second XOR gate outputs the second encoded signal.
5. The level shifter according to claim 2, characterized in that, The third encoding circuit includes: The fifth delay unit receives the first control signal at its input terminal and its output terminal is connected to the first input terminal of the fourth inverter and the first AND gate. The output of the fourth inverter is connected to the input of the sixth delay unit; The output of the sixth delay unit is connected to the second input of the first AND gate; The first AND gate outputs the first reset signal.
6. The level shifter according to claim 2, characterized in that, The second group of pulse signals includes a second reset signal, a third encoded signal, and a fourth encoded signal. The level shifting circuit includes: A first shift circuit is used to shift the first reset signal from the first voltage domain to the second voltage domain to obtain the second reset signal; The second shift circuit is used to shift the first encoded signal from the first voltage domain to the second voltage domain to obtain the third encoded signal; A third shift circuit is used to shift the second encoded signal from the first voltage domain to the second voltage domain to obtain the fourth encoded signal.
7. The level shifter according to claim 6, characterized in that, The first shift circuit includes: A first resistor, the first end of which is connected to the voltage source of the second voltage domain and the output terminal of the first Zener diode, and the second end of which is connected to the input terminal of the first Zener diode and the drain of the first transistor; The first Zener diode, the input terminal of the first Zener diode and the second terminal of the first resistor are connected to the input terminal of the first driver; The first transistor has its gate connected to the first reset signal and its source grounded. The first driver outputs the second reset signal from its output terminal.
8. The level shifter according to claim 6, characterized in that, The second shift circuit includes: The second resistor has its first end connected to the voltage source of the second voltage domain and the output terminal of the second Zener diode, and its second end connected to the input terminal of the second Zener diode and the drain of the second transistor. The second Zener diode, the input terminal of the second Zener diode and the second terminal of the second resistor are connected to the input terminal of the second driver; The second transistor has its gate connected to the first encoded signal and its source grounded. The second driver outputs the third encoded signal.
9. The level shifter according to claim 6, characterized in that, The third shift circuit includes: The third resistor has its first end connected to the voltage source of the second voltage domain and the output terminal of the third Zener diode, and its second end connected to the input terminal of the third Zener diode and the drain of the third transistor. The third Zener diode, the input terminal of the third Zener diode and the second terminal of the third resistor are connected to the input terminal of the third driver; The third transistor has its gate connected to the second encoded signal and its source grounded. The third driver outputs the fourth encoded signal at its output terminal.
10. The level shifter according to claim 6, characterized in that, The pulse decoding circuit includes: A fourth driver, the input of which is connected to the third encoded signal, and the output of which is connected to the first input of the second AND gate; The fifth driver has its input connected to the fourth encoded signal and its output connected to the second input of the second AND gate. The second AND gate, the output of which is connected to the clock signal input of the D flip-flop; The D flip-flop has the second reset signal input at its reset signal input terminal and the second control signal output at its output terminal.
11. The level shifter according to any one of claims 1-10, characterized in that, Both the first group of pulse signals and the second group of pulse signals are narrow pulse signals.
12. A chip, characterized in that, The chip includes a level shifter as described in any one of claims 1-11.
13. An electronic device, characterized in that, The electronic device includes the chip of claim 12.