SAR ADC circuit, noise suppression method and nanopore sequencing chip

Abstract

The invention discloses an SAR ADC circuit, a noise suppression method and a nanopore sequencing chip, and the SAR ADC circuit is a double-sampling circuit, and comprises a first switch module, a second switch module, a third switch module, a fourth switch module, a sampling module, an amplifier, a holding module, a comparator and a logic circuit. According to the invention, the holding module is introduced into the circuit for temporarily storing charges, meanwhile, the logic circuit is matched to carry out four-stage time sequence control on the four switch modules, and a time sequence multiplexing and capacitor charge redistribution technology is utilized, so that noise elimination is completed in a circuit sampling stage. The method does not need an additional calibration period, and the efficiency is improved; the sampling noise can be effectively inhibited only by adding the micro capacitor and the switch, the area of the sampling capacitor is greatly reduced, the array density of the nanopore sequencing chip is improved, and the cost of a chip product is reduced.

Description

Technical Field

[0001] This invention belongs to the field of analog integrated circuit technology, specifically relating to a SAR ADC circuit, a noise suppression method, and a nanopore sequencing chip. Background Technology

[0002] Nanopore sequencing chips digitize sampled signals using high-resolution ADCs (Analog-to-Digital Converters). While increasing the size of the nanopore array can rapidly reduce chip costs, it also leads to an increase in the overall number, power consumption, and area of ​​on-chip ADCs, thus limiting further increases in the size of single nanopore sequencing chip arrays.

[0003] In nanopore sequencing systems, depending on the sampling rate and resolution requirements, suitable ADC types include SD ADC (Sigma-Delta Analog to Digital Converter) and SAR ADC (Successive-Approximation Analog to Digital Converter). Due to its relatively low power consumption and fast sampling speed, SAR ADC has become the mainstream on-chip ADC solution for advanced nanopore sequencing chips.

[0004] However, in the design of high-resolution SAR ADCs, a large sampling capacitor is required to ensure that the sampling noise meets the quantization accuracy. This becomes the main factor occupying the area of ​​the SAR ADC chip, restricting the expansion of nanopore arrays. Therefore, how to effectively suppress sampling noise, reduce the sampling capacitor area, increase the array density of nanopore sequencing chips, and reduce the cost of chip products has become an urgent technical problem to be solved. Summary of the Invention

[0005] To address the aforementioned problems in the prior art, this invention provides a SAR ADC circuit, a noise suppression method, and a nanopore sequencing chip. The technical problem to be solved by this invention is achieved through the following technical solution: In a first aspect, the present invention proposes a SAR ADC circuit, which is a dual-sampling circuit, comprising a first switching module, a second switching module, a third switching module, a fourth switching module, a sampling module, an amplifier, a hold module, a comparator, and logic circuitry; wherein, The sampling module is used to capture the input signal. Its first terminal is connected to the differential input terminals VIP and VIN through the third switch module, and its second terminal is connected to the common-mode level VCM through the first switch module. The first terminal of the sampling module is also connected to the reference level VREFP, VREFN or the common-mode level VCM through the fourth switch module. The amplifier is used to amplify the signal, and its input is connected to the second terminal of the sampling module; The holding module is used to temporarily store charge. Its first end is connected to the output of the amplifier, and its second end is connected to the common-mode level VCM through the second switching module. The comparator is used to compare signals. Its input is connected to the second terminal of the hold module, and its output is connected to the input of the logic circuit. The logic circuit connects the first switch module, the second switch module, the third switch module, and the fourth switch module to control the switching logic of the circuit and output the quantized digital signal.

[0006] In one embodiment of the present invention, the third switching module includes two switch arrays S3, the fourth switching module includes two switch arrays S4, the first switching module includes two switches S1, and the sampling module includes two sampling capacitor arrays Cs; wherein... The number of switches in switch array S3 and switch array S4 is the same, and the number of capacitors in sampling capacitor array Cs is the same; the lower plate of sampling capacitor array Cs serves as the first end of the sampling module and is connected to switch array S3 and switch array S4 in a one-to-one correspondence.

[0007] The upper plate of the sampling capacitor array Cs is connected to switch S1 as the second terminal of the sampling module.

[0008] In one embodiment of the present invention, the second switching module includes two switches S2, and the holding module includes two holding capacitors Ch; wherein, The lower plate of capacitor Ch is used as the first terminal of the holding module and connected to the output terminal of the amplifier. The upper plate of capacitor Ch is connected to switch S2 as the second terminal of the holding module.

[0009] In one embodiment of the present invention, the comparator is a Latch comparator.

[0010] Secondly, this invention proposes a noise suppression method for a SAR ADC circuit, which is based on the SAR ADC circuit proposed in the first aspect of this invention. The method includes timing control of switches S1 and S2, and switch arrays S3 and S4, using logic circuits to complete noise cancellation during the circuit sampling stage. The timing control includes the following four stages: The first stage is the reset stage, where switches S1 and S2, as well as switch array S3, are turned on, switch array S4 is turned off, and the upper-level board level of sampling capacitor array Cs and holding capacitor Ch is reset to VCM. The second stage is the charge conservation stage. Switch S1 and switch array S4 are disconnected, switch S2 and switch array S3 are turned on, the charge of sampling capacitor array Cs is conserved, and the input signal is sampled and the charge difference is saved. The third stage is the noise cancellation stage. Switches S1 and S2 and switch array S4 are disconnected, switch array S3 is turned on, the charge of capacitor Ch is kept constant, and sampling noise is cancelled by charge redistribution. The fourth stage is the quantization stage. Switches S1 and S2, as well as switch array S3, are disconnected, while switch array S4 is turned on. The SARADC quantizes and compares the acquired voltage and outputs a digital signal.

[0011] Thirdly, the present invention proposes a nanopore sequencing chip, which integrates the SAR ADC circuit proposed in the first aspect of the present invention and uses the method provided in the second aspect of the present invention for noise suppression.

[0012] The beneficial effects of this invention are: 1. This invention proposes a SAR ADC circuit and its noise suppression method. The SAR ADC circuit is a dual-sampling circuit, including a first switching module, a second switching module, a third switching module, a fourth switching module, a sampling module, an amplifier, a hold module, a comparator, and logic circuitry. By introducing a hold module to temporarily store charge, and coordinating with the logic circuitry to perform four-stage timing control on the four switching modules, noise cancellation is achieved during the circuit sampling stage through timing multiplexing and capacitor charge redistribution techniques. This method eliminates the need for additional calibration cycles, improving efficiency; and by only adding miniature capacitors and switches, sampling noise can be effectively suppressed, significantly reducing the sampling capacitor area, increasing the array density of nanopore sequencing chips, and reducing the cost of chip products.

[0013] 2. The SAR ADC circuit and its noise suppression method proposed in this invention are implemented using a fully analog algorithm, without the need for digital algorithm intervention, which reduces the system complexity.

[0014] The present invention will be further described in detail below with reference to the accompanying drawings and embodiments. Attached Figure Description

[0015] Figure 1 A block diagram of a SAR ADC circuit provided in an embodiment of the present invention; Figure 2 A detailed circuit diagram of a SAR ADC circuit provided for an embodiment of the present invention; Figure 3 This is a timing diagram of the dual sampling operation provided in an embodiment of the present invention; Figure 4 The schematic diagram corresponding to the first stage of timing control provided in the embodiment of the present invention; Figure 5 The schematic diagram corresponding to the second stage of timing control provided in the embodiment of the present invention; Figure 6 The schematic diagram corresponding to the third stage of timing control provided in the embodiment of the present invention; Figure 7 The schematic diagram corresponding to the fourth stage of timing control provided in the embodiment of the present invention. Detailed Implementation

[0016] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0017] A first aspect of the present invention provides a SAR ADC circuit, which is a dual-sampling circuit. See also... Figure 1 , Figure 1 This invention provides a structural block diagram of a SAR ADC circuit, which includes a first switching module, a second switching module, a third switching module, a fourth switching module, a sampling module, an amplifier, a hold module, a comparator, and logic circuitry. The sampling module is used to capture the input signal. Its first terminal is connected to the differential input terminals VIP and VIN through the third switch module, and its second terminal is connected to the common-mode level VCM through the first switch module. The first terminal of the sampling module is also connected to the reference level VREFP, VREFN or the common-mode level VCM through the fourth switch module. The amplifier is used to amplify the signal, and its input is connected to the second terminal of the sampling module; The holding module is used to temporarily store charge. Its first end is connected to the output of the amplifier, and its second end is connected to the common-mode level VCM through the second switching module. The comparator is used to compare signals. Its input is connected to the second terminal of the hold module, and its output is connected to the input of the logic circuit. The logic circuit connects the first switch module, the second switch module, the third switch module, and the fourth switch module to control the switching logic of the circuit and output the quantized digital signal.

[0018] Specifically, please see Figure 2 , Figure 2A detailed circuit diagram of a SAR ADC circuit provided for an embodiment of the present invention.

[0019] In this embodiment, the third switching module includes two switch arrays S3, the fourth switching module includes two switch arrays S4, the first switching module includes two switches S1, and the sampling module includes two sampling capacitor arrays Cs; wherein, The number of switches in switch array S3 and switch array S4 is the same, and the number of capacitors in sampling capacitor array Cs is the same; the lower plate of sampling capacitor array Cs serves as the first end of the sampling module and is connected to switch array S3 and switch array S4 in a one-to-one correspondence.

[0020] The upper plate of the sampling capacitor array Cs is connected to switch S1 as the second terminal of the sampling module.

[0021] For further details, please continue to see Figure 2 The second switching module includes two switches S2, and the holding module includes two holding capacitors Ch, also known as offset storage capacitors; The lower plate of capacitor Ch is used as the first terminal of the holding module and connected to the output terminal of the amplifier. The upper plate of capacitor Ch is connected to switch S2 as the second terminal of the holding module.

[0022] Furthermore, the comparator in this embodiment is a Latch comparator.

[0023] It should be noted that the capacitance values ​​in the sampling capacitor array Cs and the holding capacitor Ch can be set according to the actual situation; the amplifier, comparator and logic circuit can be implemented according to conventional circuits, and will not be described in detail in this embodiment.

[0024] The SAR ADC circuit provided by this invention adds miniature capacitors and switches, resulting in low area overhead. By utilizing the inherent sampling-conversion timing of the SAR ADC and combining it with appropriate timing control logic, noise cancellation can be completed during the sampling stage without the need for additional calibration cycles.

[0025] Based on the SAR ADC circuit provided in the first aspect of the present invention, the second aspect of the present invention also provides a noise suppression method for the SAR ADC circuit. The method utilizes the logic circuit in the SAR ADC circuit to perform timing control on switches S1 and S2, as well as switch arrays S3 and S4, so as to complete noise cancellation during the circuit sampling stage.

[0026] For details, please see Figure 3 , Figure 3 The timing diagram for dual sampling provided in this embodiment of the invention mainly includes the following four stages for timing control: The first stage is the reset stage, that is... Figure 3 In stage ①, switches S1 and S2, as well as switch array S3, are turned on, switch array S4 is turned off, and the upper board level of sampling capacitor array Cs and holding capacitor Ch is reset to VCM. The second stage is the charge conservation stage, that is... Figure 3 In stage ②, switch S1 and switch array S4 are disconnected, switch S2 and switch array S3 are turned on, the charge of sampling capacitor array Cs is conserved, the input signal is sampled and the charge difference is saved. The third stage is the noise cancellation stage, that is... Figure 3 In stage ③, switches S1 and S2 and switch array S4 are disconnected, switch array S3 is turned on, the charge of capacitor Ch is kept conserved, and sampling noise is eliminated through charge redistribution. The fourth stage is the quantification stage, that is... Figure 3 In stage ④, switches S1 and S2, as well as switch array S3, are disconnected, switch array S4 is turned on, and the SAR ADC quantizes and compares the acquired voltages and outputs digital signals.

[0027] The following is combined with Figure 4-7 This paper provides a detailed introduction to the working principle of the four stages of timing control circuit.

[0028] Please see Figure 4 , Figure 4 This is a schematic diagram of the first stage of timing control provided in an embodiment of the present invention. In this stage, the sampling noise is represented by Vos, switches S1 and S2, and switch array S3 are turned on, switch array S4 is turned off, and the upper-level board level of sampling capacitor array Cs and holding capacitor Ch is reset to VCM. At this time, the output of amplifier Op is A. Vos, where A is the amplifier's gain. At this time, the input port voltage of the Latch comparator is INP2 = INN2 = VCM (AC ground).

[0029] This stage ensures that all capacitors are initially in the same state, laying the foundation for noise cancellation.

[0030] Please see Figure 5 , Figure 5This is a schematic diagram of the second stage of timing control provided in an embodiment of the present invention. In this stage, switch S1 and switch array S4 are open, while switch S2 and switch array S3 are closed. INP1 and INN1 become high-resistance points, and charge is conserved at these two points. The charge stored in the sampling capacitor Cs corresponding to node INP1 is Cs*(VCM-VIP), where VIP is the voltage value of S1 at the instant before it is turned off. The charge stored in the sampling capacitor Cs corresponding to node INN1 is Cs*(VCM-VIN), where VIN is the voltage value of S1 at the instant before it is turned off. The charge difference between nodes INP1 and INN1 is: Q_INP1-Q_INN1=-(VIP-VIN) Cs; In the formula, VIP-VIN is a constant, which can be represented by the constant k.

[0031] This stage captures the differences in the input signal, providing a benchmark for subsequent noise cancellation.

[0032] Please see Figure 6 , Figure 6 This is a schematic diagram of the third stage of timing control provided in an embodiment of the present invention. In this stage, switches S1 and S2 and switch array S4 are open, and switch array S3 is closed. INP2 and INN2 become high-resistance points, and the charge at these two points is conserved. The charge stored in the holding capacitor Ch corresponding to node INP2 is Ch*(VCM-OUTP), where OUTP is the voltage value of S2 at the instant before it is turned off. The charge stored in the holding capacitor Ch corresponding to node INN2 is Ch*(VCM-OUTN), where OUTN is the voltage value of S2 at the instant before it is turned off. The charge difference between the two nodes is: Q_INP2-Q_INN2 =-(OUTP-OUTN)*Ch=-A*(Vos+INP1-INN1)*Ch; Since the charges at points INP1 and INN1 are conserved, INP1 - INN1 = VIP - VIN + k. At the instant before S3 is turned off, the charges at points INP2 and INN2 are still conserved, and the charge difference between the two points is updated as follows: Q_INP2'-Q_INN2'={(INP2'-INN2')-[A*VOS+A*(INP1'-INN1')]}*Ch.

[0033] Furthermore, since Q_INP2 - Q_INN2 = Q_INP2' - Q_INN2', we can obtain: INP2' - INP2' = A [(INP1'-INN1')-(INP1-INN1)].

[0034] This stage achieves real-time noise cancellation through capacitor charge redistribution.

[0035] It should be noted that the results of INP2'-INN2' show that the influence of sampling noise Vos has been eliminated. In order to avoid saturation of the amplifier OP output, the value of (INP1'-INN1')-(INP1-INN1) cannot be too large. Therefore, the time interval between the falling edge of switch S2 and the falling edge of S3 should be small, generally set to less than 5ns.

[0036] Please see Figure 7 , Figure 7 This is a schematic diagram of the fourth stage of timing control provided in an embodiment of the present invention. In this stage, switches S1 and S2, as well as switch array S3, are disconnected, while switch array S4 is turned on. The ADC initiates the quantization comparison process, and the Latch comparator and SAR_LOGIC perform digitization conversion on the processed signal and output a digital signal. Since noise has been eliminated in the third stage, the quantization accuracy is significantly improved.

[0037] This invention is achieved through Figure 2 The SAR ADC circuit structure shown is as follows: Figure 3 The dual-sampling timing shown utilizes the inherent sampling-conversion timing of the SARADC to complete noise cancellation during the sampling phase, eliminating the need for additional calibration cycles and improving efficiency and accuracy of the SAR ADC.

[0038] A third aspect of the present invention also provides a nanopore sequencing chip, which integrates the SAR ADC circuit provided in the first aspect of the present invention and uses the method provided in the second aspect of the present invention for noise suppression.

[0039] This invention proposes a SAR ADC circuit and its noise suppression method. The SAR ADC circuit is a dual-sampling circuit, including a first switching module, a second switching module, a third switching module, a fourth switching module, a sampling module, an amplifier, a hold module, a comparator, and logic circuitry. By introducing a hold module to temporarily store charge, and coordinating with the logic circuitry to perform four-stage timing control on the four switching modules, noise cancellation is achieved during the circuit sampling stage using timing multiplexing and capacitor charge redistribution techniques. This method eliminates the need for additional calibration cycles, improving efficiency; and by only adding miniature capacitors and switches, sampling noise can be effectively suppressed, significantly reducing the sampling capacitor area, increasing the array density of nanopore sequencing chips, and reducing chip product costs. Furthermore, this method employs a fully analog algorithm, eliminating the need for digital algorithms and reducing system complexity.

[0040] In the description of this invention, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this invention, "a plurality of" means two or more, unless otherwise explicitly specified.

[0041] The above description, in conjunction with specific preferred embodiments, provides a further detailed explanation of the present invention. It should not be construed that the specific implementation of the present invention is limited to these descriptions. For those skilled in the art, various simple deductions or substitutions can be made without departing from the concept of the present invention, and all such modifications and substitutions should be considered within the scope of protection of the present invention.

Claims

1. A SAR ADC circuit, characterized in that, The SAR ADC circuit is a dual-sampling circuit, including a first switching module, a second switching module, a third switching module, a fourth switching module, a sampling module, an amplifier, a hold module, a comparator, and logic circuitry; wherein, The sampling module is used to capture the input signal. Its first end is connected to the differential input terminals VIP and VIN through the third switch module, and its second end is connected to the common-mode level VCM through the first switch module. The first end of the sampling module is also connected to the reference level VREFP, VREFN or the common-mode level VCM through the fourth switch module. The amplifier is used to amplify the signal, and its input terminal is connected to the second terminal of the sampling module; The holding module is used to temporarily store charge. Its first end is connected to the output of the amplifier, and its second end is connected to the common-mode level VCM through the second switching module. The comparator is used to compare signals. Its input is connected to the second terminal of the hold module, and its output is connected to the input of the logic circuit. The logic circuit is connected to the first switch module, the second switch module, the third switch module, and the fourth switch module, and is used to control the switching logic of the circuit and output the quantized digital signal.

2. The SAR ADC circuit according to claim 1, characterized in that, The third switching module includes two switch arrays S3, the fourth switching module includes two switch arrays S4, the first switching module includes two switches S1, and the sampling module includes two sampling capacitor arrays Cs; wherein... The number of switches in the switch array S3 and the switch array S4 is the same, and the number of capacitors in the sampling capacitor array Cs is the same; the lower plate of the sampling capacitor array Cs serves as the first end of the sampling module and is connected to the switch array S3 and the switch array S4 in a one-to-one correspondence. The upper plate of the sampling capacitor array Cs is connected to the switch S1 as the second end of the sampling module.

3. The SAR ADC circuit according to claim 1, characterized in that, The second switching module includes two switches S2, and the holding module includes two holding capacitors Ch; wherein, The lower plate of the holding capacitor Ch is connected to the output terminal of the amplifier as the first end of the holding module; The upper plate of the holding capacitor Ch is connected to the switch S2 as the second end of the holding module.

4. The SAR ADC circuit according to claim 1, characterized in that, The comparator is a latch comparator.

5. A noise suppression method for a SAR ADC circuit, characterized in that, The method is implemented based on the SAR ADC circuit according to any one of claims 1-4; the method includes using the logic circuit to perform timing control on switches S1 and S2, and switch arrays S3 and S4, to complete noise cancellation during the circuit sampling stage; the timing control includes the following four stages: The first stage is the reset stage, where switches S1 and S2, as well as switch array S3, are turned on, switch array S4 is turned off, and the upper-level board level of sampling capacitor array Cs and holding capacitor Ch is reset to VCM. The second stage is the charge conservation stage. Switch S1 and switch array S4 are disconnected, switch S2 and switch array S3 are turned on, the charge of sampling capacitor array Cs is conserved, and the input signal is sampled and the charge difference is saved. The third stage is the noise cancellation stage. Switches S1 and S2 and switch array S4 are disconnected, switch array S3 is turned on, the charge of capacitor Ch is kept constant, and sampling noise is cancelled by charge redistribution. The fourth stage is the quantization stage. Switches S1 and S2, as well as switch array S3, are disconnected, while switch array S4 is turned on. The SAR ADC quantizes and compares the acquired voltage and outputs a digital signal.

6. The noise suppression method for a SAR ADC circuit according to claim 5, characterized in that, During the timing control process, the time interval between the falling edge of the switch S2 and the falling edge of the switch array S3 is less than 5ns.

7. A nanopore sequencing chip, characterized in that, The nanopore sequencing chip integrates the SAR ADC circuit according to any one of claims 1-4, and uses the method described in claim 5 for noise suppression.

Images