Gallium nitride junction field effect transistor device with high-K dielectric buried layer

Abstract

The invention belongs to the technical field of semiconductors, and particularly relates to a gallium nitride junction field effect transistor device with a high-K dielectric buried layer. According to the gallium nitride junction field effect transistor device with the high-K dielectric buried layer, reverse electric leakage can be reduced, most of electric displacement lines generated by a depletion drift region under reverse bias pass through the buffer layer filled with the high-K material, so that a longitudinal electric field is dispersed, and the breakdown voltage of the device is improved; the high-K dielectric buried layer can generate a polarization charge shielding effect, the grid-control threshold voltage (Vth) is increased by more than 0.5 V, and the grid capacitance is reduced. Compared with a traditional MOSFET, the high doping concentration can be adopted in the drift region under the same breakdown voltage, the on-resistance is reduced, the reliability problem of a GaN device in practical application is solved, and the application range of the GaN device in the field of power switches is widened.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor technology, specifically relating to a gallium nitride junction field-effect transistor device with a high-k dielectric buried layer. Background Technology

[0002] Gallium nitride (GaN) has become a key material for power device development due to its wide bandgap, high critical electric field, strong radiation resistance, and high saturation velocity suitable for high-power devices. GaN-based power devices are mainly divided into two basic structures: planar (lateral) structure devices and vertical structure devices. Currently, lateral GaN HEMT devices are still the main type. However, the lateral structure suffers from problems such as gate electric field concentration effect, buffer layer leakage current, gate leakage current, and current collapse, which severely restrict the application of the high critical breakdown electric field strength characteristics of GaN devices. This means that lateral GaN devices cannot fully utilize the high breakdown characteristics of GaN material.

[0003] Vertical GaN-based devices are more suitable for power electronics applications compared to lateral GaN-based devices. This is because, under high voltage, both the gate and source at the device surface are at low voltages, thus eliminating the high electric field at the device surface and suppressing gate leakage current. Furthermore, the PN junction depletion region between the source and drain of some vertical devices effectively blocks leakage current from the buffer layer, resulting in higher breakdown voltage performance. Moreover, vertical devices can typically utilize the PN junction formed within the buffer layer, leveraging the breakdown voltage of the PN junction to further enhance the breakdown voltage characteristics of the vertical device.

[0004] In recent years, homoepitaxial technology has also developed rapidly, making vertical devices easier to fabricate and promoting them as a new research direction. Therefore, how to utilize the properties of gallium nitride and high-k materials and the characteristics of vertical device structures to achieve low on-resistance and high breakdown voltage is the technical problem to be solved in this application. Summary of the Invention

[0005] The purpose of this invention is to provide a gallium nitride junction field-effect transistor device with a high-K dielectric buried layer, which can improve the threshold voltage and reduce the gate leakage current, as well as improve the device breakdown voltage and reduce the on-resistance.

[0006] This application provides a gallium nitride junction field-effect transistor device with a high-k dielectric buried layer, comprising: The N⁺-GaN substrate layer, N⁺-GaN buffer layer, N⁻-GaN drift layer, and N⁺-GaN contact layer are arranged sequentially from bottom to top; wherein... P-type deposits are disposed on both sides of the N⁻-GaN drift layer. + -GaN gate layer; The P + A high-K dielectric buried layer is disposed between the GaN gate layer and the N-GaN buffer layer.

[0007] In one embodiment of this application, the material of the high-K dielectric buried layer is one of hafnium-based oxide, aluminum-based oxide, and zirconium-based oxide.

[0008] In one embodiment of this application, the material of the high-K dielectric buried layer is HfO2.

[0009] In one embodiment of this application, the doping concentration of the N⁺-GaN substrate layer is 5 × 10⁻⁶. 19 cm -3 .

[0010] In one embodiment of this application, the doping concentration of the N-GaN buffer layer is 1×10⁻⁶. 15 ~5×10 18 cm -3 .

[0011] In one embodiment of this application, the doping concentration of the N⁻-GaN drift layer is 5 × 10⁻⁶. 16 cm -3 .

[0012] In one embodiment of this application, the P + The GaN gate layer is doped with Mg at a concentration of 1 × 10⁻⁶. 19 cm -3 .

[0013] In one embodiment of this application, the doping concentration of the N⁺-GaN contact layer is 1×10⁻⁶. 18 ~5×10 19 cm -3 .

[0014] In one embodiment of this application, the gallium nitride junction field-effect transistor device further includes: The gate electrode is located at P + -Outer surface of the GaN gate layer; The drain electrode is disposed on the lower surface of the N⁺-GaN substrate. The source electrode is disposed on the upper surface of the N⁺-GaN contact layer.

[0015] In one embodiment of this application, the gate electrode is made of a Ni / Au alloy and is a Schottky contact; the drain electrode is made of a Ni / Au alloy; and the source electrode is made of a Ti / Al / Ni / Au alloy.

[0016] The beneficial effects of the present invention are: The gallium nitride junction field-effect transistor (GaN) device with a high-k dielectric buried layer of the present invention can reduce reverse leakage current. Since most of the electric displacement lines generated by the depletion drift region under reverse bias are dispersed by the buffer layer filled with high-k material, the longitudinal electric field is improved, increasing the device breakdown voltage. The high-k dielectric buried layer can generate a polarization charge shielding effect, increasing the gate threshold voltage (Vth) by more than 0.5V and reducing the gate capacitance. Compared with traditional MOSFETs, a higher doping concentration can be used in the drift region at the same breakdown voltage, reducing on-resistance. This helps solve the reliability problems of GaN devices in practical applications and broadens their application in power switching.

[0017] Other features and advantages of the invention will be set forth in the following description, and will be apparent in part from the description, or may be learned by practicing the invention. The objects and other advantages of the invention are realized and obtained through the structures particularly pointed out in the description and the drawings.

[0018] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, preferred embodiments are given below and described in detail with reference to the accompanying drawings. Attached Figure Description

[0019] To more clearly illustrate the specific embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the specific embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present invention. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0020] Figure 1 This is a schematic diagram of a gallium nitride junction field-effect transistor device with a high-k dielectric buried layer according to a preferred embodiment of the present invention.

[0021] In the figure: 1. Drain electrode; 2. N⁺-GaN substrate; 3. N-GaN buffer layer; 4. High-k dielectric buried layer; 5. Gate electrode; P + 6. N⁻-GaN gate layer; 7. N⁺-GaN drift layer; 8. N⁺-GaN contact layer; 9. Source electrode. Detailed Implementation

[0022] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0023] In recent years, homoepitaxial technology has also developed rapidly, making vertical devices easier to fabricate and promoting them as a new research direction. Therefore, how to utilize the properties of gallium nitride and high-k materials and the characteristics of vertical device structures to achieve low on-resistance and high breakdown voltage is the technical problem to be solved in this application.

[0024] The inventors discovered that by inducing an equivalent negative charge under reverse bias using a high-k dielectric (κ>20), current flows vertically from the bottom to the top surface in vertical devices (electrons conduct current from top to bottom), or parallel to the direction of the GaN epitaxial layer. Therefore, current conduction occurs through surface channels and then through the bulk drain drift region formed by homoepitaxial growth on the GaN substrate. Unlike lateral devices, vertical devices lack a 2DEG drain drift region near the surface and a defect-rich buffer layer like that found in GaNHEMT. Therefore, dynamic RON degradation due to impurity charge trapping or bulk trapping caused by lattice mismatch is less. One of the biggest advantages of vertical devices over lateral devices is their breakdown voltage. The high-k buried layer generates a polarization charge shielding effect, increasing the gate threshold voltage (Vth) by more than 0.5V and suppressing gate leakage current >10V. 3 This reduces the interface state density (Dit) to 1×10⁻⁶. 11 cm⁻ 2 eV⁻ 1 The following (traditional structure > 5×10) 12 ）。同时，得益于栅电荷减少，高K介质减小反向传输电容Crss 40%，使开关品质因子（Rds·Qgd）优化35%。垂直器件的击穿电压可以通过增加 N 型漂移层的厚度来提高，该 漂移层通常是低掺杂或非故意掺杂的 GaN 外延层（也称为 GaN N 型漂移层）。因此，这使得击穿电压与器件的横向尺寸无关。反向偏压下，高K介质极化产生等效负电荷密度， 平衡n⁻-GaN漂移区正电荷，使横向电场均匀化（仿真峰值电场降至1.8 MV / cm），提高器件耐压。 This application provides a gallium nitride junction field-effect transistor device with a high-k dielectric buried layer, which will be described in detail below. It should be noted that the order of description of the following embodiments is not intended to limit the preferred order of the embodiments of this application. Furthermore, the descriptions of each embodiment have their own emphasis; parts not described in detail in a certain embodiment can be referred to in the relevant descriptions of other embodiments.

[0025] See Figure 1 In one embodiment, a gallium nitride junction field-effect transistor device with a high-k dielectric buried layer includes: an N⁺-GaN substrate layer 2, an N⁻-GaN buffer layer 3, an N⁻-GaN drift layer 7, and an N⁺-GaN contact layer 8, arranged sequentially from bottom to top; wherein P⁻-GaN drift layer 7 has P⁻-GaN contact layers on both sides. + -GaN gate layer 6; the P + A high-K dielectric buried layer 4 is disposed between the GaN gate layer 6 and the N-GaN buffer layer 3.

[0026] In this embodiment, P +-GaN gate layer 6 and high-k dielectric buried layer 4 are located near the left and right surfaces of N⁻-GaN drift layer 7, and high-k dielectric buried layer 4 is located near P⁻-GaN drift layer 7. + - Below GaN gate layer 6 and above N-GaN buffer layer 3; P + An N⁻-GaN drift layer 7 may be spaced between the upper end of the GaN gate layer 6 and the N⁺-GaN contact layer 8.

[0027] Furthermore, the material of the high-k dielectric buried layer is one of hafnium-based oxides, aluminum-based oxides, and zirconium-based oxides. Hafnium-based oxides can be, but are not limited to, HfO2, HfSiO, HfSiON, etc., and are widely used due to their high k value and compatibility with silicon. Aluminum-based oxides can be, but are not limited to, Al2O3, and have high dielectric constant and thermal stability. Zirconium-based oxides can be, but are not limited to, ZrO2, and are often used to replace SiO2 as a gate dielectric material. Preferably, the material of the high-k dielectric buried layer can be HfO2.

[0028] Furthermore, the doping concentration of the N⁺-GaN substrate layer 2 can be 5 × 10⁻⁶. 19 cm -3 The doping concentration of the N-GaN buffer layer 3 can be 1×10⁻⁶. 15 ~5×10 18 cm -3 The doping concentration of the N⁻-GaN drift layer 7 can be 5 × 10⁻⁶. 16 cm -3 .

[0029] Furthermore, the P + - The doping element of GaN gate layer 6 includes Mg, with a doping concentration of 1×10⁻⁶. 19 cm -3 .

[0030] Furthermore, the doping concentration of the N⁺-GaN contact layer 8 can be 1×10⁻⁶. 18 ~5×10 19 cm -3 .

[0031] Furthermore, the gallium nitride junction field-effect transistor device also includes: a gate electrode 5, disposed on P + - The outer surface of the GaN gate layer 6; the drain electrode 1 is disposed on the lower surface of the N⁺-GaN substrate layer 2; the source electrode 9 is disposed on the upper surface of the N⁺-GaN contact layer 8.

[0032] Optionally, the gate electrode 5 is made of Ni / Au alloy and is a Schottky contact; the drain electrode 1 is made of Ni / Au alloy; and the source electrode 9 is made of Ti / Al / Ni / Au alloy.

[0033] In this embodiment, in a gallium nitride junction field-effect transistor (GaN) device with a high-k dielectric buried layer, using a high-k dielectric as the buried layer allows for a vertical device with low on-resistance under the same breakdown voltage. In this embodiment, using a GaN junction field-effect transistor with a high-k dielectric buried layer significantly reduces on-resistance and improves device conduction performance. Since most of the displacement lines generated by the depletion drift region under reverse bias pass through the high-k insulator, compared to conventional MOSFETs, a higher doping concentration can be used in the drift region for a given chip size, thereby significantly reducing on-resistance and improving device conduction performance. The high-k buried layer generates a polarization charge shielding effect, increasing the gate threshold voltage (Vth) by more than 0.5V and reducing gate capacitance.

[0034] Simulation experiments were conducted on the gallium nitride junction field-effect transistor device with a high-k dielectric buried layer in this embodiment using the simulation software Sentaurus. The results are shown in the table below. parameter Traditional GaN JFET This embodiment Increase Breakdown voltage 900V 1400V +55.6% Threshold voltage Vth -2.1V -1.3V +38% Gate leakage current <![CDATA[10⁻ 4 A / mm]]> <![CDATA[10⁻ 9 A / mm]]> <![CDATA[↓ 10 5 times]]> Cutoff frequency fT 18 GHz 35 GHz +94% Rds(on)·Ciss 2.1 Ω·nF 1.0 Ω·nF -52% Process compatibility: Compatible with existing CMOS processes.

[0035] The breakdown voltage mechanism of the gallium nitride junction field-effect transistor (JFET) with a high-k dielectric buried layer of this invention is as follows: This invention uses a high-k material buried layer and gallium nitride material in the drift region. The electric field distribution is controlled by the high-k material, achieving low specific on-resistance and high breakdown voltage. Since most of the electric displacement lines generated by the depletion of the drift region under reverse bias pass through the high-k insulator, compared to traditional MOSFETs, a higher doping concentration can be used in the drift region for a given chip size. This achieves both high breakdown voltage and effectively reduces on-resistance. The high-k buried layer generates a polarization charge shielding effect, increasing the gate control threshold voltage (Vth) by more than 0.5V and reducing gate capacitance. This invention, by introducing a high-k dielectric buried layer to reconstruct the GaN JFET band structure, breaks through the physical limits of traditional devices between gate control efficiency and high-frequency losses, providing a disruptive solution for third-generation semiconductor power devices.

[0036] It should be noted that all the devices (parts whose specific structures are not specified) selected in this application are general standard parts or parts known to those skilled in the art, and their structures and principles can be known to those skilled in the art through technical manuals or conventional experimental methods.

[0037] In the description of the present invention, it should be noted that the terms "center," "upper," "lower," "left," "right," "vertical," "horizontal," "inner," and "outer," etc., indicating orientations or positional relationships, are based on the orientations or positional relationships shown in the accompanying drawings and are intended solely to facilitate and simplify the description of the present invention. They are not intended to indicate or imply that the devices or components referred to must have, be constructed, or operate in a specific orientation, and therefore should not be construed as limitations on the present invention. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and should not be construed as indicating or implying relative importance.

[0038] Based on the above-described preferred embodiments of the present invention, and through the foregoing description, those skilled in the art can make various changes and modifications without departing from the inventive concept. The technical scope of this invention is not limited to the contents of the specification.

Claims

1. A gallium nitride junction field-effect transistor device with a high-k dielectric buried layer, characterized in that, include: The N⁺-GaN substrate layer (2), N⁺-GaN buffer layer (3), N⁻-GaN drift layer (7), and N⁺-GaN contact layer (8) are arranged sequentially from bottom to top; among them P-type deposits are disposed on both sides of the N⁻-GaN drift layer (7). + -GaN gate layer (6); The P + A high-K dielectric buried layer (4) is disposed between the GaN gate layer (6) and the N-GaN buffer layer (3).

2. The gallium nitride junction field-effect transistor device according to claim 1, characterized in that, The material of the high-K dielectric buried layer is one of hafnium-based oxide, aluminum-based oxide, and zirconium-based oxide.

3. The gallium nitride junction field-effect transistor device according to claim 2, characterized in that, The material of the high-K dielectric buried layer is HfO2.

4. The gallium nitride junction field-effect transistor device according to claim 1, characterized in that, The doping concentration of the N⁺-GaN substrate layer (2) is 5 × 10⁻⁶. 19 cm -3 .

5. The gallium nitride junction field-effect transistor device according to claim 1, characterized in that, The doping concentration of the N-GaN buffer layer (3) is 1×10⁻⁶. 15 ~5×10 18 cm -3 .

6. The gallium nitride junction field-effect transistor device according to claim 1, characterized in that, The doping concentration of the N⁻-GaN drift layer (7) is 5×10⁻⁶. 16 cm -3 .

7. The gallium nitride junction field-effect transistor device according to claim 1, characterized in that, The doping element of the P+-GaN gate layer (6) includes Mg, with a doping concentration of 1×10⁻⁶. 19 cm -3 .

8. The gallium nitride junction field-effect transistor device according to claim 1, characterized in that, The doping concentration of the N⁺-GaN contact layer (8) is 1×10⁻⁶. 18 ~5×10 19 cm -3 .

9. The gallium nitride junction field-effect transistor device according to claim 1, characterized in that, The gallium nitride junction field-effect transistor device further includes: The gate electrode (5) is set at P + -Outer surface of GaN gate layer 6; Drain electrode (1) is disposed on the lower surface of N⁺-GaN substrate layer 2; The source electrode (9) is disposed on the upper surface of the N⁺-GaN contact layer 8.

10. The gallium nitride junction field-effect transistor device according to claim 9, characterized in that, The gate electrode (5) is made of Ni / Au alloy and is a Schottky contact; The material of the drain electrode (1) is a Ni / Au alloy; The source electrode (9) is made of a Ti / Al / Ni / Au alloy.

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