Semiconductor structure and preparation method thereof

Abstract

The invention provides a semiconductor structure and a preparation method thereof, a second conductive type heavily doped region is arranged in a first conductive type well region on two sides of a JFET region in an epitaxial layer, and a first conductive type heavily doped region is arranged on one side, far away from the JFET region, of the second conductive type heavily doped region; the surface, away from the substrate layer, of the epitaxial layer is of a groove structure. According to the invention, spatial modulation of the trench structure on the semiconductor structure is utilized, so that the distance between the gate structure and the source electrode in the trench structure is converted from a transverse direction to a longitudinal direction, the transverse size of a device cell is reduced, and the conduction capability of the device is improved; meanwhile, the epitaxial layer is provided with a current expansion layer as a body region to optimize electric field distribution, and device performance is improved; in addition, the transverse width of the second conduction type heavily doped region on the side surface of the gate structure is removed, the cell size of the device is further reduced, the channel density is increased, and the device performance is improved; and finally, the first conductive type heavily doped region and the second conductive type heavily doped region are arranged at intervals along the length direction of the gate electrode region, so that the device density is further improved.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor integrated circuit manufacturing technology, and in particular relates to a semiconductor structure and its preparation method. Background Technology

[0002] As electronic devices continue to miniaturize and increase in performance, the performance requirements for semiconductor devices are becoming increasingly stringent. To meet these demands, reducing the cell size of semiconductor devices has become an important technical approach. By reducing the cell size, the integration density of devices can be significantly improved, allowing more functions to be integrated into a smaller space. In addition, reducing the cell size can also reduce on-resistance and increase switching speed, enabling electronic devices to respond more quickly, thereby meeting the high speed and efficiency requirements of modern electronic devices.

[0003] While reducing cell size offers numerous advantages, further miniaturization faces a series of technical challenges in actual manufacturing. The cell size of traditional MOSFET devices includes several key parameters, such as Lohmic (source ohmic contact width), Lgs (lateral distance from gate to source / width of interlayer dielectric layer) × 2, Loverlap (lateral overlap width between gate and source N+) × 2, Lch (channel length) × 2, and Ljfet (JFET region width). However, the widths of these components currently determining the cell size have reached the physical and technological limits of semiconductor structures. When the cell size shrinks to a certain extent, it becomes difficult to further reduce the on-resistance of the device, limiting performance improvements. Simultaneously, shrinking the cell size may also lead to a decrease in conduction performance, as smaller dimensions can introduce more manufacturing defects and instabilities. Furthermore, as the cell size decreases, the internal electric field strength increases, which may reduce reliability at high voltages and even lead to breakdown. Therefore, although reducing cell size can theoretically bring many benefits, in practical applications, these technical challenges must be overcome in order to truly improve device performance and achieve efficient operation of electronic devices.

[0004] Therefore, there is an urgent need for a structure or method that can further reduce the cell size of semiconductor devices to improve device performance.

[0005] It should be noted that the above introduction to the technical background is only for the purpose of providing a clear and complete explanation of the technical solutions of this application and facilitating the understanding of those skilled in the art. It should not be assumed that the above technical solutions are known to those skilled in the art simply because these solutions have been described in the background section of this application. Summary of the Invention

[0006] In view of the shortcomings of the prior art, the purpose of this invention is to provide a semiconductor structure and its fabrication method to solve the problem that the cell size of semiconductor devices is difficult to further reduce in order to improve device performance.

[0007] To achieve the above objectives, the present invention provides a method for preparing a semiconductor structure, the method comprising:

[0008] A substrate layer is provided, the substrate layer including opposing first and second surfaces;

[0009] An epitaxial layer is disposed on the first surface of the substrate layer;

[0010] Selective first conductivity type ion implantation is performed on the surface of the epitaxial layer away from the substrate layer to form two first conductivity type well regions in the epitaxial layer, and the epitaxial layer between the two first conductivity type well regions is a JFET region.

[0011] Selective implantation of second-conductivity ions is performed on the surface of the first conductivity type well region away from the substrate layer to form a second-conductivity type heavily doped region within the first conductivity type well region;

[0012] Selective ion implantation of a first conductivity type is performed on the surface of the epitaxial layer away from the substrate layer, and a first conductivity type heavily doped region is formed in the epitaxial layer on the side of the second conductivity type heavily doped region and the first conductivity type well region away from the JFET region; and

[0013] The surface of the epitaxial layer away from the substrate layer is etched to form a trench structure; the trench structure extends along a first direction through the JFET region and the first conductivity type well region between the JFET region and the second conductivity type heavily doped region and extends into the second conductivity type heavily doped region; the trench structure extends along a second direction into the second conductivity type heavily doped region; the bottom surface of the trench structure is higher than the bottom surface of the second conductivity type heavily doped region; the first direction is perpendicular to the second direction.

[0014] Optionally, the preparation method further includes:

[0015] A gate oxide layer is provided to cover the inner wall of the trench structure and the surface of the epitaxial layer;

[0016] A gate electrode region is formed on the gate oxide layer within the trench structure, the top surface of the gate electrode region is lower than the surface of the epitaxial layer, and the gate oxide layer covers the bottom and side surfaces of the gate electrode region;

[0017] An interlayer dielectric layer is disposed on the gate electrode region within the trench structure, and the interlayer dielectric layer and the gate oxide layer together encapsulate the gate electrode region; and

[0018] Remove the gate oxide layer and the interlayer dielectric layer other than the trench structure, so that the surface of the epitaxial layer away from the substrate layer exposes the first conductivity type heavily doped region and the second conductivity type heavily doped region.

[0019] Optionally, the method for forming the first conductivity type well region and the second conductivity type heavily doped region includes:

[0020] A patterned first mask layer is provided on the surface of the epitaxial layer away from the substrate layer to expose the surface of the region for setting the first conductivity type well region;

[0021] Using the first mask layer as a mask, the exposed surface area is implanted with ions of the first conductivity type to form a well region of the first conductivity type in the epitaxial layer.

[0022] A sidewall mask layer is formed on the side of the patterned first mask layer using a sidewall self-alignment process, exposing the surface area for setting the second conductivity type heavily doped region within the first conductivity type well region;

[0023] Using the first mask layer and the sidewall mask layer as masks, second conductivity type ion implantation is performed on the exposed surface area to form a second conductivity type heavily doped region within the first conductivity type well region; and

[0024] Remove the first mask layer and the sidewall mask layer.

[0025] Optionally, the trench structure has a preset distance from the heavily doped region of the first conductivity type along the first direction.

[0026] Optionally, the trench structure penetrates the second conductivity type heavily doped region along a first direction, and the side of the trench structure contacts the first conductivity type heavily doped region.

[0027] The present invention also provides a semiconductor structure, which is obtained by any of the above-described preparation methods, and the semiconductor structure comprises:

[0028] The substrate layer includes opposing first and second surfaces;

[0029] An epitaxial layer is located on the first surface of the substrate layer;

[0030] A first conductivity type well region is located within the surface of the epitaxial layer away from the substrate layer, wherein the epitaxial layer between adjacent first conductivity type well regions is a JFET region.

[0031] The second conductivity type heavily doped region is located within the first conductivity type well region, and the bottom surface and the side surface near the JFET region of the second conductivity type heavily doped region are wrapped by the first conductivity type well region.

[0032] A first conductivity type heavily doped region, the first conductivity type heavily doped region being located within the surface of the epitaxial layer away from the substrate layer and contacting the sides of the first conductivity type well region and the second conductivity type heavily doped region away from the JFET region; and

[0033] A trench structure is located on the surface of the epitaxial layer away from the substrate layer. The trench structure extends along a first direction through the JFET region and the first conductivity type well region between the JFET region and the second conductivity type heavily doped region, and extends along a second direction to the second conductivity type heavily doped region. The bottom surface of the trench structure is higher than the bottom surface of the second conductivity type heavily doped region. The first direction is perpendicular to the second direction.

[0034] Optionally, the semiconductor structure further includes a gate structure located within the trench structure; the gate structure includes:

[0035] A gate oxide layer, wherein the gate oxide layer is located within the trench structure;

[0036] The gate electrode region, the bottom surface and the side surface of which are covered by the gate oxide layer;

[0037] An interlayer dielectric layer is provided, which fills the gate electrode region within the trench structure, and the interlayer dielectric layer and the gate oxide layer together encapsulate the gate electrode region.

[0038] Optionally, the gate structure extends through the second conductivity type heavily doped region along a first direction, and the side of the gate structure contacts the first conductivity type heavily doped region.

[0039] Optionally, the thickness of the gate oxide layer surrounding the gate electrode region is 30-50 nanometers, and the thickness of the interlayer dielectric layer is greater than 500 nanometers.

[0040] Optionally, the gate structure extends along a third direction, and the second conductivity type heavily doped region is also located on both sides of the gate structure centered on the central axis along the third direction, adjacent to the first conductivity type heavily doped region along the third direction, and alternately distributed with the first conductivity type heavily doped region. The first conductivity type well region is also located on the bottom surface of the second conductivity type heavily doped region on both sides of the gate structure.

[0041] As described above, the semiconductor structure and its preparation method of the present invention have the following beneficial effects:

[0042] This invention spatially modulates the semiconductor structure by changing the distance between the gate structure and the source in the trench structure from lateral to vertical, thereby significantly reducing the lateral width of the semiconductor structure and optimizing the space utilization of the semiconductor structure. This further reduces the device cell size, lowers the on-resistance, and improves the conduction capability of the device when the width of each part of the device has reached the physical and process limits.

[0043] This invention optimizes the electric field distribution, reduces the on-resistance, and improves the carrier injection efficiency by setting a current spreading layer as the body region in the epitaxial layer, thereby further improving the device performance.

[0044] This invention further reduces the device cell size, increases the channel density, improves the device's conductivity, and reduces on-resistance and on-loss by removing the lateral width of the heavily doped region of the second conductivity type on the side of the gate structure.

[0045] The present invention further improves the device density by setting a first conductivity type heavily doped region and a second conductivity type heavily doped region at intervals along the length direction of the gate electrode region. Attached Figure Description

[0046] Figure 1 This diagram illustrates the cell size composition of a semiconductor structure in the prior art.

[0047] Figure 2 The diagram shown is a schematic representation of the substrate layer provided in step 1 of the semiconductor structure fabrication method of Embodiment 1 of the present invention.

[0048] Figure 3 The diagram shown is a schematic representation of the structure formed by setting the epitaxial layer in step 2 of the semiconductor structure fabrication method of Embodiment 1 of the present invention.

[0049] Figure 4 The diagram shown is a schematic representation of the structure formed in step 3 of the semiconductor structure fabrication method according to Embodiment 1 of the present invention, which is the formation of a well region of the first conductivity type.

[0050] Figure 5 The diagram shown is a schematic representation of the structure formed in step 4 of the semiconductor structure fabrication method of Embodiment 1 of the present invention, which is a heavily doped region of the second conductivity type.

[0051] Figure 6 The diagram shown is a schematic representation of the structure formed in step 5 of the semiconductor structure fabrication method according to Embodiment 1 of the present invention, which represents the formation of a heavily doped region of the first conductivity type.

[0052] Figure 7The diagram shown is a schematic representation of the trench structure formed in step 6 of the semiconductor structure fabrication method of Embodiment 1 of the present invention.

[0053] Figure 8 The diagram shown is a schematic representation of the structure with a gate oxide layer in an example of the semiconductor structure fabrication method of Embodiment 1 of the present invention.

[0054] Figure 9 The diagram shown is a schematic representation of the structure with a gate electrode region in an example of the semiconductor structure fabrication method of Embodiment 1 of the present invention.

[0055] Figure 10 The diagram shown is a schematic representation of the structure with an interlayer dielectric layer in an example of the semiconductor structure fabrication method of Embodiment 1 of the present invention.

[0056] Figure 11 The diagram shown is a schematic representation of the structure with source and drain electrodes in an example of the semiconductor structure fabrication method of Embodiment 1 of the present invention.

[0057] Figure 12 The diagram shown is a schematic diagram of the semiconductor structure in Embodiment 2 of the present invention.

[0058] Figure 13 The diagram shown is a three-dimensional view of the semiconductor structure in Embodiment 3 of the present invention.

[0059] Explanation of icon numbers

[0060] 10. Substrate layer; 11. First mask layer; 12. Sidewall mask layer; 13. Second mask layer; 14. Third mask layer; 15. Source; 16. Drain;

[0061] 20. Epitaxial layer; 21. Epitaxial layer of the second conductivity type; 22. Current spreading layer; 23. Well region of the first conductivity type; 24. Heavily doped region of the first conductivity type; 25. Heavily doped region of the second conductivity type; 26. JFET region; 27. Trench structure;

[0062] 30. Gate structure; 31. Gate oxide layer; 32. Gate electrode region; 33. Interlayer dielectric layer;

[0063] X, first direction; Y, second direction; Z, third direction. Detailed Implementation

[0064] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0065] In the detailed description of embodiments of the present invention, for ease of explanation, the schematic diagrams illustrating the device structure may be partially enlarged without adhering to the general scale, and the schematic diagrams are merely examples and should not limit the scope of protection of the present invention. Furthermore, in actual manufacturing, the three-dimensional spatial dimensions of length, width, and depth should be included.

[0066] For ease of description, spatial relation terms such as “below,” “under,” “lower than,” “below,” “above,” and “upper” may be used herein to describe the relationship between one element or feature shown in the accompanying drawings and other elements or features. It will be understood that these spatial relation terms are intended to include directions other than those depicted in the accompanying drawings for devices in use or operation.

[0067] In the context of this application, the structure described above the first feature may include embodiments in which the first and second features are in direct contact, or embodiments in which additional features are formed between the first and second features, such that the first and second features may not be in direct contact.

[0068] It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of the present invention. Therefore, the illustrations only show the components related to the present invention and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex. The quantity range given in the present invention includes the two boundary values ​​of the quantity range by default unless otherwise specified.

[0069] Reducing cell size can significantly improve device integration, lower on-resistance, and increase switching speed, enabling electronic devices to respond more quickly. However, the cell size of traditional MOSFET devices is determined by several key parameters: such as... Figure 1 As shown, the cell size = Lohmic (source ohmic contact width) + Lgs (lateral distance from gate electrode region to source / width of interlayer dielectric layer) × 2 + Lovelap (lateral overlap width of gate electrode region and heavily doped N-type source region) × 2 + Lch (channel length) × 2 + Ljfet (JFET region width). However, the widths of the various parts that determine the cell size have reached the physical and technological limits of current semiconductor structures, making it difficult to further reduce the on-resistance of the device and limiting the improvement of device performance.

[0070] Example 1:

[0071] This embodiment provides a method for fabricating a semiconductor structure, the method comprising:

[0072] Step 1: Provide a substrate layer, the substrate layer including opposing first and second surfaces;

[0073] Step 2: Deposit an epitaxial layer on the first surface of the substrate layer;

[0074] Step 3: Selective first conductivity type ion implantation is performed on the surface of the epitaxial layer away from the substrate layer to form two first conductivity type well regions in the epitaxial layer, and the epitaxial layer between the two first conductivity type well regions is a JFET region;

[0075] Step 4: Selectively implant second conductivity type ions into the surface of the first conductivity type well region away from the substrate layer to form a second conductivity type heavily doped region within the first conductivity type well region;

[0076] Step 5: Selectively implant ions of the first conductivity type onto the surface of the epitaxial layer away from the substrate layer, and form a first conductivity type heavily doped region on the side of the epitaxial layer away from the JFET region, where the second conductivity type heavily doped region and the first conductivity type well region are located.

[0077] Step 6: Etch the surface of the epitaxial layer away from the substrate layer to form a trench structure; the trench structure penetrates the JFET region and the first conductivity type well region between the JFET region and the second conductivity type heavily doped region along a first direction and extends into the second conductivity type heavily doped region; the trench structure extends into the second conductivity type heavily doped region along a second direction; the bottom surface of the trench structure is higher than the bottom surface of the second conductivity type heavily doped region; the first direction is perpendicular to the second direction.

[0078] The method for preparing the semiconductor structure of the present invention will now be described in detail with reference to the accompanying drawings. It should be noted that the above order does not strictly represent the order of the preparation method of the semiconductor structure protected by the present invention, and those skilled in the art can make changes according to the actual preparation steps.

[0079] First, proceed with step 1, as follows: Figure 2 As shown, a substrate layer 10 (N-sub) is provided, the substrate layer 10 including opposing first and second surfaces.

[0080] Then, proceed to step 2, as follows: Figure 3 As shown, an epitaxial layer 20 (N-epi) is disposed on the first surface of the substrate layer 10.

[0081] In one embodiment, such as Figure 2As shown, the method of forming the epitaxial layer 20 on the first surface of the substrate 10 includes: forming a second conductivity type epitaxial layer 21 (N-epi) on the first surface of the substrate 10; forming a current spreading layer 22 (CSL) on the surface of the second conductivity type epitaxial layer 21 away from the substrate 10; the second conductivity type epitaxial layer 21 and the current spreading layer 22 constitute the epitaxial layer 20; the first conductivity type well region 23, the first conductivity type heavily doped region 24, the second conductivity type heavily doped region 25, and the trench structure 27 are all formed within the current spreading layer 22.

[0082] The present invention improves device performance by setting a current spreading layer 22 as a body region in the epitaxial layer 20. The current spreading layer 22 can optimize the electric field distribution, reduce the on-resistance and improve the carrier injection efficiency.

[0083] In one embodiment, such as Figure 3 As shown, both the substrate layer 10 and the epitaxial layer 20 are doped with the second conductivity type to form a MOSFET device. Specifically, other device structures can also be obtained by setting the specific structure of the substrate layer 10 and the epitaxial layer 20, all of which are within the protection scope of this invention.

[0084] In one embodiment, the substrate layer 10 is a heavily doped substrate of a first conductivity type, and the epitaxial layer 20 includes an epitaxial layer 21 of a second conductivity type.

[0085] This invention obtains an IGBT device based on the concept of this scheme by setting the doping distribution of the substrate layer 10 and the epitaxial layer 20.

[0086] In one embodiment, the current spreading layer 22 is made of the same material as the substrate layer 10.

[0087] Next, proceed to step 3, as follows: Figure 4 As shown, selective first conductivity type ion implantation is performed on the surface of the epitaxial layer 20 away from the substrate layer 10, forming two first conductivity type well regions 23 (PW) in the epitaxial layer 20, and the epitaxial layer 20 between the two first conductivity type well regions 23 is a JFET region 26 (JFET).

[0088] Then, proceed to step 4, as follows: Figure 5 As shown, selective second-conductivity ion implantation is performed on the surface of the first conductivity type well region 23 away from the substrate layer 10 to form a second-conductivity type heavily doped region 25 (N+) within the first conductivity type well region 23.

[0089] In one embodiment, a method for forming the first conductivity type well region 23 and the second conductivity type heavily doped region 25 includes:

[0090] A patterned first mask layer 11 is provided on the surface of the epitaxial layer 20 away from the substrate layer 10, exposing the surface area for setting the first conductivity type well region 23.

[0091] like Figure 4 As shown, the first conductive type ion implantation is performed on the exposed area surface using the first mask layer 11 as a mask, and the first conductive type well region 23 is formed in the epitaxial layer 20.

[0092] A sidewall mask layer 12 is formed on the side of the patterned first mask layer 11 using a sidewall self-alignment process, exposing the surface of the region used to set the second conductivity type heavily doped region 25 within the first conductivity type well region 23.

[0093] like Figure 5 As shown, using the first mask layer 11 and the sidewall mask layer 12 as masks, second conductivity type ion implantation is performed on the exposed surface area to form a second conductivity type heavily doped region 25 within the first conductivity type well region 23; and

[0094] Remove the first mask layer 11 and the sidewall mask layer 12.

[0095] The present invention forms a sidewall mask layer 12 on the side of the first mask layer 11 and uses a sidewall self-alignment process to achieve high-precision setting of the position of the heavily doped region 25 of the second conductivity type, which is beneficial to improving the reliability and yield of the device.

[0096] Next, proceed to step 5, as follows: Figure 6 As shown, selective first conductivity type ion implantation is performed on the surface of the epitaxial layer 20 away from the substrate layer 10, and a first conductivity type heavily doped region 24 (P+) is formed on the side of the epitaxial layer 20 away from the JFET region 26, where the second conductivity type heavily doped region 25 and the first conductivity type well region 23 are located.

[0097] In one embodiment, such as Figure 6 As shown, the method for forming the first conductivity type heavily doped region 24 includes: forming a patterned second mask layer 13 on the surface of the epitaxial layer 20 away from the substrate layer 10, exposing the surface area for forming the first conductivity type heavily doped region 24; performing first conductivity type ion implantation on the exposed surface area using the second mask layer 13 as a mask, and forming the first conductivity type heavily doped region 24 on the side of the second conductivity type heavily doped region 25 away from the JFET region 26 in the epitaxial layer 20.

[0098] Finally, proceed to step 6, as follows: Figure 7 As shown, the surface of the epitaxial layer 20 away from the substrate layer 10 is etched to form a trench structure 27; the trench structure 27 extends along the first direction X through the JFET region 26 and the first conductivity type well region 23 between the JFET region 26 and the second conductivity type heavily doped region 25 and extends into the second conductivity type heavily doped region 25; the trench structure 27 extends along the second direction Y into the second conductivity type heavily doped region 25; the bottom surface of the trench structure 27 is higher than the bottom surface of the second conductivity type heavily doped region 25; the first direction X is perpendicular to the second direction Y.

[0099] In one embodiment, such as Figure 7 As shown, the method for forming the trench structure 27 includes: forming a patterned third mask layer 14 on the surface of the epitaxial layer 20 away from the substrate layer 10, exposing the surface of the first conductivity type well region 23 between the JFET region 26 and the second conductivity type heavily doped region 25, and the surface of the second conductivity type heavily doped region 25 adjacent to the first conductivity type well region 23; etching the exposed surface using the third mask layer 14 as a mask to obtain the trench structure 27.

[0100] In this embodiment, the trench structure 27 has a preset distance from the first conductivity type heavily doped region 24 along the first direction X.

[0101] In one embodiment, the preparation method further includes:

[0102] like Figure 8 As shown, a gate oxide layer 31 (Gox) is provided to cover the inner wall of the trench structure 27 and the surface of the epitaxial layer 20;

[0103] like Figure 9 As shown, a gate electrode region 32 is provided on the gate oxide layer 31 within the trench structure 27. The top surface of the gate electrode region 32 is lower than the surface of the epitaxial layer 20, and the gate oxide layer 31 covers the bottom and side surfaces of the gate electrode region 32.

[0104] like Figure 10 As shown, an interlayer dielectric layer 33 (Oxide) is disposed on the gate electrode region 32 within the trench structure 27, and the interlayer dielectric layer 33 and the gate oxide layer 31 together enclose the gate electrode region 32; and

[0105] Remove the gate oxide layer 31 and the interlayer dielectric layer 33 other than the trench structure 27, so that the surface of the epitaxial layer 20 away from the substrate layer 10 exposes the first conductivity type heavily doped region 24 and the second conductivity type heavily doped region 25.

[0106] In one embodiment, after the gate oxide layer 31 is formed, an annealing process is performed.

[0107] This invention, through an annealing process on the gate oxide layer 31, can repair defects, eliminate lattice damage introduced during oxide layer growth, mitigate lattice strain, and rearrange atoms in the oxide layer, thereby improving the integrity and stability of the gate oxide layer 31. Simultaneously, it reduces interface state defects between the gate oxide layer 31 and the epitaxial layer 20, improving interface quality and thus enhancing the electrical performance of the device. Furthermore, it can improve the dielectric properties of the gate oxide layer 31, reduce gate leakage current, and enhance the insulation performance of the device. Additionally, it makes the loose gate oxide layer 31 denser and strengthens the bonding strength between the gate oxide layer 31 and the epitaxial layer 20, thereby improving the stability and reliability of the gate oxide layer 31.

[0108] In one embodiment, the method of setting the gate electrode region 32 includes: growing a polysilicon structure on the surface of the gate oxide layer 31 within the trench structure 27 to fill the trench structure 27; and etching back the grown polysilicon structure to obtain the gate electrode region 32 with its top surface lower than the surface of the substrate layer 10.

[0109] In one embodiment, the interlayer dielectric layer 33 is made of the same material as the gate oxide layer 31.

[0110] In one embodiment, the method of setting the interlayer dielectric layer 33 includes: growing an insulating dielectric to fill the trench structure 27 on the surface of the gate electrode region 32; etching back the grown insulating dielectric to expose the surfaces of the first conductivity type heavily doped region 24 and the second conductivity type heavily doped region 25 in the epitaxial layer 20, thereby obtaining the interlayer dielectric layer 33 with its top surface flush with the surface of the substrate layer 10.

[0111] In one embodiment, such as Figure 11 As shown, after the gate structure 30 is set, a source 15 is set on the surface exposed by the trench structure 27 and the epitaxial layer 20, and a drain 16 is set on the second surface of the substrate layer 10.

[0112] This invention utilizes process steps to perform spatial modulation design on the semiconductor structure, modulating the distance Lgs between the gate structure 30 and the source 15 from lateral to vertical, such as... Figure 11As shown, the lateral dimension of the device cell is calculated as Lohmic (15-ohm contact width of the source electrode) + Tox (gate oxide thickness) × 2 + Lovelap (lateral overlap width of the gate electrode region 32 and the second conductivity type heavily doped region 25) × 2 + Lch (channel length) × 2 + Ljfet (width of JFET region 26). The distance Lgs between the gate structure 30 and the source electrode 15 no longer affects the lateral dimension of the cell, thereby significantly reducing the lateral dimension of the cell. This optimizes the space utilization of the semiconductor structure. Even when the width of each part of the device has reached the physical and process limits, the device cell size is further reduced, the on-resistance of the device is reduced, and the conduction capability of the device is improved.

[0113] In one embodiment, the method of setting the source 15 and the drain 16 includes: depositing source 15 metal on the exposed surfaces of the trench structure 27 and the epitaxial layer 20, depositing drain 16 metal on the second surface of the substrate layer 10; and performing an ohmic contact annealing process to form the source 15 and the drain 16.

[0114] This invention uses an ohmic contact annealing process on the source metal 15 and drain metal 16 to form a low-resistance ohmic contact between the metal electrode and the semiconductor, thereby reducing contact resistance and energy loss during current transmission; at the same time, it enhances the bonding strength between the metal and the semiconductor, ensuring the stability of contact performance during device operation.

[0115] This embodiment also provides a semiconductor structure, such as Figure 11 As shown, the semiconductor structure is obtained using any of the above-described methods for preparing a semiconductor structure, and the semiconductor structure includes:

[0116] Substrate 10 includes opposing first and second surfaces;

[0117] Epitaxial layer 20 is located on the first surface of the substrate layer 10;

[0118] First conductivity type well region 23, the first conductivity type well region 23 is located in the surface of the epitaxial layer 20 away from the substrate layer 10, wherein the epitaxial layer 20 between adjacent first conductivity type well regions 23 is a JFET region 26.

[0119] The second conductivity type heavily doped region 25 is located within the first conductivity type well region 23, and the bottom surface and the side surface near the JFET region 26 of the second conductivity type heavily doped region 25 are wrapped by the first conductivity type well region 23.

[0120] The first conductivity type heavily doped region 24 is located within the surface of the epitaxial layer 20 away from the substrate layer 10 and contacts the side surfaces of the first conductivity type well region 23 and the second conductivity type heavily doped region 25 away from the JFET region 26; and

[0121] The trench structure 27 is located on the surface of the epitaxial layer 20 away from the substrate layer 10. The trench structure 27 extends along a first direction X through the JFET region 26 and the first conductivity type well region 23 between the JFET region and the second conductivity type heavily doped region 25 and extends to the second conductivity type heavily doped region 25. The trench structure 27 extends along a second direction Y to the second conductivity type heavily doped region 25. The bottom surface of the trench structure 27 is higher than the bottom surface of the second conductivity type heavily doped region 25. The first direction X is perpendicular to the second direction Y.

[0122] In one embodiment, such as Figure 11 As shown, the semiconductor structure further includes a gate structure 30, which is located within the trench structure 27; the gate structure 30 includes:

[0123] Gate oxide layer 31, the gate oxide layer 31 being located within the trench structure 27;

[0124] Gate electrode region 32, the bottom surface and the side surface of the gate electrode region 32 are covered by the gate oxide layer 31;

[0125] An interlayer dielectric layer 33 is filled on the gate electrode region 32 within the trench structure 27, and the interlayer dielectric layer 33 and the gate oxide layer 31 together encapsulate the gate electrode region 32.

[0126] In one embodiment, such as Figure 11 As shown, the epitaxial layer 20 includes a second conductivity type epitaxial layer 21 and a current spreading layer 22. The second conductivity type epitaxial layer 21 is in contact with the first surface of the substrate layer 10. The current spreading layer 22 is located on the surface of the second conductivity type epitaxial layer 21 away from the substrate layer 10. The first conductivity type well region 23, the first conductivity type heavily doped region 24, the second conductivity type heavily doped region 25, and the gate structure 30 are all located within the current spreading layer 22. Specifically, the epitaxial layer 20 can also be configured with other numbers of layers as needed, all of which are within the protection scope of this invention.

[0127] In this embodiment, as Figure 11 As shown, there is a preset distance between the gate structure 30 and the first conductivity type heavily doped region 24 along the first direction X.

[0128] In one embodiment, the thickness of the gate oxide layer 31 enclosing the gate electrode region 32 is 30 nanometers to 50 nanometers, and the thickness of the interlayer dielectric layer 33 is greater than 500 nanometers.

[0129] This invention modulates the lateral distance Lgs between the gate structure 30 and the source 15 into a vertical distance, so that the distance Lgs between the gate structure 30 and the source 15 no longer affects the lateral size of the cell, thereby significantly reducing the lateral size of the cell and overcoming the limitations of physical conditions and process level in the prior art for reducing the size of device cells.

[0130] In one embodiment, such as Figure 11 As shown, the first conductivity type is P-type, and the second conductivity type is N-type.

[0131] In one embodiment, the first conductivity type is N-type and the second conductivity type is P-type.

[0132] Example 2:

[0133] This embodiment provides a method for fabricating a semiconductor structure. The other features of this method are the same as those in the method of Embodiment 1, except that:

[0134] In this embodiment, in step 6, the trench structure 27 penetrates the second conductivity type heavily doped region 25 along the first direction X, and the side of the trench structure 27 contacts the first conductivity type heavily doped region 24.

[0135] By setting the position of the trench structure 27, this invention removes the lateral width of the heavily doped region 25 of the second conductivity type on the side of the gate structure 30, thereby further reducing the device cell size. The size of Lohmic in the device cell size = Lohmic (source 15-ohm contact width) + Tox (gate oxide thickness) × 2 + Lovelap (lateral overlap width of gate electrode region 32 and the heavily doped region 25 of the second conductivity type) × 2 + Lch (channel length) × 2 + Ljfet (width of JFET region 26) is further reduced, thereby further increasing the channel density, improving the device's conduction capability, and reducing on-resistance and conduction loss.

[0136] This embodiment also provides a semiconductor structure, which is obtained by any of the semiconductor structure preparation methods described above. Other features of the semiconductor structure are the same as those in Embodiment 1, except that:

[0137] In this embodiment, as Figure 12 As shown, the gate structure 30 penetrates the second conductivity type heavily doped region 25 along the first direction X, and the side of the gate structure 30 contacts the first conductivity type heavily doped region 24.

[0138] Example 3:

[0139] This embodiment provides a semiconductor structure, which is obtained by any of the semiconductor structure preparation methods described in Embodiment 2. Other features of the semiconductor structure are the same as those of any of the semiconductor structures described in Embodiment 2, except that:

[0140] In this embodiment, as Figure 13 As shown, the gate structure 30 extends along the third direction Z, and the second conductivity type heavily doped region 25 is also located on both sides of the gate structure 30 with the central axis along the third direction Z as the center, adjacent to the first conductivity type heavily doped region 24 along the third direction Z and alternately distributed with the first conductivity type heavily doped region 24. The first conductivity type well region 23 is also located on the bottom surface of the second conductivity type heavily doped region 25 on both sides of the gate structure 30.

[0141] The present invention further optimizes the device space utilization by setting a first conductivity type heavily doped region 24 and a second conductivity type heavily doped region 25 at intervals along the length direction of the gate electrode region 32, thereby further reducing the device on-resistance and improving the device conduction capability.

[0142] In summary, the semiconductor structure and its fabrication method of the present invention can spatially modulate the semiconductor structure using a trench structure. By modulating the distance between the gate structure and the source electrode within the trench structure from lateral to vertical, the lateral width of the semiconductor structure can be significantly reduced, optimizing the space utilization of the semiconductor structure. This further reduces the device cell size, lowers the on-resistance, and improves the device's conductivity, even when the width of each part of the device has reached its physical and technological limits. Simultaneously, by setting a current spreading layer as a body region in the epitaxial layer, the electric field distribution can be optimized, the on-resistance reduced, and the carrier injection efficiency improved, further enhancing device performance. In addition, by removing the lateral width of the second conductivity type heavily doped region on the side of the gate structure, the device cell size is further reduced, the channel density increased, the device conductivity improved, and the on-resistance and conduction loss reduced. Finally, by spaced the first conductivity type heavily doped region and the second conductivity type heavily doped region along the length of the gate electrode region, the device density is further increased.

[0143] Therefore, this invention effectively overcomes the various shortcomings of the prior art and has high industrial application value.

[0144] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.

Claims

1. A method for fabricating a semiconductor structure, comprising: A substrate layer is provided, the substrate layer including opposing first and second surfaces; An epitaxial layer is disposed on the first surface of the substrate layer; Selective first conductivity type ion implantation is performed on the surface of the epitaxial layer away from the substrate layer to form two first conductivity type well regions in the epitaxial layer, and the epitaxial layer between the two first conductivity type well regions is a JFET region. Selective implantation of second-conductivity ions is performed on the surface of the first conductivity type well region away from the substrate layer to form a second-conductivity type heavily doped region within the first conductivity type well region; Selective first conductivity type ion implantation is performed on the surface of the epitaxial layer away from the substrate layer, and a first conductivity type heavily doped region is formed in the epitaxial layer on the side of the second conductivity type heavily doped region and the first conductivity type well region away from the JFET region; as well as The surface of the epitaxial layer away from the substrate layer is etched to form a trench structure; The trench structure extends along a first direction through the JFET region and the first conductivity type well region between the JFET region and the second conductivity type heavily doped region, and extends into the second conductivity type heavily doped region. The trench structure extends along a second direction into the second conductivity type heavily doped region. The bottom surface of the trench structure is higher than the bottom surface of the second conductivity type heavily doped region. The first direction is perpendicular to the second direction.

2. The method for preparing a semiconductor structure according to claim 1, characterized in that, The preparation method further includes: setting a gate oxide layer to cover the inner wall of the trench structure and the surface of the epitaxial layer; A gate electrode region is formed on the gate oxide layer within the trench structure, the top surface of the gate electrode region is lower than the surface of the epitaxial layer, and the gate oxide layer covers the bottom and side surfaces of the gate electrode region; An interlayer dielectric layer is disposed on the gate electrode region within the trench structure, and the interlayer dielectric layer and the gate oxide layer together encapsulate the gate electrode region; and Remove the gate oxide layer and the interlayer dielectric layer other than the trench structure, so that the surface of the epitaxial layer away from the substrate layer exposes the first conductivity type heavily doped region and the second conductivity type heavily doped region.

3. The method for preparing a semiconductor structure according to claim 1, characterized in that, The method for forming the first conductivity type well region and the second conductivity type heavily doped region includes: A patterned first mask layer is provided on the surface of the epitaxial layer away from the substrate layer to expose the surface of the region for setting the first conductivity type well region; Using the first mask layer as a mask, the exposed surface area is implanted with ions of the first conductivity type to form a well region of the first conductivity type in the epitaxial layer. A sidewall mask layer is formed on the side of the patterned first mask layer using a sidewall self-alignment process, exposing the surface area for setting the second conductivity type heavily doped region within the first conductivity type well region; Using the first mask layer and the sidewall mask layer as masks, second conductivity type ion implantation is performed on the exposed surface area to form a second conductivity type heavily doped region within the first conductivity type well region; and Remove the first mask layer and the sidewall mask layer.

4. The method for preparing a semiconductor structure according to claim 1, characterized in that, The trench structure has a preset distance from the heavily doped region of the first conductivity type along the first direction.

5. The method for preparing a semiconductor structure according to claim 1, characterized in that, The trench structure penetrates the second conductivity type heavily doped region along a first direction, and the side of the trench structure contacts the first conductivity type heavily doped region.

6. A semiconductor structure, obtained by the preparation method according to any one of claims 1-5, wherein the semiconductor structure comprises: The substrate layer includes opposing first and second surfaces; An epitaxial layer is located on the first surface of the substrate layer; A first conductivity type well region is located within the surface of the epitaxial layer away from the substrate layer, wherein the epitaxial layer between adjacent first conductivity type well regions is a JFET region. The second conductivity type heavily doped region is located within the first conductivity type well region, and the bottom surface and the side surface near the JFET region of the second conductivity type heavily doped region are wrapped by the first conductivity type well region. The first conductivity type heavily doped region is located within the surface of the epitaxial layer away from the substrate layer and is in contact with the side of the first conductivity type well region and the second conductivity type heavily doped region away from the JFET region. as well as A trench structure is located on the surface of the epitaxial layer away from the substrate layer. The trench structure extends along a first direction through the JFET region and the first conductivity type well region between the JFET region and the second conductivity type heavily doped region, and extends along a second direction to the second conductivity type heavily doped region. The bottom surface of the trench structure is higher than the bottom surface of the second conductivity type heavily doped region. The first direction is perpendicular to the second direction.

7. The semiconductor structure according to claim 6, characterized in that, The semiconductor structure further includes a gate structure located within the trench structure; the gate structure includes: A gate oxide layer, wherein the gate oxide layer is located within the trench structure; The gate electrode region, the bottom surface and the side surface of which are covered by the gate oxide layer; An interlayer dielectric layer is provided, which fills the gate electrode region within the trench structure, and the interlayer dielectric layer and the gate oxide layer together encapsulate the gate electrode region.

8. The semiconductor structure according to claim 7, characterized in that, The gate structure extends through the second conductivity type heavily doped region along a first direction, and the side of the gate structure contacts the first conductivity type heavily doped region.

9. The semiconductor structure according to claim 7, characterized in that, The thickness of the gate oxide layer surrounding the gate electrode region is 30-50 nanometers, and the thickness of the interlayer dielectric layer is greater than 500 nanometers.

10. The semiconductor structure according to claim 7, characterized in that, The gate structure extends along a third direction, and the second conductivity type heavily doped region is also located on both sides of the gate structure with the central axis along the third direction as the center, adjacent to the first conductivity type heavily doped region along the third direction and alternately distributed with the first conductivity type heavily doped region. The first conductivity type well region is also located on the bottom surface of the second conductivity type heavily doped region on both sides of the gate structure.

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