Layout splitting method and system, equipment, storage medium and computer program
By splitting the mask pattern into multiple sub-mask patterns and merging them, the problem of low pattern transfer accuracy after pattern splitting is solved, achieving higher pattern transfer accuracy and a larger exposure process window, and reducing the difficulty of photolithography.
Patent Information
- Application Number
- CN202410547627.2
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-04-30
- Publication Date
- 2025-10-31
AI Technical Summary
In existing technologies, the accuracy of pattern transfer after layout splitting still needs to be improved, and the photolithography process becomes more difficult, affecting the yield of wafer products.
The mask pattern to be split is split into a first sub-mask pattern and a second sub-mask pattern. The patterns in the first sub-mask pattern are subjected to a first merging process, so that they contact each other in a first direction to form a first merged pattern. The patterns in the second sub-mask pattern are subjected to a second merging process, so that they contact each other in a second direction to form a second merged pattern. Finally, a third sub-mask pattern is provided to trim the patterns as a third photomask pattern.
The increased exposure window improves pattern transfer accuracy, reduces the difficulty of photolithography, and ensures that the pattern formed on the wafer is consistent with the mask layout to be separated.
Smart Images
Figure CN120874734A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the field of semiconductor manufacturing, and in particular to a layout splitting method and system, device and storage medium, and computer program. Background Technology
[0002] With the continuous development of technology, higher demands are being placed on the performance and integration density of integrated circuits, which has become a rapid driving force for the research, development, and manufacturing of integrated circuits. According to Moore's Law, current integrated circuit design and manufacturing processes face challenges. Due to various limitations in photolithography technology (new light sources, photolithography lenses, photoresist), the smallest feature size achievable with a single pattern has reached its limit. Following Moore's Law, to meet the requirements of smaller chip feature sizes and continuously improving performance, MP (Multi-Patterning) technology is the most practical photolithography process for a considerable period of time to come.
[0003] As designs become larger and more complex, the accuracy of pattern transfer after layout decomposition still needs to be improved. Summary of the Invention
[0004] The problem solved by the embodiments of the present invention is to provide a layout splitting method and system, device and storage medium, and computer program, which is beneficial to further improve the efficiency of optical proximity correction methods.
[0005] To address the aforementioned problems, this invention provides a method for splitting a mask layout, comprising: acquiring a mask layout to be split, wherein the mask layout to be split contains multiple graphics, the multiple graphics including first graphics arranged in parallel along a first direction and second graphics arranged in parallel along a second direction, the first direction being perpendicular to the second direction, and the regions of the first graphics spaced apart along the first direction and the regions of the second graphics spaced apart along the second direction being trimmed areas; splitting the mask layout to be split into a first sub-mask layout and a second sub-mask layout, such that the first graphics are distributed on the first sub-mask layout and the second graphics are distributed on the second sub-mask layout. On the mask pattern; a first merging process is performed on the first pattern in the first sub-mask pattern, so that multiple first patterns contact each other in the first direction to form a first merged pattern, and the first merged pattern is used as a first photomask pattern; a second merging process is performed on the second pattern in the second sub-mask pattern, so that multiple second patterns contact each other in the second direction to form a second merged pattern, and the second merged pattern is used as a second photomask pattern; a third sub-mask pattern is provided, the sub-mask pattern including multiple trimmed patterns, the distribution of the multiple trimmed patterns in the third sub-mask pattern corresponding to the distribution of the trimmed areas, and the trimmed patterns are used as a third photomask pattern.
[0006] Optionally, the mask layout to be split can be divided into a first sub-mask layout and a second sub-mask layout according to the layout splitting limit rule.
[0007] Optionally, the layout splitting restriction rules include the minimum spacing requirement for adjacent graphics on the same mask layout.
[0008] Optionally, the step of performing a first merging process on the first graphic in the first sub-mask layout includes: extending the end of the first graphic along the first direction until the ends of adjacent first graphics contact each other, and combining multiple contacting first graphics into a first merged graphic.
[0009] Optionally, in the step of obtaining the mask layout to be split, the second graphic is distributed in the regions on both sides of the first graphic; the step of performing a second merging process on the second graphic in the second sub-mask layout includes: extending the outlines of the second graphics on both sides of the first graphic along a second direction until the outlines of adjacent second graphics are in contact, and combining the contacting second graphics into a second merged graphic.
[0010] Optionally, the first pattern includes a metal wire partition layer; the second pattern includes a metal wire partition layer.
[0011] Optionally, the trimmed pattern includes openings.
[0012] Accordingly, this invention also provides a layout splitting system, comprising: an acquisition module for acquiring a mask layout to be split, wherein the mask layout to be split contains multiple graphics, the multiple graphics including first graphics arranged in parallel along a first direction and second graphics arranged in parallel along a second direction, the first direction being perpendicular to the second direction, and the regions of the first graphics spaced apart in the first direction and the regions of the second graphics spaced apart in the second direction being trimmed areas; and a splitting module for splitting the mask layout to be split into a first sub-mask layout and a second sub-mask layout, such that the first graphics are distributed on the first sub-mask layout and the second graphics are distributed on the second sub-mask layout; A first merging module is used to perform a first merging process on a first pattern in the first sub-mask layout, causing multiple first patterns to contact each other in the first direction to form a first merged pattern, and using the first merged pattern as a first photomask pattern; a second merging module is used to perform a second merging process on a second pattern in the second sub-mask layout, causing multiple second patterns to contact each other in the second direction to form a second merged pattern, and using the second merged pattern as a second photomask pattern; a providing module is used to provide a third sub-mask layout, the sub-mask layout including multiple trimmed patterns, the distribution of the multiple trimmed patterns in the third sub-mask layout corresponding to the distribution of the trimmed areas, and using the trimmed patterns as a third photomask pattern.
[0013] Optionally, the first merging module includes: a first extension unit, used to extend the end of the first graphic along the first direction until the ends of adjacent first graphics contact each other, and to combine multiple contacting first graphics into a first merged graphic.
[0014] Optionally, in the step of obtaining the mask layout to be split, the second graphic is distributed in the regions on both sides of the first graphic; the second merging module includes: a second extension unit, used to extend the outlines of the second graphics on both sides of the first graphic along a second direction until the outlines of adjacent second graphics are in contact, and combine the contacting second graphics into a second merged graphic.
[0015] Accordingly, embodiments of the present invention also provide an apparatus, including at least one memory and at least one processor, wherein the memory stores one or more computer instructions, wherein the one or more computer instructions are executed by the processor to implement the layout splitting method provided in embodiments of the present invention.
[0016] Accordingly, embodiments of the present invention also provide a storage medium storing one or more computer instructions, which are used to implement the layout splitting method provided in embodiments of the present invention.
[0017] Accordingly, embodiments of the present invention also provide a computer program product, including computer instructions, which, when executed by a processor, are used to implement the layout splitting method provided in embodiments of the present invention.
[0018] Compared with the prior art, the technical solution of the embodiments of the present invention has the following advantages:
[0019] This invention provides a method for splitting a mask layout, which splits the mask layout to be split into a first sub-mask layout and a second sub-mask layout, such that the first pattern is distributed on the first sub-mask layout and the second pattern is distributed on the second sub-mask layout. A first merging process is performed on the first pattern in the first sub-mask layout, causing multiple first patterns to contact each other in a first direction to form a first merged pattern, which is then used as a first photomask pattern. A second merging process is performed on the second pattern in the second sub-mask layout, causing multiple second patterns to contact each other in a second direction to form a second merged pattern, which is then used as a second photomask pattern. A third sub-mask layout is then provided, wherein the sub-mask layout includes multiple trimmed patterns, the distribution of which in the third sub-mask layout corresponds to the distribution of the trimmed areas, and the trimmed patterns are used as the third photomask pattern. Compared to the approach of segmenting the pattern in the mask layout to be split into multiple sub-patterns, and then splitting these sub-patterns onto different sub-mask layouts, this embodiment of the invention first directly splits the pattern in the mask layout to be split onto a first sub-mask layout and a second sub-mask layout. Then, the first pattern on the first sub-mask layout is merged, increasing the size of the merged first pattern along a first direction. This increases the process window for pattern formation on the wafer during the subsequent process of using the merged first pattern as the first photomask pattern to form a pattern. Simultaneously, the second pattern on the second sub-mask layout is merged, increasing the size of the merged second pattern on the second sub-mask layout. The size of the pattern also increases along the second direction. In the subsequent process of using the second merged pattern as the second photomask pattern to form a pattern on the wafer, the process window for forming the pattern on the wafer can also be increased. Finally, a third sub-mask pattern is provided, which includes multiple trimmed patterns. Since the distribution of the multiple trimmed patterns in the third sub-mask pattern corresponds to the distribution of the trimmed areas, the pattern formed by the first and second photomask patterns can be separated during the process of the third photomask pattern forming a pattern on the wafer. This allows for a pattern distribution on the wafer that is consistent with the mask pattern to be separated, thereby increasing the exposure process window, improving the pattern transfer accuracy, and reducing the process difficulty. Attached Figure Description
[0020] Figure 1This is a flowchart of a method for partitioning a map;
[0021] Figure 2 This is a flowchart of an embodiment of the layout splitting method of the present invention;
[0022] Figures 3 to 8 This is a schematic diagram of the structure corresponding to each step in one embodiment of the layout splitting method of the present invention;
[0023] Figure 9 This is a functional block diagram of an embodiment of the layout splitting method system of the present invention;
[0024] Figure 10 This is a hardware structure diagram of an embodiment of the device provided by the present invention. Detailed Implementation
[0025] Currently, the accuracy of pattern transfer after map splitting still needs improvement. (Reference) Figure 1 The flowchart illustrates a layout splitting method.
[0026] The map splitting method includes the following basic steps:
[0027] Step s1: Obtain the mask layout to be split, wherein the mask layout to be split contains multiple graphics;
[0028] Step s2: Segment the graphic into multiple sub-graphics;
[0029] Step s3: Divide the mask layout to be split into multiple sub-mask layouts, so that multiple sub-patterns are distributed on different sub-mask layouts.
[0030] Research has revealed that with the development of semiconductor technology, the number and density of patterns have increased dramatically. It is no longer possible to expose all the patterns on the mask layout to be separated onto the wafer in a single photolithography process. It is necessary to split the mask layout to be separated into multiple sub-mask layouts. At the same time, the development of semiconductor technology also leads to the decreasing critical dimension (CD) of the pattern. After the pattern is segmented into multiple sub-patterns, the exposure process window is too small during the process of forming the pattern on the wafer using the sub-patterns on the sub-mask layout as photomask patterns. This increases the difficulty of the etching process, increases the error rate of pattern transfer, and thus affects the product yield of the wafer.
[0031] To address the aforementioned technical problem, embodiments of the present invention provide a layout splitting method. (See reference...) Figure 2 The flowchart of an embodiment of the layout splitting method of the present invention is shown.
[0032] In this embodiment, the layout splitting method includes the following basic steps:
[0033] Step S1: Obtain the mask layout to be split. The mask layout to be split contains multiple graphics, including first graphics arranged in parallel along a first direction and second graphics arranged in parallel along a second direction. The first direction is perpendicular to the second direction, and the areas of the first graphics that are spaced apart in the first direction and the areas of the second graphics that are spaced apart in the second direction are all trimming areas.
[0034] Step S2: Divide the mask layout to be split into a first sub-mask layout and a second sub-mask layout, so that the first pattern is distributed on the first sub-mask layout and the second pattern is distributed on the second sub-mask layout.
[0035] Step S3: Perform a first merging process on the first pattern in the first sub-mask layout, so that multiple first patterns contact each other in the first direction to form a first merged pattern, and use the first merged pattern as the first photomask pattern.
[0036] Step S4: Perform a second merging process on the second pattern in the second sub-mask layout, so that multiple second patterns contact each other in the second direction to form a second merged pattern, and use the second merged pattern as the second photomask pattern.
[0037] Step S5: Provide a third sub-mask layout, the third sub-mask layout including multiple trimmed patterns, the distribution of the multiple trimmed patterns in the third sub-mask layout corresponding to the distribution of the trimmed areas, and use the trimmed patterns as the third photomask pattern.
[0038] In this embodiment of the invention, the mask layout to be split is divided into a first sub-mask layout and a second sub-mask layout, with the first pattern distributed on the first sub-mask layout and the second pattern distributed on the second sub-mask layout. A first merging process is performed on the first pattern in the first sub-mask layout, causing multiple first patterns to contact each other in the first direction to form a first merged pattern, which is then used as a first photomask pattern. A second merging process is performed on the second pattern in the second sub-mask layout, causing multiple second patterns to contact each other in the second direction to form a second merged pattern, which is then used as a second photomask pattern. A third sub-mask layout is provided, comprising multiple trimmed patterns. The distribution of the multiple trimmed patterns in the third sub-mask layout corresponds to the distribution of the trimmed areas, and the trimmed patterns are used as the third photomask pattern. Compared to the approach of segmenting the pattern in the mask layout to be split into multiple sub-patterns, and then splitting these sub-patterns onto different sub-mask layouts, this embodiment of the invention first directly splits the pattern in the mask layout to be split onto a first sub-mask layout and a second sub-mask layout. Then, the first pattern on the first sub-mask layout is merged, increasing the size of the merged first pattern along a first direction. This increases the process window for pattern formation on the wafer during the subsequent process of using the merged first pattern as the first photomask pattern to form a pattern. Simultaneously, the second pattern on the second sub-mask layout is merged, increasing the size of the merged second pattern on the second sub-mask layout. The size of the pattern also increases along the second direction. In the subsequent process of using the second merged pattern as the second photomask pattern to form a pattern on the wafer, the process window for forming the pattern on the wafer can also be increased. Finally, a third sub-mask pattern is provided, which includes multiple trimmed patterns. Since the distribution of the multiple trimmed patterns in the third sub-mask pattern corresponds to the distribution of the trimmed areas, the pattern formed by the first and second photomask patterns can be separated during the process of the third photomask pattern forming a pattern on the wafer. This allows for a pattern distribution on the wafer that is consistent with the mask pattern to be separated, thereby increasing the exposure process window, improving the pattern transfer accuracy, and reducing the process difficulty.
[0039] To make the above-mentioned objects, features and advantages of the present invention more apparent and understandable, specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.
[0040] Figures 3 to 8 This is a schematic diagram of the structure corresponding to each step in one embodiment of the layout splitting method of the present invention.
[0041] refer to Figure 3 Step S1: Obtain the mask layout 102 to be split, wherein the mask layout 102 to be split contains multiple patterns, the multiple patterns including those along a first direction (e.g., Figure 3 The first pattern 100, arranged in parallel at intervals (as shown in the X direction), and along the second direction (as shown in the X direction) Figure 3 The second pattern 101 is arranged in parallel at intervals (as shown in the Y direction). The first direction is perpendicular to the second direction, and the regions of the first pattern 100 that are spaced apart in the first direction and the regions of the second pattern 101 that are spaced apart in the second direction are both trimming areas 100A.
[0042] Specifically, the mask layout 102 to be split provides the technological basis for the subsequent layout splitting step.
[0043] In this embodiment, the step of obtaining the mask layout 102 to be split includes: providing an original layout (not shown), the original layout being composed of multiple initial layouts; and using the initial layout layer to be split in the original layout as the mask layout 102 to be split.
[0044] In this embodiment, the pattern is used to create a photomask, which enables photolithography to be performed on the photomask to form the corresponding target structure on the wafer.
[0045] As an example, both the first graphic 100 and the second graphic 101 include a metal wire partition layer.
[0046] Specifically, in the process of forming patterns on a wafer using photolithography with the first pattern 100 and the second pattern 101 respectively, the first pattern 100 and the second pattern 101 are used to separate the metal lines on the wafer, thereby separating the metal lines.
[0047] In other embodiments, the first pattern 100 and the second pattern 101 may also be dielectric insulating walls.
[0048] In this embodiment, the second graphic 101 is distributed in the regions on both sides of the first graphic 100.
[0049] Specifically, the second pattern 101 is distributed in the regions on both sides of the first pattern 100, which facilitates the subsequent extension of the second pattern 101 on both sides of the first pattern 100 along the second direction, so that the second pattern 101 on both sides of the first pattern 100 can contact each other in the second direction to form a second merged pattern. In the subsequent process of using the second merged pattern as a photomask pattern to form a pattern on the wafer, the exposure process window is increased and the pattern transfer accuracy is improved.
[0050] It should be noted that the trimming region 100A is used to correspond to the trimming pattern in the third sub-mask layout provided later. Specifically, the distribution of the trimming region 100A in the mask layout 102 to be split corresponds to the distribution of the trimming pattern in the third sub-mask layout.
[0051] It should also be noted that in the mask layout 102 to be split, a first pattern 100 and a second pattern 101 are provided on both sides of the trimming area 100A. After the first pattern 100 is subjected to a first merging process to form a first merged pattern, and the second pattern 101 is subjected to a second merging process to form a second merged pattern, the first merged pattern and the second merged pattern are used as photomask patterns to form a pattern on the wafer. However, the pattern distribution is inconsistent with the pattern distribution on the mask layout to be split. Therefore, by setting the trimming area 100A in the regions of the first pattern 100 that are spaced apart in the first direction and the regions of the second pattern 101 that are spaced apart in the second direction, it is beneficial to provide the trimmed pattern in the third sub-mask layout according to the distribution of the trimming area 100A. This makes the distribution of the trimmed pattern consistent with the distribution of the trimming area 100A, so that the trimmed pattern can be used as a photomask pattern to re-etch the pattern already formed on the wafer, thereby making the pattern formed on the wafer consistent with the pattern on the mask layout to be split, and improving the accuracy of pattern transfer.
[0052] refer to Figures 4 to 5 Step S2: The mask layout 102 to be split is split into a first sub-mask layout 106 and a second sub-mask layout 108, such that the first pattern 100 is distributed on the first sub-mask layout 106 and the second pattern 101 is distributed on the second sub-mask layout 108.
[0053] Specifically, in this embodiment, a pattern is formed on a wafer by performing a photolithography process using the mask pattern 102 to be split. The mask pattern 102 to be split is divided into a first sub-mask pattern 106 and a second sub-mask pattern 108. In the subsequent semiconductor structure formation process, the first sub-mask pattern 106 and the second sub-mask pattern 108 are used to perform multiple photolithography processes, which increases the exposure process window in the photolithography process and improves the accuracy of pattern transfer in the photolithography process.
[0054] As an example, according to the layout splitting limit rule, the mask layout 102 to be split is split into a first sub-mask layout 106 and a second sub-mask layout 108.
[0055] In this embodiment, the layout splitting restriction rules include the minimum spacing requirement for adjacent graphics on the same mask layout.
[0056] refer to Figure 6 Step S3: Perform a first merging process on the first pattern 100 in the first sub-mask layout 106, so that multiple first patterns 100 contact each other in the first direction to form a first merged pattern 110, and use the first merged pattern 110 as the first photomask pattern.
[0057] It should be noted that merging the first pattern 100 on the first sub-mask layout 106 increases the size of the first merged pattern 110 on the first sub-mask layout 106 along the first direction. In the subsequent process of using the first merged pattern 110 as the first photomask pattern to form a pattern on the wafer, the process window for forming the pattern on the wafer can be increased. At the same time, merging the second pattern 101 on the second sub-mask layout 108 increases the size of the second merged pattern on the second sub-mask layout 108 along the second direction. In the subsequent process of using the second merged pattern as the second photomask pattern to form a pattern on the wafer, the process window for forming the pattern on the wafer can also be increased, improving the pattern transfer accuracy and reducing the process difficulty.
[0058] In this embodiment, the step of performing a first merging process on the first pattern 100 in the first sub-mask layout 106 includes: extending the end of the first pattern 100 along the first direction until the ends of adjacent first patterns 100 contact each other, and combining multiple contacting first patterns 100 into a first merged pattern 110.
[0059] refer to Figure 7 Step S4: Perform a second merging process on the second pattern 101 in the second sub-mask layout 108, so that multiple second patterns 101 contact each other in the second direction to form a second merged pattern 120, and use the second merged pattern 120 as the second photomask pattern.
[0060] It should be noted that multiple second patterns 101 contact each other in the second direction to form a second merged pattern 120, and the second merged pattern 120 is used as a second photomask pattern, so that the size of the second merged pattern 120 on the second sub-mask pattern 108 also increases along the second direction. In the subsequent process of using the second merged pattern 120 as a second photomask pattern to form a pattern on the wafer, the process window for forming the pattern on the wafer can be increased, the pattern transfer accuracy can be improved, and the process difficulty can be reduced.
[0061] As an example, the step of performing a second merging process on the second graphic 101 in the second sub-mask layout 108 includes: extending the outlines of the second graphic 101 on both sides of the first graphic 100 along a second direction until the outlines of adjacent second graphics 101 are in contact, and combining the contacting second graphics 101 into a second merged graphic 120.
[0062] refer to Figure 8Step S5: Provide a third sub-mask layout 140, the third sub-mask layout 140 including a plurality of trimmed patterns 160, the distribution of the plurality of trimmed patterns 160 in the third sub-mask layout 140 corresponding to the distribution of the trimmed area 100A, and use the trimmed patterns 160 as the third photomask pattern.
[0063] Specifically, after the first merged pattern 110 and the second merged pattern 120 are formed on the wafer as photomask patterns, the pattern distribution is inconsistent with the pattern distribution on the mask layout to be split. Therefore, by setting trimming regions 100A in the regions of the first pattern 100 spaced apart in the first direction and the regions of the second pattern 101 spaced apart in the second direction, it is beneficial to provide trimmed patterns 160 in the third sub-mask layout 140 according to the distribution of trimmed regions 100A, so that the distribution of trimmed patterns 160 is consistent with the distribution of trimmed regions 100A. Trimmed patterns 160, as the third photomask pattern, can re-etch the pattern already formed on the wafer, thereby making the pattern formed on the wafer consistent with the pattern on the mask layout to be split, and improving the accuracy of pattern transfer.
[0064] As an example, the trimmed graphic 160 includes an opening.
[0065] Specifically, during the etching process of the pattern already formed on the wafer using the trimmed pattern 160 as the third photomask pattern, the opening will expose part of the metal line isolation layer. The exposed metal line isolation layer is removed by the etching process, so that the pattern formed on the wafer is consistent with the pattern on the mask layout to be split, thereby increasing the process window and improving the accuracy of pattern transfer.
[0066] It should be noted that there is no order restriction on the execution of steps S3, S4 and S5.
[0067] Accordingly, the present invention also provides a layout splitting method system. Figure 9 This is a functional block diagram of an embodiment of the layout splitting method system of the present invention.
[0068] In this embodiment, the layout splitting method system 210 includes: an acquisition module 200, used to acquire a mask layout to be split, wherein the mask layout to be split has multiple graphics, the multiple graphics including first graphics arranged in parallel along a first direction and second graphics arranged in parallel along a second direction, the first direction being perpendicular to the second direction, and the regions of the first graphics spaced apart in the first direction and the regions of the second graphics spaced apart in the second direction being trimmed areas; a splitting module 201, used to split the mask layout to be split into a first sub-mask layout and a second sub-mask layout, such that the first graphics are distributed on the first sub-mask layout and the second graphics are distributed on the second sub-mask layout; a first merging module; and a first merging module. Block 202 is used to perform a first merging process on the first pattern in the first sub-mask layout, so that multiple first patterns contact each other in the first direction to form a first merged pattern, and the first merged pattern is used as a first photomask pattern; the second merging module 203 is used to perform a second merging process on the second pattern in the second sub-mask layout, so that multiple second patterns contact each other in the second direction to form a second merged pattern, and the second merged pattern is used as a second photomask pattern; the providing module 204 is used to provide a third sub-mask layout, the sub-mask layout including multiple trimmed patterns, the distribution of the multiple trimmed patterns in the third sub-mask layout corresponding to the distribution of the trimmed area, and the trimmed patterns are used as a third photomask pattern.
[0069] It should be noted that the splitting module 201 first directly splits the pattern in the mask layout to be split onto the first sub-mask layout and the second sub-mask layout. Then, the first merging module 202 merges the first pattern on the first sub-mask layout, making the size of the first merged pattern on the first sub-mask layout larger along the first direction. In the subsequent process of using the first merged pattern as the first photomask pattern to form a pattern on the wafer, the process window for forming the pattern on the wafer can be increased. At the same time, the second merging module 203 merges the second pattern on the second sub-mask layout, making the size of the second merged pattern on the second sub-mask layout also larger along the second direction. In the subsequent process of forming a pattern on the wafer using the second merged pattern as the second photomask pattern, the process window for forming the pattern on the wafer can also be increased. The module 204 provides a third sub-mask layout, which includes multiple trimmed patterns. Since the distribution of the multiple trimmed patterns in the third sub-mask layout corresponds to the distribution of the trimmed areas, the pattern formed by the first photomask pattern and the second photomask pattern can be separated during the process of forming the pattern on the wafer using the third photomask pattern. This allows for a pattern distribution on the wafer that is consistent with the mask layout to be separated, thereby increasing the exposure process window, improving the pattern transfer accuracy, and reducing the process difficulty.
[0070] Specifically, the acquisition module 200 is used to acquire the mask layout to be split.
[0071] Specifically, the mask layout to be split provides the technological basis for the subsequent layout splitting step.
[0072] In this embodiment, the step of obtaining the mask layout to be split includes: providing an original layout, which is composed of multiple initial layouts; and using the initial layout layer that needs to be split in the original layout as the mask layout to be split.
[0073] In this embodiment, the pattern is used to create a photomask, which enables photolithography to be performed on the photomask to form the corresponding target structure on the wafer.
[0074] As an example, both the first and second graphics include a metal wire partition layer.
[0075] Specifically, in the process of forming patterns on a wafer using photolithography with the first and second patterns respectively, the first and second patterns are used to separate the metal lines on the wafer, thus separating the metal lines.
[0076] In other embodiments, the first and second patterns may also be dielectric insulating walls.
[0077] In this embodiment, the second graphic is distributed in the regions on both sides of the first graphic.
[0078] Specifically, the second pattern is distributed in the regions on both sides of the first pattern, which facilitates the subsequent extension of the second pattern on both sides of the first pattern along the second direction, so that the second pattern on both sides of the first pattern can contact each other in the second direction to form a second merged pattern. In the subsequent process of using the second merged pattern as a photomask pattern to form a pattern on the wafer, the exposure process window is increased and the pattern transfer accuracy is improved.
[0079] It should be noted that the trimmed area corresponds to the trimmed pattern in the third sub-mask layout provided later. Specifically, the distribution of the trimmed area in the mask layout to be split corresponds to the distribution of the trimmed pattern in the third sub-mask layout.
[0080] It should also be noted that in the mask layout to be split, a first pattern and a second pattern are set on both sides of the trimming area. After the first pattern is merged to form a first merged pattern and the second pattern is merged to form a second merged pattern, the first merged pattern and the second merged pattern are used as photomask patterns to form a pattern on the wafer. However, the pattern distribution is inconsistent with the pattern distribution on the mask layout to be split. Therefore, by setting trimming areas in the regions of the first pattern that are spaced apart in the first direction and the regions of the second pattern that are spaced apart in the second direction, it is beneficial to provide trimmed patterns in the third sub-mask layout according to the distribution of the trimming areas. This makes the distribution of the trimmed patterns consistent with the distribution of the trimming areas, so that the trimmed patterns can be used as photomask patterns to re-etch the pattern already formed on the wafer, thereby making the pattern formed on the wafer consistent with the pattern on the mask layout to be split, and improving the accuracy of pattern transfer.
[0081] Specifically, compared to the approach of forming a pattern on a wafer using a single photolithography process on a mask pattern to be split, this embodiment uses a splitting module 201 to split the mask pattern to be split into a first sub-mask pattern and a second sub-mask pattern. In the subsequent semiconductor structure formation process, multiple photolithography processes are performed using the first sub-mask pattern and the second sub-mask pattern, which increases the exposure process window in the photolithography process and improves the accuracy of pattern transfer in the photolithography process.
[0082] As an example, the mask layout to be split is divided into a first sub-mask layout and a second sub-mask layout according to the layout splitting limit rule.
[0083] In this embodiment, the layout splitting restriction rules include the minimum spacing requirement for adjacent graphics on the same mask layout.
[0084] It should be noted that the first merging module 202 merges the first patterns on the first sub-mask layout, making the size of the first merged pattern on the first sub-mask layout larger along the first direction. In the subsequent process of using the first merged pattern as the first photomask pattern to form a pattern on the wafer, it can increase the process window for forming the pattern on the wafer. At the same time, it merges the second patterns on the second sub-mask layout, making the size of the second merged pattern on the second sub-mask layout larger along the second direction. In the subsequent process of using the second merged pattern as the second photomask pattern to form a pattern on the wafer, it can also increase the process window for forming the pattern on the wafer, improve the pattern transfer accuracy, and reduce the process difficulty.
[0085] In this embodiment, the first merging module 202 includes: a first extension unit, used to extend the end of the first graphic along the first direction until the ends of adjacent first graphics contact each other, and combine multiple contacting first graphics into a first merged graphic.
[0086] It should be noted that the second merging module 203 forms a second merged pattern by having multiple second patterns come into contact with each other in the second direction, and uses the second merged pattern as the second photomask pattern. This makes the size of the second merged pattern on the second sub-mask pattern also larger in the second direction. In the subsequent process of forming a pattern on the wafer using the second merged pattern as the second photomask pattern, the process window for forming the pattern on the wafer can be increased, the pattern transfer accuracy can be improved, and the process difficulty can be reduced.
[0087] As an example, the second merging module 203 includes: a second extension unit, used to extend the outlines of the second graphics on both sides of the first graphic along a second direction until the outlines of adjacent second graphics are in contact, and to combine the contacting second graphics into a second merged graphic.
[0088] Specifically, after the first and second merged patterns are formed on the wafer as photomask patterns, the pattern distribution is inconsistent with the pattern distribution on the mask layout to be split. Therefore, by setting trimming areas in the regions of the first pattern that are spaced apart in the first direction and the regions of the second pattern that are spaced apart in the second direction, the module 204 can subsequently provide trimmed patterns in the third sub-mask layout according to the distribution of the trimming areas, so that the distribution of the trimmed patterns is consistent with the distribution of the trimming areas. The trimmed patterns, as the third photomask patterns, can re-etch the pattern already formed on the wafer, thereby making the pattern formed on the wafer consistent with the pattern on the mask layout to be split, and improving the accuracy of pattern transfer.
[0089] As an example, the trimmed graphic includes an opening.
[0090] Specifically, during the etching process of the trimmed pattern as the third photomask pattern on the pattern already formed on the wafer, the opening will expose part of the metal line isolation layer. The exposed metal line isolation layer is removed by the etching process, so that the pattern formed on the wafer is consistent with the pattern on the mask layout to be split, thereby increasing the process window and improving the accuracy of pattern transfer.
[0091] It should be noted that there is no restriction on the operating order of the first merging module 202, the second merging module 203, and the providing module 204.
[0092] This invention also provides a device that can implement the layout splitting method provided in this invention through the above-described optical proximity correction method in the form of a loaded program. An optional hardware structure of the terminal device provided in this invention can be as follows: Figure 10 As shown, it includes: at least one processor 01, at least one communication interface 02, at least one memory 03, and at least one communication bus 04.
[0093] In this embodiment, the number of processor 01, communication interface 02, memory 03, and communication bus 04 is at least one, and processor 01, communication interface 02, and memory 03 communicate with each other through communication bus 04. Communication interface 02 can be an interface of a communication module for network communication, such as the interface of a GSM module. Processor 01 may be a central processing unit (CPU), an application-specific integrated circuit (ASIC), or one or more integrated circuits configured to implement embodiments of the present invention. Memory 03 may include high-speed RAM and may also include non-volatile memory (NVM), such as at least one disk storage device. Memory 03 stores one or more computer instructions, which are executed by processor 01 to implement the layout splitting method provided in this embodiment of the present invention.
[0094] It should be noted that the aforementioned terminal device may also include other devices (not shown) that may not be essential to understanding the content disclosed in the embodiments of the present invention; given that these other devices may not be essential for understanding the content disclosed in the embodiments of the present invention, the embodiments of the present invention will not describe them one by one.
[0095] This invention also provides a storage medium storing one or more computer instructions for implementing the layout splitting method provided in this invention.
[0096] Embodiments of the present invention can be implemented by various means, such as hardware, firmware, software, or combinations thereof. In a hardware configuration, the method according to an exemplary embodiment of the present invention can be implemented by one or more application-specific integrated circuits (ASICs), digital signal processors (DSPs), digital signal processing devices (DSPDs), programmable logic devices (PLDs), field-programmable gate arrays (FPGAs), processors, controllers, microcontrollers, microprocessors, etc. In a firmware or software configuration, embodiments of the present invention can be implemented in the form of modules, processes, functions, etc. Software code can be stored in memory units and executed by a processor. The memory units are located inside or outside the processor and can send data to and receive data from the processor via various known means.
[0097] Accordingly, embodiments of the present invention also provide a computer program product, including computer instructions, which, when executed by a processor, are used to implement the layout splitting method provided in embodiments of the present invention.
[0098] While the present invention has been disclosed above, it is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.
Claims
1. A method for partitioning a map, characterized in that, include: Obtain a mask layout to be split, wherein the mask layout to be split contains multiple graphics, including first graphics arranged in parallel along a first direction and second graphics arranged in parallel along a second direction, wherein the first direction is perpendicular to the second direction, and the areas of the first graphics that are spaced apart in the first direction and the areas of the second graphics that are spaced apart in the second direction are all trimming areas. The mask layout to be split is divided into a first sub-mask layout and a second sub-mask layout, such that the first pattern is distributed on the first sub-mask layout and the second pattern is distributed on the second sub-mask layout. A first merging process is performed on the first pattern in the first sub-mask layout, so that multiple first patterns contact each other in the first direction to form a first merged pattern, and the first merged pattern is used as the first photomask pattern. A second merging process is performed on the second pattern in the second sub-mask layout, so that multiple second patterns contact each other in the second direction to form a second merged pattern, and the second merged pattern is used as the second photomask pattern; A third sub-mask layout is provided, the third sub-mask layout including multiple trimmed patterns, the distribution of the multiple trimmed patterns in the third sub-mask layout corresponding to the distribution of the trimmed areas, and the trimmed patterns are used as the third photomask pattern.
2. The layout splitting method as described in claim 1, characterized in that, According to the layout splitting limit rules, the mask layout to be split is split into a first sub-mask layout and a second sub-mask layout.
3. The layout splitting method as described in claim 2, characterized in that, The layout splitting restriction rules include the minimum spacing requirement for adjacent graphics on the same mask layout.
4. The layout splitting method as described in claim 1, characterized in that, The step of performing a first merging process on the first graphic in the first sub-mask layout includes: extending the end of the first graphic along the first direction until the ends of adjacent first graphics contact each other, and combining multiple contacting first graphics into a first merged graphic.
5. The layout splitting method as described in claim 1, characterized in that, In the step of obtaining the mask layout to be split, the second graphic is distributed in the regions on both sides of the first graphic; The step of performing a second merging process on the second graphic in the second sub-mask layout includes: extending the outlines of the second graphics on both sides of the first graphic along a second direction until the outlines of adjacent second graphics are in contact, and combining the contacting second graphics into a second merged graphic.
6. The layout splitting method as described in claim 1, characterized in that, The first pattern includes a metal wire partition layer; The second pattern includes a metal wire partition layer.
7. The layout splitting method as described in claim 1, characterized in that, The trimmed pattern includes an opening.
8. A layout splitting system, characterized in that, include: The acquisition module is used to acquire the mask layout to be split, wherein the mask layout to be split contains multiple graphics, including first graphics arranged in parallel along a first direction and second graphics arranged in parallel along a second direction, wherein the first direction is perpendicular to the second direction, and the areas of the first graphics that are spaced apart in the first direction and the areas of the second graphics that are spaced apart in the second direction are all trimming areas. The splitting module is used to split the mask layout to be split into a first sub-mask layout and a second sub-mask layout, such that the first graphic is distributed on the first sub-mask layout and the second graphic is distributed on the second sub-mask layout. The first merging module is used to perform a first merging process on the first pattern in the first sub-mask layout, so that multiple first patterns contact each other in the first direction to form a first merged pattern, and use the first merged pattern as the first photomask pattern. The second merging module is used to perform a second merging process on the second pattern in the second sub-mask layout, so that multiple second patterns contact each other in the second direction to form a second merged pattern, and use the second merged pattern as the second photomask pattern. A module is provided for providing a third sub-mask layout, the sub-mask layout including multiple trimmed patterns, the distribution of the multiple trimmed patterns in the third sub-mask layout corresponding to the distribution of the trimmed areas, and using the trimmed patterns as the third photomask pattern.
9. The layout splitting system as described in claim 8, characterized in that, The first merging module includes: a first extension unit, used to extend the ends of the first graphic along the first direction until the ends of adjacent first graphics contact each other, and to combine multiple contacting first graphics into a first merged graphic.
10. The layout splitting system as described in claim 8, characterized in that, In the step of obtaining the mask layout to be split, the second graphic is distributed in the regions on both sides of the first graphic; The second merging module includes: a second extension unit, used to extend the outlines of the second graphics on both sides of the first graphic along a second direction until the outlines of adjacent second graphics are in contact, and to combine the contacting second graphics into a second merged graphic.
11. A device, characterized in that, It includes at least one memory and at least one processor, the memory storing one or more computer instructions, wherein the one or more computer instructions are executed by the processor to implement the layout splitting method as described in any one of claims 1-7.
12. A storage medium, characterized in that, The storage medium stores one or more computer instructions, which are used to implement the layout splitting method as described in any one of claims 1-7.
13. A computer program product, characterized in that, It includes computer instructions, which, when executed by a processor, are used to implement the layout splitting method as described in any one of claims 1 to 7.