Tight coupling system architecture and method for accelerating mixed quantum classical calculation

Abstract

The invention discloses a tight coupling system architecture and method for accelerating mixed quantum classical computation, and the system architecture comprises a hardware architecture which carries out the tight integration of a main processor and a quantum accelerator, and a software architecture which carries out the expansion of an instruction set architecture of the main processor. A uniform memory space shared by a main processor and a quantum accelerator is deployed on a hardware architecture, an efficient quantum controller and a multi-stage hardware pipeline are realized, an extended instruction set is constructed on a software architecture, and a dynamic incremental compiling mechanism, a fine-grained memory consistency synchronization mechanism and an efficient quantum-classical scheduling mechanism are realized. Through software and hardware collaborative design, the execution efficiency of the mixed quantum classical algorithm can be effectively improved.

Description

Technical Field

[0001] This invention belongs to the field of quantum computing technology, specifically relating to a tightly coupled system architecture and method for accelerating hybrid quantum-classical computing. Background Technology

[0002] Hybrid quantum classical algorithms, as a highly promising research direction in the current field of quantum computing, are widely regarded as an important way to tap the computational potential of near-term noisy intermediate-scale quantum (NISQ) devices. However, the hardware architecture of existing quantum computing systems severely limits the execution efficiency of these algorithms, becoming a key factor hindering the further development of hybrid quantum classical algorithms.

[0003] Current mainstream quantum computing systems generally adopt a decoupled architecture. This architecture typically includes a classical host processor, a quantum accelerator, and an FPGA controller to connect the two. Its workflow is as follows: Figure 1 As shown: the main processor handles classical computational tasks such as parameter calculation and cost function evaluation, while the quantum accelerator focuses on performing quantum computing tasks. The main processor transmits the compiled quantum program binary file to the FPGA controller via gigabit Ethernet or similar methods. After receiving the instructions, the FPGA controller parses them and then generates pulse signals to control the evolution of the superconducting qubits through a pulse generation unit (PGU). The signals are then sent to the quantum chip after passing through a digital-to-analog converter (DAC). After the quantum chip completes the calculation, its measurement results are acquired by an analog-to-digital converter (ADC) and returned to the main processor for further processing.

[0004] However, this decoupled architecture has the following serious drawbacks: A significant communication bottleneck exists: communication between the main processor and the quantum accelerator relies on a low-speed, network-based connection (such as Ethernet or USB), resulting in unacceptable transmission delays at the millisecond level (1ms-10ms).

[0005] Inefficient quantum-classical interaction: The architecture lacks a dedicated hardware interface and efficient instruction set designed for seamless interaction between the quantum and classical components. This results in significant runtime overhead; analysis shows that communication, classical computation, and repetitive compilation overhead account for over 90% of the total runtime, while the actual quantum execution time is minimal (e.g., in the 64-qubit VQE algorithm, quantum computation accounts for only 7.9%).

[0006] Software optimization is limited: Existing instruction set architectures (ISAs) are typically dedicated instruction sets designed for quantum chips, without considering interaction with the main processor. This results in very long compiled instruction sequences, and due to the lack of efficient data exchange mechanisms, the entire quantum program must be recompiled from scratch in each iteration of the hybrid algorithm, incurring compilation overheads of 1ms to 100ms.

[0007] Fixed execution mode: Classical computing tasks and quantum computing tasks must be executed sequentially and cannot be overlapped, which further reduces the overall execution efficiency of the system.

[0008] Therefore, existing technologies suffer from problems such as high communication latency, large interaction overhead, compilation redundancy, and low execution efficiency when executing hybrid quantum classical algorithms, which urgently require new hardware architectures and optimization strategies to solve. Summary of the Invention

[0009] In view of the above, the purpose of this invention is to provide a tightly coupled system architecture and method for accelerating hybrid quantum classical computing. Based on a hardware architecture that tightly integrates classical processors and quantum accelerators, a corresponding instruction set, and software optimization methods, this invention significantly improves the end-to-end execution speed of hybrid quantum classical computing by eliminating communication bottlenecks and achieving fine-grained hardware and software interaction and optimization.

[0010] To achieve the above-mentioned objectives, the present invention provides the following technical solution: In a first aspect, embodiments of the present invention provide a tightly coupled system architecture for accelerating hybrid quantum classical computing, comprising: The hardware architecture that tightly integrates the main processor and the quantum accelerator includes: a unified memory hierarchy: providing a unified memory space shared by the main processor and the quantum accelerator, containing a quantum controller cache at the same level as the main processor's L1 cache; the quantum accelerator includes a quantum controller, computing units, and a quantum chip; an efficient quantum controller: managing the unified memory hierarchy and internal and external communication through the quantum controller, providing dedicated data paths and hardware interfaces to connect the main processor and the quantum controller cache; and a multi-stage hardware pipeline: efficiently generating quantum control pulses in the computing units through a multi-stage hardware pipeline for the quantum chip to perform quantum measurements. The software architecture that extends the instruction set architecture of the main processor includes: Extended instruction set: Adding data communication instructions and computation instructions to extend the original instruction set to support efficient interaction between the main processor and the quantum controller cache; Compiler execution of fine-grained memory consistency synchronization mechanism: Deploying lightweight memory barriers within the quantum controller to support low-latency querying of data synchronization status by the main processor; Compiler execution of efficient quantum-classical scheduling mechanism: Based on the fine-grained memory consistency synchronization mechanism, using a batch transmission strategy to package and transmit quantum measurement results.

[0011] Preferably, the quantum controller cache is organized into a scalable two-dimensional space. The first dimension is divided into multiple functional segments, including at least a .program segment for storing quantum programs, a .pulse segment for storing control pulses, a .measure segment for storing measurement results, a .regfile segment for storing frequently updated parameters, and a .slt segment for storing the jump lookup table mapping gate parameters to pulse addresses. The second dimension divides each functional segment into blocks that correspond one-to-one with a quantum bit, and each block has an independent quantum address.

[0012] Preferably, the quantum controller cache includes a public cache and a private cache. The public cache stores the .program segment, .measure segment, and .regfile segment, while the private cache stores the .pulse segment and .slt segment.

[0013] Preferably, the registers in the main processor interact with the public cache of the quantum controller through the RoCC interface, the L2 cache in the main processor interacts with the public cache and private cache of the quantum controller through the quantum controller interface, and the quantum chip interacts with the public cache and private cache of the quantum controller through the analog-to-digital interface.

[0014] Preferably, the quantum controller internally designs a rearranged buffer queue to handle out-of-order bus responses, a write buffer queue to match the data bit widths of different components, and uses memory barriers to ensure cache consistency.

[0015] Preferably, the multi-stage hardware pipeline includes: Phase 1: Fetch instructions from the .program segment based on the program counter; Phase 2: Decode the instruction. If the reg_flag bit in the instruction is 1, the parameter is obtained from the ..regfile segment. Then, the instruction type and data field are used as an index to query the skip lookup table in the .slt segment. If the skip lookup table is matched, it means that the pulse corresponding to the parameter already exists. The quantum address is directly obtained and updated in the .program segment, and the subsequent pipeline stages are terminated. If the skip lookup table is not matched, a new quantum address will be allocated according to the least-used strategy and passed to the next stage. Phase 3: If the jump lookup table is not found, the parameters are sent to an idle pulse generation unit for calculation, and the parallel scheduling of multiple pulse generation units is achieved through a priority encoder and arbitrator. Stage 4: Write the pulse data calculated by the pulse generation unit into the .pulse segment according to the new quantum address.

[0016] Preferably, the data communication instructions include: a q_update instruction for enabling communication between the registers in the main processor and the public cache of the quantum controller; a q_set instruction for enabling communication between the L2 cache in the main processor and the public cache and private cache of the quantum controller, respectively; and a q_acquire instruction for enabling communication between the public cache and private cache of the quantum controller and the L2 cache in the main processor, respectively. The computational instructions include: a q_gen instruction for controlling the waveform generated by the quantum control pulse, and a q_run instruction for enabling the quantum chip to communicate with the public and private caches of the quantum controller and execute the quantum program.

[0017] Preferably, the software architecture further includes a dynamic incremental compilation mechanism, which uses the q_update instruction to update only the parameters that change in the quantum controller cache during the hybrid algorithm iteration process, without recompiling and transmitting the entire quantum program.

[0018] Secondly, embodiments of the present invention also provide a method for accelerating hybrid quantum classical computing, implemented using the aforementioned tightly coupled system architecture for accelerating hybrid quantum classical computing, comprising the following steps: The quantum-classical hybrid algorithm is compiled into an extended instruction set by a compiler. Data is executed through the extended instruction set. During execution, the instructions and parameters of the computation task are loaded into a unified memory space. Classical and quantum computing tasks are retrieved and executed separately from a unified memory space using a main processor and a quantum accelerator. The computing unit executes a multi-level hardware pipeline to generate quantum control pulses based on quantum programs and parameters in the quantum controller cache. The quantum control pulses are then transmitted to the quantum chip to perform quantum measurements to accelerate quantum computing. Based on an efficient quantum-classical scheduling mechanism, the quantum measurement results executed by the quantum chip are written into the quantum controller cache. Before subsequent tasks access the shared data, a fine-grained memory consistency synchronization mechanism is used to query the state of the lightweight memory barrier in the quantum controller with low latency and non-blocking, confirming that the data synchronization is complete.

[0019] Thirdly, embodiments of the present invention also provide an electronic device, including a memory and one or more processors, wherein the memory is used to store a computer program, and the processor is used to implement the above-described method for accelerating hybrid quantum classical computing when the computer program is executed.

[0020] Compared with the prior art, the beneficial effects of the present invention include at least the following: (1) Significantly improved end-to-end performance: Compared with the current best decoupled architecture, the present invention can achieve an end-to-end performance speedup of up to 14.9 times when executing hybrid quantum classical algorithms.

[0021] (2) Significant reduction in classical execution overhead: This invention greatly reduces communication latency, compilation overhead, and classical computation time. Communication latency is reduced from the millisecond (ms) level to the nanosecond (ns) level, and redundant compilation overhead is almost eliminated. This results in a total execution time acceleration of up to 441.5 times for the classical part, with quantum execution time accounting for nearly 90% of the total time, proving that classical overhead has been minimized.

[0022] (3) Improved utilization of computing resources: Through multi-stage hardware pipelines and the skip lookup table (SLT) mechanism, the pulse generation speed can be increased by up to 647.9 times, and the computing requirements are reduced by more than 98%. Through fine-grained synchronization and batch transfer scheduling, the parallelism and bus bandwidth utilization of classical main processors and quantum accelerators are greatly improved.

[0023] (4) Good scalability: The architecture of this invention is flexible. By expanding the quantum controller cache and utilizing chip pins, it can support a larger number of qubits and still maintain high efficiency after expansion. Attached Figure Description

[0024] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0025] Figure 1 This is an example diagram of an existing decoupled hardware architecture running a hybrid quantum classical algorithm; Figure 2 This is a schematic diagram of a tightly coupled system architecture for accelerating hybrid quantum classical computing provided in an embodiment of the present invention; Figure 3 This is a schematic diagram of the unified memory hierarchy and quantum controller provided in an embodiment of the present invention; Figure 4 This is a detailed design schematic diagram of the quantum controller cache interface provided in an embodiment of the present invention; Figure 5 This is a flowchart of the four-stage hardware pipeline for pulse calculation provided in an embodiment of the present invention; Figure 6 This is a flowchart of the skip lookup table (SLT) provided in an embodiment of the present invention; Figure 7This is a timing comparison diagram of different synchronization methods provided in the embodiments of the present invention; Figure 8 This is a flowchart illustrating a method for accelerating hybrid quantum classical computing provided in an embodiment of the present invention. Detailed Implementation

[0026] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and do not limit the scope of protection of this invention.

[0027] The inventive concept of this invention is as follows: Addressing the problems of high communication latency, large classical computational overhead, redundant compilation, and low hardware-software coordination efficiency in existing decoupled quantum computing architectures when executing hybrid quantum-classical algorithms, this invention provides a tightly coupled system architecture and method for accelerating hybrid quantum-classical computing. It constructs a hardware architecture including a unified memory hierarchy and a high-efficiency quantum controller, achieving nanosecond-level low-latency communication and data sharing between the main processor and the quantum accelerator. By deploying a multi-stage hardware pipeline in the computing unit, its core introduces a skip lookup table mechanism, significantly reducing redundant pulse generation overhead by reusing already computed pulse addresses. Furthermore, by expanding the instruction set and introducing dynamic incremental compilation, fine-grained memory consistency synchronization, and a high-efficiency quantum-classical scheduling mechanism, deep hardware-software coordination is achieved, thereby systematically and significantly reducing communication latency, classical computational overhead, compilation overhead, and synchronization waiting time during the hybrid algorithm iteration process, and improving the execution efficiency of hybrid quantum-classical computing.

[0028] like Figure 2 As shown, the embodiment provides a tightly coupled system architecture for accelerating hybrid quantum classical computing, including: a hardware architecture and a software architecture.

[0029] 1. Hardware architecture: Its core is the tight integration of the main processor (RISC-V chip) and the quantum accelerator.

[0030] (1) Unified memory hierarchy: such as Figure 2 As shown, this embodiment of the invention designs a unified memory hierarchy shared by the main processor and the quantum accelerator, thereby seamlessly integrating the main processor and the quantum accelerator and achieving efficient data sharing. Specifically, a 5.66MB quantum controller cache (taking 64 qubits as an example) is designed, which is physically implemented as SRAM and is at the same level as the main processor's L1 cache to ensure high-speed access and provide high-bandwidth, low-latency data communication.

[0031] A quantum accelerator comprises a quantum controller, computing units, and quantum chips. The quantum controller cache is organized into a scalable two-dimensional space. The first dimension is divided into five functional segments: .program (stores the quantum program), .pulse (stores control pulses), .measure (stores measurement results), ..regfile (stores frequently updated parameters), and .slt (a jump lookup table). The second dimension divides each functional segment into chunks corresponding one-to-one with a qubit. Each chunk has an independent quantum address (QAddress), thus eliminating the need to explicitly encode qubit indices in the instructions and reducing program size.

[0032] For example, the .program segment used to store quantum programs is 520KB in size, divided into 64 blocks, each corresponding to a qubit, with addresses starting from 0x0. Each qubit has 1024 entries. Each entry contains the type, data, and a reg_flag bit. If reg_flag is set to 1, it indicates that the gate's parameters are variable, and its data field stores the index in the ..regfile segment, rather than the direct parameter value. This design provides hardware support for subsequent incremental compilation.

[0033] (2) High-efficiency quantum controllers: such as Figure 3 and Figure 4 As shown, this embodiment of the invention designs a high-performance quantum controller to manage a unified memory hierarchy and internal and external communication.

[0034] like Figure 3 As shown, the quantum controller cache includes a public cache and a private cache. The public cache stores the .program, .measure, and .regfile segments, while the private cache stores the .pulse and .slt segments. Simultaneously, the quantum controller provides multiple dedicated data paths and hardware interfaces (such as the RoCC interface and the Tilelink bus interface) to connect the main processor and the quantum controller cache, achieving nanosecond-level (10ns-100ns) low-latency access. Figure 3 As shown, the quantum controller provides four data paths for interaction with the main processor. Path ① connects the registers in the main processor core 1 and the quantum controller's public cache via the RoCC interface, used for transmitting small amounts of high-frequency data (such as updating a single parameter), with a latency of only one cycle. Paths ② and ③ connect the L2 cache in the main processor and the public and private caches of the quantum controller via a customized quantum controller interface, used for transmitting batch data such as quantum programs. Path ④ connects the quantum chip and the public and private caches of the quantum controller via an analog-to-digital interface, used for real-time bidirectional transmission of computational parameters and quantum measurement data.

[0035] In addition, such as Figure 4 The diagram illustrates the key interface design within the quantum controller used to connect the main processor's L2 cache and the quantum controller cache (including public and private parts). A reorder buffer queue (RBQ) is designed inside the quantum controller to handle out-of-order bus responses, and a write buffer queue (WBQ) is designed to match the data bit widths of different components. A memory barrier ensures cache consistency. The design goal of this interface is to address the three major challenges of achieving efficient and consistent batch data communication in a tightly coupled architecture: handling out-of-order bus responses, matching different data bit widths, and ensuring memory consistency.

[0036] The specific solutions and mechanisms are as follows: (i) Resolving out-of-order bus responses: Reordering buffer queues (RBQ).

[0037] Problem: The system bus in this invention uses a TileLink interface, which allows responses to be returned out of order after a request is sent (Out-of-Order Response). Directly processing these out-of-order responses will lead to data errors.

[0038] Solutions and mechanisms: like Figure 4 As shown, the interface includes a Reordered Buffer Queue (RBQ). When the quantum controller issues a read request (Req) to the system bus, it attaches a unique tag to the request, such as... Figure 4 The RBQ area is shown in the diagram. When the system bus returns response data (Resp), this data carries a corresponding tag. The response data is first decoded by the decoder according to the tag and stored in the corresponding position of the 32 entries in the RBQ (represented by #1, #2, ..., #n in the diagram). The correct output order is determined by querying the tag queue, and then the data is retrieved and output in the original request order through a 32-to-1 MUX (32-1 multiplexer). In this way, even if the bus response is out of order, the RBQ can ensure that the data is correctly reordered.

[0039] (ii) Resolve data bit width mismatch: Write Buffer Queue (WBQ).

[0040] Problem: The bit width of the system bus (e.g., 256 bits) often does not match the bit width of data entries in the quantum controller cache (e.g., 32 bits for entries in the common cache .program segment). Direct writes can lead to low bus bandwidth utilization or require complex control logic.

[0041] Solutions and mechanisms: like Figure 4 As shown, the interface employs a Write Buffer Queue (WBQ) along the path to the public cache. This WBQ consists of eight independent, 32-bit wide parallel queues (represented as #1, #2, ..., #8 in the diagram). When a write request arrives, the requested data length signal determines which queues the data will be stored in. Subsequently, an index signal (SIndex) controls an 8-to-1 MUX to select the correct data from these eight queues and write it to the corresponding address in the public cache. This design allows write requests of different lengths to be processed and mapped efficiently, resolving the bit-width mismatch problem.

[0042] (iii) Ensure memory consistency: memory barriers.

[0043] Problem: When the main processor and quantum controller concurrently read and write to the shared memory area, data consistency must be guaranteed to prevent the main processor from reading outdated or incompletely written data.

[0044] Solutions and mechanisms: like Figure 4 As shown, the interface includes a memory barrier module. When the quantum controller issues a write request (the M_XWR signal in the diagram) to update main memory, the state of the memory barrier is updated synchronously. This barrier records which addresses have had write requests sent to the system bus, indicating that data at those addresses is being synchronized. The main processor can query the state of this barrier non-blockingly through a low-latency RoCC interface to determine whether the target data has been transferred and is available, without using the FENCE instruction, which would cause pipeline stalls. This mechanism is key to achieving fine-grained, high-efficiency synchronization.

[0045] Other key components: Address Translator: Figure 4 The diagram shows that this module is connected to a private cache and is responsible for converting the "Host Address" used by the system bus to the "Quantum Address (QAddress)" used inside the quantum controller, ensuring the correct mapping between different address spaces.

[0046] MUX (Multi-way Arbitrator): In addition to the MUX mentioned above, Figure 4 There is also a MUX used to select whether to access the public cache or the private cache during read and write operations.

[0047] (3) Multi-level hardware pipeline: such as Figure 5As shown, to efficiently generate control pulses, this embodiment of the invention implements a four-stage hardware pipeline to maximize computational parallelism.

[0048] Its workflow is divided into stages as follows: Phase 1: Instruction fetching.

[0049] Function: This stage is responsible for retrieving the quantum gate instructions to be executed from the .program segment cached by the quantum controller.

[0050] mechanism: A program counter (PC) provides the address of an instruction. This address is sent to the .program file, which retrieves a complete 65-bit instruction entry from that address.

[0051] like Figure 5 As shown in the enlarged diagram of the instruction format, this entry contains multiple fields: type (gate type, such as RY), R (flag indicating whether the parameter is in the .regfile), data (gate parameter or .regfile index), status (indicating whether QAddress is valid), and QAddress (corresponding pulse buffer address). After instruction fetching is complete, the PC updates to the address of the next instruction.

[0052] Phase 2: Decoding and Address Lookup.

[0053] Function: This stage decodes the retrieved instructions and executes the core optimization step of the invention—querying the Skip Lookup Table (SLT) to skip redundant calculations.

[0054] mechanism: Parameter retrieval: The pipeline first checks the R flag in the instruction ( Figure 5 (The 60th position is in the middle). If R is 1, it indicates that this is a variable parameter, and the data field will be used as an index to obtain the actual gate parameter from the .regfile; otherwise, the data field itself is the gate parameter.

[0055] QAddress validity check: Next, check the status flags ( Figure 5 (The middle part is bit 32). If the status is 1, it indicates that the QAddress of the instruction is valid, meaning that its corresponding pulse has been generated or mapped. In this case, the data will be sent directly to stage 4 for output preparation. If the status is 0, it indicates that the QAddress is invalid and needs to be looked up or calculated.

[0056] SLT Query: When the state is invalid, the instruction type and data fields are sent to the SLT for querying.

[0057] Hit: If a valid mapping for the parameter exists in the SLT, the SLT returns a cached QAddress. This QAddress is written back to the program index buffer in stage 1 to update the instruction, making its state valid for future direct use. Simultaneously, the pipeline skips the computation stage.

[0058] Hit (!hit): If the parameter is not found in the SLT, it indicates a new pulse that needs to be calculated. In this case, the instruction parameter and the new QAddress assigned by the SLT are passed to stage 3 for actual pulse calculation.

[0059] Decode the instruction. If the reg_flag bit in the instruction is 1, the parameter is obtained from the .regfile segment. Then, the instruction type and data field are used as an index to query the skip lookup table in the .slt segment. If the skip lookup table matches, it means that the pulse corresponding to the parameter already exists. The quantum address (QAddress) is directly obtained and updated in the .program segment, and the subsequent pipeline stages are terminated. If the skip lookup table does not match, a new QAddress is allocated according to the least-used strategy and passed to the next stage.

[0060] Phase 3: Pulse generation.

[0061] Function: This stage utilizes multiple pulse generation units (PGUs) to perform actual pulse waveform calculations in parallel.

[0062] mechanism: The parameters passed from stage 2 first enter a decoder.

[0063] A priority encoder monitors the busy status of all PGUs (PGU #0 to PGU #n) in real time and selects an idle PGU to handle the computation task.

[0064] If all PGUs are busy, the encoder will issue a stall signal, pausing phase 1 and phase 2 until a PGU is released.

[0065] The computation results of all PGUs are fed into an arbiter, which is responsible for handling data contention and selecting a valid output signal from all parallel PGUs to pass to the next stage.

[0066] Phase 4: Write back.

[0067] Function: This stage writes the pulse data calculated in stage 3 back to the specified location in the .pulse segment cached by the quantum controller.

[0068] mechanism: The pulse data output from the arbitrator and its associated QAddress are fed into the decoder at this stage. The decoder uses the QAddress as the address to accurately write the 640-bit wide pulse data into the corresponding pulse buffer (waveform Pulse #0 to waveform Pulse #64) for subsequent transmission to the quantum chip.

[0069] like Figure 6 As shown, the core optimization of the pipeline lies in the second-level skip lookup table (SLT), and its workflow is as follows: Figure 6 As shown. The fundamental purpose of SLT is to avoid redundant and repetitive computations on pulses with the same parameters by caching the mapping from gating parameters to their pulse addresses (QAddress), which is crucial for iterative hybrid quantum classical algorithms. Its specific workflow can be divided into the following four steps: Step 1: Query and compare.

[0070] Function: Determines whether the quantum gate parameters being processed have been calculated recently.

[0071] mechanism: When pipeline stage 2 needs to process a quantum gate instruction, a unique input tag is generated based on the gate's operation type and parameter value (e.g., RY(π / 2)). This intag is used for lookup in the SLT, comparing it with the Tag field of each item in the table.

[0072] Hit: If a matching tag is found and its valid bit V is 1, it is considered a "hit". This means that the pulse corresponding to the parameter has been calculated and its address is stored in the SLT. At this time, the system will perform two operations: (1) increment the usage count of the entry by one for subsequent replacement decisions; (2) immediately return the cached QAddress (QAddr.), and the pipeline will directly use this address, skipping the subsequent pulse generation stage (stage 3), thus successfully avoiding redundant calculations.

[0073] Miss: If no valid matching entry is found in the SLT, it is considered a "miss". This means that there is no record for this parameter in the local cache, and the replacement and query process needs to be started.

[0074] Step 2: Replacement strategy.

[0075] Function: When a "miss" occurs, determine which entry in the SLT will be replaced by the new entry.

[0076] mechanism: This invention employs a least-count (LC) replacement strategy. This strategy first searches for invalid entries (i.e., entries with V=0) in the SLT.

[0077] If an invalid entry exists, it is replaced first, because this avoids writing the old data back to memory.

[0078] If all entries are valid, the entry with the smallest Count value will be selected for eviction.

[0079] When an entry is evicted, its tag and QAddress information are written back to a dedicated, larger storage area, QSpace, in main memory for long-term storage.

[0080] Step 3: Memory operations and address allocation.

[0081] Function: After determining the replacement location, look up or assign a QAddress to the new entry from the main memory QSpace.

[0082] mechanism: The system will use intag to perform a lookup in QSpace to confirm whether the pulse for that parameter was calculated earlier (i.e. it was in SLT but was later expelled to QSpace).

[0083] If a valid record is found in QSpace, the system will directly retrieve its QAddress and prepare to load it into SLT.

[0084] If there is no record in the QSpace (i.e., the corresponding entry in the QSpace is also invalid), it means that this parameter's pulse is appearing for the first time. At this time, the system will notify the Allocator module, which will generate a brand new, unique QAddress. This new address will be sent along with the parameter to pipeline stage 3 for actual pulse calculation.

[0085] Step 4: Update SLT.

[0086] Function: Write the new parameter mapping relationship to SLT to complete the cache update.

[0087] mechanism: Whether the address is retrieved from QSpace or newly generated by Allocator, it will be written along with the intag to the SLT entry selected in step ②.

[0088] At the same time, the valid bit V of the entry is set to 1, and the Count is reset. This concludes a complete query-miss-update process.

[0089] In summary, SLT (Speed ​​Local Cache) employs a two-level caching mechanism—a Fast Local Cache (SLT) and a large-capacity backing store (QSpace)—combined with an efficient LC (Limited-Local) replacement strategy. This ensures that for any given gate parameter, the pulse waveform calculation is performed only once when it first appears. Subsequent requests for the same parameter will be skipped by SLT hits, significantly reducing computational redundancy in iterative algorithms.

[0090] 2. Software architecture: Its core is to extend the instruction set architecture of the main processor (RISC-V chip).

[0091] (1) Extended instruction set: As shown in Table 1, new data communication instructions and computation instructions are added to extend the original instruction set to support efficient interaction between the main processor and the quantum controller cache. During compilation, the hybrid algorithm compiles normally for fixed quantum gates; for parameterized quantum gates that require iterative optimization, the reg_flag bit is set to 1 in the .program cache, and its data field is set to an index in ..regfile.

[0092] Table 1 Extended Instruction Set The data communication instructions include: the `q_update` instruction for communication between the registers in the main processor and the public cache of the quantum controller; the `q_set` instruction for communication between the L2 cache in the main processor and the public and private caches of the quantum controller, respectively; and the `q_acquire` instruction for communication between the public and private caches of the quantum controller and the L2 cache in the main processor, respectively. These communication instructions, such as `q_update`, allow the main processor to directly and efficiently read and write specific data in the quantum controller's caches, such as updating individual gate parameters.

[0093] The computational instructions include: the q_gen instruction for controlling the waveform generation of quantum control pulses, and the q_run instruction for enabling the quantum chip to communicate with the public and private caches of the quantum controller and execute quantum programs.

[0094] During algorithm execution, the initialized quantum program is loaded from main memory into the .program segment of the quantum controller cache once via the q_set instruction. In each iteration, after the classical optimizer calculates the new parameters on the main processor, it does not recompile the entire program. Instead, it directly writes the new parameters into the corresponding entries in the .regfile segment via the q_update instruction. Subsequently, the q_gen instruction triggers the hardware pipeline to generate pulses (at this time, SLT skips the calculation of unchanged parameters), and then the q_run instruction runs the quantum program.

[0095] (2) Dynamic incremental compilation mechanism: Using the above extended instruction set, this invention realizes dynamic incremental compilation. During the hybrid algorithm iteration process, only some parameters change. This invention updates only these changed parameters through the q_update instruction, without recompiling and transmitting the entire quantum program, reducing the overhead of repeated compilation from milliseconds to nanoseconds.

[0096] (3) Compiler executes a fine-grained memory consistency synchronization mechanism: This invention employs a fine-grained memory consistency mechanism by implementing a lightweight memory barrier within the quantum controller. The main processor can query the status of this barrier non-blockingly via the RoCC interface with a single-cycle delay to determine whether data synchronization is complete. This mechanism allows tasks such as quantum execution, data transmission, and classical post-processing to overlap, effectively hiding latency.

[0097] (4) The compiler executes an efficient quantum-classical scheduling mechanism: Based on a fine-grained memory consistency synchronization mechanism, this invention proposes a batch transmission scheduling strategy. This strategy packages the results of multiple quantum measurements together until the data volume matches the bus width before performing a single transmission, thereby maximizing bus bandwidth utilization and reducing the number of transmissions and overhead.

[0098] After `q_run` is executed, the quantum controller immediately begins writing the measurement results into main memory in batches and updating the memory barrier state. The post-processing task on the main processor does not need to wait for all data transmission to complete; it can query the memory barrier through the RoCC interface and begin processing as soon as a portion of the data becomes available. Simultaneously, a batch transmission strategy is employed. For example, for a 64-qubit (64-bit data) and 256-bit bus, the results of four measurements are packaged and then transmitted via a single bus pass to fully utilize bandwidth and reduce the number of bus accesses.

[0099] like Figure 7 As shown, by comparing two different synchronization mechanisms, the significant performance advantage of the fine-grained memory barrier method proposed in this invention compared to the traditional FENCE instruction is intuitively demonstrated. In the figure, PC / MC / ADI represent the execution and data processing at the quantum terminal.

[0100] like Figure 7 As shown in (a), the timing is illustrated when using the traditional FENCE instruction for synchronization. This is a blocking, serialized process, and its inefficiency is reflected in: Forced pause: When a classical processor needs to obtain the result of a quantum computation, it must execute a FENCE instruction. This instruction blocks the entire processor pipeline, putting it into a long wait pause state (tSTALL) until all the quantum operations (tRUN) preceding it have completed.

[0101] Serial execution: Quantum execution (tRUN), data transfer (PUT), and classical post-processing (PRO) are executed strictly in sequence. The processor must wait for quantum execution to complete, and then wait for all data to be transferred through the QCI bus (guaranteed by the second FENCE instruction) before it can begin post-processing the data.

[0102] Resource waste: During tSTALL and data transfer, the classic processor is completely idle, resulting in a serious waste of computing resources and causing the execution time of the entire system to be unnecessarily prolonged by waiting.

[0103] like Figure 7 As shown in (b), the timing characteristics after employing the fine-grained memory barrier mechanism of this invention are illustrated. This is a non-blocking, overlapable, and efficient process, the advantages of which are: Eliminating pauses: This invention replaces the FENCE instruction with a non-blocking, queryable memory barrier. Classic processors can query the data synchronization status at any time via the RoCC interface at very low cost without pausing.

[0104] Execution overlap: The core advantage of this mechanism lies in its ability to allow quantum execution, data transfer, and classical post-processing to overlap in parallel. During quantum execution (tRUN), once a partial measurement result is generated, the quantum controller can immediately send it to the host memory via a PUT instruction. The classical processor can then begin processing the synchronized first part of the data (#1 synchronization), while subsequent quantum execution and data transfer are still in progress.

[0105] Highly efficient collaboration: The processor can process small chunks of synchronized data on demand (e.g., process #3 synchronization after #1 synchronization) instead of waiting for all data to arrive. This "transfer-and-compute" model greatly hides the latency of data transmission and some computation, significantly reducing the overall system execution time (tQ).

[0106] In summary, by comparing Figure 7(a) and (b), it can be clearly seen that the fine-grained memory barrier mechanism of this invention breaks through the strict serialization bottleneck brought about by the traditional FENCE instruction. By realizing deep overlap and parallelism of tasks, it greatly reduces the idle waiting time of the processor, thereby significantly improving the overall execution efficiency and system throughput of the hybrid quantum classical algorithm.

[0107] In summary, through the above-mentioned hardware and software co-design, the embodiments of the present invention can improve the execution efficiency of hybrid quantum classical algorithms by more than an order of magnitude.

[0108] Based on the same inventive concept, embodiments of the present invention also provide a method for accelerating hybrid quantum classical computing, comprising the following steps: S1 decomposes the quantum-classical hybrid algorithm into an extended instruction set through the compiler, and loads the instructions and parameters of the computation task into a unified memory space through the extended instruction set.

[0109] S2 utilizes the main processor and quantum accelerator to retrieve and execute classical and quantum computing tasks from a unified memory space, respectively. The computing unit executes a multi-stage hardware pipeline to generate quantum control pulses based on the quantum program and parameters in the quantum controller cache, and transmits the quantum control pulses to the quantum chip to perform quantum measurements to accelerate quantum computing.

[0110] S3, based on an efficient quantum-classical scheduling mechanism, writes the quantum measurement results after the quantum chip is executed into the quantum controller cache. Before subsequent tasks access the shared data, the main processor queries the state of the lightweight memory barrier in the quantum controller in a low-latency, non-blocking manner based on a fine-grained memory consistency synchronization mechanism to confirm that the data synchronization is complete.

[0111] Based on the above steps, the actual accelerated computation is a cyclical process. The program only needs to be compiled once, and then in each loop, the following steps are executed: load data → calculate quantum control waveform → transmit to quantum chip → quantum chip execution → transmit back to classical computation.

[0112] Based on the same inventive concept, embodiments of the present invention also provide an electronic device, including a memory and one or more processors, wherein the memory is used to store a computer program, and the processor is used to implement the above-described method for accelerating hybrid quantum classical computing when executing the computer program. It should be noted that the methods and electronic devices for accelerating hybrid quantum classical computing provided in the above embodiments belong to the same inventive concept as the tightly coupled system architecture for accelerating hybrid quantum classical computing. For details of their implementation process, please refer to the embodiments of the tightly coupled system architecture for accelerating hybrid quantum classical computing, which will not be repeated here.

[0113] The specific embodiments described above illustrate the technical solution and beneficial effects of the present invention in detail. It should be understood that the above description is only the most preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, additions, and equivalent substitutions made within the scope of the principles of the present invention should be included within the protection scope of the present invention.

Claims

1. A tightly coupled system architecture for accelerating hybrid quantum classical computing, characterized in that, include: The hardware architecture that tightly integrates the main processor and the quantum accelerator includes: a unified memory hierarchy: providing a unified memory space shared by the main processor and the quantum accelerator, containing a quantum controller cache at the same level as the main processor's L1 cache; the quantum accelerator includes a quantum controller, computing units, and a quantum chip; an efficient quantum controller: managing the unified memory hierarchy and internal and external communication through the quantum controller, providing dedicated data paths and hardware interfaces to connect the main processor and the quantum controller cache; and a multi-stage hardware pipeline: efficiently generating quantum control pulses in the computing units through a multi-stage hardware pipeline for the quantum chip to perform quantum measurements. The software architecture that extends the instruction set architecture of the main processor includes: Extended instruction set: Adding data communication instructions and computation instructions to extend the original instruction set to support efficient interaction between the main processor and the quantum controller cache; Compiler execution of fine-grained memory consistency synchronization mechanism: Deploying lightweight memory barriers within the quantum controller to support low-latency querying of data synchronization status by the main processor; Compiler execution of efficient quantum-classical scheduling mechanism: Based on the fine-grained memory consistency synchronization mechanism, using a batch transmission strategy to package and transmit quantum measurement results.

2. The tightly coupled system architecture for accelerating hybrid quantum classical computing according to claim 1, characterized in that, The quantum controller cache is organized into a scalable two-dimensional space. The first dimension is divided into multiple functional segments, including at least a .program segment for storing quantum programs, a .pulse segment for storing control pulses, a .measure segment for storing measurement results, a .regfile segment for storing frequently updated parameters, and a .slt segment for storing the jump lookup table mapping gate parameters to pulse addresses. The second dimension divides each functional segment into blocks that correspond one-to-one with a quantum bit, and each block has an independent quantum address.

3. The tightly coupled system architecture for accelerating hybrid quantum classical computing according to claim 2, characterized in that, The quantum controller cache includes a public cache and a private cache. The public cache stores the .program, .measure, and .regfile segments, while the private cache stores the .pulse and .slt segments.

4. The tightly coupled system architecture for accelerating hybrid quantum classical computing according to claim 3, characterized in that, The registers in the main processor interact with the public cache of the quantum controller through the RoCC interface. The L2 cache in the main processor interacts with the public cache and private cache of the quantum controller through the quantum controller interface. The quantum chip interacts with the public cache and private cache of the quantum controller through the analog-to-digital interface.

5. The tightly coupled system architecture for accelerating hybrid quantum classical computing according to claim 1 or 4, characterized in that, The quantum controller incorporates an internal rearranged buffer queue to handle out-of-order bus responses, a write buffer queue to match the data bit widths of different components, and a memory barrier to ensure cache consistency.

6. The tightly coupled system architecture for accelerating hybrid quantum classical computing according to any one of claims 2 to 4, characterized in that, The multi-stage hardware pipeline includes: Phase 1: Fetch instructions from the .program segment based on the program counter; Phase 2: Decode the instruction. If the reg_flag bit in the instruction is 1, the parameter is obtained from the ..regfile segment. Then, the instruction type and data field are used as an index to query the skip lookup table in the .slt segment. If the skip lookup table is matched, it means that the pulse corresponding to the parameter already exists. The quantum address is directly obtained and updated in the .program segment, and the subsequent pipeline stages are terminated. If the skip lookup table is not matched, a new quantum address will be allocated according to the least-used strategy and passed to the next stage. Phase 3: If the jump lookup table is not found, the parameters are sent to an idle pulse generation unit for calculation, and the parallel scheduling of multiple pulse generation units is achieved through a priority encoder and arbitrator. Stage 4: Write the pulse data calculated by the pulse generation unit into the .pulse segment according to the new quantum address.

7. The tightly coupled system architecture for accelerating hybrid quantum classical computing according to claim 4, characterized in that, The data communication instructions include: a q_update instruction for enabling communication between the registers in the main processor and the public cache of the quantum controller; a q_set instruction for enabling communication between the L2 cache in the main processor and the public and private caches of the quantum controller, respectively; and a q_acquire instruction for enabling communication between the public and private caches of the quantum controller and the L2 cache in the main processor, respectively. The computational instructions include: a q_gen instruction for controlling the waveform generated by the quantum control pulse, and a q_run instruction for enabling the quantum chip to communicate with the public and private caches of the quantum controller and execute the quantum program.

8. The tightly coupled system architecture for accelerating hybrid quantum classical computing according to claim 7, characterized in that, The software architecture also includes a dynamic incremental compilation mechanism that uses the q_update instruction to update only the parameters that change in the quantum controller cache during the hybrid algorithm iteration process, without having to recompile and transmit the entire quantum program.

9. A method for accelerating hybrid quantum classical computing, implemented using the tightly coupled system architecture for accelerating hybrid quantum classical computing as described in any one of claims 1 to 8, characterized in that, Includes the following steps: The quantum-classical hybrid algorithm is compiled into an extended instruction set by a compiler. Data is executed through the extended instruction set. During execution, the instructions and parameters of the computation task are loaded into a unified memory space. Classical and quantum computing tasks are retrieved and executed separately from a unified memory space using a main processor and a quantum accelerator. The computing unit executes a multi-level hardware pipeline to generate quantum control pulses based on quantum programs and parameters in the quantum controller cache. The quantum control pulses are then transmitted to the quantum chip to perform quantum measurements to accelerate quantum computing. Based on an efficient quantum-classical scheduling mechanism, the quantum measurement results executed by the quantum chip are written into the quantum controller cache. Before subsequent tasks access the shared data, a fine-grained memory consistency synchronization mechanism is used to query the state of the lightweight memory barrier in the quantum controller with low latency and non-blocking, confirming that the data synchronization is complete.

10. An electronic device comprising a memory and one or more processors, the memory being used to store a computer program, characterized in that, The processor is used to implement the method for accelerating hybrid quantum classical computing as described in claim 9 when executing a computer program.

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