Control instruction rate matching method for distributed controller-driver

Abstract

The invention discloses a control instruction rate matching method of a distributed controller-driver, and relates to the technical field of distributed control, and the method comprises the steps: carrying out instruction frequency detection through employing a clock source of the driver, and obtaining a frequency error value of a controller instruction; performing interpolation caching processing on the controller instruction based on the frequency error value of the controller instruction to obtain frequency error information of instruction caching; and performing dynamic period adjustment according to the frequency error value of the controller instruction and the frequency error information of the instruction cache, and obtaining a control instruction rate matching result. Frequency detection and dynamic period adjustment are independently completed through the driver, a controller does not need to participate in clock calibration, the communication bandwidth is prevented from being occupied by a calibration instruction, and the system communication efficiency is remarkably improved; and in combination with interpolation cache processing, clock skew can be compensated in real time, the instruction frequency error is controlled within an extremely low range, the system fluctuation risk is effectively reduced, a communication protocol does not need to be modified, and the method is completely compatible with an existing hardware architecture.

Description

Technical Field

[0001] This invention relates to the field of distributed control technology, and in particular to a method for matching control command rates between a distributed controller and a driver. Background Technology

[0002] In existing distributed controller-driver combinations, the controller and driver typically use different clock sources. Due to frequency deviations in these clock sources, accumulated errors over time cause periodic jitter in the data, leading to synchronization misalignment between the position commands sent by the controller and the actual execution time of the driver. Traditional synchronization schemes often rely on the controller sending clock calibration commands to the driver to eliminate the deviation through periodic correction. However, this process consumes limited communication bandwidth, and the transmission delay of the calibration commands introduces new synchronization errors. Especially in high-frequency control scenarios, the accumulation of clock deviations can cause command execution time offsets, resulting in system response lag or overshoot, and in severe cases, even equipment instability. Furthermore, traditional methods require high customization of communication protocols, making it difficult to be compatible with controller-driver combinations from different manufacturers, thus limiting the system's versatility and scalability.

[0003] Therefore, there is an urgent need for a distributed controller-driver control command rate matching method to address the shortcomings of existing technologies. Summary of the Invention

[0004] The purpose of this invention is to propose a control command rate matching method for a distributed controller-driver system, so as to solve the problems of mismatch between command sending and reading frequencies caused by independent clock sources for the controller and driver, as well as the bandwidth occupation and poor compatibility of traditional synchronization schemes.

[0005] To achieve the above objectives, the present invention provides a control command rate matching method for a distributed controller-driver, comprising the following steps: S1. Use the driver's clock source to detect the command frequency and obtain the frequency error value of the controller command; S2. Based on the frequency error value of the controller command, perform interpolation and caching processing on the controller command to obtain the frequency error information of the command cache; S3. Perform dynamic periodic adjustment based on the frequency error value of the controller command and the frequency error information of the command cache to obtain the control command rate matching result.

[0006] Optionally, S1, using the driver's clock source to detect the command frequency and obtain the frequency error value of the controller command, including: The dual timers are initialized based on the clock source of the driver, and the dual timers include a first timer and a second timer; The actual control command cycle is obtained using the first timer based on the clock source of the driver; The theoretical control command cycle is generated using the second timer; The actual control command cycle is compared with the theoretical control command cycle to obtain the frequency error value of the controller command.

[0007] Optionally, the actual control command cycle is compared with the theoretical control command cycle to obtain the frequency error value of the controller command, including: The actual controller command frequency and the theoretical controller command frequency are calculated using the actual control command cycle and the theoretical control command cycle, respectively. The error between the actual controller command frequency and the theoretical controller command frequency is calculated, and the relative frequency error between the actual controller command frequency and the theoretical controller command frequency is obtained as the relative frequency error of the controller command. A reference time interval is set based on the relative frequency error of the controller command and the relative frequency error of the corresponding historical control command. The frequency error value of the controller command is obtained based on the relative frequency error between the reference time interval and the controller command.

[0008] Optionally, S2, based on the frequency error value of the controller command, perform interpolation buffering processing on the controller command to obtain the frequency error information of the command buffer, including: Based on the frequency error value of the controller command, set the interpolation factor and the frequency error threshold; Determine whether the frequency error value of the controller command is greater than or equal to the frequency error threshold. If so, obtain linear interpolation as a smooth interpolation algorithm and execute the first operation; otherwise, obtain spline interpolation as a smooth interpolation algorithm and execute the first operation. The first operation is as follows: using the interpolation factor and the smooth interpolation algorithm to perform interpolation caching on the controller instructions, and obtaining the frequency error information of the instruction cache.

[0009] Optionally, the controller instructions are interpolated and cached using the interpolation factor and the smooth interpolation algorithm to obtain frequency error information of the instruction cache, including: Based on the interpolation factor, the controller instructions are smoothly interpolated using the smooth interpolation algorithm to obtain a smoothly interpolated controller instruction sequence. The controller instruction sequence of the smooth interpolation is cached to obtain the change in the cached instructions; Based on the change in cached instructions, the interpolation factor, and the theoretical control instruction cycle, the frequency error information of the instruction cache is obtained.

[0010] Optionally, S3, dynamically periodically adjust the frequency error based on the frequency error value of the controller command and the frequency error information of the command cache to obtain the control command rate matching result, including: The frequency error value of the controller command is weighted and fused with the frequency error information of the command cache to obtain a comprehensive error value; Based on the comprehensive error value, determine the dynamic periodic adjustment parameters; The carrier period of the controller is adjusted using the dynamic period adjustment parameters to obtain the control command rate matching result.

[0011] Optionally, the frequency error value of the controller command and the frequency error information of the command cache are weighted and fused to obtain a comprehensive error value, including: Based on the frequency error value of the controller command, set the frequency error threshold of the controller command as the coarse error threshold; Determine whether the frequency error value of the controller instruction is greater than the coarse error threshold. If so, obtain the frequency error value weight of the first controller instruction and the frequency error information weight of the first instruction cache as the weight allocation result, and perform the second operation. Otherwise, obtain the frequency error value weight of the second controller instruction and the frequency error information weight of the second instruction cache as the weight allocation result, and perform the second operation. The second operation is as follows: based on the weight allocation result, the frequency error value of the controller instruction and the frequency error information of the instruction cache are weighted and fused to obtain a comprehensive error value.

[0012] Optionally, based on the comprehensive error value, the dynamic periodic adjustment parameters are determined, including: Based on the comprehensive error value, a comprehensive error threshold is set; Determine whether the overall error value is greater than the overall error threshold. If so, obtain the dynamic periodic adjustment parameter using a lookup table based on the overall error value. Otherwise, input the overall error value into the PI controller to obtain the dynamic periodic adjustment parameter.

[0013] Optionally, adjusting the carrier period of the controller using the dynamic period adjustment parameter to obtain the control command rate matching result includes: The target carrier period is calculated using the aforementioned dynamic period adjustment parameters; The carrier period of the controller is adjusted according to the target carrier period to obtain the adjusted carrier period; Based on the adjusted carrier period, detection processing is performed to obtain the instruction buffer status and the controller instruction input rate; Based on the instruction cache status and the controller instruction input rate combined with the control instruction rate matching determination condition, the control instruction rate matching result is obtained.

[0014] Optionally, the control command rate matching determination condition is: The instruction cache state is stable within a preset range, and the controller instruction input rate is less than the controller instruction input rate threshold.

[0015] Compared with the closest existing technology, the present invention has the following advantages: Compared to traditional synchronization methods, this invention only requires the driver to implement the relevant technologies, without requiring additional communication time or additional design of controller and driver protocols, and is fully compatible with existing controller-driver structures. The controller instruction interpolation buffer effectively increases the controller's instruction issuance frequency, synchronizing the controller's relatively low instruction issuance frequency with the driver's relatively high instruction execution frequency, thus improving frequency error detection accuracy while ensuring a wider frequency error detection range. Specific effects are as follows: This invention achieves frequency detection and rate matching independently through the driver, eliminating the need for the controller to participate in clock calibration. This eliminates the bandwidth occupation of calibration commands and improves system communication efficiency. By combining interpolation buffering with dynamic periodic adjustment, it can compensate for clock deviations in real time, keeping the frequency error between command transmission and reading within an extremely low range, significantly reducing the risk of system fluctuations caused by synchronization deviations. It requires no modification to the communication protocol between the controller and the driver, is fully compatible with existing hardware architectures, and can be directly applied to distributed systems from different manufacturers, greatly improving the versatility and engineering practicality of the technical solution. The dynamic periodic adjustment mechanism can adapt to dynamic changes in the controller command frequency, maintaining efficient rate matching even in scenarios where controller load fluctuations cause unstable command transmission frequencies. Attached Figure Description

[0016] To more clearly illustrate the specific embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the specific embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present invention. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0017] Figure 1 This is a flowchart illustrating a control command rate matching method for a distributed controller-driver according to an embodiment of the present invention. Detailed Implementation

[0018] To make the objectives, technical solutions, and advantages of this invention clearer, the technical solutions in the embodiments of this invention will be clearly and completely described below with reference to specific embodiments and corresponding drawings. Obviously, the described embodiments are only a part of the embodiments of this invention, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of this invention without creative effort are within the scope of protection of this invention.

[0019] The terminology used in the embodiments section of this invention is for the purpose of explaining specific embodiments of the invention only, and is not intended to limit the invention.

[0020] like Figure 1 As shown, this embodiment of the invention provides a control command rate matching method for a distributed controller-driver, comprising: S1. Use the driver's clock source to detect the command frequency and obtain the frequency error value of the controller command; Command Frequency Detection Layer: The driver calculates the time interval between commands issued by the controller in real time using its own clock source and compares it with the theoretical reference time interval to detect the frequency error between the controller and the driver. This step can automatically identify a wide range of frequency deviations, avoiding the complexity of additional communication and protocol synchronization required in traditional solutions. This step achieves efficient and independent detection of the controller command frequency, providing basic data support for subsequent synchronization adjustments.

[0021] S2. Based on the frequency error value of the controller command, perform interpolation and caching processing on the controller command to obtain the frequency error information of the command cache; Interpolation Buffer Extraction Layer: The driver smooths the received controller commands using an interpolation algorithm, generating multiple intermediate commands and buffering them. Changes in the amount of effective data in the buffer reflect more refined frequency error information. This step expands the accuracy range of error detection by increasing the virtual multiple of the command issuance frequency. This step ensures high resolution of error detection while remaining compatible with the controller's original low-frequency command mode, enhancing the system's synchronization adaptability.

[0022] S3. Perform dynamic periodic adjustment based on the frequency error value of the controller command and the frequency error information of the command cache to obtain the control command rate matching result; The driver combines coarse error (instruction frequency detection layer) and fine error (interpolation buffer extraction layer) information to dynamically adjust the carrier frequency using a lookup table method or a PI controller, thereby adjusting the instruction buffer consumption rate. This step achieves stepless adjustment of the carrier frequency, ensuring precise synchronization between the controller instructions and the driver execution time. This step significantly improves synchronization accuracy and system stability, while requiring no modification to existing communication protocols or increasing the controller load, and is fully compatible with existing hardware architectures.

[0023] In summary, steps S1 to S3 achieve command synchronization by having the driver autonomously detect the frequency error of the controller commands and dynamically adjust the carrier frequency. Specifically, this involves three steps: First, the driver uses its own clock source to detect the frequency error of the controller commands (coarse error); second, it smooths the commands and extracts more refined frequency error information (fine error) through interpolation buffering; finally, it dynamically adjusts the carrier frequency based on the coarse and fine errors to match the command rate. This solution requires no additional communication protocol or controller modification, is compatible with existing architectures, and expands the error detection range and improves synchronization accuracy through interpolation buffering. It effectively solves the problem of command execution asynchrony caused by clock source deviation, improving system stability and control accuracy.

[0024] As one possible implementation, in the above embodiments, step S1 may specifically include the following steps: S1-1. Initialize the dual timers using a driver-based clock source; The driver uses its own high-precision clock source to initialize the dual timers (first and second timers). The driver uses these two timers to detect the frequency of controller command issuance. The first timer measures the actual time interval (actual period) between controller commands, while the second timer operates based on a preset theoretical command period (such as a fixed time base). The clock source uses a temperature-compensated crystal oscillator or a temperature-controlled crystal oscillator. The two timers employ a synchronous counter architecture, with their counting pulses directly derived from the driver's clock source after frequency division of the standard clock signal. For example, a 10MHz clock source is divided to 1MHz to ensure a timing accuracy of 1 microsecond.

[0025] During initialization, the system performs synchronous calibration on both timers by sending a reset signal via the internal bus to clear the initial count values ​​of both timers to zero, ensuring strict synchronization at startup with a synchronization error ≤ 1 clock cycle. This step, by sharing the same highly stable clock source and achieving synchronous initialization of both timers, guarantees that the timing reference of the actual control command cycle is completely consistent with that of the theoretical control command cycle. This avoids the error accumulation problem caused by differences in timing references from the source, providing a highly consistent time reference for subsequent frequency error calculations.

[0026] To avoid counting errors caused by timer overflow, this embodiment also includes a dynamic overflow warning mechanism: when the timer's count value reaches 90% of its maximum range, an interrupt signal is triggered. The controller will automatically record the current count value and reset the counter in the interrupt response, ensuring the continuity of the timing process. Furthermore, the dual timers are linked to the driver's clock source calibration module, updating the counting reference synchronously with the automatic calibration of the clock source every hour, eliminating accumulated errors during long-term operation.

[0027] S1-2. Obtain the actual control instruction cycle using the first timer based on the clock source of the driver; The first timer is configured in "event-triggered counting mode," which triggers timing by capturing the edge signal (such as rising / falling edge) of the controller's command, records the timestamps of adjacent commands in real time, and calculates the actual control command cycle based on the driver's clock source. Specifically: When the driver's signal conditioning circuit detects an edge signal of the control command, it immediately sends a start signal to the first timer, and the timer begins to accumulate counts. When the next edge of the same type is detected, a stop signal is sent, and the counter stops counting. The counting result of the first timer is transmitted to the arithmetic unit in real time via a dedicated data bus. The arithmetic unit divides the count value by the frequency of the driver's clock source (e.g., a 1MHz clock source corresponds to 1 microsecond per counting unit) to obtain the time interval between two adjacent command edges, i.e., the actual control command cycle. In addition, to improve detection accuracy, a multi-cycle averaging method is used to continuously record the measured values ​​of M (M≥5) actual control command cycles. After removing the maximum and minimum values, the arithmetic mean is taken as the final actual control command cycle.

[0028] This step, through edge-triggered real-time counting, can accurately capture the time interval of the command signal. The multi-cycle averaging method effectively suppresses measurement fluctuations caused by instantaneous noise interference, reducing the measurement error of the actual control command cycle. The high-speed transmission of the dedicated data bus ensures that the counting results are transmitted without delay, providing high-fidelity raw data for subsequent error calculation.

[0029] S1-3. Generate the theoretical control command cycle through the second timer; The second timer is configured in "fixed period output mode" to generate the theoretical control command cycle. This timer operates independently, unaffected by the actual behavior of the controller, and always provides a stable theoretical cycle reference. Its working principle is as follows: The comparison register value is configured according to the preset theoretical control command frequency (e.g., a nominal 100Hz corresponds to a 10ms cycle), and an automatic reload mode is used to continuously maintain a fixed time interval (e.g., triggering a count every 1ms). Specifically: Receives user-defined theoretical control command frequency through the configuration interface. F refThe arithmetic unit converts it into a theoretical period. T ref =1 / F ref And the number of clock pulses corresponding to that period ( T ref The clock source frequency (×) is written to the comparison register of the second timer. The second timer uses an automatic reload mode. When the count reaches the value of the comparison register, an interrupt is automatically triggered and the counter is reset to start the next cycle of counting. At the same time, a synchronization pulse signal is output as a marker of the theoretical instruction cycle. For example, if the theoretical cycle is 1ms and the clock source frequency is 1MHz, the value of the comparison register is set to 1000 (1ms = 1000 microseconds, corresponding to 1000 count units). Every time the second timer counts to 1000, a theoretical cycle completion signal is generated, which can be used for subsequent comparison with the actual instruction cycle. In addition, the system supports dynamic modification of the theoretical control instruction frequency. By writing a new comparison register value, the second timer can switch to the new theoretical cycle within one clock cycle to adapt to the control requirements under different operating conditions.

[0030] The automatic reloading counting mode in this step ensures a stable output of the theoretical control command cycle, and its accuracy is determined solely by the stability of the driver clock source, avoiding theoretical cycle drift caused by software calculation delays. The dynamic switching function enhances the system's flexibility, allowing the theoretical cycle parameters to be updated in real time according to the adjustment of the control strategy, providing a reliable benchmark reference for dynamic comparison of frequency errors.

[0031] S1-4. Compare the actual control command cycle with the theoretical control command cycle to obtain the frequency error value of the controller command; This step calculates the frequency error value of the controller command by comparing the actual control command cycle with the theoretical control command cycle, avoiding rounding errors in the frequency conversion process and making the error calculation more accurate.

[0032] In summary, after the driver starts up, steps S1-1 to S1-4 first activate its own clock source, entering the controller command issuance frequency detection stage. Two timers are used to calculate the actual control command cycle and the theoretical control command cycle, respectively, and then a large-range frequency error value is obtained through real-time comparison. Using the driver's own clock source as a reference, the frequency of the commands sent by the controller is detected in real time. The driver's clock source has high stability and accuracy, providing a reliable reference standard for frequency detection. This process, by initializing dual timers with the driver's high-precision clock source, effectively avoids detection errors caused by the instability of external reference sources, ensuring consistency between the actual and theoretical control command cycle timing references, and guaranteeing timing range and continuity. The first timer, combined with a multi-cycle averaging method, accurately obtains the actual cycle, suppressing noise interference. The second timer generates a stable theoretical cycle in automatic reloading mode and supports dynamic switching. Comparing the cycles yields the frequency error, facilitating improvements in the accuracy of control command rate matching, system flexibility, and maintainability, and providing a reliable basis for dynamic adjustment of the control cycle.

[0033] As one possible implementation, in the above embodiments, steps S1-4 may specifically include the following steps: S1-4-1. Calculate the actual controller command frequency and the theoretical controller command frequency using the actual control command cycle and the theoretical control command cycle, respectively. The actual control command cycle obtained using the first timer T 1. The driver execution cycle is calculated using the reciprocal relationship between frequency and cycle to determine the actual controller command frequency, i.e.: Actual controller command frequency f 1 = 1 / T 1; At the same time, according to the system's preset theoretical control command cycle T 0 represents the theoretical command cycle of the controller. The theoretical controller command frequency is calculated using the reciprocal relationship: Theoretical controller command frequency f 0 = 1 / T 0; This step transforms the periodic differences, which were originally measured in time units, into frequency parameters that more intuitively reflect the “speed” of command transmission. This directly reflects the clock source deviation between the controller and the driver, providing a standardized input for subsequent relative frequency error calculations.

[0034] S1-4-2. Calculate the error between the actual controller command frequency and the theoretical controller command frequency, and obtain the relative frequency error between the actual controller command frequency and the theoretical controller command frequency as the relative frequency error of the controller command. The relative frequency error is obtained by calculating the difference between the actual controller command frequency and the theoretical controller command frequency, dividing this difference by the theoretical controller command frequency, and multiplying by 100%. This relative frequency error of the controller command is then used as the calculation formula: δ f =[( f 1- f 0) / f 0]×100% in, δ f This represents the relative frequency error of the controller commands.

[0035] This process eliminates the influence of the absolute value of the frequency on error assessment, and can more accurately reflect the deviation ratio of the actual frequency from the theoretical frequency. For example, the severity of the same absolute error at different theoretical frequencies can be uniformly and objectively assessed through relative error, providing a standardized quantitative indicator for subsequent threshold judgment.

[0036] S1-4-3. Based on the relative frequency error of the controller command and the relative frequency error of the corresponding historical control command, a reference time interval is set; By analyzing the relative frequency error of the current controller command and the relative frequency error sequence of the corresponding historical controller commands over a period of time, the fluctuation pattern, trend, and stability of the error are observed, and the reference time interval is dynamically set accordingly. For example, if the historical error fluctuates little in the past 50ms, such as within ±0.5%, and the difference between the current error and the historical error is <1%, then the reference time interval is set to 50ms (reflecting the stable state of the error); if the error fluctuates more than ±5% in the past 20ms, such as jumping from -10% to +8%, then the reference time interval is set to 20ms (capturing high-frequency fluctuations). In this embodiment, the reference time interval is dynamically updated according to the error stability, wherein the interval is increased when stable to reduce the amount of calculation, and decreased when fluctuating to improve the response speed.

[0037] This step extends error analysis from a single moment to trend analysis over time by introducing a reference time interval, avoiding misjudgments caused by instantaneous errors and improving the robustness of error detection. At the same time, by dynamically adjusting the interval size according to the error characteristics, it ensures the accuracy of error detection while also taking into account the system's computational efficiency.

[0038] S1-4-4. Obtain the frequency error value of the controller command based on the relative frequency error between the reference time interval and the controller command; Based on a pre-set reference time interval, and considering the relative frequency error change of the controller commands within that time interval (e.g., whether the error change is within a preset threshold or whether abnormal fluctuations occur), the frequency error value of the controller commands is determined. If the change in relative frequency error within the reference time interval (e.g., 50ms) is less than or equal to a preset threshold (e.g., ±1%), the average relative error within that time interval is taken as the final frequency error value (e.g., -16.5%). If the change is greater than the threshold (e.g., from -10% to -20% within 50ms), the maximum deviation value within that time interval (e.g., -20%) is taken and marked as "abnormal fluctuation". In this embodiment, the final frequency error value can be described by combining the error magnitude and stability.

[0039] The error value output by this step not only includes information on the magnitude of the deviation, but also incorporates stability characteristics over time, making the error assessment more comprehensive. This provides a more practical basis for decision-making regarding controller calibration, fault diagnosis, and adjustment of system control strategies.

[0040] In summary, steps S1-4-1 to S1-4-4, through quantitative analysis and trend judgment over time, ultimately yield a frequency error value with a wide range that combines accuracy and practicality. This value accurately reflects the degree of deviation of the controller commands and provides an operational basis for system optimization, such as triggering calibration, alarms, or adjusting control strategies based on the error value.

[0041] As one possible implementation, in the above embodiments, step S2 may specifically include the following steps: S2-1. Based on the frequency error value of the controller command, set the interpolation multiple and the frequency error threshold; The driver first presets two key parameters based on the system's control accuracy requirements: the interpolation factor N (e.g., 16 times) and the frequency error threshold Δ. f th (e.g., ±3%). Interpolation factor. N = floor ( T 0 / T 1) This determines the temporal resolution of the instruction sequence; a higher multiplier results in higher accuracy for subsequent error detection, but also a greater computational load. floor (∙) indicates the floor function; the frequency error threshold is used to distinguish between significant errors requiring fast response (coarse errors) and minute errors requiring high-precision processing (fine errors). When the detected command frequency error exceeds this threshold, the system must prioritize processing speed over accuracy. The settings of these two parameters need to comprehensively consider the controller's maximum permissible deviation, the driver's computing power, and the smoothness requirements of motion control.

[0042] In addition, the frequency error threshold in this embodiment is set to 3%. The setting of this threshold takes into account the typical instantaneous error characteristics of 1% to 5% of industrial-grade independent clocks, the system's tolerance for "data periodic jitter" caused by errors exceeding 3%, and the technical layering correspondence with the "command frequency detection layer (coarse error detection)" to ensure that large errors can trigger corresponding processing such as linear interpolation.

[0043] S2-2. Determine whether the frequency error value of the controller command is greater than or equal to the frequency error threshold. If so, obtain linear interpolation as a smooth interpolation algorithm and execute S2-3. Otherwise, obtain spline interpolation as a smooth interpolation algorithm and execute S2-3. The driver selects an appropriate smooth interpolation algorithm, such as linear interpolation or cubic spline interpolation, based on the detected controller command frequency error (coarse error) and a set threshold. When the coarse error is |Δ f 粗 When |≥3%, linear interpolation algorithms with low computational cost and fast response speed are preferred. Their characteristic of requiring no additional communication time allows for rapid coverage of a large range of errors with low computational cost. When the coarse error |Δ f 粗 When the error rate is less than 3%, smoothness is prioritized, such as in precision motion control. Spline interpolation algorithms, which offer better fitting results, are chosen to enhance command smoothness. Polynomial fitting is used to extract frequency error values ​​within a smaller range, avoiding jitter in precision control. The choice of interpolation algorithm is related to the frequency error value of the controller command. An error-adaptive interpolation algorithm is selected, balancing computational efficiency and interpolation accuracy, ensuring that the interpolation results cover the error range while meeting real-time requirements.

[0044] S2-3. Use the interpolation factor and the smooth interpolation algorithm to perform interpolation caching on the controller instructions to obtain the frequency error information of the instruction cache. The driver smoothly interpolates the controller's commands based on a set interpolation factor (e.g., 16x) using a selected smooth interpolation algorithm (linear / spline). This converts a single controller command into multiple commands, which are then buffered. The difference in the effective data volume within the buffer contains frequency error information between the controller and the driver. Due to the interpolation buffer, this information includes a small range of frequency error values. By detecting the dynamic changes in the number of effective commands in the buffer (reflecting the frequency matching status), the originally minute controller-driver frequency error (±0.1% level) is amplified into a quantifiable and detectable difference in the buffer state. This allows for the extraction of small-range frequency error values, ultimately forming the frequency error information of the command buffer. This interpolation buffering mechanism significantly improves the sensitivity of frequency error detection while maintaining command continuity through high-frequency processing.

[0045] In summary, steps S2-1 to S2-3 achieve dynamic matching of the algorithm through threshold grading, which ensures processing efficiency while taking into account instruction smoothness. This effectively compensates for the inconsistency of instruction transmission and obtains more refined error characteristics through cache analysis, providing a precise basis for subsequent control cycle adjustment and improving the response speed and stability of the entire control system.

[0046] As one possible implementation, in the above embodiments, step S2-3 may specifically include the following steps: S2-3-1. Based on the interpolation factor, the smooth interpolation algorithm is used to perform smooth interpolation processing on the controller instructions to obtain a smooth interpolated controller instruction sequence; The driver performs real-time interpolation processing on received controller commands based on a preset interpolation factor (e.g., 16 times) and a selected smooth interpolation algorithm (linear or spline interpolation). Through interpolation algorithms between adjacent command points, a single controller command is converted into multiple commands. Linear interpolation uses uniform segmentation, while spline interpolation maintains high-order continuity. During interpolation, the theoretical timestamp offset of the command is calculated based on the frequency error value to ensure that the parameters of intermediate commands (e.g., position and velocity commands) exhibit a continuous transition state on the time axis. For example, if the original command has uneven time intervals due to frequency errors, the interpolation algorithm supplements the excessively large intervals with intermediate values ​​that conform to the error trend, ensuring that the entire command sequence has no significant jumps in either time or parameter dimensions, ultimately forming a continuous and smooth interpolated command sequence—the smooth interpolation result of the controller commands.

[0047] This process calculates the original controller instruction sequence and adds appropriate intermediate instructions at locations where the instruction intervals are too large or there are abrupt changes. This makes the instruction sequence, which may have been discontinuous due to frequency fluctuations, continuous and smooth, effectively eliminating instruction gaps caused by frequency errors and improving the temporal continuity and data integrity of the instruction sequence.

[0048] Taking linear interpolation as an example (interpolation factor) N =16): Obtain two consecutive command points issued by the controller. P k and P k+1 Calculate the midpoint P interp ( i This results in an instruction stream 16 times the original frequency, which is the controller instruction sequence with smooth interpolation. The intermediate point calculation formula is as follows: P interp ( i )= P k +[( Pk+1- P k )× i / N ]( i =1,2,…,15) in, i This is the interpolation point index. For example, if... P k =0、 P k+1 =100, the interpolated sequence is [0,6.25,12.5,…,93.75,100].

[0049] S2-3-2. Cache the controller instruction sequence of the smooth interpolation and obtain the cache instruction change amount; The controller instruction sequence, after smoothing and interpolation, is stored sequentially in a pre-defined cache space, forming a temporary data buffer area. At this point, the instruction density in the cache has been increased to a level compatible with the driver's execution frequency through interpolation. The number of valid instructions in the cache is monitored in real time. When there is a frequency error between the controller and the driver, a mismatch will occur between the instruction storage rate (determined by the controller instruction frequency) and the consumption rate (determined by the driver execution frequency), causing the number of instructions in the cache to accumulate or decrease. By recording the increase or decrease in the number of cached instructions per unit time, the change in cached instructions can be obtained. This step provides a direct quantitative representation of frequency error through cache processing; the change in cached instructions directly reflects the degree of frequency deviation between the controller and the driver.

[0050] S2-3-3. Obtain the frequency error information of the instruction cache based on the change in the cached instruction, the interpolation factor, and the theoretical control instruction period; The cache instruction variation ΔC is converted into a precise frequency error signal using the formula ΔC. f =Δ C / ( N × T 0) Calculate the actual frequency deviation Δ f ,in, N The interpolation factor. T 0 represents the theoretical control instruction cycle. This error signal has an amplification effect at the interpolation multiple level; for example, a 16x interpolation can increase the detection sensitivity by 16 times, enabling the identification of minute frequency deviations. For instance, when the interpolation multiple is 16, the frequency deviation corresponding to a unit value of the buffered instruction change is 1 / 16 of the original instruction frequency deviation.

[0051] This step converts the changes in cached instructions into specific frequency error values. Due to the interpolation factor, the range of these error values ​​is narrowed, allowing for a more accurate reflection of the actual frequency deviation. The resulting integrated instruction cache frequency error information provides precise and detailed data for subsequent dynamic adjustment of the control cycle.

[0052] In summary, steps S2-3-1 to S2-3-3 effectively compensate for the discontinuity of instruction data through interpolation, improving the integrity and continuity of the instruction sequence. The caching operation enhances the system's resilience to instruction transmission fluctuations. The obtained instruction cache frequency error information further refines the data dimensions of the frequency error, helping to improve the accuracy of subsequent adjustments. Interpolation caching focuses this information on frequency error values ​​within a smaller range. For example, when the interpolation factor is 16, the driver's execution frequency is set to 16 times the controller instruction frequency. The corresponding period error will cause the number of valid instructions in the cache to increase or decrease. Furthermore, by setting a threshold, the instruction consumption rate can be dynamically adjusted based on the increase or decrease in the number of valid instructions in the cache caused by the period error, ultimately obtaining the instruction cache frequency error information.

[0053] As one possible implementation, in the above embodiments, step S3 may specifically include the following steps: S3-1. Weighted fusion of the frequency error value of the controller instruction and the frequency error information of the instruction cache is performed to obtain a comprehensive error value; Weights are assigned based on the characteristics of the two types of errors. For example, buffer errors have a higher weight due to their more granular nature. By weighting the calculations and combining them with time-related corrections to resolve conflict terms, a comprehensive error value is obtained. This step eliminates the limitations of a single error source, forming a unified evaluation index that comprehensively reflects the system's frequency deviation, providing accurate and comprehensive error data for subsequent adjustments.

[0054] S3-2. Determine the dynamic periodic adjustment parameters based on the comprehensive error value; Based on the comprehensive error value, dynamic adjustment parameters are generated using a lookup table method or a PI controller. The lookup table method matches the preset adjustment level according to the error magnitude; the PI controller achieves smooth adjustment through proportional-integral calculations. Dual error fusion ensures both rapid adjustment response (coarse error) and high-precision synchronization (fine error), avoiding over-adjustment or under-adjustment problems caused by a single error source.

[0055] S3-3. Adjust the carrier period of the controller using the dynamic period adjustment parameter to obtain the control command rate matching result; The carrier period is adjusted according to the obtained adjustment parameters to change the instruction buffer consumption rate. At the same time, the rate matching is checked. If the deviation is within the threshold, the matching is considered successful; otherwise, the adjustment is repeated. This process achieves dynamic rate matching through closed-loop adjustment, ensuring stable system operation.

[0056] In summary, step S3-1 and step S3-3 weighted and fused the frequency errors of the controller commands and the command cache to obtain a comprehensive error value, and then determined the dynamic period adjustment parameter based on this value. Finally, the carrier period was adjusted using this parameter, and dynamic rate matching was achieved through closed-loop detection, ensuring stable system operation.

[0057] As one possible implementation, in the above embodiments, step S3-1 may specifically include the following steps: S3-1-1. Based on the frequency error value of the controller command, set the frequency error threshold of the controller command as the coarse error threshold; According to the frequency error value Δ from the controller command f coarse A coarse error threshold is dynamically set, serving as a critical value to distinguish between large and small deviations. In this embodiment, the coarse error threshold is ±1%. When Δ f coarse When the threshold is exceeded, the system is deemed to have a significant clock deviation, and a coarse-error-dominated adjustment strategy should be prioritized; otherwise, it enters the precision adjustment mode. The threshold value can be configured according to the actual application scenario, for example, ±2% for high-dynamic scenarios and ±0.5% for precision control scenarios. This step enables automatic classification of error states, providing a basis for subsequent weight allocation and avoiding oscillations caused by frequent switching of adjustment modes.

[0058] S3-1-2. Determine whether the frequency error value of the controller instruction is greater than the coarse error threshold. If so, obtain the frequency error value weight of the first controller instruction and the frequency error information weight of the first instruction cache as the weight allocation result, and execute S3-1-3. Otherwise, obtain the frequency error value weight of the second controller instruction and the frequency error information weight of the second instruction cache as the weight allocation result, and execute S3-1-3. By comparing frequency error with a coarse error threshold, different weight combinations are selected. Specifically, when a large deviation is detected, the system prioritizes a rapid adjustment strategy dominated by coarse errors to ensure the system state is brought back to a safe range within a short time. When the error decreases below the threshold, it automatically switches to a precision adjustment mode dominated by fine errors to continuously optimize the system state. Specifically: |Δ f coarse Threshold (Large Deviation Mode): First weight combination, i.e., the frequency error weight of the first controller command. W coarse=0.8, the weight of the frequency error information in the first instruction cache W fine =0.2, focusing on quickly suppressing major deviations from coarse errors; |Δ f coarse |≤Threshold (Small Deviation Mode): Second weight combination, i.e., the frequency error weight of the second controller command. W coarse =0.2, the frequency error information weight of the second instruction cache W fine =0.8, relying on fine error to achieve precise fine-tuning.

[0059] In this embodiment, the weight values ​​can be self-tuned online. This dynamic weight allocation mechanism enables the system to respond quickly when significant deviations occur, while maintaining extremely high control accuracy under stable operating conditions, ultimately achieving a perfect balance between response speed and steady-state accuracy.

[0060] S3-1-3. Based on the weight allocation result, perform weighted fusion processing on the frequency error value of the controller instruction and the frequency error information of the instruction cache to obtain a comprehensive error value; The frequency error Δ of the controller command based on the assigned weights f coarse Frequency error information Δ with instruction cache f fin Perform linear weighted fusion: Δ f total = W coarse ⋅Δ f coarse + W fine ⋅Δ f fine Where, Δ f total This is the integrated error value after fusion. The output integrated error value is used for subsequent coordinated adjustment of carrier period and duty cycle. This step provides a more comprehensive and accurate error benchmark for subsequent adjustments, avoiding the bias caused by a single error source. Additionally, Δ needs to be adjusted before fusion. f coarse Perform moving average filtering on Δ f fine Apply a ±5% rate of change limit to suppress noise interference.

[0061] In summary, steps S3-1-1 to S3-1-3 achieve adaptive adjustment of weights, highlighting the role of cached error information optimized by interpolation when the error is large, while retaining the dominance of the original instruction error when the error is small. This enables the comprehensive error value to more accurately reflect the actual deviation state of the system, providing a more reliable error basis for subsequent adjustments and improving the flexibility and accuracy of error fusion.

[0062] As one possible implementation, in the above embodiments, step S3-2 may specifically include the following steps: S3-2-1. Set the comprehensive error threshold based on the comprehensive error value; The overall error threshold is set based on the system's response requirements and adjustment accuracy to deviations, combined with the degree of influence of deviations on control command rate matching during actual operation. Here, the overall error threshold is set to 0.1, i.e., when |Δ f total When |>0.1, it is judged as a large deviation; when |Δ f total When |≤0.1, it is judged as a small deviation. The setting of this threshold takes into account both the need for rapid adjustment under large deviations to prevent problems such as obvious rate mismatch and instruction cache abnormalities, and the need for fine adjustment under small deviations to ensure control accuracy. It can effectively distinguish different degrees of deviation and provide a clear and definite judgment standard for subsequent selection of appropriate adjustment modes.

[0063] S3-2-2. Determine whether the comprehensive error value is greater than the comprehensive error threshold. If so, obtain the dynamic cycle adjustment parameter by looking up the table based on the comprehensive error value. Otherwise, input the comprehensive error value into the PI controller to obtain the dynamic cycle adjustment parameter. When the overall error value exceeds the preset overall error threshold, it indicates that the current deviation of the system is large, requiring rapid adjustment to prevent further expansion of the deviation. In this case, a lookup table method is used to obtain the dynamic periodic adjustment parameters. This method involves establishing a correspondence table between the overall error value and the dynamic periodic adjustment parameters based on a large amount of experimental data and simulation results. The table covers the optimal adjustment parameters corresponding to different ranges of overall error values, such as the period shortening or lengthening amount. In practical applications, simply look up the matching adjustment parameter in the correspondence table based on the current overall error value. The advantage of this method is its fast response speed, enabling it to quickly react to large errors and ensure that the system returns to a relatively stable state within a short time, avoiding problems such as instruction buffer overflow or idling caused by adjustment delays.

[0064] When the overall error value is within the overall error threshold range, the system deviation is small. In this case, fine-tuning is required to achieve precise matching of the control command rate. A PI controller (proportional-integral controller) can quickly respond to the current error through its proportional element and eliminate steady-state error through its integral element, making it ideal for adjusting such small deviations. After the overall error value is input into the PI controller, the proportional element outputs a corresponding adjustment amount based on the magnitude of the error, making the adjustment speed proportional to the error magnitude; the integral element accumulates the error and outputs an adjustment amount based on the accumulated amount to eliminate persistent small deviations. Through the combined action of the PI controller, precise dynamic periodic adjustment parameters can be output, allowing the system to gradually stabilize under small deviations, achieving high-precision matching of the control command rate, while avoiding the adverse effects on system stability caused by frequent and drastic adjustments.

[0065] As one possible implementation, in the above embodiments, step S3-3 may specifically include the following steps: S3-3-1. Calculate the target carrier period using the aforementioned dynamic period adjustment parameters; First, determine the reference carrier period of the current controller, which is the initial period before adjustment. Then, calculate the target carrier period based on the dynamic period adjustment parameters. Assuming a period adjustment of ±5%, if the adjustment parameter increases by 5%, then the target carrier period = reference carrier period × (1 + 5%); if the adjustment parameter decreases by 5%, then the target carrier period = reference carrier period × (1 - 5%).

[0066] S3-3-2. Adjust the carrier period of the controller according to the target carrier period to obtain the adjusted carrier period; The controller incorporates a carrier cycle adjustment module. The calculated target carrier cycle is input into this module, which adjusts the current carrier cycle to the target value by changing the clock signal frequency or counting period. During adjustment, the smoothness of cycle changes is monitored in real time to prevent system oscillations caused by sudden, large adjustments. For example, for adjustments with large deviations of ±5%, a smooth transition can be achieved through staged fine-tuning. This step transforms the theoretically calculated target cycle into the controller's actual operating cycle, laying the foundation for adjusting the instruction cache consumption rate.

[0067] S3-3-3: Based on the adjusted carrier period, perform detection processing to obtain the instruction buffer status and the controller instruction input rate; After adjusting the carrier period, continuously collect the real-time fill amount of the instruction buffer, i.e. the number of unexecuted instructions in the current buffer, and the input rate of control instructions, i.e. the number of instructions input per unit time.

[0068] S3-3-4. Based on the instruction cache state and the controller instruction input rate combined with the control instruction rate matching judgment condition, obtain the control instruction rate matching result; When the real-time fill amount of the instruction buffer and the controller instruction input rate meet the control instruction rate matching criteria, the control instruction rate is considered successfully matched, and this is taken as the control instruction rate matching result. If the real-time fill amount of the instruction buffer and the controller instruction input rate do not meet the control instruction rate matching criteria, the control instruction rate is considered unsuccessfully matched, and the system must return to the comprehensive error calculation stage to re-acquire adjustment parameters and re-adjust the cycle until the matching criteria are met. This step, through closed-loop detection and feedback, ensures that the system ultimately achieves stable rate matching.

[0069] In summary, steps S3-3-1 to S3-3-4 combine the dynamic period adjustment parameters with the reference carrier period to calculate the target period, and smoothly adjust the carrier period, thereby detecting the buffer status and command input rate in real time to obtain the matching result. This process achieves dynamic matching of the control command rate through a closed-loop feedback mechanism, effectively improving the control accuracy and stability of the system, and avoiding command buffer overflow or idling problems caused by rate mismatch.

[0070] Furthermore, the control command rate matching determination condition is as follows: The instruction cache state is stable within a preset range, and the controller instruction input rate is less than the controller instruction input rate threshold.

[0071] The matching criteria are set as follows: when the buffer fill amount is stable within a preset range, and the deviation between the input rate determined by the carrier period and the buffer consumption rate, i.e., the controller command input rate threshold, is less than 5%. In this embodiment, the preset range is set to 30%-70% of the total capacity.

[0072] Those skilled in the art will understand that embodiments of the present invention can be provided as methods, systems, or computer program products. Therefore, the present invention can take the form of a completely hardware embodiment, a completely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, the present invention can take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0073] This invention is described with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of this application. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, generate instructions for implementing the flowchart illustrations and / or block diagrams. Figure 1 One or more processes and / or boxes Figure 1 A device that provides the functions specified in one or more boxes.

[0074] These computer program instructions may also be stored in a computer-readable storage medium that can direct a computer or other programmable data processing device to function in a particular manner, such that the instructions stored in the computer-readable storage medium produce an article of manufacture including instruction means, which are implemented in a process Figure 1 One or more processes and / or boxes Figure 1 The function specified in one or more boxes.

[0075] These computer program instructions may also be loaded onto a computer or other programmable data processing equipment to cause a series of operational steps to be performed on the computer or other programmable equipment to produce a computer-implemented process, thereby providing instructions that execute on the computer or other programmable equipment for implementing the process. Figure 1 One or more processes and / or boxes Figure 1 The steps of the function specified in one or more boxes.

[0076] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and not to limit it. Although the present invention has been described in detail with reference to the above embodiments, those skilled in the art should understand that modifications or equivalent substitutions can still be made to the specific implementation of the present invention. Any modifications or equivalent substitutions that do not depart from the spirit and scope of the present invention should be covered within the scope of protection of the claims of the present invention.

Claims

1. A method for matching control command rates between a distributed controller and a driver, characterized in that, include: S1. Use the driver's clock source to detect the command frequency and obtain the frequency error value of the controller command; S2. Based on the frequency error value of the controller command, perform interpolation caching on the controller command to obtain the frequency error information of the command cache; S3. Perform dynamic periodic adjustment based on the frequency error value of the controller command and the frequency error information of the command cache to obtain the control command rate matching result.

2. The control command rate matching method for a distributed controller-driver according to claim 1, characterized in that, S1. Utilize the driver's clock source to detect the command frequency and obtain the frequency error value of the controller command, including: The dual timers are initialized based on the clock source of the driver, and the dual timers include a first timer and a second timer; The actual control command cycle is obtained using the first timer based on the clock source of the driver; The theoretical control command cycle is generated using the second timer; The actual control command cycle is compared with the theoretical control command cycle to obtain the frequency error value of the controller command.

3. The control command rate matching method for a distributed controller-driver according to claim 2, characterized in that, The actual control command cycle is compared with the theoretical control command cycle to obtain the frequency error value of the controller command, including: The actual controller command frequency and the theoretical controller command frequency are calculated using the actual control command cycle and the theoretical control command cycle, respectively. The error between the actual controller command frequency and the theoretical controller command frequency is calculated, and the relative frequency error between the actual controller command frequency and the theoretical controller command frequency is obtained as the relative frequency error of the controller command. A reference time interval is set based on the relative frequency error of the controller command and the relative frequency error of the corresponding historical control command. The frequency error value of the controller command is obtained based on the relative frequency error between the reference time interval and the controller command.

4. The control command rate matching method for a distributed controller-driver according to claim 2, characterized in that, S2. Based on the frequency error value of the controller command, perform interpolation buffering processing on the controller command to obtain the frequency error information of the command buffer, including: Based on the frequency error value of the controller command, set the interpolation factor and the frequency error threshold; Determine whether the frequency error value of the controller command is greater than or equal to the frequency error threshold. If so, obtain linear interpolation as a smooth interpolation algorithm and execute the first operation; otherwise, obtain spline interpolation as a smooth interpolation algorithm and execute the first operation. The first operation is as follows: using the interpolation factor and the smooth interpolation algorithm to perform interpolation caching on the controller instructions, and obtaining the frequency error information of the instruction cache.

5. The control command rate matching method for a distributed controller-driver according to claim 4, characterized in that, The controller instructions are interpolated and cached using the interpolation factor and the smooth interpolation algorithm to obtain frequency error information of the instruction cache, including: Based on the interpolation factor, the controller instructions are smoothly interpolated using the smooth interpolation algorithm to obtain a smoothly interpolated controller instruction sequence. The controller instruction sequence of the smooth interpolation is cached to obtain the change in the cached instructions; Based on the change in cached instructions, the interpolation factor, and the theoretical control instruction cycle, the frequency error information of the instruction cache is obtained.

6. The control command rate matching method for a distributed controller-driver according to claim 1, characterized in that, S3. Perform dynamic periodic adjustment based on the frequency error value of the controller command and the frequency error information of the command cache to obtain the control command rate matching result, including: The frequency error value of the controller command is weighted and fused with the frequency error information of the command cache to obtain a comprehensive error value; Based on the comprehensive error value, determine the dynamic periodic adjustment parameters; The carrier period of the controller is adjusted using the dynamic period adjustment parameters to obtain the control command rate matching result.

7. The control command rate matching method for a distributed controller-driver according to claim 6, characterized in that, The frequency error value of the controller command and the frequency error information of the command cache are weighted and fused to obtain a comprehensive error value, including: Based on the frequency error value of the controller command, set the frequency error threshold of the controller command as the coarse error threshold; Determine whether the frequency error value of the controller instruction is greater than the coarse error threshold. If so, obtain the frequency error value weight of the first controller instruction and the frequency error information weight of the first instruction cache as the weight allocation result, and perform the second operation. Otherwise, obtain the frequency error value weight of the second controller instruction and the frequency error information weight of the second instruction cache as the weight allocation result, and perform the second operation. The second operation is as follows: based on the weight allocation result, the frequency error value of the controller instruction and the frequency error information of the instruction cache are weighted and fused to obtain a comprehensive error value.

8. The control command rate matching method for a distributed controller-driver according to claim 6, characterized in that, Based on the comprehensive error value, the dynamic periodic adjustment parameters are determined, including: Based on the comprehensive error value, a comprehensive error threshold is set; Determine whether the overall error value is greater than the overall error threshold. If so, obtain the dynamic periodic adjustment parameter using a lookup table based on the overall error value. Otherwise, input the overall error value into the PI controller to obtain the dynamic periodic adjustment parameter.

9. The control command rate matching method for a distributed controller-driver according to claim 6, characterized in that, Adjusting the carrier period of the controller using the dynamic period adjustment parameters to obtain the control command rate matching result includes: The target carrier period is calculated using the aforementioned dynamic period adjustment parameters; The carrier period of the controller is adjusted according to the target carrier period to obtain the adjusted carrier period; Based on the adjusted carrier period, detection processing is performed to obtain the instruction buffer status and the controller instruction input rate; Based on the instruction cache status and the controller instruction input rate combined with the control instruction rate matching determination condition, the control instruction rate matching result is obtained.

10. A control command rate matching method for a distributed controller-driver according to claim 9, characterized in that, The control command rate matching determination condition is as follows: The instruction cache state is stable within a preset range, and the controller instruction input rate is less than the controller instruction input rate threshold.

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