Semiconductor electrical property measuring structure, measuring device and measuring method

Abstract

The invention provides a semiconductor electrical property measurement structure, which comprises a test array, the test array comprises a plurality of test units, the plurality of test units are distributed in a matrix, each test unit comprises at least two transistors, the plurality of transistors are electrically connected in sequence, and in the test units, adjacent transistors share the same electrode; in the test array, the middle electrodes of part of the test units are grounded, the edge electrodes serve as first signal output ends, the middle electrodes of the other part of the test units serve as second signal output ends, and the edge electrodes are grounded; when the electrode of the transistor is in a high-resistance state, the output current of the test unit is reduced, and the decreasing amplitude range of the output current represents the type of the electrode in the high-resistance state in the test unit. According to the invention, the distribution behavior of a small number of defective via holes in a large number of dense via holes can be monitored, and the positions of the defective via holes can be positioned.

Description

Technical Field

[0001] This invention relates to the field of semiconductor manufacturing technology, and in particular to a semiconductor electrical measurement structure, measurement device and measurement method. Background Technology

[0002] As semiconductor device dimensions shrink, more and more devices are integrated within a unit area. Vias are critical structures in semiconductor devices used to connect metal wires or device endpoints between different layers. Therefore, as device dimensions shrink, via sizes also decrease and their numbers increase. The processes associated with vias and the surrounding pattern become important factors affecting yield.

[0003] In semiconductor products, especially semiconductor memory products using array device patterns, the high pattern density of gates and vias means that defects in some vias within the product can negatively impact product performance and production yield. When a small number of vias have high resistance but are not open-circuited, it is difficult to locate the high-resistance vias during electronic scanning imaging. While measuring each via individually can provide accurate monitoring, it is impossible to detect the distribution behavior of a small number of defective vias within a large number of densely packed vias during mass production. Summary of the Invention

[0004] The purpose of this invention is to provide a semiconductor electrical measurement structure, measurement device and measurement method that can monitor the distribution behavior of a small number of defective vias in a large number of dense vias and locate the position of the defective vias.

[0005] To solve the above-mentioned technical problems, the present invention is achieved through the following technical solution: The present invention provides a semiconductor electrical measurement structure, including a test array, the test array including multiple test units, and the multiple test units are arranged in a matrix, wherein each test unit includes at least two transistors, and the multiple transistors are electrically connected in sequence, and adjacent transistors in the test unit share the same electrode; In the test array, the middle electrode of some of the test units is grounded and the edge electrode is used as a first signal output terminal, while the middle electrode of another part of the test units is used as a second signal output terminal and the edge electrode is grounded. When the electrodes of the transistor are in a high-resistance state, the output current of the test unit decreases, and the range of the decrease in the output current characterizes the type of electrode in the test unit that is in a high-resistance state.

[0006] In one embodiment of the present invention, the test array includes: Multiple first vias, the first end of which is connected to the electrode of the transistor; A first metal layer is electrically connected to a portion of the second end of the first via, and the first metal layer is grounded; and The second metal layer is electrically connected to the second end of another portion of the first via, and the second metal layer serves as the signal output terminal of the test array and is electrically connected to the host computer.

[0007] In one embodiment of the present invention, the measurement structure includes an interlayer dielectric layer disposed between the transistor and the first metal layer and between adjacent metal layers, wherein the second metal layer is located on the side of the first metal layer away from the transistor, and the extension distribution direction of the second metal layer is perpendicular to the extension distribution direction of the first metal layer.

[0008] In one embodiment of the present invention, the test array includes: Multiple first address lines are used to locate the row where the test unit is located, the first metal layer is distributed according to the first address lines, wherein the first address lines are allowed to be selected by the host computer; and Multiple second address lines are used to locate the column where the test unit is located, and the second metal layer is distributed according to the second address lines, wherein the second address lines are allowed to be selected by the host computer.

[0009] In one embodiment of the present invention, the test array includes a plurality of first-type test units and a plurality of second-type test units, wherein the first-type test units and the second-type test units are randomly distributed or distributed in the test array in a preset manner; In the first type of test unit, the middle electrode is the source electrode and the source electrode is grounded, and the edge electrode is the drain electrode and the drain electrode is the first signal output terminal; In the second type of test unit, the middle electrode is the drain electrode and the drain electrode is grounded, and the edge electrode is the source electrode and the source electrode is the second signal output terminal.

[0010] In one embodiment of the present invention, in the test unit, when the first via connected to the drain electrode is in a high resistance state, the current signal output by the test unit has a reduction amplitude greater than a first reduction amplitude and less than a second reduction amplitude compared to the reference signal. When the first via connected to the source electrode is in a high resistance state, the current signal output by the test unit has a reduction amplitude greater than the second reduction amplitude compared to the reference signal, wherein the second reduction amplitude is greater than the first reduction amplitude.

[0011] This invention provides a semiconductor electrical measurement device, comprising: A semiconductor electrical measurement structure as described above, wherein the semiconductor electrical measurement structure includes a test array; An address encoder is electrically connected to the test array and is used to select any test unit in the test array; The control module is electrically connected to the address encoder and sends address signals to the address encoder; and The data output module is electrically connected to the first signal output terminal and the second signal output terminal of the test unit, and outputs the current signal of the selected test unit.

[0012] In one embodiment of the present invention, the control module or host computer is electrically connected to the data output module and obtains the decrease in the current signal compared to the reference signal; When the decrease in the current signal is greater than the first decrease and less than the second decrease, the via connected to the drain electrode in the test unit is at high resistance, and the control module or the host computer outputs the first logic signal. When the decrease in the current signal is greater than the second decrease, the via connected to the source electrode in the test unit is at a high resistance, and the control module or the host computer outputs a second logic signal, wherein the second decrease is greater than the first decrease.

[0013] In one embodiment of the present invention, the semiconductor electrical measurement structure, the address encoder, the control module and the data output module are disposed on the same wafer.

[0014] This semiconductor electrical measurement method, based on the semiconductor electrical measurement structure described above, includes the following steps: The current signals of the test units in the semiconductor electrical measurement structure are obtained by traversing through them; Compare the current signal and the reference signal, and obtain the decrease in the current signal compared to the reference signal; and Based on the range of decrease in the current signal, the type of electrode in the test unit that is in a high-resistance state is identified.

[0015] As described above, this invention provides a semiconductor electrical measurement structure, measurement device, and measurement method. The unexpected technical effects of this invention are: the testing method provided is suitable for mass production testing and can distinguish between high-resistance defects in source or drain vias, accurately locating the specific location of each defect. The electrical measurement structure provided by this invention exhibits high detection sensitivity and accuracy. Specifically, in source-grounded mode, drain via resistance can be detected by a linear decrease in current, while in drain-grounded mode, source via resistance can be detected by an exponential decrease in current, covering resistance anomalies from minor to severe. The matrix arrangement of this invention can simulate high-density circuits, ensuring that the detection results are consistent with actual chip behavior. Furthermore, through large-scale data statistics, it can identify process fluctuations and guide process debugging. This invention can significantly improve the detection rate and yield control accuracy of via defects, and is suitable for testing advanced process memory arrays and high-reliability chips.

[0016] Of course, any product implementing this invention does not necessarily need to achieve all of the advantages described above at the same time. Attached Figure Description

[0017] To more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0018] Figure 1 This is a schematic diagram of the test device in one embodiment of the present invention.

[0019] Figure 2 This is a schematic diagram of the via structure in a semiconductor device according to an embodiment of the present invention.

[0020] Figure 3 This is a schematic diagram of the distribution structure of the test array in one embodiment of the present invention.

[0021] Figure 4 This is a schematic diagram of the structure of the first type of test unit in one embodiment of the present invention.

[0022] Figure 5 This is a schematic diagram of the structure of the second type of test unit in one embodiment of the present invention.

[0023] Figure 6 This is a schematic diagram of the control module in one embodiment of the present invention.

[0024] In the diagram: 100, Control module; 110, Address gating unit; 120, Data acquisition unit; 130, Data analysis unit; 200, First encoder; 300, Second encoder; 400, Test array; 410, First type of test unit; 420, Second type of test unit; 500, Substrate; 501, Active region; 502, Isolation structure; 503, Interlayer dielectric layer; 504, Polysilicon layer; M, Interconnect layer; CT, Via; D, Drain electrode; S, Source electrode; CT1, First via; CT2, Second via; M1, First metal layer; M2, Second metal layer; GND, Ground terminal; D_OUT, Output terminal; 600, Data output module. Detailed Implementation

[0025] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0026] Please see Figure 1 and Figure 2 As shown, the semiconductor electrical measurement structure and method provided by this invention are used to test the resistance deviation of via CTs, and this invention can monitor and acquire the resistance distribution behavior of a large number of dense via CTs. The semiconductor electrical measurement structure provided by this invention is disposed on a test wafer or a multi-project wafer (MPW), and the semiconductor electrical measurement structure is disposed in the core region of the wafer. The core region refers to the region on the wafer excluding the edge region and redundant region. The semiconductor measurement structure provided by this invention is manifested as a test array 400. The test array 400 can be used as the object under test and is electrically connected to a test device. In this embodiment, the test device includes a control module 100, a first encoder 200, a second encoder 300, and a data output module 600. The measurement method provided by this invention can be stored in a storage medium in the form of firmware. When the control module 100 calls and runs the firmware in the storage medium, the semiconductor electrical measurement method provided by this invention can be implemented. Specifically, the control module 100 can call the first encoder 200, the second encoder 300, the test array 400, and the data output module 600 to acquire test data. Based on the acquired test data, the control module 100 can actively analyze the test data and simulate the resistance distribution of the vias in the test array 400.

[0027] Please see Figure 1 and Figure 3As shown, in one embodiment of the present invention, the semiconductor electrical measurement structure includes a test array 400. The test array 400 includes multiple test units arranged in a matrix. Each test unit includes at least two transistors, and the transistors are sequentially electrically connected. In this embodiment, sequential electrical connection refers to the sequential arrangement of the transistors and the sequential connection of their electrodes. Adjacent transistors in a test unit share the same electrode. In this embodiment, the transistor is a MOS transistor, and the transistor includes a source electrode S, a gate electrode, and a drain electrode D. When voltage is applied to the gate electrode, the channel between the source electrode S and the drain electrode D is turned on, and the MOS transistor is activated. In this embodiment, the number of transistors in one test unit is, for example, two. Figure 3 The first and second transistors are shown. The first and second transistors share a common source electrode S or drain electrode D, and their gate electrodes are electrically connected to the power supply terminal. According to the conduction sequence set by the control module 100, the test unit is selected and turned on, thereby realizing the output of a current signal. The semiconductor electrical measurement structure provided by this invention can simulate the real circuit environment of a product. In this embodiment, the test unit adopts a design where at least two transistors share the same electrode and are arranged in a matrix, with a dense arrangement consistent with the high-density via CT environment of actual memory arrays. This structure can more realistically simulate the process defects and resistance distribution behavior of via CTs in actual circuits. Furthermore, by statistically measuring the large-scale matrix-distributed test unit, the tail behavior of the resistance distribution of via CTs can be captured, avoiding a decrease in overall yield due to a few defects. Moreover, the large-scale matrix-distributed test unit set by this invention eliminates random noise interference through statistical regularity, ensuring the reliability of the test results. The large-scale test unit refers to a test array 400 with a size of, for example, 512kB to 2MB.

[0028] Please see Figure 1 , Figures 3 to 5As shown, in one embodiment of the present invention, in the test array 400, the middle electrode of some test units is grounded, and the edge electrode serves as the first signal output terminal D_OUT; the middle electrode of another part of the test units serves as the second signal output terminal D_OUT, and the edge electrode is grounded. The middle electrode is the common electrode of adjacent transistors in the test unit, and the edge electrode is the non-common electrode located at the edge of the transistor connection chain in the test unit. In this invention, a dual-mode electrode configuration is adopted. By the difference in output current between the two modes, high-resistance defects of source via CTs or drain via CTs can be distinguished, and the location of high-resistance via CTs can be accurately located. Specifically, in this embodiment, in the first mode, the middle electrode in the test unit is grounded, and the edge electrode serves as the output terminal D_OUT. This allows for focused monitoring of the resistance of the via CT connected to the drain electrode D. When the via CT connected to the drain electrode D has high resistance, the output current will decrease slightly due to the voltage division effect. In the second mode, the edge electrode of the test unit is grounded, and the middle electrode serves as the output terminal D_OUT. This mode focuses on monitoring the resistance of the via CT connected to the source electrode S. When the via CT connected to the source electrode S has high resistance, it significantly increases the source voltage, causing a decrease in the gate-source voltage. Simultaneously, the threshold voltage of the transistor increases, resulting in a substantial decrease in the output current. In this embodiment, without switching between the ground terminal GND and the output terminal D_OUT of the first type of test unit 410, the location of the high-resistance via CT can be determined by comparing the current data with a reference current and based on the magnitude of the decrease in the current data compared to the reference current. Therefore, this invention employs a shared electrode design, where adjacent transistors share an electrode, forcing the current to be conducted through the via CT under test. This further amplifies the impact of the high-resistance via CT on the output current, improving detection sensitivity.

[0029] Please see Figure 1 , Figures 3 to 5 As shown, it should be noted that the electrical measurement structure of the present invention uses a standard MOS transistor design, requiring no special process and can be directly integrated into the wafer. Furthermore, it can adapt to the testing requirements of different process nodes by adjusting the matrix size or transistor type. Adjusting the matrix size, for example, involves increasing the number of test cells in the test array 400. The transistor type refers to setting the transistors as NMOS transistors or PMOS transistors. It should be noted that multiple transistors in the test cells of the present invention are of the same type. In one embodiment of the present invention, the test cells in the test array 400 can use different transistor types. In another embodiment of the present invention, all test cells in the test array 400 can use the same transistor type, thereby adapting to the testing requirements of different process nodes.

[0030] Please see Figure 1 and Figure 3As shown, in one embodiment of the present invention, a test array 400 is disposed on a wafer. The transistor includes a substrate 500, an isolation structure 502, an interlayer dielectric layer 503, a via CT, and an interconnect layer M. The substrate 500 is a silicon substrate used to form the semiconductor structure. The isolation structure 502 is disposed in the substrate 500 and isolates multiple active regions 501 within the substrate 500. In this embodiment, the isolation structure 502 is formed using a shallow trench isolation (STI) process. Ion implantation is performed on the active regions 501 to form multiple doped regions, thereby forming the drain electrode D and source electrode S of the transistor. A polysilicon layer 504 is then formed on the active regions 501, and the polysilicon layer 504 is patterned to form the gate electrode of the transistor. In this embodiment, the critical dimensions of the transistor can be consistent with the critical dimensions of the product to simulate the product's process environment as closely as possible. The substrate 500, source electrode S, drain electrode D, and gate electrode form the device layer of the semiconductor electrical measurement structure. In this embodiment, an interlayer dielectric layer 503 is disposed on the device layer and is used to isolate the device layer and the metal interconnect structure. In this embodiment, one end of the via CT passes through the interlayer dielectric layer 503 and is electrically connected to the electrode of the transistor, or to an interconnect layer M. The other end of the via CT is electrically connected to the interconnect layer M. The interconnect layer M is a base layer in a semiconductor stack structure and is used to connect various semiconductor devices to form an integrated circuit.

[0031] Please see Figure 1 , Figures 3 to 5 As shown, in one embodiment of the present invention, the electrical measurement structure includes multiple first vias CT1, multiple second vias CT2, a first metal layer M1, and a second metal layer M2. The first end of each first via CT1 is connected to the source electrode S or drain electrode D of the transistor, and the second end of each first via CT1 passes through the interlayer dielectric layer 503 and is connected to either the first metal layer M1 or the second metal layer M2. The first metal layer M1 is grounded, and the second metal layer M2 serves as the signal output terminal D_OUT of the electrical measurement structure. A current signal can be output through the signal output terminal D_OUT. In this embodiment, the second metal layer M2 is located above the first metal layer M1, and the second metal layer M2 and the first metal layer M1 can be adjacent layers or separated by multiple interconnect layers M. In this embodiment, the second metal layer M2 is located on the side of the first metal layer M1 away from the transistor, and the extension direction of the second metal layer M2 is perpendicular to the extension direction of the first metal layer M1. For example, the horizontal direction X is set as the first direction, and the vertical direction Y is set as the second direction. The first metal layer M1 extends along the first direction, and the second metal layer M2 extends along the second direction. In this embodiment, the first end of the second via CT2 is connected to the gate electrode, and there can be multiple second vias CT2 connected to the gate electrode.

[0032] Please see Figure 1 , Figures 3 to 5 As shown, in one embodiment of the present invention, the electrical measurement structure includes a polysilicon layer 504 disposed on a substrate 500. Patterning the polysilicon layer 504 can form the gate layer of a transistor. In this embodiment, there are multiple polysilicon layers 504, and the polysilicon layers 504 can extend in a predetermined direction, for example, in a direction perpendicular to the transistor connection direction of the test unit. The polysilicon layer 504 covers the active regions 501 of multiple transistors and simultaneously serves as the gate electrode of multiple transistors. A high voltage is applied to the second via CT2, and the gate electrodes of multiple transistors are simultaneously turned on, thereby achieving simultaneous conduction of multiple transistors. The coverage pattern of the polysilicon layer 504 provided in this embodiment is only an example. In other embodiments of the present invention, the coverage pattern scheme of the polysilicon layer 504 can be adjusted according to different test requirements or test scales. For example, a polysilicon layer 504 connecting multiple transistors can be provided, or a polysilicon layer 504 connecting a single transistor can be provided.

[0033] Please see Figure 1 , Figures 3 to 5 As shown, in one embodiment of the present invention, the test array 400 includes multiple first address lines and multiple second address lines. The first address lines are used to locate the row containing the test unit. In this embodiment, the first metal layer M1 can be distributed according to the first address lines, and the first address lines can be selected by the host computer. The multiple second address lines are used to locate the column containing the test unit. In this embodiment, the second metal layer M2 is distributed according to the second address lines, and the second address lines can be selected by the host computer. During testing, when a continuity test is to be performed on any test unit in the test array 400, the corresponding test unit can be precisely selected by selecting the corresponding first address line and second address line. In this embodiment, each address line has a unique corresponding number.

[0034] Please see Figure 1 , Figures 3 to 5 As shown, in one embodiment of the present invention, the test array 400 includes a plurality of first-type test units 410 and a plurality of second-type test units 420. The first-type test units 410 and the second-type test units 420 are randomly distributed or distributed in the test array 400 according to a preset method. Regarding the preset distribution method, as... Figure 1 and Figure 3As shown, multiple first-type test units 410 share a common gate electrode and are distributed along the extension direction of the polysilicon layer 504. Multiple second-type test units 420 share a common gate electrode and are also distributed along the extension direction of the polysilicon layer 504. The array rows of the multiple first-type test units 410 and the array rows of the multiple second-type test units 420 can be staggered. In this invention, the distribution of the first-type test units 410 and the second-type test units 420 in the test array 400 can be adjusted by adjusting the distribution of the polysilicon layer 504. In another embodiment of this invention, a first region and a second region can be provided, with the first region used to distribute the first-type test units 410 and the second region used to distribute the second-type test units 420. This approach can better distinguish the test results of the first-type test units 410 and the second-type test units 420 and control the conduction test process of the first region and the second region.

[0035] Please see Figure 1 , Figures 3 to 5 As shown, in one embodiment of the present invention, in the first type of test unit 410, the middle electrode is the source electrode S and the source electrode S is grounded, and the edge electrode is the drain electrode D and the drain electrode D is the first signal output terminal D_OUT. In the second type of test unit 420, the middle electrode is the drain electrode D and the drain electrode D is grounded, and the edge electrode is the source electrode S and the source electrode S is the second signal output terminal D_OUT.

[0036] Please refer to Figure 1 , Figures 3 to 5As shown, in one embodiment of the present invention, the semiconductor electrical measurement device includes a semiconductor electrical measurement structure and peripheral circuitry. In this embodiment, the peripheral circuitry includes a first encoder 200, a second encoder 300, a data output module 600, and a control module 100. The control module 100 can be a logic circuit capable of implementing the semiconductor electrical measurement method provided by the present invention, or it can be a processor capable of calling firmware to implement the measurement method of the present invention, such as an ARM processor. When the control module 100 is a logic circuit, the control module 100 can be formed on the same wafer as the semiconductor electrical measurement structure provided by the present invention, and the control module 100 can serve as peripheral circuitry. The control module 100 is electrically connected to a host computer and can acquire current data of the semiconductor electrical measurement structure according to the timing signals and control instructions set by the host computer. The host computer is used to set the control commands and timing signals required for measurement, and converts these parameters into electrical signals that the control module 100 (logic circuit) can recognize, ensuring that the measurement actions are executed in an orderly manner according to preset logic. Control commands include, for example, starting / stopping current acquisition and setting the current acquisition accuracy range. Timing signals include, for example, the time interval between the control module 100 driving the measurement structure to acquire data and the signal triggering sequence. Furthermore, after acquiring current data from the semiconductor measurement structure, the control module 100 uploads the data to the host computer, which then collects the current data. In this embodiment, both the first encoder 200 and the second encoder 300 are address encoders. The first encoder 200 is electrically connected to the first address line and the control module 100, and can receive address signals from the control module 100, decode the address signals to obtain specific address information, and thus select the first address line corresponding to the address information. The second encoder 300 is electrically connected to the second address line and the control module 100, and can receive address signals from the control module 100, decode the address signals to obtain specific address information, and thus select the second address line corresponding to the address information. Specifically, the first address line can be used to locate the row where the test unit is located, and the second address line can be used to locate the column where the test unit is located.

[0037] Please refer to Figure 1 , Figures 3 to 5 As shown, in one embodiment of the present invention, the control module 100 may further include a clock unit for outputting timing signals for selecting test units, thereby adjusting the selection order of each test unit. It should be noted that the timing signals output by the clock unit can be adjusted depending on the process used or the scale of the object to be tested. For example, by adjusting the timing, the first type of test unit 410 may be selected preferentially, or a certain column may be selected preferentially, or one or more test units that had problems in previous tests may be selected preferentially.

[0038] Please refer to Figure 1 , Figures 3 to 5As shown, in one embodiment of the present invention, the data output control module 100 includes, for example, an operational amplifier circuit and an output port D_OUT. In this embodiment, the operational amplifier circuit is electrically connected to the first signal output port D_OUT and the second signal output port D_OUT, amplifies the current signal, and outputs it through the output port D_OUT. The output port D_OUT is electrically connected to the host computer, transmitting the output current signal to the host computer. In this embodiment, the test unit in the test array 400 may further include a selection transistor. After the first encoder 200 and the second encoder 300 parse the address signal, they can select the selection transistor of the corresponding test unit and output the current signal of the corresponding test unit. The selection transistor is a MOSFET.

[0039] Please refer to Figure 1 , Figures 3 to 6 As shown, in one embodiment of the present invention, the control module 100 includes an address selection unit 110. The address selection unit 110 is electrically connected to the first encoder 200 and the second encoder 300, and is used to generate an address signal to select the corresponding test unit in the test array 400. In this embodiment, the data output module 600 is electrically connected to a host computer, and the host computer performs data analysis on the acquired current signal. In another embodiment of the present invention, the data acquisition unit 120 is electrically connected to the data output module 600, acquires the current signal, and converts the current signal into current data through analog-to-digital conversion. The data analysis unit 130 is electrically connected to the data acquisition unit 120 and acquires the current data of each test unit. It should be noted that the reference current used as a comparison reference in the test can be current data preset by the tester, or it can be the average current data of the test array 400. All test units in the test array 400 are transistors formed simultaneously using the same process. In this embodiment, if the current data of the test unit is less than the reference current, a high resistance condition occurs in the via current transformer (CT) of the test unit. In mass testing, abnormal test units can be directly identified through current data. In this embodiment, the data analysis unit 130 can be a comparator.

[0040] Please refer to Figure 1 , Figures 3 to 6As shown, in one embodiment of the present invention, taking an NMOS transistor as an example, the abnormal test unit is analyzed. If the test unit is a first type of test unit 410, the ground terminal GND is the central electrode and the source electrode S, and the output terminal D_OUT is the edge electrode and the drain electrode D. When reading the current of the test unit, the high resistance of the via CT at both ends has a smaller weakening effect on the read current, while the high resistance of the via CT at the middle position has a larger weakening effect on the read current. Therefore, when the drain electrode D is a high resistance via CT, the current data shows a slight decrease. When the source electrode S is a high resistance via CT, the current data shows a significant decrease. If the test unit is a second type of test unit 420, the ground terminal GND is the edge electrode and the source electrode S, and the output terminal D_OUT is the middle electrode and the drain electrode D. When reading the current of the test unit, the high resistance of the via CT at both ends has a larger weakening effect on the read current, while the high resistance of the via CT at the middle position has a smaller weakening effect on the read current. Therefore, when the drain electrode D is a via CT with high resistance, the current data shows a slight decrease. When the source electrode S is a via CT with high resistance, the current data shows a significant decrease.

[0041] It should be noted that the magnitude of the decrease (small or large) mentioned in this invention can be distinguished by setting a first threshold range and a second threshold range. For example, a decrease in current data of 0-20% is considered a small decrease. A decrease in current data of 20-50% is considered a large decrease.

[0042] Please see Figures 1 to 6As shown, the present invention provides a semiconductor electrical measurement structure, including a test array 400. The test array 400 includes multiple test units arranged in a matrix. Each test unit includes at least two transistors, and the transistors are electrically connected sequentially. Adjacent transistors in the test unit share the same electrode. In the test array 400, the middle electrode of some test units is grounded, and the edge electrode serves as a first signal output terminal D_OUT; the middle electrode of other test units serves as a second signal output terminal D_OUT, and the edge electrode is grounded. When the transistor electrode is in a high-resistance state, the output current of the test unit decreases, and the range of the output current decrease characterizes the type of electrode in the test unit that is in a high-resistance state. The present invention also provides a semiconductor electrical measurement device, including a semiconductor electrical measurement structure, an address encoder, a control module 100, and a data output module 600. The address encoder is electrically connected to the test array 400 and is used to select any test unit in the test array 400. The control module 100 is electrically connected to the address encoder and sends an address signal to the address encoder. The data output module 600 is electrically connected to the first signal output terminal D_OUT and the second signal output terminal D_OUT of the test unit, and outputs the current signal of the selected test unit.

[0043] The unexpected technical advantages of this invention are as follows: The testing method provided by this invention is suitable for mass testing and can distinguish between high-resistance defects in source or drain vias, accurately locating the specific location of each defect. The electrical measurement structure provided by this invention exhibits high detection sensitivity and accuracy. Specifically, in source-grounded mode, drain via resistance can be detected by a linear decrease in current, while in drain-grounded mode, source via resistance can be detected by an exponential decrease in current, covering resistance anomalies from minor to severe. The matrix arrangement of this invention can simulate high-density circuits, ensuring that the detection results are consistent with the actual chip behavior. Furthermore, through large-scale data statistics, it can identify process fluctuations and guide process debugging. This invention can significantly improve the detection rate and yield control accuracy of via defects, and is suitable for testing advanced process memory arrays and high-reliability chips.

[0044] The embodiments of the present invention disclosed above are merely illustrative of the invention. The embodiments do not exhaustively describe all details, nor do they limit the invention to the specific implementations described. Clearly, many modifications and variations can be made based on the content of this specification. This specification selects and specifically describes these embodiments to better explain the principles and practical applications of the invention, thereby enabling those skilled in the art to better understand and utilize the invention. The invention is limited only by the claims and their full scope and equivalents.

Claims

1. A semiconductor electrical measurement structure, characterized in that, The test array includes multiple test units arranged in a matrix, wherein each test unit includes at least two transistors and the transistors are electrically connected in sequence, and adjacent transistors in the test unit share the same electrode. In the test array, the middle electrode of some of the test units is grounded and the edge electrode is used as a first signal output terminal, while the middle electrode of another part of the test units is used as a second signal output terminal and the edge electrode is grounded. When the electrodes of the transistor are in a high-resistance state, the output current of the test unit decreases, and the range of the decrease in the output current characterizes the type of electrode in the test unit that is in a high-resistance state.

2. The semiconductor electrical measurement structure according to claim 1, characterized in that, The test array includes: Multiple first vias, the first end of which is connected to the electrode of the transistor; A first metal layer is electrically connected to a portion of the second end of the first via, and the first metal layer is grounded; and The second metal layer is electrically connected to the second end of another portion of the first via, and the second metal layer serves as the signal output terminal of the test array and is electrically connected to the host computer.

3. The semiconductor electrical measurement structure according to claim 2, characterized in that, The measurement structure includes an interlayer dielectric layer disposed between the transistor and the first metal layer, and between adjacent metal layers, wherein the second metal layer is located on the side of the first metal layer away from the transistor, and the extension direction of the second metal layer is perpendicular to the extension direction of the first metal layer.

4. The semiconductor electrical measurement structure according to claim 2, characterized in that, The test array includes: Multiple first address lines are used to locate the row where the test unit is located, the first metal layer is distributed according to the first address lines, wherein the first address lines are allowed to be selected by the host computer; and Multiple second address lines are used to locate the column where the test unit is located, and the second metal layer is distributed according to the second address lines, wherein the second address lines are allowed to be selected by the host computer.

5. A semiconductor electrical measurement structure according to claim 2, characterized in that, The test array includes multiple first-type test units and multiple second-type test units, which are randomly distributed or distributed in the test array according to a preset method. In the first type of test unit, the middle electrode is the source electrode and the source electrode is grounded, and the edge electrode is the drain electrode and the drain electrode is the first signal output terminal; In the second type of test unit, the middle electrode is the drain electrode and the drain electrode is grounded, and the edge electrode is the source electrode and the source electrode is the second signal output terminal.

6. The semiconductor electrical measurement structure according to claim 5, characterized in that, In the test unit, when the first via connected to the drain electrode is in a high resistance state, the current signal output by the test unit has a drop greater than a first drop and less than a second drop compared to the reference signal. When the first via connected to the source electrode is in a high resistance state, the current signal output by the test unit has a drop greater than a second drop compared to the reference signal, wherein the second drop is greater than the first drop.

7. A semiconductor electrical measurement device, characterized in that, include: A semiconductor electrical measurement structure as described in any one of claims 1 to 6, wherein the semiconductor electrical measurement structure includes a test array; An address encoder is electrically connected to the test array and is used to select any test unit in the test array; The control module is electrically connected to the address encoder and sends address signals to the address encoder; as well as The data output module is electrically connected to the first signal output terminal and the second signal output terminal of the test unit, and outputs the current signal of the selected test unit.

8. A semiconductor electrical measurement device according to claim 7, characterized in that, The control module or host computer is electrically connected to the data output module and obtains the decrease in the current signal compared to the reference signal; When the decrease in the current signal is greater than the first decrease and less than the second decrease, the via connected to the drain electrode in the test unit is at high resistance, and the control module or the host computer outputs the first logic signal. When the decrease in the current signal is greater than the second decrease, the via connected to the source electrode in the test unit is at a high resistance, and the control module or the host computer outputs a second logic signal, wherein the second decrease is greater than the first decrease.

9. A semiconductor electrical measurement device according to claim 7, characterized in that, The semiconductor electrical measurement structure, the address encoder, the control module, and the data output module are mounted on the same wafer.

10. A semiconductor electrical measurement method, based on the semiconductor electrical measurement structure as described in claim 1, characterized in that, Includes the following steps: The current signals of the test units in the semiconductor electrical measurement structure are obtained by traversing through them; Compare the current signal with the reference signal, and obtain the decrease in the current signal compared to the reference signal; as well as Based on the range of decrease in the current signal, the type of electrode in the test unit that is in a high-resistance state is identified.

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