Low-delay level shift circuit

Abstract

The invention provides a low-delay level shift circuit, and belongs to the technical field of analog integrated circuit power management, the circuit comprises a level shift core circuit and an edge detection logic circuit, the level shift core circuit adopts a high-voltage-resistant LDMOS to complete conversion of different voltage domain signals on the basis of a traditional cross coupling structure, and the edge detection logic circuit is connected with the edge detection logic circuit. The edge detection logic circuit detects a fast falling edge of the level shift core circuit, and an output signal only related to the fast edge is obtained after logic operation. The low-delay level shift circuit provided by the invention has no static power consumption, the delay of the level shift circuit can be reduced to below 1ns, the delay time of the low-delay level shift circuit is obviously reduced compared with the delay time of a traditional two-stage cross coupling level shift circuit, and the low-delay level shift circuit is suitable for the field of SiC MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) driving with higher requirements on propagation delay.

Description

Technical Field

[0001] This invention relates to the field of analog integrated circuit power management technology, and in particular to a low-delay level shifting circuit. Background Technology

[0002] As power electronic systems develop towards higher frequencies, higher efficiency, and higher temperatures, SiC MOSFETs, with their excellent material properties (such as high breakdown field strength, high thermal conductivity, and high electron mobility), are gradually becoming core power devices in high-voltage and high-temperature applications (such as new energy vehicles, rail transit, and smart grids). In addition, the high-frequency switching characteristics of SiC devices (reaching hundreds of kHz or even MHz) place stringent requirements on the transmission delay of drive signals.

[0003] Typically, SiC MOSFETs operate at a drive voltage of 18–20V. However, the safe operating range of the gate-source voltage for on-chip thin-gate oxide devices is only around 5V. Therefore, an on-chip level shifting circuit is needed to transmit signals from the low-voltage domain to the high-voltage domain. Since the level shifting circuit is a key component of the drive signal chain, reducing its delay is crucial for minimizing system propagation delay. Traditional level shifting circuits based on cross-coupling structures use NMOS pull-down transistors larger than PMOS pull-up transistors to break positive feedback, resulting in strong pull-down capabilities and weak pull-up capabilities. This leads to propagation delays typically around 10ns, making them unsuitable for high-frequency applications. Summary of the Invention

[0004] The purpose of this invention is to solve the problem that traditional level shifting circuits have high delays and are not suitable for high-frequency applications of SiC MOSFETs.

[0005] A low-delay level shifting circuit includes a level shifting core circuit and an edge detection logic circuit. The level shifting core circuit includes a first NMOS transistor, a second NMOS transistor, a third NMOS transistor, a fourth NMOS transistor, a first PMOS transistor, a second PMOS transistor, a third PMOS transistor, a fourth PMOS transistor, and a seventh inverter. The edge detection logic circuit includes a first inverter, a second inverter, a third inverter, a fourth inverter, a fifth inverter, a sixth inverter, a first NAND gate, a second NAND gate, a third NAND gate, a fourth NAND gate, and a first NOR gate.

[0006] Furthermore, the source of the first NMOS transistor is connected to the low-side ground VSSL, the drain is connected to the drain of the first PMOS transistor, and the gate is connected to the input terminal VIN of the seventh inverter; the output of the seventh inverter is connected to the gate of the second NMOS transistor, the source of the second NMOS transistor is connected to VSSL, and the drain is connected to the drain of the second PMOS transistor.

[0007] The gate of the first PMOS transistor is connected to the high-side ground VSSH, and the source is connected to the drain of the third NMOS transistor and the third PMOS transistor, as well as the input terminal of the first inverter; the gate of the second PMOS transistor is connected to VSSH, and the source is connected to the drain of the fourth NMOS transistor and the fourth PMOS transistor, as well as the input terminal of the second inverter.

[0008] The source of the third NMOS transistor is connected to VSSH, and its gate is connected to the gate of the third PMOS transistor and the output of the sixth inverter; the source of the fourth NMOS transistor is connected to VSSH, and its gate is connected to the gate of the fourth NMOS transistor and the output of the fifth inverter; the sources of the third and fourth PMOS transistors are connected to the power supply voltage VDDH.

[0009] The output of the first inverter is connected to the input of the fifth inverter and one input of the first NAND gate, the second NAND gate, and the third NAND gate; the output of the second inverter is connected to the input of the sixth inverter, one input of the fourth NAND gate, and the other input of the first NAND gate.

[0010] The output of the first NAND gate is connected to one input of the first NOR gate; the other input of the first NOR gate is connected to the output of the third NAND gate and the other input of the fourth NAND gate; the output of the fourth NAND gate is connected to the other input of the third NAND gate.

[0011] The output of the first NOR gate is connected to the input of the third inverter; the output of the third inverter is connected to the other input of the second NAND gate; the output of the second NAND gate is connected to the input of the fourth inverter; the output of the fourth inverter is connected to the output V. OUT .

[0012] Furthermore, the level shifting core circuit transmits the low-voltage domain signals VSSL~VDDL to the high-voltage domains VSSH~VDDH. When the input V... IN When the voltage changes from low to high, the first NMOS transistor turns on, the input voltage A of the first inverter is quickly pulled down, the output of the seventh inverter is low, the second NMOS transistor turns off, and the input voltage B of the second inverter is slowly pulled up by the fourth PMOS transistor MP4.

[0013] Furthermore, the rising edge delay is the delay of three logic gates, namely the first inverter, the second NAND gate, and the fourth inverter; the falling edge delay is the delay of six logic gates, namely the second inverter, the first NAND gate, the first NOR gate, the third inverter, the second NAND gate, and the fourth inverter.

[0014] The beneficial technical effects of this invention are as follows: The low-delay level shifting circuit proposed in this invention includes a level shifting core circuit and an edge detection logic circuit. The level shifting core circuit, based on the traditional cross-coupling structure, uses a high-voltage resistant LDMOS to complete the conversion of signals in different voltage domains. Through the designed edge detection logic circuit, the fast falling edge of the level shifting core circuit is detected. After logic operation, an output signal that is only related to the fast edge is obtained. That is, the output VOUT is only related to the falling edges of points A and B. The output voltage is determined only by the fast edge, which can significantly reduce the delay of the traditional level shifting circuit and is more suitable for high-frequency application scenarios of SiC MOSFET. Attached Figure Description

[0015] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0016] Figure 1 This is a schematic diagram of the structure of a conventional cross-coupled level shifting circuit provided in an embodiment of the present invention;

[0017] Figure 2 This is a schematic diagram of a low-delay level shifting circuit provided in an embodiment of the present invention;

[0018] Figure 3 This is a timing diagram of the low-delay level shifting circuit provided in an embodiment of the present invention;

[0019] Figure 4 This is a simulation waveform diagram of the low-delay level shifting circuit provided in the embodiment of the present invention. Detailed Implementation

[0020] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0021] Figure 1 A traditional cross-coupled level shifting circuit diagram is given, where VDDH is the power supply voltage, VSSH is the on-chip high-side ground, VDDL is the on-chip low-voltage power supply, and VSSL is the ground potential. When the input voltage V... INWhen the voltage is high, point A is pulled down while point B is pulled up. The difference between points A and B drives the cross-coupled NMOS transistor, thus affecting the voltage at node V. OUT Output high level. To achieve V IN When the voltage is high, point A can be pulled down normally. PMOS transistors are generally designed to be relatively small, therefore V... IN When the level is high, the pull-up speed at point B is limited, which affects the delay of the level shifting circuit.

[0022] Figure 2 This is a circuit diagram of a low-delay level shifting circuit proposed in this invention. The low-delay level shifting circuit includes a level shifting core circuit and an edge detection logic circuit, wherein VDDH is the power supply voltage, VSSH is the on-chip high-side ground, VDDL is the on-chip low-voltage power supply, and VSSL is the ground potential; V IN A is the input voltage of the seventh inverter, B is the input voltage of the first inverter, C is the output voltage of the first inverter, D is the output voltage of the second inverter, E is the output voltage of the first NAND gate, Q is the output voltage of the third NAND gate, F is the output voltage of the third inverter, and V is the input voltage of the seventh inverter. OUT It is the output voltage of the fourth inverter.

[0023] The level shifting core circuit can transmit low-voltage domain signals (VSSL~VDDL) to high-voltage domain signals (VSSH~VDDH). The level shifting core circuit includes a first NMOS transistor MN1, a second NMOS transistor MN2, a third NMOS transistor MN3, a fourth NMOS transistor MN4, a first PMOS transistor MP1, a second PMOS transistor MP2, a third PMOS transistor MP3, a fourth PMOS transistor MP4, and a seventh inverter INV7. Among them, the first NMOS transistor MN1, the second NMOS transistor MN2, the first PMOS transistor MP1, and the second PMOS transistor MP2 are all high-voltage LDMOS transistors.

[0024] The edge detection logic circuit includes a first inverter INV1, a second inverter INV2, a third inverter INV3, a fourth inverter INV4, a fifth inverter INV5, a sixth inverter INV6, a first NAND gate NAND1, a second NAND gate NAND2, a third NAND gate NAND3, a fourth NAND gate NAND4, and a first NOR gate NOR1.

[0025] The working principle is described as follows:

[0026] When the input signal V INWhen the voltage changes from low to high: the input voltage A of the first inverter is quickly pulled down by the first NMOS transistor MN1. The first inverter INV1, through a special design—increasing the size of the PMOS transistor and decreasing the size of the NMOS transistor—can quickly detect the drop in voltage at point A. At this time, the output voltage C of the first inverter INV1 quickly rises to a high level, with a delay of td1. Simultaneously, the output of the fifth inverter INV5 drops, MP4 turns on, MN4 turns off, and the voltage at point B rises. The rising voltage at point B causes the output of the second inverter INV2 to go low, the output of the sixth inverter INV6 to go high, MP3 to turn off, and MN3 to turn on, thus causing point A to drop to VSSH. The output voltage F of the third inverter INV3 is at V... IN The voltage remains high during the transition from low to high. Therefore, after the output voltage C of the first inverter INV1 becomes high, it is delayed by td2 after passing through the second NAND gate NAND2 and the fourth inverter INV4, resulting in the output V. OUT Change to high level, such as Figure 3 The timing diagram of the low-delay level shifting circuit is shown. From the above analysis, the rising edge delay is: t PLH =td1+td2, mainly refers to the delay of three logic gates: the first inverter INV1, the second NAND gate NAND2, and the fourth inverter INV4. The delay of a single logic gate is usually only 100ps to 200ps, so the total delay is very small.

[0027] When the input signal V IN When the voltage changes from high to low: the voltage at node B is pulled low by the second NMOS transistor MN2. The second inverter INV2 and the first inverter INV1 are designed identically, so the output voltage D of the second inverter rises rapidly, with a delay of td1. At this time, because point A is in a slow path, its voltage rises more slowly, and the pull-down capability of the first inverter INV1 is weak. Therefore, the output voltage C of the first inverter remains high for a period of time. The output voltage D of the second inverter is processed by the first NAND gate NAND1 to obtain the output voltage E of the first NAND gate, with a delay of td2. Simultaneously, the output of the sixth inverter INV6 goes low, turning on MP3 and turning off MP3. At point A, the voltage rises, then the output node C of the first inverter INV1 decreases, and the output of the fifth inverter INV5 rises. MP4 is turned off, and MN4 is turned on, thus pulling the voltage at point B down to VSSH. The output voltage E of the first NOR gate NOR1 passes through the first NOR gate NOR1 and the third inverter INV3 to reach the output voltage F of the third inverter, with a delay of td3. When the output voltage F of the third inverter INV3 drops to a low level, since the output voltage C of the first inverter is at a high level, the output voltage F of the third inverter INV3 passes through the second NAND gate NAND2 and the fourth inverter INV4 to reach the output VSSH. OUT V OUTIt goes low, with a delay of td4, as follows. Figure 3 The timing diagram of the low-delay level shifting circuit is shown. Therefore, the falling edge delay is t. PHL =td1+td2+td3+td4, mainly representing the delays of six logic gates: the second inverter INV2, the first NAND gate NAND1, the first NOR gate NOR1, the third inverter INV3, the second NAND gate NAND2, and the fourth inverter INV4. The delays are relatively low but higher than t. PLH .

[0028] Therefore, the rising and falling edge delays of the low-delay level shift circuit designed in this invention are the total delays of several logic gates, while the delay of a single logic gate is typically only 100ps to 200ps. Thus, the total circuit delay is less than 1ns. Figure 4 The simulation waveform of the low-delay level shifting circuit is shown in the figure. It is consistent with the above analysis principle, meets the low-delay design requirements, and is suitable for high-frequency application scenarios of SiC MOSFET.

[0029] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A low-delay level shifting circuit, characterized in that, The circuit includes a level shifting core circuit and an edge detection logic circuit. The level shifting core circuit includes a first NMOS transistor, a second NMOS transistor, a third NMOS transistor, a fourth NMOS transistor, a first PMOS transistor, a second PMOS transistor, a third PMOS transistor, a fourth PMOS transistor, and a seventh inverter. The edge detection logic circuit includes a first inverter, a second inverter, a third inverter, a fourth inverter, a fifth inverter, a sixth inverter, a first NAND gate, a second NAND gate, a third NAND gate, a fourth NAND gate, and a first NOR gate.

2. The low-delay level shifting circuit according to claim 1, characterized in that, The source of the first NMOS transistor is connected to low-side ground VSSL, and the drain is connected to the drain of the first PMOS transistor. The gate is connected to the input terminal VIN of the seventh inverter. The output of the seventh inverter is connected to the gate of the second NMOS transistor, the source of the second NMOS transistor is connected to VSSL, and the drain is connected to the drain of the second PMOS transistor. The gate of the first PMOS transistor is connected to the high-side ground VSSH, and the source is connected to the drain of the third NMOS transistor and the third PMOS transistor, as well as the input terminal of the first inverter; the gate of the second PMOS transistor is connected to VSSH, and the source is connected to the drain of the fourth NMOS transistor and the fourth PMOS transistor, as well as the input terminal of the second inverter. The source of the third NMOS transistor is connected to VSSH, and its gate is connected to the gate of the third PMOS transistor and the output of the sixth inverter; the source of the fourth NMOS transistor is connected to VSSH, and its gate is connected to the gate of the fourth NMOS transistor and the output of the fifth inverter; the sources of the third and fourth PMOS transistors are connected to the power supply voltage VDDH. The output of the first inverter is connected to the input of the fifth inverter and one input of the first NAND gate, the second NAND gate, and the third NAND gate; the output of the second inverter is connected to the input of the sixth inverter, one input of the fourth NAND gate, and the other input of the first NAND gate. The output of the first NAND gate is connected to one input of the first NOR gate; the other input of the first NOR gate is connected to the output of the third NAND gate and the other input of the fourth NAND gate; the output of the fourth NAND gate is connected to the other input of the third NAND gate. The output of the first NOR gate is connected to the input of the third inverter; the output of the third inverter is connected to the other input of the second NAND gate; the output of the second NAND gate is connected to the input of the fourth inverter; the output of the fourth inverter is connected to the output V. OUT .

3. The low-delay level shifting circuit according to claim 1, characterized in that, The level shifting core circuit transmits the low-voltage domain signals VSSL~VDDL to the high-voltage domains VSSH~VDDH. When the input V... IN When the voltage changes from low to high, the first NMOS transistor turns on, the input voltage A of the first inverter is quickly pulled down, the output of the seventh inverter is low, the second NMOS transistor turns off, and the input voltage B of the second inverter is slowly pulled up by the fourth PMOS transistor MP4.

4. The low-delay level shifting circuit according to claim 1, characterized in that, The rising edge delay is the delay of three logic gates: the first inverter, the second NAND gate, and the fourth inverter; the falling edge delay is the delay of six logic gates: the second inverter, the first NAND gate, the first NOR gate, the third inverter, the second NAND gate, and the fourth inverter.

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