Light emitting diode and manufacturing method of light emitting diode
By setting grooves and through-hole structures in the light-emitting diode and filling them with an insulating layer, the problem of insufficient resistance to current diffusion (EOS) in light-emitting diodes is solved, and the stability and resistance to current diffusion of the device are improved.
Patent Information
- Application Number
- CN202510805961.8
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-06-17
- Publication Date
- 2025-10-31
AI Technical Summary
Existing light-emitting diodes (LEDs) have insufficient resistance to overcurrent stress (EOS), and are prone to failure at the edge of the second semiconductor layer, especially when the current is large.
Grooves are formed on the second semiconductor layer and the active layer, and a first through hole and an annular second through hole corresponding to the groove are formed on the transparent conductive layer. An insulating layer is filled to reduce the area of the silver mirror structure and the area of the transparent conductive layer at the edge of the second semiconductor layer. The current diffusion capability is weakened by forming a third through hole.
This improves the LED's resistance to EOS (Effective Oscillation of Light), reduces current accumulation and diffusion at edge locations, and enhances device stability.
Smart Images
Figure CN120882180A_ABST
Abstract
Description
Technical Field
[0001] This disclosure relates to the field of light-emitting devices, and in particular to a light-emitting diode and a method for manufacturing a light-emitting diode. Background Technology
[0002] A light-emitting diode (LED) is a semiconductor light-emitting device that can be used in display, lighting, and other display applications.
[0003] Related technologies provide a light-emitting diode, which includes: a first semiconductor layer, an active layer and a second semiconductor layer stacked sequentially; a transparent conductive layer located on the second semiconductor layer; and a silver mirror structure located on the transparent conductive layer.
[0004] For the above-mentioned light-emitting diodes, how to further improve their resistance to electrical over stress (EOS) is a current research focus. Summary of the Invention
[0005] This disclosure provides a light-emitting diode (LED) and a method for manufacturing an LED, which can improve the LED's resistance to EOS (Effective Oxidation Sequencer). The technical solution is as follows:
[0006] On one hand, a light-emitting diode (LED) is provided, the LED comprising:
[0007] A first semiconductor layer, an active layer, and a second semiconductor layer are stacked sequentially, and the second semiconductor layer and the active layer have grooves extending to the first semiconductor layer;
[0008] A transparent conductive layer is located on the second semiconductor layer. The transparent conductive layer has a first through hole corresponding to the groove and an annular second through hole surrounding the first through hole. The projection of the groove on the bottom surface of the first semiconductor layer is located within the projection of the first through hole on the bottom surface of the first semiconductor layer.
[0009] A silver mirror structure is located on the transparent conductive layer. The silver mirror structure has a third through hole corresponding to the groove. The projection of the third through hole on the bottom surface of the first semiconductor layer is located between the projections of the first through hole and the second through hole on the bottom surface of the first semiconductor layer.
[0010] An insulating layer is located within the second via and between the second semiconductor layer and the silver mirror structure.
[0011] Optionally, the minimum distance between the projection of the second via on the bottom surface of the first semiconductor layer and the projection of the third via on the bottom surface of the first semiconductor layer is 5 to 10 μm.
[0012] Optionally, the second through hole is a strip-shaped through hole with a width of 4 to 10 μm.
[0013] Optionally, the projection of the inner ring of the second via onto the bottom surface of the first semiconductor layer is similar to the projection of the first via onto the bottom surface of the first semiconductor layer.
[0014] Optionally, the second through hole includes a plurality of circular holes arranged in a ring, the diameter of which is 4 to 10 μm.
[0015] Optionally, the spacing between adjacent circular holes is 10 to 50 μm.
[0016] On the other hand, a method for manufacturing a light-emitting diode is provided, the method comprising:
[0017] A first semiconductor layer, an active layer, and a second semiconductor layer are fabricated sequentially, and the second semiconductor layer and the active layer have grooves extending into the first semiconductor layer;
[0018] A transparent conductive layer is fabricated on the second semiconductor layer. The transparent conductive layer has a first through hole corresponding to the groove and an annular second through hole surrounding the first through hole. The projection of the groove on the bottom surface of the first semiconductor layer is located within the projection of the first through hole on the bottom surface of the first semiconductor layer.
[0019] An insulating layer is formed, the insulating layer being located within the second through-hole;
[0020] A silver mirror structure is fabricated, the silver mirror structure being located on the transparent conductive layer, the silver mirror structure having a third through hole corresponding to the groove, the projection of the third through hole onto the bottom surface of the first semiconductor layer being located between the projections of the first through hole and the second through hole onto the bottom surface of the first semiconductor layer; the insulating layer is located between the second semiconductor layer and the silver mirror structure.
[0021] Optionally, the minimum distance between the projection of the second via on the bottom surface of the first semiconductor layer and the projection of the third via on the bottom surface of the first semiconductor layer is 5 to 10 μm.
[0022] Optionally, the second through hole is a strip-shaped through hole with a width of 4 to 10 μm.
[0023] Optionally, the second through hole includes a plurality of circular holes arranged in a ring, the diameter of which is 4 to 10 μm.
[0024] The beneficial effects of the technical solutions provided in this disclosure are:
[0025] In this embodiment, the second semiconductor layer and the active layer have grooves extending into the first semiconductor layer. The transparent conductive layer has a first via corresponding to the groove and an annular second via surrounding the first via. An insulating layer is filled in the second via, which is located between the second semiconductor layer and the silver mirror structure. Since the first and second semiconductor layers experience significant current accumulation at the groove, and the area of the second semiconductor layer is relatively small, failure is likely to occur at the edge of the second semiconductor layer when the current is high. Therefore, the location of the third via reduces the area of the silver mirror structure, and the second via reduces the area of the transparent conductive layer at the edge of the second semiconductor layer and fills it with an insulating layer, weakening the current diffusion capability at the edge. In other words, the aforementioned second via and insulating layer configuration weakens the current diffusion capability around the groove, thereby improving the anti-EOS capability of the light-emitting diode with the silver mirror structure. Attached Figure Description
[0026] To more clearly illustrate the technical solutions in the embodiments of this disclosure, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this disclosure. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0027] Figure 1 This is a schematic diagram of the structure of a light-emitting diode provided in an embodiment of this disclosure;
[0028] Figure 2 This is a schematic diagram of electrode positions provided in an embodiment of this disclosure;
[0029] Figure 3 This is a schematic diagram of a through-hole relationship provided in an embodiment of this disclosure;
[0030] Figure 4 This is another schematic diagram of through-hole relationships provided in an embodiment of this disclosure;
[0031] Figure 5 This is a flowchart illustrating a method for manufacturing a light-emitting diode according to an embodiment of the present disclosure;
[0032] Figure 6 This is a flowchart of another method for manufacturing a light-emitting diode provided in this embodiment.
[0033] The attached figures are labeled as follows:
[0034] 100: Substrate; 101: First semiconductor layer; 102: Active layer; 103: Second semiconductor layer; 104: Transparent conductive layer; 105: Silver mirror structure; 106: Insulating layer; 123: Groove; 141: First via; 142: Second via; 151: Third via; 107: First passivation layer; 108: First electrode; 109: Second electrode; 110: Second passivation layer; 111: First electrode pad; 112: Second electrode pad; 113: Fourth via; 114: Fifth via; 115: Sixth via; 116: Seventh via. Detailed Implementation
[0035] To make the objectives, technical solutions, and advantages of this disclosure clearer, the embodiments of this disclosure will be described in further detail below with reference to the accompanying drawings.
[0036] Figure 1 This is a schematic diagram of the structure of a light-emitting diode provided in an embodiment of this disclosure. See also... Figure 1 The light-emitting diode includes: a first semiconductor layer 101, an active layer 102, a second semiconductor layer 103, a transparent conductive layer 104, a silver mirror structure 105, and an insulating layer 106.
[0037] The first semiconductor layer 101, the active layer 102, and the second semiconductor layer 103 are stacked sequentially. The second semiconductor layer 103 and the active layer 102 have grooves 123 extending to the first semiconductor layer 101. The transparent conductive layer 104 is located on the second semiconductor layer 103. The transparent conductive layer 104 has a first through-hole 141 corresponding to the groove 123 and an annular second through-hole 142 surrounding the first through-hole 141. The silver mirror structure 105 is located on the transparent conductive layer 104. The silver mirror structure 105 has a third through-hole 151 corresponding to the groove 123. The insulating layer 106 is located in the second through-hole 142 and is located between the second semiconductor layer 103 and the silver mirror structure 105.
[0038] Figure 2 This is a schematic diagram of electrode positions provided in an embodiment of this disclosure. Figure 1 yes Figure 2 Cross-sectional view at point A-A'. Figure 3 This is a schematic diagram of a through-hole relationship provided in an embodiment of this disclosure, that is... Figure 2 A detailed schematic diagram showing the relationship at groove 123. (See attached diagram.) Figures 1 to 3The projection of the groove 123 on the bottom surface of the first semiconductor layer 101 is located within the projection of the first through hole 141 on the bottom surface of the first semiconductor layer 101, and the projection of the third through hole 151 on the bottom surface of the first semiconductor layer 101 is located between the projections of the first through hole 141 and the second through hole 142 on the bottom surface of the first semiconductor layer 101.
[0039] In this embodiment, the second semiconductor layer and the active layer have grooves extending into the first semiconductor layer. The transparent conductive layer has a first via corresponding to the groove and an annular second via surrounding the first via. An insulating layer is filled in the second via, which is located between the second semiconductor layer and the silver mirror structure. Since the first and second semiconductor layers experience significant current accumulation at the groove, and the area of the second semiconductor layer is relatively small, failure is likely to occur at the edge of the second semiconductor layer when the current is high. Therefore, the location of the third via reduces the area of the silver mirror structure, and the second via reduces the area of the transparent conductive layer at the edge of the second semiconductor layer and fills it with an insulating layer, weakening the current diffusion capability at the edge. In other words, the aforementioned second via and insulating layer configuration weakens the current diffusion capability around the groove, thereby improving the anti-EOS capability of the light-emitting diode with the silver mirror structure.
[0040] like Figure 1 As shown, the light-emitting diode also includes a substrate 100, a first semiconductor layer 101, an active layer 102, and a second semiconductor layer 103 sequentially stacked on the surface of the substrate 100. The first semiconductor layer 101, the active layer 102, and the second semiconductor layer 103 form a stepped structure, with the stepped surface located on the first semiconductor layer 101. The stepped structure here includes the aforementioned groove located in the middle and the isolation groove located at the edge.
[0041] The bottom surface of the first semiconductor layer 101 is the side of the first semiconductor layer 101 facing the substrate 100.
[0042] like Figure 1 As shown, the light-emitting diode also includes a first passivation layer 107, a first electrode 108, a second electrode 109, a second passivation layer 110, a first electrode pad 111, and a second electrode pad 112.
[0043] The first passivation layer 107 covers the stepped structure and the silver mirror structure 105.
[0044] The first electrode 108 penetrates the first passivation layer 107 and is connected to the first semiconductor 101, and the second electrode 109 penetrates the first passivation layer 107 and is connected to the silver mirror structure 105.
[0045] The second passivation layer 110 covers the first passivation layer 107, the first electrode 108, and the second electrode 109.
[0046] The first electrode pad 111 penetrates the second passivation layer 110 and is connected to the first electrode 108, and the second electrode pad 112 penetrates the second passivation layer 110 and is connected to the second electrode 109.
[0047] In the embodiments disclosed herein, the substrate 100 may be any of the following: sapphire substrate, silicon substrate, etc. The material of the substrate is not limited in this disclosure.
[0048] For example, substrate 100 is a sapphire substrate.
[0049] In this embodiment of the disclosure, the first semiconductor layer 101 can be an N-type semiconductor layer, the active layer 102 can be a multi-quantum well layer, and the second semiconductor layer 103 can be a P-type semiconductor layer.
[0050] For example, the first semiconductor layer 101 is an N-type GaN layer, the active layer 102 is an InGaN / GaN layer, and the second semiconductor layer 103 is a P-type GaN layer.
[0051] In another example, the first semiconductor layer 101 can be a P-type semiconductor layer, the active layer 102 can be a multi-quantum well layer, and the second semiconductor layer 103 can be an N-type semiconductor layer.
[0052] In this embodiment of the disclosure, the transparent conductive layer 104 may be an indium tin oxide (ITO) layer.
[0053] The thickness of the transparent conductive layer 104 can be 50 to 300 angstroms.
[0054] For example, the thickness of the transparent conductive layer 104 can be 250 angstroms.
[0055] In this embodiment of the disclosure, the insulating layer 106 may be a silicon dioxide layer, an aluminum oxide layer, or a silicon nitride layer.
[0056] The thickness of the insulating layer 106 can be 50 to 300 angstroms.
[0057] For example, the thickness of the insulating layer 106 can be 250 angstroms.
[0058] like Figure 3 As shown, the minimum distance 'a' between the projection of the second via 142 onto the bottom surface of the first semiconductor layer 101 and the projection of the third via 151 onto the bottom surface of the first semiconductor layer 101 is 5 to 10 μm.
[0059] For example, the minimum distance 'a' between the projection of the second via 142 onto the bottom surface of the first semiconductor layer 101 and the projection of the third via 151 onto the bottom surface of the first semiconductor layer 101 is 8 μm.
[0060] In this implementation, if the distance is too small, the area of the silver mirror structure around the second semiconductor layer is too small, which is too unfavorable for the current diffusion of the first semiconductor layer at this location. The chip is prone to current accumulation on the first semiconductor at this location, which can lead to chip failure. If the distance is too large, it will not have the effect of weakening the current diffusion capability of the first semiconductor layer near the second semiconductor layer.
[0061] like Figure 3 As shown, in one example, the second through hole 142 is a strip-shaped through hole, and the width b of the strip-shaped through hole is 4 to 10 μm.
[0062] For example, the second through hole 142 is a strip-shaped through hole, and the width b of the strip-shaped through hole is 6μm.
[0063] In this implementation, the width is designed as described above because a narrower width would reduce the effect of current diffusion in the first semiconductor layer, making it easier for current to accumulate in the second semiconductor layer and cause failure; a wider width, on the other hand, would make it easier for failure to occur in the first semiconductor layer, which is closer to the second semiconductor layer.
[0064] The projection of the inner ring of the second through hole 142 onto the bottom surface of the first semiconductor layer 101 is similar to the projection of the first through hole 141 onto the bottom surface of the first semiconductor layer 101.
[0065] Figure 4 This is another schematic diagram of through-hole relationships provided in an embodiment of this disclosure. For example... Figure 4 As shown, in another example, the second through hole 142 includes a plurality of circular holes arranged in a ring, the diameter of which is 4 to 10 μm.
[0066] For example, the diameter of the circular hole is 6 μm.
[0067] The spacing c between adjacent circular holes is 10 to 50 μm.
[0068] For example, the spacing between adjacent circular holes is 15 μm.
[0069] In this implementation, in addition to affecting current diffusion in the same way as the aforementioned distance a and width b, if the spacing c is designed too small, it is more difficult to manufacture because the ITO etching process is difficult to control and is prone to over-etching; if the hole spacing is too large, it will not play a role in reducing current diffusion.
[0070] In this embodiment of the disclosure, the first passivation layer 107 and the second passivation layer 110 can be SiO2 layer, TiO2 layer, Al2O3, or SiN. x Any one or more of the insulating films, where x is greater than 0.
[0071] In the embodiments of this disclosure, the passivation layer formed using the above-described materials has a good passivation effect. When the passivation layer comprises a single film layer, it can be any one or more of the aforementioned film layers; the passivation layer can also comprise multiple film layers, which can be formed using different insulating materials. The passivation layer formed by stacking multiple film layers can further increase the film quality of the passivation layer, making it less susceptible to being broken through by metal particles.
[0072] In this embodiment, the first passivation layer 107 has a fourth through hole 113 and a fifth through hole 114. The fourth through hole 113 penetrates the first passivation layer 107 and communicates with the first semiconductor layer 101, while the fifth through hole 114 penetrates the first passivation layer 107 and communicates with the silver mirror structure 105.
[0073] In this embodiment of the present disclosure, the second passivation layer 110 has a sixth through hole 115 and a seventh through hole 116. The sixth through hole 115 penetrates the second passivation layer 110 and communicates with the first electrode 108, and the seventh through hole 116 penetrates the second passivation layer 110 and communicates with the second electrode 109.
[0074] In this embodiment of the disclosure, the first electrode 108 and the second electrode 109 include a Cr layer, an Al layer, a Ti layer, a Ni layer, a Pt layer and an Au layer stacked sequentially.
[0075] In this embodiment of the present disclosure, the first electrode pad 111 and the second electrode pad 112 include Ti layer, Al layer, Ni layer, Pt layer, Au layer and AuSn layer stacked sequentially.
[0076] In one example, when the first semiconductor layer 101 is an N-type semiconductor layer, the first electrode 108 is an N-type electrode and the first electrode pad 111 is an N-type electrode pad. When the second semiconductor layer 103 is a P-type semiconductor layer, the second electrode 109 is a P-type electrode and the second electrode pad 112 is a P-type electrode pad.
[0077] In another example, when the first semiconductor layer 101 is a P-type semiconductor layer, the first electrode 108 is a P-electrode and the first electrode pad 111 is a P-electrode pad; when the second semiconductor layer 103 is an N-type semiconductor layer, the second electrode 109 is an N-electrode and the second electrode pad 112 is an N-electrode pad.
[0078] Figure 5 A method for manufacturing a light-emitting diode (LED) is provided as an embodiment of this disclosure. See also: Figure 5 The method includes the following steps:
[0079] S11. A first semiconductor layer, an active layer, and a second semiconductor layer are fabricated sequentially. The second semiconductor layer and the active layer have grooves extending to the first semiconductor layer.
[0080] In this embodiment of the disclosure, the first semiconductor layer can be an N-type semiconductor layer, the active layer can be a multi-quantum well layer, and the second semiconductor layer can be a P-type semiconductor layer.
[0081] For example, the first semiconductor layer is an N-type GaN layer, the active layer is an InGaN / GaN layer, and the second semiconductor layer is a P-type GaN layer.
[0082] S12. Fabricate a transparent conductive layer, the transparent conductive layer being located on the second semiconductor layer, the transparent conductive layer having a first through hole corresponding to the groove and an annular second through hole surrounding the first through hole, the projection of the groove on the bottom surface of the first semiconductor layer being located within the projection of the first through hole on the bottom surface of the first semiconductor layer.
[0083] S13. Fabricate an insulating layer, wherein the insulating layer is located within the second through hole.
[0084] S14. Fabricate a silver mirror structure, wherein the silver mirror structure is located on the transparent conductive layer, the silver mirror structure has a third through hole corresponding to the groove, and the projection of the third through hole on the bottom surface of the first semiconductor layer is located between the projections of the first through hole and the second through hole on the bottom surface of the first semiconductor layer; the insulating layer is located between the second semiconductor layer and the silver mirror structure.
[0085] In this embodiment, the second semiconductor layer and the active layer have grooves extending into the first semiconductor layer. The transparent conductive layer has a first via corresponding to the groove and an annular second via surrounding the first via. An insulating layer is filled in the second via, which is located between the second semiconductor layer and the silver mirror structure. Since the first and second semiconductor layers experience significant current accumulation at the groove, and the area of the second semiconductor layer is relatively small, failure is likely to occur at the edge of the second semiconductor layer when the current is high. Therefore, the location of the third via reduces the area of the silver mirror structure, and the second via reduces the area of the transparent conductive layer at the edge of the second semiconductor layer and fills it with an insulating layer, weakening the current diffusion capability at the edge. In other words, the aforementioned second via and insulating layer configuration weakens the current diffusion capability around the groove, thereby improving the anti-EOS capability of the light-emitting diode with the silver mirror structure.
[0086] Figure 6 A flowchart illustrating another method for fabricating a light-emitting diode (LED) according to an embodiment of this disclosure. See also... Figure 6 The method includes the following steps:
[0087] S21. A first semiconductor layer, an active layer, and a second semiconductor layer are sequentially fabricated on the surface of a substrate, wherein the first semiconductor layer, the active layer, and the second semiconductor layer form a stepped structure.
[0088] In this embodiment of the disclosure, the first semiconductor layer is an N-type GaN layer, the active layer is an InGaN / GaN layer, and the second semiconductor layer is a P-type GaN layer.
[0089] In one example, step S21 includes:
[0090] The first step is to grow the first semiconductor layer.
[0091] The first semiconductor layer is an N-type GaN layer.
[0092] For example, an N-type GaN layer can be grown on a substrate surface using a metal-organic chemical vapor deposition (MOCVD) device.
[0093] In the embodiments disclosed herein, semiconductor layer growth can be achieved using Veeco K465i, C4, or RB MOCVD equipment or AIXTRON metal-organic chemical vapor deposition equipment. High-purity H2 (hydrogen), high-purity N2 (nitrogen), or a mixture of high-purity H2 and high-purity N2 is used as the carrier gas; high-purity NH3 is used as the N source; trimethylgallium (TMGa) and triethylgallium (TEGa) are used as gallium sources; trimethylindium (TMIn) is used as the indium source; silane (SiH4) is used as the N-type dopant; trimethylaluminum (TMAl) is used as the aluminum source; and magnesium pyrocene (CP2Mg) is used as the P-type dopant.
[0094] The second step is to grow the active layer.
[0095] The active layer is an InGaN / GaN layer.
[0096] For example, an InGaN / GaN layer is grown on the surface of an N-type GaN layer using an MOCVD device.
[0097] The third step is to grow a second semiconductor layer.
[0098] The second semiconductor layer is a P-type GaN layer.
[0099] For example, a P-type GaN layer is grown on the surface of an InGaN / GaN layer using an MOCVD device.
[0100] The fourth step involves patterning the first semiconductor layer, the active layer, and the second semiconductor layer to form a stepped structure.
[0101] For example, inductively coupled plasma (ICP) etching technology is used to pattern the first semiconductor layer, the active layer, and the second semiconductor layer that are stacked sequentially in the epitaxial structure to form a stepped structure.
[0102] S22. Fabricate a transparent conductive layer, wherein the transparent conductive layer is located on the second semiconductor layer.
[0103] In one example, step S22 includes:
[0104] A transparent conductive film is deposited on the surface of the second semiconductor layer; the transparent conductive film is patterned to obtain a transparent conductive layer having a first through hole corresponding to the groove and an annular second through hole surrounding the first through hole.
[0105] Patterning refers to first forming a photoresist mask on the surface of a transparent conductive film using photolithography, then etching away the excess parts (the parts corresponding to the first and second vias) under the protection of the photoresist mask, and finally removing the photoresist mask.
[0106] Wherein, the projection of the groove on the bottom surface of the first semiconductor layer is located within the projection of the first via on the bottom surface of the first semiconductor layer.
[0107] The transparent conductive layer is an ITO layer.
[0108] In this embodiment of the present disclosure, the minimum distance between the projection of the second via 142 onto the bottom surface of the first semiconductor layer 101 and the projection of the third via 151 onto the bottom surface of the first semiconductor layer 101 is 5 to 10 μm.
[0109] In one example, the second through hole 142 is a strip-shaped through hole with a width of 4 to 10 μm.
[0110] The projection of the inner ring of the second through hole 142 onto the bottom surface of the first semiconductor layer 101 is similar to the projection of the first through hole 141 onto the bottom surface of the first semiconductor layer 101.
[0111] In another example, the second through hole 142 includes a plurality of circular holes arranged in a ring, the diameter of which is 4 to 10 μm.
[0112] The spacing between adjacent circular holes is 10–50 μm.
[0113] S23. Fabricate an insulating layer, wherein the insulating layer is located within the second through hole.
[0114] In this embodiment of the disclosure, the insulating layer may be a silicon dioxide layer, an aluminum oxide layer, or a silicon nitride layer.
[0115] For example, an insulating film can be deposited first, and then patterned to retain the portion located within the second via, thus obtaining the insulating layer.
[0116] Patterning refers to first forming a photoresist mask on the surface of an insulating film using photolithography, then etching away the excess portion (the portion other than the second via) under the protection of the photoresist mask, and finally removing the photoresist mask.
[0117] S24. Fabricate a silver mirror structure, wherein the silver mirror structure is located on the transparent conductive layer.
[0118] In one example, step S24 includes:
[0119] A silver mirror structure is formed on a transparent conductive layer using sputtering technology. The silver mirror structure has a third through hole corresponding to the groove.
[0120] The projection of the third via on the bottom surface of the first semiconductor layer is located between the projections of the first via and the second via on the bottom surface of the first semiconductor layer; the insulating layer is located between the second semiconductor layer and the silver mirror structure.
[0121] Since the second via is filled with an insulating layer, the insulating layer protects the second semiconductor layer during silver mirror sputtering, preventing sputtering damage to the surface of the second semiconductor layer and thus affecting the chip's optoelectronic performance.
[0122] Sputtering technology can refer to first forming a photoresist mask on a transparent conductive layer by photolithography. This photoresist mask has notches, which correspond to the areas where a silver mirror needs to be made. Then, sputtering is performed, and finally the photoresist mask is removed.
[0123] The silver mirror structure can be a stack of Ag and TiW.
[0124] S25. Fabricate a first passivation layer, which covers the stepped structure and the silver mirror structure.
[0125] In one example, the first passivation layer can be a SiO2 layer, a TiO2 layer, an Al2O3 layer, or a SiN layer. x Any one or more of the insulating films, where x is greater than 0.
[0126] In one example, step S25 includes: depositing an Al2O3 thin film over the entire surface using an atomic layer deposition (ALD) device; depositing a SiO2 thin film using a plasma-enhanced chemical vapor deposition (PECVD) device; and forming a fourth and a fifth via on the Al2O3 and SiO2 thin films using a patterning technique to obtain a first passivation layer.
[0127] Among them, patterning technology can refer to photolithography to form a mask, followed by etching.
[0128] S26. Fabricate a first electrode and a second electrode, wherein the first electrode penetrates the first passivation layer and is connected to the first semiconductor, and the second electrode penetrates the first passivation layer and is connected to the silver mirror structure.
[0129] In one example, step S26 includes:
[0130] A mask is formed by photolithography, and then the first and second electrodes are fabricated using electron beam evaporation technology.
[0131] In this embodiment of the disclosure, the first electrode and the second electrode include a Cr layer, an Al layer, a Ti layer, a Ni layer, a Pt layer and an Au layer stacked sequentially.
[0132] S27. Fabricate a second passivation layer, which covers the first passivation layer, the first electrode, and the second electrode. The second passivation layer includes a plurality of alternately stacked dielectric layers and metal layers.
[0133] In one example, the second passivation layer can be a SiO2 layer, a TiO2 layer, an Al2O3 layer, or a SiN layer. x Any one or more of the insulating films, where x is greater than 0.
[0134] In one example, step S27 includes: depositing a SiO2 thin film using a PECVD device; and forming a sixth and a seventh through-hole in the SiO2 thin film using a patterning technique to obtain a second passivation layer.
[0135] S28. Fabricate a first electrode pad and a second electrode pad, wherein the first electrode pad penetrates the second passivation layer and is connected to the first electrode, and the second electrode pad penetrates the second passivation layer and is connected to the second electrode.
[0136] In one example, step S28 includes:
[0137] A mask is formed by photolithography, and then the first electrode pad and the second electrode pad are fabricated using electron beam evaporation technology.
[0138] In this embodiment of the present disclosure, the first electrode pad and the second electrode pad include Ti layer, Al layer, Ni layer, Pt layer, Au layer and AuSn layer stacked sequentially.
[0139] Table 1 below compares the relevant technologies obtained through comparative experiments with the embodiments of this disclosure. Figure 2 and Figure 4 Parameter comparison of the two structures:
[0140] Table 1
[0141] Anti-EOS(V) LOP(mW) VF(V) WLD(nm) Related technologies 60 1050 3.028 455.5 Figure 2 75 1058 3.032 455.5 Figure 4 70 1053 3.030 455.5
[0142] It can be seen that the embodiments provided in this disclosure Figure 2 and Figure 4 Both solutions significantly improve their ability to counter EOS. Among them, Figure 2 The strip-shaped second via design shown exhibits poorer current spread around the groove and a greater improvement in EOS resistance, but also a significant increase in voltage VF; while Figure 4 The use of a second through-hole composed of multiple circles improves the resistance to EOS. Figure 2 Smaller, but the voltage VF increases relatively. Figure 2 There are also relatively few.
[0143] The above description is merely an optional embodiment of this disclosure and is not intended to limit this disclosure. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this disclosure should be included within the protection scope of this disclosure.
Claims
1. A light-emitting diode, characterized in that, The light-emitting diode includes: A first semiconductor layer (101), an active layer (102), and a second semiconductor layer (103) are stacked sequentially. The second semiconductor layer (103) and the active layer (102) have grooves (123) extending to the first semiconductor layer (101). A transparent conductive layer (104) is located on the second semiconductor layer (103). The transparent conductive layer (104) has a first through hole (141) corresponding to the groove (123) and an annular second through hole (142) surrounding the first through hole (141). The projection of the groove (123) on the bottom surface of the first semiconductor layer (101) is located within the projection of the first through hole (141) on the bottom surface of the first semiconductor layer (101). A silver mirror structure (105) is located on the transparent conductive layer (104). The silver mirror structure (105) has a third through hole (151) corresponding to the groove (123). The projection of the third through hole (151) on the bottom surface of the first semiconductor layer (101) is located between the projections of the first through hole (141) and the second through hole (142) on the bottom surface of the first semiconductor layer (101). An insulating layer (106) is located within the second via (142) and is situated between the second semiconductor layer (103) and the silver mirror structure (105).
2. The light-emitting diode according to claim 1, characterized in that, The minimum distance between the projection of the second via (142) on the bottom surface of the first semiconductor layer (101) and the projection of the third via (151) on the bottom surface of the first semiconductor layer (101) is 5 to 10 μm.
3. The light-emitting diode according to claim 1 or 2, characterized in that, The second through hole (142) is a strip-shaped through hole with a width of 4 to 10 μm.
4. The light-emitting diode according to claim 3, characterized in that, The projection of the inner ring of the second via (142) onto the bottom surface of the first semiconductor layer (101) is similar to the projection of the first via (141) onto the bottom surface of the first semiconductor layer (101).
5. The light-emitting diode according to claim 1 or 2, characterized in that, The second through hole (142) includes a plurality of circular holes arranged in a ring, the diameter of which is 4 to 10 μm.
6. The light-emitting diode according to claim 5, characterized in that, The spacing between adjacent circular holes is 10–50 μm.
7. A method for manufacturing a light-emitting diode, characterized in that, The method includes: A first semiconductor layer, an active layer, and a second semiconductor layer are fabricated sequentially, and the second semiconductor layer and the active layer have grooves extending into the first semiconductor layer; A transparent conductive layer is fabricated on the second semiconductor layer. The transparent conductive layer has a first through hole corresponding to the groove and an annular second through hole surrounding the first through hole. The projection of the groove on the bottom surface of the first semiconductor layer is located within the projection of the first through hole on the bottom surface of the first semiconductor layer. An insulating layer is formed, the insulating layer being located within the second through-hole; A silver mirror structure is fabricated, the silver mirror structure being located on the transparent conductive layer, the silver mirror structure having a third through hole corresponding to the groove, the projection of the third through hole onto the bottom surface of the first semiconductor layer being located between the projections of the first through hole and the second through hole onto the bottom surface of the first semiconductor layer; the insulating layer is located between the second semiconductor layer and the silver mirror structure.
8. The method according to claim 7, characterized in that, The minimum distance between the projection of the second via on the bottom surface of the first semiconductor layer and the projection of the third via on the bottom surface of the first semiconductor layer is 5 to 10 μm.
9. The method according to claim 7 or 8, characterized in that, The second through hole is a strip-shaped through hole with a width of 4 to 10 μm.
10. The method according to claim 7 or 8, characterized in that, The second through hole includes a plurality of circular holes arranged in a ring, the diameter of which is 4 to 10 μm.