Storage and calculation integrated chip voltage regulation method and system based on hybrid architecture, and medium

Abstract

The invention provides a storage and calculation integrated chip voltage regulation method and system based on a hybrid architecture, and a medium. Comprising the following steps: obtaining dynamic voltage regulation parameters by obtaining and processing storage hierarchical type feature data and data read-write demand data of chips, regulating initial configuration voltage, obtaining adaptive voltage, monitoring operation data of each chip of a chip cluster in real time, and processing through a preset global voltage regulation decision model, so as to obtain adaptive voltage; global voltage optimal adjustment strategy data is obtained for voltage adjustment, operation monitoring record data after adjustment is monitored, global voltage adjustment actual effect data is obtained through analysis and processing, and therefore the global voltage adjustment state is determined; according to the invention, the dynamic voltage regulation parameters of different storage layers are obtained through analysis and processing, the corresponding initial configuration voltage is preliminarily adjusted, global analysis is carried out on the chip cluster to determine the global voltage optimal regulation strategy data, and the regulation state is monitored in real time, so that voltage adaptation regulation is carried out on the storage and calculation integrated chip based on the hybrid architecture.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of memory-compute integrated chips, in particular to a memory-compute integrated chip voltage regulation method, system and medium based on a hybrid architecture. BACKGROUND

[0002] As a new chip architecture, memory-compute integrated chips effectively alleviate the "memory wall" problem in traditional architectures by combining storage and computing functions, and improve data processing efficiency. However, in actual applications, memory-compute integrated chips face the challenge of high power consumption, especially when processing complex and variable task loads. Currently, dynamic voltage regulation technology, as an effective power management means, has been widely used in various chips. Traditional dynamic voltage regulation methods are mainly based on monitoring the overall load of the chip and adjusting the operating voltage of the chip through simple rules or models. For example, some methods determine whether to increase or decrease the voltage according to a single indicator such as CPU utilization. This approach cannot fully consider the complex characteristics of the hybrid architecture of memory-compute integrated chips. In addition, in the context of multiple chips working together, there is a lack of effective inter-chip collaborative voltage regulation mechanism, which cannot achieve energy consumption optimization and performance guarantee of the entire computing cluster. Therefore, there is an urgent need for a dynamic voltage regulation method for memory-compute integrated chips that can be applied to complex scenarios and effectively reduce power consumption.

[0003] In view of the above problems, there is an urgent need for an effective technical solution. SUMMARY

[0004] The purpose of the present application is to provide a memory-compute integrated chip voltage regulation method, system and medium based on a hybrid architecture, which can obtain dynamic voltage regulation parameters for different storage layers by analysis and processing, preliminarily adjust the corresponding initial voltage, and then perform global analysis on the chip cluster to determine global voltage optimization regulation strategy data. Real-time monitoring of the regulation state can be achieved to realize voltage adaptation and regulation of memory-compute integrated chips based on a hybrid architecture.

[0005] In a first aspect, the present application provides a memory-compute integrated chip voltage regulation method based on a hybrid architecture, comprising the following steps: Obtaining storage layer type feature data, data read-write demand data and initial voltage of a memory-compute integrated chip; Processing the storage layer type feature data and the corresponding data read-write demand data to obtain dynamic voltage regulation parameters, including cache dynamic voltage regulation parameters, main memory dynamic voltage regulation parameters and auxiliary memory dynamic voltage regulation parameters; Adjusting the initial voltage of the memory-compute integrated chip according to the dynamic voltage regulation parameters to obtain an adaptive voltage of the memory-compute integrated chip, including a cache adaptive voltage, a main memory adaptive voltage and an auxiliary memory adaptive voltage; According to the adaptive voltage control, the operation of the compute-in-memory chip is controlled, load monitoring data, energy consumption monitoring data and operation state monitoring data corresponding to each chip of the compute-in-memory chip cluster are obtained; The load monitoring data, energy consumption data and operation state data are input into a preset global voltage adjustment decision model for processing to obtain global voltage optimal adjustment strategy data, and voltage adjustment is performed on the compute-in-memory chip cluster respectively; Operation monitoring record data corresponding to each chip of the compute-in-memory chip cluster are obtained and processed to obtain global voltage adjustment effectiveness data, and the global voltage adjustment state is determined according to the global voltage adjustment effectiveness data.

[0006] Optionally, in the voltage adjustment method for the compute-in-memory chip based on the hybrid architecture, the storage hierarchical type feature data of the compute-in-memory chip and the corresponding data read-write demand data are obtained, including: The storage hierarchical type feature data of the compute-in-memory chip is obtained, including cache type feature data, main memory type feature data and auxiliary memory type feature data; According to the cache type feature data, main memory type feature data or auxiliary memory type feature data, a preset storage hierarchical type and chip initial matching voltage mapping table is queried respectively to obtain the corresponding initial matching voltage, including cache initial matching voltage, main memory initial matching voltage and auxiliary memory initial matching voltage; The data read-write demand data is obtained, including cache data read-write demand data, main memory data read-write demand data and auxiliary memory data read-write demand data; The cache data read-write demand data includes read-write frequency, cache actual temperature and data access demand prediction level; The main memory data read-write demand data includes main memory real-time load, read-write bandwidth, data request queue length and task type label data; The auxiliary memory data read-write demand data includes data operation type feature data and data volume.

[0007] Optionally, in the voltage adjustment method for the compute-in-memory chip based on the hybrid architecture, the storage hierarchical type feature data and the corresponding data read-write demand data are processed to obtain dynamic voltage adjustment parameters, including cache dynamic voltage adjustment parameters, main memory dynamic voltage adjustment parameters and auxiliary memory dynamic voltage adjustment parameters, including: According to the data access demand prediction level, a preset access demand weight value list is queried to obtain a first dynamic voltage weight value; According to the read-write frequency, the read-write frequency average of a historical preset time period is processed to obtain a read-write frequency fluctuation rate, and according to the cache actual temperature, the cache temperature average of a historical preset time period is processed to obtain a cache temperature fluctuation rate; According to the read-write frequency fluctuation rate and the cache temperature fluctuation rate, the first dynamic voltage adjustment weight value is processed to obtain a cache dynamic voltage adjustment parameter; The main memory real-time load is compared with a preset load threshold to obtain a main memory real-time load level. The read-write bandwidth is processed with a preset peak bandwidth to obtain a bandwidth proportion. The data request queue length is compared with a preset queue length threshold to obtain a data request queue proportion. According to the task type label data, a preset task weight value list is queried to obtain a second dynamic voltage adjustment weight value. According to the main memory real-time load level, the bandwidth proportion, and the data request queue proportion, the second dynamic voltage adjustment weight value is combined for weighted mean processing to obtain a main memory dynamic voltage adjustment parameter. The data amount is compared with a preset data amount threshold to obtain a data amount level. According to the data operation type feature data, a corresponding data amount level and a secondary storage voltage adjustment gradient list are obtained. According to the data amount level, a corresponding data amount level and a secondary storage voltage adjustment gradient list are queried to obtain a secondary storage dynamic voltage adjustment parameter.

[0008] Optionally, in the voltage adjustment method of the storage-computing integrated chip based on the hybrid architecture, the initial voltage of the storage-computing integrated chip is adjusted according to the dynamic voltage adjustment parameter to obtain an adaptive voltage of the storage-computing integrated chip, including a cache adaptive voltage, a main memory adaptive voltage, and a secondary storage adaptive voltage, which includes: The cache initial voltage is adjusted according to the cache dynamic voltage adjustment parameter to obtain a cache adaptive voltage. The main memory initial voltage is adjusted according to the main memory dynamic voltage adjustment parameter to obtain a main memory adaptive voltage. The secondary storage initial voltage is adjusted according to the secondary storage dynamic voltage adjustment parameter to obtain a secondary storage adaptive voltage.

[0009] Optionally, in the voltage adjustment method of the storage-computing integrated chip based on the hybrid architecture, the storage-computing integrated chip is controlled to run according to the adaptive voltage, and load monitoring data, energy consumption monitoring data, and running state monitoring data corresponding to each chip of a storage-computing integrated chip cluster are obtained, which includes: Load monitoring data, energy consumption monitoring data, and running state monitoring data corresponding to each chip of a storage-computing integrated chip cluster are obtained. The load monitoring data includes CPU utilization and a to-be-processed data queue length. The energy consumption monitoring data includes real-time voltage, real-time current, and a preset collection time. The running state monitoring data includes a chip real temperature mean value and a data transmission rate.

[0010] Optionally, in the voltage regulation method for the memory-compute integrated chip based on the hybrid architecture, the load monitoring data, energy consumption data and running state data are input into a preset global voltage regulation decision model for processing to obtain global voltage optimal regulation strategy data, and voltage regulation is performed on the memory-compute integrated chip cluster, comprising: The real-time voltage, real-time current and preset collection time are processed to obtain real-time energy consumption data; The CPU utilization rate, length of the data queue to be processed, real-time energy consumption data, average chip real temperature and data transmission rate are input into a preset global voltage regulation decision model for processing to obtain global voltage optimal regulation strategy data; The global voltage optimal regulation strategy data comprises planned regulation voltage and planned regulation time corresponding to each chip of the memory-compute integrated chip cluster.

[0011] Optionally, in the voltage regulation method for the memory-compute integrated chip based on the hybrid architecture, the running monitoring record data corresponding to each chip of the memory-compute integrated chip cluster are obtained and processed to obtain global voltage regulation effectiveness data, and the global voltage regulation state is determined according to the global voltage regulation effectiveness data, comprising: The running monitoring record data corresponding to each chip of the memory-compute integrated chip cluster are obtained, comprising CPU utilization rate, task time rate, energy consumption rate, data throughput improvement rate and chip temperature rate; The CPU utilization rate and length of the data queue to be processed are processed to obtain real-time load level corresponding to each chip of the memory-compute integrated chip cluster; The real-time load level is used to query a preset load-global voltage regulation effectiveness weight value mapping table to obtain regulation effectiveness evaluation weight value corresponding to each chip; The CPU utilization rate, task time rate, energy consumption rate, data throughput improvement rate and chip temperature rate are combined with the regulation effectiveness evaluation weight value corresponding thereto for weighted mean processing to obtain chip voltage regulation effectiveness data corresponding to each chip; The chip voltage regulation effectiveness data is combined with the regulation effectiveness evaluation weight value for weighted mean processing to obtain global voltage regulation effectiveness data; If the global voltage regulation effectiveness data is less than preset global voltage regulation expected data, it is determined that the global voltage regulation state is unqualified; If the global voltage regulation effectiveness data is greater than or equal to the preset global voltage regulation expected data, it is determined that the global voltage regulation state is qualified.

[0012] Optionally, in the voltage regulation method for the memory-compute integrated chip based on the hybrid architecture, further comprising: Obtain the instantaneous load of the storage-computing integrated chip; According to the short-time sliding window algorithm, the instantaneous load is compared with the preset load reference value to obtain an instantaneous increase rate; If the instantaneous increase rate is greater than a preset instantaneous increase rate threshold, it is determined that the instantaneous load is a short-time burst load, and a PID controller is controlled to adjust the voltage according to a preset proportion to obtain an instantaneous voltage; The storage-computing integrated chip is controlled to run according to the instantaneous voltage.

[0013] In a second aspect, the application provides a storage-computing integrated chip voltage adjustment system based on a hybrid architecture, which comprises a memory and a processor, wherein the memory comprises a program of a storage-computing integrated chip voltage adjustment method based on a hybrid architecture, and the program of the storage-computing integrated chip voltage adjustment method based on the hybrid architecture is implemented when the processor is executed to implement the following steps: Obtain the storage layer type feature data, data read-write demand data and initial matching voltage of the storage-computing integrated chip; According to the storage layer type feature data and the corresponding data read-write demand data, dynamic voltage adjustment parameters are obtained, including cache dynamic voltage adjustment parameters, main memory dynamic voltage adjustment parameters and auxiliary memory dynamic voltage adjustment parameters; According to the dynamic voltage adjustment parameters, the initial matching voltage of the storage-computing integrated chip is adjusted to obtain the adaptive voltage of the storage-computing integrated chip, including the cache adaptive voltage, the main memory adaptive voltage and the auxiliary memory adaptive voltage; According to the adaptive voltage, the storage-computing integrated chip is controlled to run, and the load monitoring data, energy consumption monitoring data and running state monitoring data corresponding to each chip of the storage-computing integrated chip cluster are obtained; The load monitoring data, energy consumption data and running state data are input into a preset global voltage adjustment decision model for processing to obtain global voltage optimal adjustment strategy data, and the storage-computing integrated chip cluster is respectively adjusted in voltage; Obtain the running monitoring record data corresponding to each chip of the storage-computing integrated chip cluster, process the running monitoring record data, obtain global voltage adjustment effectiveness data, and determine the global voltage adjustment state according to the global voltage adjustment effectiveness data.

[0014] In a third aspect, the application further provides a computer readable storage medium, wherein the computer readable storage medium stores a program of a storage-computing integrated chip voltage adjustment method based on a hybrid architecture, and the program of the storage-computing integrated chip voltage adjustment method based on the hybrid architecture is implemented when the processor is executed to implement the steps of the storage-computing integrated chip voltage adjustment method based on the hybrid architecture as described in any one of the above aspects.

[0015] From the above, the application provides a voltage adjustment method, system and medium based on a mixed architecture memory-computing integrated chip, which obtains dynamic voltage adjustment parameters of different memory layers through analysis and processing, preliminarily adjusts the corresponding initial voltage, and then globally analyzes the chip cluster to determine global voltage optimal adjustment strategy data, and monitors the adjustment state in real time, so as to realize voltage adaptation adjustment of the memory-computing integrated chip based on the mixed architecture.

[0016] Other features and advantages of the present application will be set forth in the following description, and in part will become apparent from the description, or can be learned by practice of the present application. The objects and other advantages of the present application will be realized and attained by the structure particularly pointed out in the written description and claims hereof. BRIEF DESCRIPTION OF DRAWINGS

[0017] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the following will briefly introduce the drawings needed to be used in the embodiments of the present application. It should be understood that the following drawings only show some embodiments of the present application, and therefore should not be regarded as a limitation on the scope, and for those skilled in the art, other related drawings can also be obtained without creative labor on the basis of these drawings.

[0018] Figure 1 The flowchart of the voltage adjustment method of the memory-computing integrated chip based on the mixed architecture provided by the embodiments of the present application; Figure 2 The flowchart of obtaining dynamic voltage adjustment parameters of the voltage adjustment method of the memory-computing integrated chip based on the mixed architecture provided by the embodiments of the present application; Figure 3 The flowchart of determining the global voltage adjustment state of the voltage adjustment method of the memory-computing integrated chip based on the mixed architecture provided by the embodiments of the present application; Figure 4 The high-level flowchart of the method of various embodiments of the present application. DETAILED DESCRIPTION

[0019] The technical solutions in the embodiments of the present application will be described clearly and completely below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, not all the embodiments. The components of the embodiments of the present application described and shown in the drawings herein can be arranged and designed in various different configurations. Therefore, the following detailed description of the embodiments of the present application provided in the drawings is not intended to limit the scope of the claimed present application, but only represents selected embodiments of the present application. Based on the embodiments of the present application, all other embodiments obtained by those skilled in the art without creative labor are within the scope of protection of the present application.

[0020] It should be noted that like reference numerals and characters refer to like elements throughout the following description with like reference numerals and characters referring to like elements throughout the following description and the appended drawings are not necessarily drawn to scale. Also, in the following description, terms "first", "second", and the like, merely identify different instances of the categories and do not imply or suggest relative importance.

[0021] Please refer to Figure 1 , Figure 1 is a flowchart of a voltage regulation method based on a hybrid architecture in some embodiments of the present application. The voltage regulation method based on a hybrid architecture is used in terminal equipment, such as computers, mobile phones, and the like. The voltage regulation method based on a hybrid architecture includes the following steps: S11, obtaining storage hierarchy type feature data, data read-write requirement data, and initial matching voltage of a storage-computing integrated chip; S12, processing the storage hierarchy type feature data and the corresponding data read-write requirement data to obtain dynamic voltage regulation parameters, including cache dynamic voltage regulation parameters, main memory dynamic voltage regulation parameters, and auxiliary memory dynamic voltage regulation parameters; S13, regulating the initial matching voltage of the storage-computing integrated chip according to the dynamic voltage regulation parameters to obtain adaptive voltage of the storage-computing integrated chip, including cache adaptive voltage, main memory adaptive voltage, and auxiliary memory adaptive voltage; S14, controlling the operation of the storage-computing integrated chip according to the adaptive voltage, and obtaining load monitoring data, energy consumption monitoring data, and operation state monitoring data corresponding to each chip of a storage-computing integrated chip cluster; S15, inputting the load monitoring data, energy consumption data, and operation state data into a preset global voltage regulation decision model for processing to obtain global voltage optimal regulation strategy data, and regulating the voltage of the storage-computing integrated chip cluster respectively; S16, obtaining operation monitoring record data corresponding to each chip of the storage-computing integrated chip cluster, processing the operation monitoring record data to obtain global voltage regulation effectiveness data, and determining a global voltage regulation state according to the global voltage regulation effectiveness data.

[0022] It should be noted that according to the characteristics of different storage levels, the storage hierarchical management method is developed to realize the good balance of high performance and low power consumption of the storage-computing integrated chip in different application scenarios. According to historical operation records and experience, the initial matching voltage is set by the person skilled in the art, and then the dynamic voltage adjustment parameters are obtained by processing the storage layer type characteristic data and the corresponding data read-write demand data, and the initial matching voltage of different storage layers is dynamically adjusted. Each chip integrates a high-speed inter-chip communication module, which can quickly and stably share state information with other chips during operation, realize real-time monitoring and data sharing of the chip cluster, and realize collaborative voltage regulation according to the global voltage regulation decision model, and real-time evaluation of the effectiveness of global voltage regulation, and dynamic adjustment of the global voltage optimal regulation strategy data according to the evaluation results.

[0023] According to the embodiment of the application, the storage layer type characteristic data and the corresponding data read-write demand data of the storage-computing integrated chip are obtained, including: The storage layer type characteristic data of the storage-computing integrated chip includes cache type characteristic data, main memory type characteristic data and auxiliary storage type characteristic data; According to the cache type characteristic data, main memory type characteristic data or auxiliary storage type characteristic data, a preset storage layer type and chip initial matching voltage mapping table is queried to obtain the corresponding initial matching voltage, including cache initial matching voltage, main memory initial matching voltage and auxiliary storage initial matching voltage; The data read-write demand data includes cache data read-write demand data, main memory data read-write demand data and auxiliary storage data read-write demand data; The cache data read-write demand data includes read-write frequency, cache real temperature and data access demand prediction level; The main memory data read-write demand data includes main memory real-time load, read-write bandwidth, data request queue length and task type label data; The auxiliary storage data read-write demand data includes data operation type characteristic data and data volume.

[0024] It should be noted that in the memory computing integrated chip, the memory hierarchy and dynamic voltage adaptation can improve the overall performance and energy efficiency ratio of the chip, wherein the memory hierarchy type includes cache, main memory and large capacity auxiliary storage, that is, represented by cache type feature data, main memory type feature data and auxiliary storage type feature data, in this embodiment, the cache type feature data, main memory type feature data and auxiliary storage type feature data are represented by different numerical values and can be adjusted, the preset memory hierarchy type and chip initial voltage mapping table is obtained by analyzing a large number of historical chip running information by a person skilled in the art, and can be dynamically adjusted; the cache data read-write demand data includes read-write frequency, cache real temperature and data access demand prediction level, wherein the data access demand prediction level is obtained by a person skilled in the art using time series analysis algorithm such as ARIMA to process the historical data access time, access frequency and data volume of cache, and to predict the probability of data access and the corresponding data volume in the next time period; the main memory data read-write demand data includes main memory real-time load, read-write bandwidth, data request queue length and task type label data, wherein the task type includes simple lightweight task and complex high load task, the task type of the current running task can be identified by means of task scheduling system and software label, and the simple lightweight task type label data and complex high load task type label data are represented by different numerical values; the auxiliary storage data read-write demand data includes data operation type feature data and data volume, wherein the data operation type includes data writing and data reading (including sequential reading and random reading), and the data writing feature data and data reading feature data are represented by different numerical values.

[0025] Please refer to Figure 2 , Figure 2 is a flowchart of obtaining dynamic voltage adjustment parameters in the mixed architecture-based memory computing integrated chip voltage adjustment method in some embodiments of the present application. According to the embodiment of the present application, the processing of the memory hierarchy type feature data and the corresponding data read-write demand data to obtain dynamic voltage adjustment parameters, including cache dynamic voltage adjustment parameters, main memory dynamic voltage adjustment parameters and auxiliary storage dynamic voltage adjustment parameters, comprises: S211, querying a preset access demand weight value list according to the data access demand prediction level to obtain a first dynamic voltage weight value; S212, processing the read-write frequency in combination with the read-write frequency average of the historical preset time period to obtain the read-write frequency fluctuation rate, and processing the cache real temperature in combination with the cache temperature average of the historical preset time period to obtain the cache temperature fluctuation rate; S213, processing the read-write frequency fluctuation rate and the cache temperature fluctuation rate in combination with the first dynamic voltage weight value to obtain the cache dynamic voltage adjustment parameter; S221, compare the main real-time load with a preset load threshold to obtain a main real-time load level, process the read-write bandwidth with a preset peak bandwidth to obtain a bandwidth proportion, compare the data request queue length with a preset queue length threshold to obtain a data request queue proportion; S222, query a preset task weight value list according to the task type label data to obtain a second dynamic voltage regulation weight value; S223, combine the second dynamic voltage regulation weight value with the main real-time load level, the bandwidth proportion, and the data request queue proportion to obtain a main dynamic voltage regulation parameter through weighted mean processing; S231, compare the data volume with a preset data volume threshold to obtain a data volume level; S232, obtain a corresponding data volume level and a secondary storage voltage adjustment gradient list according to the data operation type feature data, and obtain a secondary dynamic voltage regulation parameter according to the data volume level and the corresponding data volume level and secondary storage voltage adjustment gradient list.

[0026] It should be noted that different data access demand prediction levels correspond to different weight value allocation, wherein the preset access demand weight value list is obtained by a person skilled in the art according to a large amount of historical data access demand prediction levels and corresponding weight values, and can be dynamically adjusted, the read-write frequency fluctuation rate is the ratio of the difference between the read-write frequency and the read-write frequency average to the read-write frequency average, the cache temperature fluctuation rate is the ratio of the difference between the cache actual temperature and the cache temperature average to the cache temperature average, the read-write frequency fluctuation rate and the cache temperature fluctuation rate are combined with the first dynamic voltage regulation weight value for weighted mean processing to obtain the cache dynamic voltage regulation parameter; if the main memory real-time load is greater than the preset load threshold, the main memory real-time load level is high load, otherwise it is low load, the main memory real-time load level of high load or low load is represented by a specific numerical value, different task types correspond to different weight value allocation, the second dynamic voltage regulation weight value is obtained by querying the preset task weight value list according to the task type label data, the preset task weight value list is obtained by a person skilled in the art according to a large amount of historical task type label data and corresponding second dynamic voltage regulation weight values, and can be dynamically adjusted, the main memory real-time load level, the bandwidth occupancy ratio and the data request queue occupancy ratio are combined with the second dynamic voltage regulation weight value for weighted mean processing to obtain the main memory dynamic voltage regulation parameter; data reading and data writing have different voltage regulation requirements, and different data levels have different gradient requirements for voltage regulation, therefore, the storage data volume of the large-capacity auxiliary storage is compared with the preset data volume threshold to obtain the data level, if it is less than the preset data volume threshold, it is low level, otherwise it is high level, the low level and the high level are represented by specific numerical values, the corresponding data level and the auxiliary storage voltage adjustment gradient list are obtained according to the data operation type characteristic data, the data level and the auxiliary storage voltage adjustment gradient list are obtained by a person skilled in the art according to a large amount of historical data operation type characteristic data corresponding to the data level and the auxiliary storage voltage adjustment gradient, and then the auxiliary storage dynamic voltage regulation parameter is obtained by querying the data level and the auxiliary storage voltage adjustment gradient list according to the low level or the high level.

[0027] According to the embodiment of the application, the initial voltage of the memory-computing integrated chip is adjusted according to the dynamic voltage regulation parameter to obtain an adaptive voltage of the memory-computing integrated chip, including a cache adaptive voltage, a main memory adaptive voltage and an auxiliary storage adaptive voltage, comprising: adjusting the cache initial voltage according to the cache dynamic voltage regulation parameter to obtain a cache adaptive voltage; adjusting the main memory initial voltage according to the main memory dynamic voltage regulation parameter to obtain a main memory adaptive voltage; adjusting the auxiliary storage initial voltage according to the auxiliary storage dynamic voltage regulation parameter to obtain an auxiliary storage adaptive voltage.

[0028] It should be noted that the cache dynamic voltage adjustment parameter, the main memory dynamic voltage adjustment parameter and the auxiliary memory dynamic voltage adjustment parameter are used to adjust the corresponding cache initial matching voltage, the main memory initial matching voltage and the auxiliary memory initial matching voltage respectively, and the cache matching voltage, the main memory matching voltage and the auxiliary memory matching voltage are obtained, for example, the cache dynamic voltage adjustment parameter is 0.2, and the cache initial matching voltage is 1.0v, then (1+0.2)*1.0=1.2v is the cache matching voltage, and the main memory matching voltage and the auxiliary memory matching voltage can be obtained in the same way.

[0029] According to the embodiment of the present application, the operation of the storage-computing integrated chip is controlled according to the matching voltage, and the load monitoring data, the energy consumption monitoring data and the running state monitoring data corresponding to each chip of the storage-computing integrated chip cluster are obtained, comprising: The load monitoring data, the energy consumption monitoring data and the running state monitoring data corresponding to each chip of the storage-computing integrated chip cluster are obtained; The load monitoring data includes CPU utilization and data queue length to be processed; The energy consumption monitoring data includes real-time voltage, real-time current and preset collection time; The running state monitoring data includes chip real temperature mean value and data transmission rate.

[0030] It should be noted that in the computing cluster scenario composed of multiple chips, the load and energy consumption of each chip are significantly different, and the traditional independent voltage regulation mode is difficult to realize overall energy consumption optimization and performance guarantee. By establishing a high-speed inter-chip communication network between each chip, real-time information is shared; the load monitoring data including CPU utilization and data queue length to be processed is collected in real time, which is used to evaluate the load of each chip; the energy consumption monitoring data including real-time voltage, real-time current and preset collection time is used to evaluate the real-time energy consumption; and the running state monitoring data including chip real temperature mean value and data transmission rate is used to evaluate the running state of the chip.

[0031] According to the embodiment of the present application, the load monitoring data, the energy consumption data and the running state data are input into a preset global voltage regulation decision model for processing to obtain global voltage optimal regulation strategy data, and the storage-computing integrated chip cluster is regulated by voltage, comprising: The real-time voltage, the real-time current and the preset collection time are processed to obtain real-time energy consumption data; The CPU utilization, the data queue length to be processed, the real-time energy consumption data, the chip real temperature mean value and the data transmission rate are input into a preset global voltage regulation decision model for processing to obtain global voltage optimal regulation strategy data; The global voltage optimal regulation strategy data includes the planned regulation voltage and the planned regulation time corresponding to each chip of the storage-computing integrated chip cluster.

[0032] It should be noted that the real-time energy consumption data refers to the product of real-time voltage, real-time current and preset collection time, and the preset global voltage adjustment decision model is obtained by a person skilled in the art through obtaining a large number of historical samples of CPU utilization rate, data queue length to be processed, real-time energy consumption data, and the chip average temperature and data transmission rate and the corresponding global voltage optimal adjustment strategy data, using a distributed consistency algorithm to propose, vote and accept the voltage adjustment scheme, and finally obtaining the global optimal voltage adjustment strategy data, that is, the planned adjustment voltage and the planned adjustment time.

[0033] Please refer to Figure 3 , Figure 3 is the flow chart of determining the global voltage adjustment state in the mixed architecture-based memory-computing integrated chip voltage adjustment method in some embodiments of the present application. According to the embodiment of the present application, the running monitoring record data corresponding to each chip of the memory-computing integrated chip cluster is obtained and processed to obtain global voltage adjustment effectiveness data, and the global voltage adjustment state is determined according to the global voltage adjustment effectiveness data, which comprises: S31, obtaining running monitoring record data corresponding to each chip of the memory-computing integrated chip cluster, including CPU utilization rate, task time utilization rate, energy consumption rate, data throughput improvement rate and chip temperature drop rate; S32, processing according to the CPU utilization rate and the data queue length to be processed, obtaining real-time load level corresponding to each chip of the memory-computing integrated chip cluster; S33, querying the preset load and global voltage adjustment effectiveness weight value mapping table according to the real-time load level, obtaining adjustment effectiveness evaluation weight value corresponding to each chip; S34, combining the CPU utilization rate, task time utilization rate, energy consumption rate, data throughput improvement rate and chip temperature drop rate with the corresponding adjustment effectiveness evaluation weight value for weighted mean processing, obtaining chip voltage adjustment effectiveness data corresponding to each chip; S35, combining the chip voltage adjustment effectiveness data with the adjustment effectiveness evaluation weight value for weighted mean processing, obtaining global voltage adjustment effectiveness data; S351, if the global voltage adjustment effectiveness data is less than the preset global voltage adjustment expected data, it is determined that the global voltage adjustment state is unqualified; S352, if the global voltage adjustment effectiveness data is greater than or equal to the preset global voltage adjustment expected data, it is determined that the global voltage adjustment state is qualified.

[0034] It should be noted that the CPU utilization rate is compared with the preset CPU utilization threshold, and the data queue length to be processed is compared with the preset data queue length threshold, if they are all greater than the corresponding threshold, the real-time load level is a third load level, if they are all less than the corresponding threshold, the real-time load level is a first load level, and the rest is a second load level, wherein the third load level has the highest real-time load; the preset load and global voltage adjustment effectiveness weight value mapping table is queried according to the real-time load level adjusted by the global voltage, to obtain the adjustment effectiveness evaluation weight value corresponding to each chip, wherein the preset load and global voltage adjustment effectiveness weight value mapping table is obtained by a person skilled in the art by analyzing a large number of historical samples of real-time load level and corresponding global voltage adjustment effectiveness weight value, and can be dynamically adjusted, then the obtained CPU utilization rate, task time rate, energy consumption rate, data throughput rate and chip temperature rate are combined with the corresponding adjustment effectiveness evaluation weight value for weighted mean processing, to obtain the chip voltage adjustment effectiveness data corresponding to each chip, wherein the CPU utilization rate is the ratio of the difference between the CPU utilization rate before voltage adjustment and the CPU utilization rate after voltage adjustment to the CPU utilization rate before voltage adjustment, the task time rate is the ratio of the difference between the task time before voltage adjustment and the task time after voltage adjustment to the task time before voltage adjustment, the energy consumption rate is the ratio of the difference between the real-time energy consumption data before voltage adjustment and the real-time energy consumption data after voltage adjustment to the real-time energy consumption data before voltage adjustment, the data throughput rate is the ratio of the difference between the data throughput after voltage adjustment and the data throughput before voltage adjustment to the data throughput before voltage adjustment, and the chip temperature rate is the ratio of the difference between the chip real temperature mean value before voltage adjustment and the chip real temperature mean value after voltage adjustment to the chip real temperature mean value before voltage adjustment, and finally the threshold comparison is used to determine whether the global voltage adjustment state is qualified.

[0035] According to the embodiment of the application, the method further comprises: obtaining the instantaneous load of the storage-computing integrated chip; comparing the instantaneous load with the preset load reference value according to the short-time sliding window algorithm to obtain an instantaneous increase rate; if the instantaneous increase rate is greater than a preset instantaneous increase rate threshold, determining that the instantaneous load is a short-time burst load, and controlling the PID controller to adjust the voltage according to a preset proportion to obtain an instantaneous voltage; controlling the storage-computing integrated chip to run according to the instantaneous voltage.

[0036] It should be noted that high-frequency current sensors (sampling rate 1MHz) and instruction counters are deployed at key positions such as computing units and storage modules to monitor the instantaneous load of computing tasks in real time. For example, by monitoring the number of floating-point operation instructions in the instruction stream, the sudden computing demand can be quickly identified. A short sliding window algorithm (short window size 100us) is used in combination with a preset load reference value to analyze the sensor data in real time, obtain the instantaneous increase rate of the load, and compare it with the preset instantaneous increase rate threshold. If it is greater than the preset instantaneous increase rate threshold, it is determined to be a sudden load, and voltage adjustment needs to be realized in a very short time to ensure the timeliness of adjustment, that is, the PID controller adjusts the voltage according to the preset proportion to obtain the instantaneous voltage.

[0037] Please refer to Figure 4 , Figure 4 is a high-level flowchart of the method of various embodiments of the present application, which can be used for voltage adjustment method of mixed architecture-based memory-computing integrated chip. According to the embodiment of the present application, first, the initial matching voltage is determined according to different storage hierarchical types, the initial matching voltage is adjusted for the first time according to the dynamic voltage adjustment parameters obtained from the storage hierarchical type characteristic data and the corresponding data read-write demand data, and the corresponding adaptive voltage is obtained. Then, for the computing cluster scene composed of multiple chips, a preset global voltage adjustment decision model is constructed to realize global collaborative voltage adjustment. Finally, the voltage adjustment effectiveness state is monitored and evaluated in real time to realize voltage adaptation and adjustment of the memory-computing integrated chip based on the mixed architecture.

[0038] It is worth mentioning that, according to the embodiment of the present application, further comprising: obtain task characteristic parameter data of the task to be processed, including task metadata, task computing complexity, task data throughput and task timeliness level; divide the task flow according to the task metadata through a preset task flow decomposition template to obtain a task flow; obtain computing capability parameter data set, storage capability parameter data set and communication capability parameter data set of the chip; perform weighted sum processing on the computing capability parameter data to obtain a computing capability value, perform weighted sum processing on the storage capability parameter data set to obtain a storage capability value, and perform weighted sum processing on the communication capability parameter data set to obtain a communication capability value; standardize and weight the computing capability value, the storage capability value and the communication capability value to obtain a processing capability vector of the chip; match the computing complexity, the task data throughput and the task timeliness level with the processing capability vector to obtain a chip group corresponding to the task flow; obtain a corresponding voltage adjustment strategy according to the task flow, and perform voltage adjustment on the corresponding chip group.

[0039] It should be noted that the task flow-based chip dynamic grouping and voltage adjustment can effectively dynamically manage and voltage adapt the chips in the multi-chip cluster according to the characteristics of the computing task, and improve the overall energy efficiency of the cluster. First, according to the task metadata (such as task type label), the task flow is divided by the preset task flow decomposition template to obtain the task flow, such as dividing the big data analysis task into data collection, preprocessing, complex algorithm analysis and result output four task flows. Then, the processing capacity of the chip is evaluated, and the weighted sum processing is performed through the computing capacity parameter data (including floating point operation peak value, integer operation throughput and computing unit utilization fluctuation value) to obtain the computing capacity value, the weighted sum processing is performed according to the storage capacity parameter data set (storage capacity, read-write bandwidth and cache hit rate) to obtain the storage capacity value, the weighted sum processing is performed according to the communication capability parameter data set (including inter-chip transmission bandwidth, communication delay and network congestion rate) to obtain the communication capability value, and then the communication capability value is standardized to the interval [0, 1], and then the vector representation is performed in combination with the corresponding weight value, such as the computing capacity value, the storage capacity value and the communication capability value are 0.7, 0.9 and 0.6 respectively, and the corresponding weight value is 0.2, 0.6 and 0.2 respectively, then the processing capacity vector is [0.7*0.2, 0.9*0.6, 0.6*0.2], that is, [0.14, 0.54, 0.12]. Finally, the computing complexity, task data throughput and task timeliness level are matched with the processing capacity vector to obtain the chip group corresponding to the task flow. Each group of chips determines the matching voltage adjustment strategy according to the corresponding task flow.

[0040] The application also discloses a memory-compute integrated chip voltage adjustment system based on a hybrid architecture, which comprises a memory and a processor. Obtain the storage hierarchical type feature data, data read-write demand data and initial matching voltage of the memory-compute integrated chip. According to the storage hierarchical type feature data and the corresponding data read-write demand data, the dynamic voltage adjustment parameters are obtained, including the cache dynamic voltage adjustment parameter, the main memory dynamic voltage adjustment parameter and the auxiliary memory dynamic voltage adjustment parameter. According to the dynamic voltage adjustment parameters, the initial matching voltage of the memory-compute integrated chip is adjusted to obtain the adaptive voltage of the memory-compute integrated chip, including the cache adaptive voltage, the main memory adaptive voltage and the auxiliary memory adaptive voltage. According to the adaptive voltage, the operation of the memory-compute integrated chip is controlled to obtain the load monitoring data, the energy consumption monitoring data and the running state monitoring data of each chip in the memory-compute integrated chip cluster. The load monitoring data, energy consumption data and running state data are input into a preset global voltage regulation decision model for processing to obtain global voltage optimal regulation strategy data, and voltage regulation is performed on the storage-computing integrated chip cluster respectively; The running monitoring record data corresponding to each chip of the storage-computing integrated chip cluster are acquired and processed to obtain global voltage regulation effectiveness data, and the global voltage regulation state is determined according to the global voltage regulation effectiveness data.

[0041] It should be noted that, according to the characteristics of different storage levels, a storage hierarchical management method is developed to achieve a good balance between high performance and low power consumption of the storage-computing integrated chip in different application scenarios. The initial matching voltage of different storage hierarchies is set by the person skilled in the art according to historical running records and experience, and the dynamic voltage regulation parameters are obtained by processing the storage hierarchy type characteristic data and the corresponding data read-write demand data, and the initial matching voltage of different storage hierarchies is dynamically adjusted. Each chip integrates an inter-chip communication module, which can quickly and stably share state information with other chips during operation, realize real-time monitoring and data sharing of the chip cluster, and thus realize collaborative voltage regulation according to the global voltage regulation decision model, and real-time evaluation of global voltage regulation effectiveness, and dynamic adjustment of global voltage optimal regulation strategy data according to the evaluation results.

[0042] According to the embodiment of the application, the storage hierarchy type characteristic data and the corresponding data read-write demand data of the storage-computing integrated chip are obtained, including: The storage hierarchy type characteristic data of the storage-computing integrated chip includes cache type characteristic data, main memory type characteristic data and auxiliary storage type characteristic data; According to the cache type characteristic data, main memory type characteristic data or auxiliary storage type characteristic data, a preset storage hierarchy type and chip initial matching voltage mapping table is queried to obtain the corresponding initial matching voltage, including cache initial matching voltage, main memory initial matching voltage and auxiliary storage initial matching voltage; The data read-write demand data includes cache data read-write demand data, main memory data read-write demand data and auxiliary storage data read-write demand data; The cache data read-write demand data includes read-write frequency, cache real temperature and data access demand prediction level; The main memory data read-write demand data includes main memory real-time load, read-write bandwidth, data request queue length and task type label data; The auxiliary storage data read-write demand data includes data operation type characteristic data and data volume.

[0043] It should be noted that in the memory-computing integrated chip, the memory hierarchy and dynamic voltage adaptation can improve the overall performance and energy efficiency ratio of the chip, wherein the memory hierarchy type includes cache, main memory and large capacity auxiliary storage, that is, represented by cache type feature data, main memory type feature data and auxiliary storage type feature data, in the embodiment, the cache type feature data, the main memory type feature data and the auxiliary storage type feature data are represented by different numerical values and can be adjusted, and the preset memory hierarchy type and chip initial voltage mapping table is obtained by analyzing a large amount of historical chip running information by a person skilled in the art, and can be dynamically adjusted; the cache data read-write demand data includes read-write frequency, cache real temperature and data access demand prediction level, wherein the data access demand prediction level is obtained by a person skilled in the art using time series analysis algorithm such as ARIMA to process historical data access time, access frequency and data volume of cache, and to predict the probability of data access and corresponding data volume in the next time period; the main memory data read-write demand data includes main memory real-time load, read-write bandwidth, data request queue length and task type label data, wherein the task type includes simple lightweight task and complex high-load task, the task type of the current running task can be identified by means of task scheduling system and software label, and the simple lightweight task type label data and the complex high-load task type label data are represented by different numerical values; the auxiliary storage data read-write demand data includes data operation type feature data and data volume, wherein the data operation type includes data writing and data reading (including sequential reading and random reading), and the data writing feature data and the data reading feature data are represented by different numerical values.

[0044] According to the embodiment of the application, the processing according to the memory hierarchy type feature data and the corresponding data read-write demand data to obtain dynamic voltage adjustment parameters includes cache dynamic voltage adjustment parameters, main memory dynamic voltage adjustment parameters and auxiliary storage dynamic voltage adjustment parameters, which includes: According to the data access demand prediction level, a preset access demand weight value list is queried to obtain a first dynamic voltage weight value; According to the read-write frequency, the read-write frequency average of the historical preset time period is processed to obtain the read-write frequency fluctuation rate, and according to the cache real temperature, the cache temperature average of the historical preset time period is processed to obtain the cache temperature fluctuation rate; According to the read-write frequency fluctuation rate and the cache temperature fluctuation rate, the first dynamic voltage weight value is processed to obtain the cache dynamic voltage adjustment parameter; The main memory real-time load is compared with the preset load threshold to obtain the main memory real-time load level, the read-write bandwidth is processed with the preset peak bandwidth to obtain the bandwidth ratio, and the data request queue length is compared with the preset queue length threshold to obtain the data request queue ratio; According to the task type label data, a preset task weight value list is queried to obtain a second dynamic voltage regulation weight value; According to the main memory real-time load level, bandwidth proportion, and data request queue proportion, combined with the second dynamic voltage regulation weight value, weighted mean processing is performed to obtain a main memory dynamic voltage regulation parameter; The data amount is compared with a preset data amount threshold to obtain a data level; According to the data operation type feature data, a corresponding data level and auxiliary storage voltage adjustment gradient list are obtained, and according to the data level, the corresponding data level and auxiliary storage voltage adjustment gradient list are queried to obtain an auxiliary storage dynamic voltage regulation parameter.

[0045] It should be noted that different data access demand prediction levels correspond to different weight value distributions, wherein the preset access demand weight value list is obtained by a person skilled in the art according to a large amount of historical data access demand prediction levels and corresponding weight values, and can be dynamically adjusted. The read-write frequency fluctuation rate is the ratio of the difference between the read-write frequency and the read-write frequency mean to the read-write frequency mean. The cache temperature fluctuation rate is the ratio of the difference between the cache real temperature and the cache temperature mean to the cache temperature mean. The read-write frequency fluctuation rate and the cache temperature fluctuation rate are combined with the first dynamic voltage regulation weight value to obtain a weighted mean processing to obtain a cache dynamic voltage regulation parameter. If the main memory real-time load is greater than a preset load threshold, the main memory real-time load level is high load, otherwise it is low load. The high load or low load of the main memory real-time load level is represented by a specific numerical value. Different task types correspond to different weight value distributions. According to the task type label data, a preset task weight value list is queried to obtain a second dynamic voltage regulation weight value. The preset task weight value list is obtained by a person skilled in the art according to a large amount of historical task type label data and corresponding second dynamic voltage regulation weight values, and can be dynamically adjusted. The main memory real-time load level, bandwidth proportion, and data request queue proportion are combined with the second dynamic voltage regulation weight value to obtain a weighted mean processing to obtain a main memory dynamic voltage regulation parameter. Data reading and data writing have different voltage regulation requirements, and different data levels have different gradient requirements for voltage regulation. Therefore, the storage data amount of the large-capacity auxiliary storage is compared with a preset data amount threshold to obtain a data level. If it is less than the preset data amount threshold, it is low level, otherwise it is high level. The low level and the high level are represented by specific numerical values. First, according to the data operation type feature data, a corresponding data level and auxiliary storage voltage adjustment gradient list are obtained. The data level and auxiliary storage voltage adjustment gradient list are obtained by a person skilled in the art according to a large amount of historical data operation type feature data corresponding to the data level and auxiliary storage voltage adjustment gradient. Then, according to the low level or high level, the data level and auxiliary storage voltage adjustment gradient list are queried to obtain an auxiliary storage dynamic voltage regulation parameter.

[0046] According to the embodiment of the present application, the initial voltage of the chip is adjusted according to the dynamic voltage adjustment parameter, and the adaptive voltage of the chip is obtained, including the cache adaptive voltage, the main memory adaptive voltage and the auxiliary memory adaptive voltage, which comprises: The initial voltage of the cache is adjusted according to the dynamic voltage adjustment parameter of the cache, and the adaptive voltage of the cache is obtained. The initial voltage of the main memory is adjusted according to the dynamic voltage adjustment parameter of the main memory, and the adaptive voltage of the main memory is obtained. The initial voltage of the auxiliary memory is adjusted according to the dynamic voltage adjustment parameter of the auxiliary memory, and the adaptive voltage of the auxiliary memory is obtained.

[0047] It should be noted that the initial voltage of the cache, the initial voltage of the main memory and the initial voltage of the auxiliary memory are respectively adjusted according to the obtained dynamic voltage adjustment parameter of the cache, the dynamic voltage adjustment parameter of the main memory and the dynamic voltage adjustment parameter of the auxiliary memory, and the adaptive voltage of the cache, the adaptive voltage of the main memory and the adaptive voltage of the auxiliary memory are obtained, for example, the dynamic voltage adjustment parameter of the cache is 0.2, the initial voltage of the cache is 1.0v, then (1+0.2)*1.0=1.2v is the adaptive voltage of the cache, and the adaptive voltage of the main memory and the adaptive voltage of the auxiliary memory can be obtained in the same way.

[0048] According to the embodiment of the present application, the adaptive voltage is used to control the operation of the chip, and the load monitoring data, the energy consumption monitoring data and the running state monitoring data corresponding to each chip in the chip cluster are obtained, which comprises: The load monitoring data, the energy consumption monitoring data and the running state monitoring data corresponding to each chip in the chip cluster are obtained. The load monitoring data includes CPU utilization and data queue length. The energy consumption monitoring data includes real-time voltage, real-time current and preset collection time. The running state monitoring data includes chip real temperature mean and data transmission rate.

[0049] It should be noted that in the computing cluster scenario composed of multiple chips, the load and energy consumption of each chip are significantly different, and the traditional independent voltage adjustment method is difficult to realize the overall energy consumption optimization and performance guarantee. By establishing a high-speed inter-chip communication network between each chip, real-time information is shared; the load monitoring data including CPU utilization and data queue length is collected in real time, which is used to evaluate the load of each chip; the energy consumption monitoring data including real-time voltage, real-time current and preset collection time is used to evaluate the real-time energy consumption; and the running state monitoring data including chip real temperature mean and data transmission rate is used to evaluate the running state of the chip.

[0050] According to the embodiment of the present application, the load monitoring data, energy consumption data and running state data are input into a preset global voltage regulation decision model for processing to obtain global voltage optimal regulation strategy data, and the storage-computing integrated chip cluster is regulated in voltage respectively, comprising: According to the real-time voltage, real-time current and preset collection time, real-time energy consumption data is obtained by processing; The CPU utilization rate, to-be-processed data queue length, real-time energy consumption data, chip real temperature mean value and data transmission rate are input into a preset global voltage regulation decision model for processing to obtain global voltage optimal regulation strategy data; The global voltage optimal regulation strategy data comprises planned regulation voltage and planned regulation time corresponding to each chip of the storage-computing integrated chip cluster.

[0051] It should be noted that the real-time energy consumption data refers to the product of real-time voltage, real-time current and preset collection time, and the preset global voltage regulation decision model is obtained by a distributed consistency algorithm for proposing, voting and accepting voltage regulation scheme by obtaining a large number of historical samples of CPU utilization rate, to-be-processed data queue length, real-time energy consumption data, chip real temperature mean value and data transmission rate and corresponding global voltage optimal regulation strategy data, and finally obtaining global optimal voltage regulation strategy data, i.e. planned regulation voltage and planned regulation time.

[0052] According to the embodiment of the present application, the running monitoring record data corresponding to each chip of the storage-computing integrated chip cluster is obtained and processed to obtain global voltage regulation effectiveness data, and the global voltage regulation state is determined according to the global voltage regulation effectiveness data, comprising: The running monitoring record data corresponding to each chip of the storage-computing integrated chip cluster is obtained, comprising CPU utilization rate, task time utilization rate, energy consumption rate, data throughput improvement rate and chip temperature drop rate; According to the CPU utilization rate and to-be-processed data queue length, real-time load level corresponding to each chip of the storage-computing integrated chip cluster is obtained by processing; According to the real-time load level, a preset load and global voltage regulation effectiveness weight value mapping table is queried to obtain regulation effectiveness evaluation weight value corresponding to each chip; The CPU utilization rate, task time utilization rate, energy consumption rate, data throughput improvement rate and chip temperature drop rate are combined with the corresponding regulation effectiveness evaluation weight value for weighted mean processing to obtain chip voltage regulation effectiveness data corresponding to each chip; The chip voltage regulation effectiveness data is combined with the regulation effectiveness evaluation weight value for weighted mean processing to obtain global voltage regulation effectiveness data; If the global voltage regulation actual data is less than the preset global voltage regulation expected data, it is determined that the global voltage regulation state is unqualified. If the global voltage regulation actual data is greater than or equal to the preset global voltage regulation expected data, it is determined that the global voltage regulation state is qualified.

[0053] It should be noted that the CPU utilization rate and the preset CPU utilization threshold, the data queue length and the preset data queue length threshold are compared, if they are all greater than the corresponding threshold, the real-time load level is a third load level, if they are all less than the corresponding threshold, the real-time load level is a first load level, and the rest is a second load level, wherein the third load level has the highest real-time load; according to the real-time load level after global voltage regulation, a preset load and global voltage regulation actual weight value mapping table is queried to obtain the adjustment actual evaluation weight value corresponding to each chip, wherein the preset load and global voltage regulation actual weight value mapping table is obtained by a person skilled in the art by analyzing a large number of historical sample real-time load levels and corresponding global voltage regulation actual weight values, and can be dynamically adjusted, then the obtained CPU utilization rate, task time utilization rate, energy consumption rate, data throughput rate and chip temperature rate are combined with the corresponding adjustment actual evaluation weight value for weighted mean processing to obtain the chip voltage regulation actual data corresponding to each chip, wherein the CPU utilization rate is the ratio of the difference between the CPU utilization rate before voltage regulation and the CPU utilization rate after voltage regulation to the CPU utilization rate before voltage regulation, the task time utilization rate is the ratio of the difference between the task time before voltage regulation and the task time after voltage regulation to the task time before voltage regulation, the energy consumption rate is the ratio of the difference between the real-time energy consumption data before voltage regulation and the real-time energy consumption data after voltage regulation to the real-time energy consumption data before voltage regulation, the data throughput rate is the ratio of the difference between the data throughput after voltage regulation and the data throughput before voltage regulation to the data throughput before voltage regulation, and the chip temperature rate is the ratio of the difference between the chip real temperature mean value before voltage regulation and the chip real temperature mean value after voltage regulation to the chip real temperature mean value before voltage regulation, and finally the threshold is compared to determine whether the global voltage regulation state is qualified.

[0054] According to the embodiment of the application, further comprising: Obtaining the instantaneous load of the storage-computing integrated chip; Comparing the instantaneous load with the preset load reference value according to the short-time sliding window algorithm to obtain an instantaneous increase rate; If the instantaneous increase rate is greater than the preset instantaneous increase rate threshold, it is determined that the instantaneous load is a short-time burst load, and the PID controller is controlled to adjust the voltage according to the preset proportion to obtain an instantaneous voltage; Controlling the storage-computing integrated chip to run according to the instantaneous voltage.

[0055] It should be noted that high-frequency current sensors (sampling rate 1MHz) and instruction counters are deployed at key positions such as computing units and storage modules to monitor the instantaneous load of computing tasks in real time. For example, by monitoring the number of floating-point operation instructions in the instruction stream, the sudden computing demand can be quickly identified. A short sliding window algorithm (short window size 100us) is used in combination with a preset load reference value to analyze the sensor data in real time, obtain the instantaneous increase rate of the load, and compare it with the preset instantaneous increase rate threshold. If it is greater than the preset instantaneous increase rate threshold, it is determined to be a sudden load, and voltage adjustment needs to be realized in a very short time to ensure the timeliness of adjustment, that is, the PID controller adjusts the voltage according to the preset proportion to obtain the instantaneous voltage.

[0056] According to the embodiment of the present application, first, the initial matching voltage is determined according to different storage hierarchical types, and the initial matching voltage is adjusted according to the dynamic voltage adjustment parameters obtained from the storage hierarchical type characteristic data and the corresponding data read-write demand data to obtain the corresponding adaptive voltage. Then, for the computing cluster scene composed of multiple chips, a preset global voltage adjustment decision model is constructed to realize global collaborative voltage adjustment. Finally, the voltage adjustment effectiveness state is monitored and evaluated in real time to realize voltage adaptation adjustment of the compute-in-memory chip based on the hybrid architecture.

[0057] It is worth mentioning that, according to the embodiment of the present application, further comprising: Obtain task characteristic parameter data of the task to be processed, including task metadata, task computing complexity, task data throughput, and task timeliness level; Divide the task flow according to the task metadata through a preset task flow decomposition template to obtain a task flow; Obtain computing capability parameter data set, storage capability parameter data set, and communication capability parameter data set of the chip; Perform weighted summation processing on the computing capability parameter data to obtain a computing capability value, perform weighted summation processing on the storage capability parameter data set to obtain a storage capability value, and perform weighted summation processing on the communication capability parameter data set to obtain a communication capability value; Standardize and weight the computing capability value, storage capability value, and communication capability value to obtain a processing capability vector of the chip; Match the computing complexity, task data throughput, and task timeliness level with the processing capability vector to obtain a chip group corresponding to the task flow; Obtain the corresponding voltage adjustment strategy according to the task flow, and perform voltage adjustment on the corresponding chip group.

[0058] It should be noted that the task flow based chip dynamic grouping and voltage regulation can effectively dynamically manage and voltage adapt the chips in the multi-chip cluster according to the characteristics of the computing task, and improve the overall energy efficiency of the cluster; first, according to the task metadata (such as task type label), the task flow is divided by the preset task flow decomposition template, and the task flow is obtained, such as dividing the big data analysis task into data collection, preprocessing, complex algorithm analysis and result output four task flows, then, the processing capacity of the chip is evaluated, the computing capacity parameter data (including floating point operation peak value, integer operation throughput and computing unit utilization fluctuation value) is processed by weighted summation, the computing capacity value is obtained, the storage capacity parameter data set (storage capacity, read-write bandwidth and cache hit rate) is processed by weighted summation, the storage capacity value is obtained, the communication capability parameter data set (including inter-chip transmission bandwidth, communication delay and network congestion rate) is processed by weighted summation, the communication capability value is obtained, and then standardized to the [0, 1] interval, and then combined with the corresponding weight value to perform vectorization, such as the computing capacity value, the storage capacity value and the communication capability value are 0.7, 0.9 and 0.6 respectively, and the corresponding weight values are 0.2, 0.6 and 0.2 respectively, then the processing capability vector is [0.7*0.2, 0.9*0.6, 0.6*0.2], that is, [0.14, 0.54, 0.12]; finally, the computing complexity, task data throughput and task timeliness level are matched with the processing capability vector to obtain the chip group corresponding to the task flow, and each chip group determines the matching voltage regulation strategy according to the corresponding task flow.

[0059] The third aspect of the application provides a readable storage medium, wherein a hybrid architecture based memory-computing integrated chip voltage regulation method program is stored in the readable storage medium, and the hybrid architecture based memory-computing integrated chip voltage regulation method program is executed by a processor to implement the steps of the hybrid architecture based memory-computing integrated chip voltage regulation method according to any one of the above.

[0060] The hybrid architecture based memory-computing integrated chip voltage regulation method, system and medium disclosed by the application obtain dynamic voltage regulation parameters of different storage layers through analysis and processing, preliminarily adjust the corresponding initial matching voltage, and then globally analyze the chip cluster to determine the global voltage optimal regulation strategy data, and monitor the regulation state in real time, so as to realize voltage adaptation and regulation of the memory-computing integrated chip based on the hybrid architecture.

[0061] In several embodiments provided in the present application, it should be understood that the disclosed devices and methods can be implemented in other manners. The above described device embodiments are merely exemplary. For example, the division of the units is merely a logical function division. There can be another division manner for the actual implementation, for example, multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. In addition, the displayed or discussed coupling, or direct coupling or communication connection between the components can be indirect coupling or communication connection through some interfaces, devices, or units, and can be electrical, mechanical, or in other forms.

[0062] The units described as separate components can or can not be physically separate, and the components shown as units can or can not be physical units; they can be located in one place or distributed on multiple network units; and part or all of the units can be selected as needed to achieve the purposes of the embodiments.

[0063] In addition, each functional unit in each embodiment of the present application can be integrated into one processing unit, or each unit can be a separate unit, or two or more units can be integrated into one unit; and the integrated unit can be implemented in the form of hardware or hardware plus software functional units.

[0064] Those of ordinary skill in the art can understand that all or part of the steps of the above-described method embodiments can be completed by a program instructing related hardware, and the foregoing program can be stored in a readable storage medium, and when the program is executed, the steps of the method embodiments are executed; and the foregoing storage medium includes mobile storage devices, read-only memories (ROMs), random access memories (RAMs), magnetic disks or optical disks, and various media that can store program codes.

[0065] Alternatively, the integrated units of the present application, if implemented in the form of software functional modules and sold or used as independent products, can also be stored in a readable storage medium. Based on this understanding, the technical solutions of the embodiments of the present application can be embodied in the form of a software product, which is stored in a storage medium and includes several instructions for causing a computer device (which can be a personal computer, a server, or a network device, etc.) to execute all or part of the methods described in the embodiments of the present application. The foregoing storage medium includes mobile storage devices, ROMs, RAMs, magnetic disks or optical disks, and various media that can store program codes.

Claims

1. A voltage regulation method for in-memory computing chips based on a hybrid architecture, characterized in that, Includes the following steps: Obtain the storage tier type characteristic data, data read / write requirement data, and initial voltage of the in-memory computing chip; The storage tier type feature data and the corresponding data read / write requirements data are processed to obtain dynamic voltage adjustment parameters, including cache dynamic voltage adjustment parameters, main memory dynamic voltage adjustment parameters and secondary storage dynamic voltage adjustment parameters. The initial voltage of the in-memory computing chip is adjusted according to the dynamic voltage adjustment parameters to obtain the adaptation voltage of the in-memory computing chip, including the cache adaptation voltage, the main memory adaptation voltage and the secondary memory adaptation voltage. The in-memory computing chip is controlled to operate according to the adaptive voltage, and load monitoring data, energy consumption monitoring data and operating status monitoring data corresponding to each chip in the in-memory computing chip cluster are obtained. The load monitoring data, energy consumption data, and operating status data are input into a preset global voltage regulation decision model for processing to obtain global optimal voltage regulation strategy data, and voltage regulation is performed on the in-memory computing chip cluster respectively. The system acquires and processes the operational monitoring data corresponding to each chip in the in-memory computing chip cluster to obtain global voltage regulation effectiveness data, and determines the global voltage regulation status based on the global voltage regulation effectiveness data.

2. The voltage regulation method for in-memory computing chips based on a hybrid architecture according to claim 1, characterized in that, The acquisition of the storage tier type characteristic data and corresponding data read / write requirement data of the in-memory computing chip includes: Obtain the storage tier type characteristic data of the in-memory computing chip, including cache type characteristic data, main memory type characteristic data and secondary storage type characteristic data; Based on the cache type feature data, main memory type feature data, or secondary memory type feature data, respectively query the preset storage layer type and chip initial voltage mapping table to obtain the corresponding initial voltage, including cache initial voltage, main memory initial voltage, and secondary memory initial voltage. Obtain data read / write requirements, including cache data read / write requirements, main memory data read / write requirements, and secondary storage data read / write requirements. The cache data read / write demand data includes read / write frequency, cache temperature, and data access demand prediction level. The main memory data read / write requirement data includes main memory real-time load, read / write bandwidth, data request queue length, and task type label data; The secondary storage data read / write requirements include data operation type characteristics and data volume.

3. The voltage regulation method for in-memory computing chips based on a hybrid architecture according to claim 2, characterized in that, The process involves processing the storage tier type characteristic data and corresponding data read / write requirements to obtain dynamic voltage adjustment parameters, including cache dynamic voltage adjustment parameters, main memory dynamic voltage adjustment parameters, and secondary storage dynamic voltage adjustment parameters, including: Based on the data access demand prediction level, query the list of preset access demand weight values ​​to obtain the first dynamic voltage regulation weight value; The read / write frequency fluctuation rate is obtained by processing the read / write frequency in combination with the average read / write frequency over a historical preset time period. The cache temperature fluctuation rate is obtained by processing the cache actual temperature in combination with the average cache temperature over a historical preset time period. The read / write frequency fluctuation rate and cache temperature fluctuation rate are combined with the first dynamic voltage regulation weight value to obtain the cache dynamic voltage regulation parameters. The real-time load of the main memory is compared with a preset load threshold to obtain the real-time load level of the main memory; the read / write bandwidth is processed with a preset peak bandwidth to obtain the bandwidth ratio; and the data request queue length is compared with a preset queue length threshold to obtain the data request queue ratio. Based on the task type label data, query the preset task weight value list to obtain the second dynamic voltage regulation weight value; The main memory dynamic voltage regulation parameters are obtained by weighting and averaging the main memory real-time load level, bandwidth ratio, and data request queue ratio in combination with the second dynamic voltage regulation weight value. The data volume is compared with a preset data volume threshold to obtain the data volume level; Based on the data operation type characteristic data, obtain the corresponding data volume and secondary storage voltage adjustment gradient list, and obtain the secondary storage dynamic voltage adjustment parameters by querying the corresponding data volume and secondary storage voltage adjustment gradient list based on the data volume.

4. The voltage regulation method for in-memory computing chips based on a hybrid architecture according to claim 3, characterized in that, The adjustment of the initial voltage of the in-memory computing chip according to the dynamic voltage adjustment parameters to obtain the adaptation voltage of the in-memory computing chip includes cache adaptation voltage, main memory adaptation voltage, and secondary memory adaptation voltage, including: Adjust the initial voltage of the cache according to the cache dynamic voltage adjustment parameters to obtain the cache adaptation voltage; The initial voltage of the main memory is adjusted according to the main memory dynamic voltage adjustment parameters to obtain the main memory adaptation voltage; Adjust the initial voltage of the secondary storage according to the secondary storage dynamic voltage adjustment parameters to obtain the secondary storage adaptation voltage.

5. The voltage regulation method for in-memory computing chips based on a hybrid architecture according to claim 4, characterized in that, The step of controlling the operation of the in-memory computing chip according to the adapted voltage, and acquiring load monitoring data, energy consumption monitoring data, and operating status monitoring data corresponding to each chip in the in-memory computing chip cluster, includes: Acquire load monitoring data, energy consumption monitoring data, and operating status monitoring data for each chip in the in-memory computing chip cluster; The load monitoring data includes CPU utilization and the length of the data queue to be processed. The energy consumption monitoring data includes real-time voltage, real-time current, and preset acquisition time; The operational status monitoring data includes the average chip temperature and data transmission rate.

6. The voltage regulation method for a hybrid architecture-based in-memory computing chip according to claim 5, characterized in that, The process involves inputting the load monitoring data, energy consumption data, and operating status data into a preset global voltage regulation decision model for processing to obtain global optimal voltage regulation strategy data, and then performing voltage regulation on the in-memory computing chip cluster, including: The real-time voltage, real-time current and preset acquisition time are processed to obtain real-time energy consumption data; The CPU utilization, the length of the data queue to be processed, the real-time energy consumption data, the average actual temperature of the chip and the data transmission rate are input into a preset global voltage regulation decision model for processing to obtain global voltage optimal regulation strategy data. The global voltage optimal adjustment strategy data includes the planned adjustment voltage and planned adjustment time for each chip in the in-memory computing chip cluster.

7. The voltage regulation method for a memory computing chip based on a hybrid architecture according to claim 6, characterized in that, The process of acquiring and processing the operational monitoring records of each chip in the in-memory computing chip cluster to obtain global voltage regulation effectiveness data, and determining the global voltage regulation status based on the global voltage regulation effectiveness data, includes: Acquire the operation monitoring record data corresponding to each chip in the in-memory computing chip cluster, including CPU utilization decline rate, task time decline rate, energy consumption decline rate, data throughput improvement rate, and chip temperature decline rate; The CPU utilization and the length of the data queue to be processed are used to obtain the real-time load level of each chip in the in-memory computing chip cluster. Based on the real-time load level, query the preset load and global voltage regulation effectiveness weight value mapping table to obtain the regulation effectiveness evaluation weight value corresponding to each chip; The CPU utilization decline rate, task time decline rate, energy consumption decline rate, data throughput improvement rate and chip temperature decline rate are combined with the corresponding adjustment effectiveness evaluation weight values ​​and weighted averaged to obtain the chip voltage adjustment effectiveness data for each chip. The chip voltage regulation effectiveness data is combined with the regulation effectiveness evaluation weight value and weighted average is processed to obtain global voltage regulation effectiveness data. If the actual global voltage regulation data is less than the preset expected global voltage regulation data, the global voltage regulation status is determined to be unqualified. If the actual global voltage regulation data is greater than or equal to the preset expected global voltage regulation data, then the global voltage regulation status is determined to be qualified.

8. The voltage regulation method for a hybrid architecture-based in-memory computing chip according to claim 7, characterized in that, Also includes: Obtain the instantaneous load of the in-memory computing chip; The instantaneous load is compared with a preset load baseline value using a short-time sliding window algorithm to obtain the instantaneous increase rate. If the instantaneous rise rate is greater than the preset instantaneous rise rate threshold, the instantaneous load is determined to be a short-term burst load, and the PID controller is controlled to adjust the voltage according to a preset ratio to obtain the instantaneous voltage; The operation of the in-memory computing chip is controlled based on the instantaneous voltage.

9. A voltage regulation system for in-memory computing chips based on a hybrid architecture, characterized in that, The system includes a memory and a processor. The memory contains a program for a voltage regulation method for an in-memory computing chip based on a hybrid architecture. When the processor executes the program for the voltage regulation method for an in-memory computing chip based on a hybrid architecture, it performs the following steps: Obtain the storage tier type characteristic data, data read / write requirement data, and initial voltage of the in-memory computing chip; The storage tier type feature data and the corresponding data read / write requirements data are processed to obtain dynamic voltage adjustment parameters, including cache dynamic voltage adjustment parameters, main memory dynamic voltage adjustment parameters and secondary storage dynamic voltage adjustment parameters. The initial voltage of the in-memory computing chip is adjusted according to the dynamic voltage adjustment parameters to obtain the adaptation voltage of the in-memory computing chip, including the cache adaptation voltage, the main memory adaptation voltage and the secondary memory adaptation voltage. The in-memory computing chip is controlled to operate according to the adaptive voltage, and load monitoring data, energy consumption monitoring data and operating status monitoring data corresponding to each chip in the in-memory computing chip cluster are obtained. The load monitoring data, energy consumption data, and operating status data are input into a preset global voltage regulation decision model for processing to obtain global optimal voltage regulation strategy data, and voltage regulation is performed on the in-memory computing chip cluster respectively. The system acquires and processes the operational monitoring data corresponding to each chip in the in-memory computing chip cluster to obtain global voltage regulation effectiveness data, and determines the global voltage regulation status based on the global voltage regulation effectiveness data.

10. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores a program for a voltage regulation method for a hybrid architecture-based in-memory computing chip. When the program for the voltage regulation method for a hybrid architecture-based in-memory computing chip is executed by a processor, it implements the steps of the voltage regulation method for a hybrid architecture-based in-memory computing chip as described in any one of claims 1 to 8.

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