Custom logic circuit and design method for peripheral interface

Abstract

The application relates to the fields of integrated circuits and chip design, and provides a customized logic circuit and design method for peripheral interfaces, which comprises a clock generation module for generating clock signals required by different peripheral interface IPs according to a main clock signal; a synchronous reset module for generating reset signals required by different peripheral interface IPs according to a main reset signal; a self-defined register read-write module for connecting detection signals of the peripheral interface IPs to a state register, reading the state register through a bus, connecting control signals of the peripheral interface IPs to a to-be-configured register, and performing a configuration operation on the register inside the peripheral interface IP through the bus; and a parity check module for generating parity check codes on data links at outputs and inputs of the peripheral interface, and comparing the parity check codes. The application can save a chip design period and accelerate the integration time of a high-speed peripheral interface IP of an SoC chip.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of integrated circuits and chip design, in particular to a customized logic circuit for peripheral interface and a design method. BACKGROUND

[0002] In the process of SoC (System on Chip) chip design, it is necessary to integrate the controller circuit of high-speed peripheral interface IP (Intellectual Property, refers to the "design module" of DDR controller or PHY, which is integrated into SoC as intellectual property IP), such as DDR SDRAM (Double Data Rate Synchronous Dynamic Random Access Memory), PCIE (Peripheral Component Interconnect Express) and other device controllers.

[0003] With the continuous improvement of the performance of SoC chip processor core, the demand for peripheral access rate also gradually increases. With the continuous development of high-speed peripheral interface circuit, the mainstream peripheral interface circuit, such as DDR interface, PCIE interface, etc., gradually forms an IP product with perfect function and high performance. In the process of SoC chip design, it is necessary to integrate high-speed peripheral interface circuit IP. With the increase of the scale of SoC chip and the scale of high-speed peripheral interface circuit IP, the complexity of SoC chip integrated high-speed peripheral interface circuit IP also increases. The design efficiency of interface circuit IP affects the whole SoC chip design and process, and also affects the performance of the chip. SUMMARY

[0004] In view of the problems existing in the prior art, the present application provides a customized logic circuit for peripheral interface and a design method.

[0005] The present application provides a customized logic circuit for peripheral interface, which comprises a clock generation module, a synchronous reset module, a self-defined register read-write module and a parity check module, wherein:

[0006] The clock generation module is used for generating clock signals required by different peripheral interface IPs according to the input main clock signal;

[0007] The synchronous reset module is used for generating reset signals required by different peripheral interface IPs according to the input main reset signal;

[0008] The custom register read-write module is used for connecting the detection signal of the peripheral interface IP to the state register, so that the chip processor core can read the state register through the bus, and connecting the control signal of the peripheral interface IP to the to-be-configured register, so that the chip processor core can perform configuration operation on the register inside the peripheral interface IP through the bus.

[0009] The parity check module is used for generating parity check codes on the data link at the output and input of the peripheral interface IP, and comparing the parity check codes.

[0010] According to the application, the clock generation module is specifically used for:

[0011] Obtaining a plurality of main clock signals inputted;

[0012] According to a preset clock frequency requirement, a clock enable signal generated by the custom register read-write module is accessed;

[0013] According to the clock enable signal, a required main clock signal is selected from the plurality of main clock signals;

[0014] According to the required main clock signal, a clock signal required by different peripheral interface IPs is generated.

[0015] According to the application, the synchronous reset module is specifically used for:

[0016] Obtaining a main reset signal inputted;

[0017] According to a preset reset requirement, a reset enable signal generated by the custom register read-write module is accessed;

[0018] According to the reset enable signal, the clock signal required by different peripheral interface IPs and the main reset signal, a reset signal required by different peripheral interface IPs is generated.

[0019] According to the application, the custom register read-write module is specifically used for:

[0020] Obtaining a to-be-detected peripheral interface IP identifier;

[0021] According to a correspondence between a preset peripheral interface IP identifier and a state register label, a to-be-read state register is determined;

[0022] Reading state information of the to-be-detected peripheral interface IP from the to-be-read state register through the bus.

[0023] The application provides a customized logic circuit for peripheral interface, and the self-defined register read-write module is specifically used for:

[0024] obtaining register parameter information corresponding to a control signal type to be configured;

[0025] determining a label of a register to be configured in the peripheral interface IP;

[0026] configuring parameters on the register corresponding to the label through the bus according to the register parameter information.

[0027] The application provides a customized logic circuit for peripheral interface, and the parity check module comprises a parity check generation module and a parity check checking module, wherein:

[0028] The parity check generation module is used for generating a first parity check code on a data link at an input of the peripheral interface IP;

[0029] The parity check checking module is used for generating a second parity check code on a data link at an output of the peripheral interface IP, and comparing the first parity check code with the second parity check code.

[0030] The application further provides a customized logic circuit design method for peripheral interface, comprising:

[0031] generating a clock signal required by adaptation to different peripheral interface IPs according to an input main clock signal;

[0032] generating a reset signal required by adaptation to different peripheral interface IPs according to an input main reset signal;

[0033] connecting a detection signal of the peripheral interface IP to a state register, so that a chip processor core can read the state register through a bus, and connecting a control signal of the peripheral interface IP to a register to be configured, so that the chip processor core can perform a configuration operation on the register in the peripheral interface IP through the bus;

[0034] generating parity check codes on data links at outputs and inputs of the peripheral interface IP, and comparing the parity check codes.

[0035] The application further provides an electronic device, which comprises a memory, a processor and a computer program stored in the memory and capable of running on the processor, and the processor implements the customized logic circuit design method for peripheral interface when running the program.

[0036] The application further provides a non-transitory computer-readable storage medium, which has a computer program stored thereon, and the computer program is executed by a processor to implement any of the above-mentioned customized logic circuit design methods for peripheral interface.

[0037] The application further provides a computer program product, which comprises a computer program, and the computer program is executed by a processor to implement any of the above-mentioned customized logic circuit design methods for peripheral interface.

[0038] The application provides a customized logic circuit for peripheral interface and a design method, which generates clock signals required by different peripheral interface IPs according to a main clock signal, generates reset signals required by different peripheral interface IPs according to a main reset signal, connects detection signals of the peripheral interface IPs to a state register, enables a chip processor core to read the state register through a bus, connects control signals of the peripheral interface IPs to a to-be-configured register, enables the chip processor core to perform configuration operation on registers in the peripheral interface IPs through the bus, generates parity check codes on data links at outputs and inputs of the peripheral interface IPs, and compares the parity check codes, which can enable a SoC chip to efficiently integrate high-speed peripheral interface IPs and improve flexibility of the SoC chip in integrating the high-speed peripheral interface IPs, thereby reducing chip design complexity, saving chip design period, and accelerating integration time of high-speed peripheral interface IPs of the SoC chip. BRIEF DESCRIPTION OF DRAWINGS

[0039] In order to more clearly illustrate the technical solutions in the application or prior art, the following will briefly introduce the drawings needed to be used in the embodiments or prior art description. Obviously, the drawings in the following description are some embodiments of the application, and other drawings can be obtained by those skilled in the art without any creative effort on the basis of these drawings.

[0040] Figure 1 is a structural schematic diagram of the customized logic circuit for peripheral interface provided by the application.

[0041] Figure 2 is a structural schematic diagram of the clock generation module provided by the application.

[0042] Figure 3 is a structural schematic diagram of the synchronous reset module provided by the application.

[0043] Figure 4 is a self-defined register read-write logic flowchart provided by the application.

[0044] Figure 5 is a structural schematic diagram of the self-defined register read-write module provided by the application.

[0045] Figure 6 is a parity check logic flowchart provided by the present application.

[0046] Figure 7 is a structure diagram of a parity check module provided by the present application.

[0047] Figure 8 is a flowchart of a design method of a custom logic circuit facing a peripheral interface provided by the present application.

[0048] Figure 9 is a structure diagram of an electronic device provided by the present application. DETAILED DESCRIPTION

[0049] In order to make the objects, technical solutions and advantages of the present application clearer, the technical solutions in the present application will be described clearly and completely below with reference to the drawings in the present application. Obviously, the described embodiments are some embodiments of the present application, but not all the embodiments. Based on the embodiments in the present application, all the other embodiments obtained by those skilled in the art without creative labor fall within the protection scope of the present application.

[0050] The custom logic circuit facing a peripheral interface and the design method of the present application will be described below. Figures 1-9 The custom logic circuit facing a peripheral interface and the design method of the present application will be described below.

[0051] Figure 1 A structure diagram of a custom logic circuit facing a peripheral interface provided by the present application is shown, referring to FIG. 1. Figure 1 The circuit includes a clock generation module 11, a synchronous reset module 12, a self-defined register read-write module 13 and a parity check module 14, wherein:

[0052] The clock generation module is used for generating clock signals required by different peripheral interface IPs according to an input main clock signal;

[0053] The synchronous reset module is used for generating reset signals required by different peripheral interface IPs according to an input main reset signal;

[0054] The self-defined register read-write module is used for connecting detection signals of the peripheral interface IP to a state register, so that a chip processor core can read the state register through a bus, and connecting control signals of the peripheral interface IP to a to-be-configured register, so that the chip processor core can perform configuration operation on the registers inside the peripheral interface IP through the bus;

[0055] The parity check module is used for generating parity check codes on data links at outputs and inputs of the peripheral interface IP, and comparing the parity check codes.

[0056] To this end, it is necessary to note that in the process of SoC (System on Chip, System on Chip) chip design, the controller circuit of devices such as DDR SDRAM (Double Data Rate Synchronous Dynamic Random Access Memory, Double Data Rate Synchronous Dynamic Random Access Memory), PCIE (Peripheral Component Interconnect Express, Peripheral Component Interconnect Express Bus) and the like needs to be integrated with high-speed peripheral interface IP (Intellectual Property, Intellectual Property, refers to the "design module" of the DDR controller or PHY, which is integrated into the SoC as an intellectual property IP).

[0057] With the continuous improvement of the performance of the SoC chip processor core, the demand for peripheral access rate is gradually increasing. With the continuous development of high-speed peripheral interface circuit, the mainstream peripheral interface circuit, such as DDR interface, PCIE interface, etc., gradually forms an IP product with perfect function and high performance. In the process of SoC chip design, it is necessary to integrate high-speed peripheral interface circuit IP. With the increase of the scale of SoC chip and high-speed peripheral interface circuit IP, the complexity of SoC chip integrated high-speed peripheral interface circuit IP also increases. The design efficiency of interface circuit IP affects the entire SoC chip design and process, and also affects the performance of the chip.

[0058] Therefore, the design of the customized logic circuit for high-speed peripheral interface IP can improve the efficiency and flexibility of the SoC chip integrated high-speed peripheral controller circuit, reduce the chip circuit design time overhead, and achieve the purpose of reducing the entire SoC chip design cycle, and provide a theoretical basis for the design of high-speed peripheral interface circuit of SoC chip.

[0059] In the present application, the customized logic circuit for peripheral interface needs to accelerate the integration process of SoC chip high-speed peripheral interface IP, and can also improve the reliability of data transmission between SoC chip and peripheral components. However, the SoC chip needs to integrate multiple high-speed peripheral interface IPs. Different high-speed peripheral interface IPs, the execution action of the business data processed by each of them needs to be closely related to the clock signal. Therefore, the customized logic circuit for peripheral interface includes a clock generation module, which can generate the clock signal required by each high-speed peripheral interface IP through PLL locking of the main clock, and can realize the integration effect of SoC chip high-speed peripheral interface IP in clock synchronization.

[0060] In the application, in the operation of the programmable chip electronic device, the program may run off or jump, and the hardware specific interface can be manually or automatically sent to restore the software operation to a specific program segment, which is the reset process, and in this process, the signal sent to the hardware specific interface by manual or automatic method is the reset signal. The synchronous reset signal refers to the signal generated by resetting the flip-flop when the clock active edge comes; the asynchronous reset signal does not depend on the clock signal and is generated only when the system reset is valid. Therefore, the customized logic circuit facing the peripheral interface includes a synchronous reset module, which generates reset signals required by different peripheral interface IPs according to the input main reset signal, and can realize the integration effect of the high-speed peripheral interface IP of the SoC chip in the synchronous reset.

[0061] In the application, the detection signal of the high-speed peripheral interface IP is connected to the state register according to the needs of the user, so that the chip processor core can read the state register through the AHB or APB AMBA configuration bus, and the state information in the self-defined state register includes clock enable, reset, parity enable, parity interrupt, ECC interrupt, initialization interrupt, low-power interrupt and other state signals. In addition, the chip processor core can also configure and operate the registers in the peripheral interface IP through the AHB or APB bus.

[0062] In the application, the parity module can improve the reliability of data transmission between the SoC chip and the peripheral components by generating parity codes on the data link at the output and input of the interface IP and realizing the comparison function of the parity codes.

[0063] In the further circuit of the above-mentioned circuit, the clock generation module is specifically used for:

[0064] Obtaining the input of a plurality of main clock signals;

[0065] According to the preset clock frequency requirement, the clock enable signal generated by the self-defined register read-write module is accessed;

[0066] According to the clock enable signal, the required main clock signal is selected from the plurality of main clock signals;

[0067] According to the required main clock signal, the clock signal required by different peripheral interface IPs is generated.

[0068] To this end, it should be noted that the clock signal can be divided into high-speed clock signal and low-speed clock signal, high-speed clock signal refers to the clock signal with higher frequency. In digital electronic system, clock signal is like a metronome, controlling the rhythm of various operations in the circuit. The frequency of high-speed clock signal is usually between tens of megahertz (MHz) to thousands of megahertz (GHz). For example, in modern high-performance computers, the clock frequency of processor can reach 3-5GHz or even higher. Such high-speed clock signal allows the processor to process a large number of instructions and data operations in unit time. The frequency of low-speed clock signal is relatively low, usually between several hertz (Hz) to several megahertz (MHz). It is mainly used in some circuits or devices that do not require high speed but require stable timing control. For this purpose, the required clock frequency requirement can be preconfigured. Whether high-speed or low-speed, in the clock generation module, a plurality of main clock signals are configured in advance, such as based on one of the main clock signals, different high-speed clock signals can be obtained, and based on another main clock signal, different low-speed clock signals can be obtained. Therefore, according to the preset clock frequency requirement, the clock enable signal generated by the custom register read-write module is accessed, and according to the clock enable signal, the required main clock signal is selected from the plurality of main clock signals, that is, according to the clock enable signal, one of the plurality of main clock signals can play a role in the clock generation module, and then according to the required main clock signal, the clock signal with different frequencies required by different peripheral interface IP is generated.

[0069] As Figure 2is a clock generation module in the present application, and clk and dft_bypass_clk can be regarded as various master clock signals in the figure. Different interface IP clock signals are generated by the master clock clk, such as axi0_clk, axi1_clk, axi2_clk, axi3_clk, clk_d2, clk_ctrl_sync, reghclk. Among them, axi0_clk, axi1_clk, axi2_clk, axi3_clk are used for axi1 channel, axi2 channel, axi3 channel, axi4 channel, and are used for axi control signal and read-write data transmission. clk_d2 is a clock for DDR controller. clk_ctrl_sync is a clock for DDR PHY (physical layer). reghclk is a clock for AHB bus data transmission, address transmission and control signal transmission. axi0_clken, axi1_clken, axi2_clken, axi3_clken, ctrl_clken, phy_clken, ahb_clken are clock enable signals generated by the custom register read-write module, and axi0_clken, axi1_clken, axi2_clken, axi3_clken, ctrl_clken, phy_clken, ahb_clken signals are assigned 1'b1. When When scanmode is 1'b1, dft_bypass_clk is passed through ckbuf to form axi0_clk, axi1_clk, axi2_clk, axi3_clk, clk_d2, clk_ctrl_sync, reghclk clock signals and the frequency is consistent with the frequency of dft_bypass_clk. dft_bypass_clk is a low-speed scan clock.

[0070] In the further circuit of the above-mentioned circuit, the synchronous reset module is specifically used for:

[0071] Obtaining an input master reset signal;

[0072] According to the preset reset requirement, the reset enable signal generated by the custom register read-write module is connected;

[0073] The reset signal required by the different peripheral interface IPs is generated according to the reset enable signal, the clock signal required by the different peripheral interface IPs and the main reset signal.

[0074] It should be noted that, referring to Figure 3 is the reset synchronization module in the present application, which generates corresponding reset signals such as regHRESETn, Sync_rst_n_ctrl, Sync_rst_n_phy, axi0_ARESETn, axi1_ARESETn, axi2_ARESETn and axi3_ARESETn according to the clock frequencies of different interfaces. axi0_ARESETn, axi1_ARESETn, axi2_ARESETn and axi3_ARESETn are used for resetting axi 1 channel, axi 2 channel, axi 3 channel and axi 4 channel. Sync_rst_n_phy is used for resetting DDR PHY (physical layer). Sync_rst_n_ctrl is used for resetting the DDR controller. regHRESETn is used for resetting the AHB / APB configuration bus of the DDR controller and the custom register read-write module. The user_ddr_ctrl_rst_n and user_axi_rst_n signals are reset enable signals generated by the custom register read-write module. When regHRESET is 1'b0, the user_ddr_ctrl_rst_n and user_axi_rst_n signals are assigned 1'b1. rst_n and user_ddr_ctrl_rst_n are ANDed, and the obtained signal is output through a two-stage flip-flop structure. If the clock signal of the flip-flop is clk, the output signal is Sync_rst_n_ctrl; if the clock signal of the flip-flop is phy_clk, the output signal is Sync_rst_n_phy. rst_n and user_axi_rst_n are ANDed, and the obtained signal is output through a two-stage flip-flop structure. The clock signal of the flip-flop is , and the output signal is The reset signal of the AHB / APB bus regHRESETn is clocked by ahb_clk, the reset signal is rst_n, and rst_n is output through a two-stage flip-flop, and the output signal is regHRESETn.

[0075] In further circuits of the above-mentioned circuits, the custom register read-write module is specifically used for:

[0076] obtaining a peripheral interface IP identifier to be detected;

[0077] According to the correspondence between the pre-stored peripheral interface IP identifier and the state register number, the state register to be read is determined;

[0078] The state information of the peripheral interface IP to be detected is read from the state register to be read through the bus;

[0079] The register parameter information corresponding to the control signal type to be configured is obtained;

[0080] The number of the register to be configured inside the peripheral interface IP is determined;

[0081] The register parameter information is configured on the register corresponding to the number through the bus.

[0082] It should be noted that, Figure 4 is the custom register read-write logic in the example of the present application, including steps S41 to S410, which will be described below.

[0083] Step S41, after generating the ahb_op_en signal, the value of the regHWRITE signal is judged.

[0084] Step S42, the ahb_rd_en signal is generated.

[0085] Step S43, the value of the custom_sel signal is judged.

[0086] Step S44, the custom register is read according to the corresponding register number.

[0087] Step S45, the ahb_wr_en signal is assigned a value.

[0088] Step S46, the regHWREADY signal is judged.

[0089] Step S47, the ahb_wr_user_reg_en signal is assigned a value.

[0090] Step S48, the register number and the register type are defined.

[0091] Step S49, the parameter is written into the register.

[0092] Step S410, the ahb_wr_user_reg_en signal is assigned a value.

[0093] Further, in step S41, the value of the regHWRITE signal is judged to be 1’b0 or 1’b1, when the value of the regHWRITE signal is 1’b0, the next step enters step S42. When the value of the regHWRITE signal is 1’b1, the next step enters step S45.

[0094] Further, in step S42, the regHWRITE is first negated, and then the obtained signal is ANDed with the ahb_op_en, and the result is the ahb_rd_en signal, so the ahb_rd_en signal is assigned as 1'b1.

[0095] Further, in step S43, it is judged whether the value of the custom_sel signal is 1'b0 or 1'b1. When the value of the custom_sel signal is 1'b1, the next step enters step S44.

[0096] Further, in step S44, the value in the custom register is read by matching the register number.

[0097] Further, in step S45, the ahb_op_en is ANDed with the regHWRITE, and the ahb_wr_en signal is obtained, so the ahb_wr_en signal is assigned as 1'b1.

[0098] Further, in step S46, it is judged whether the value of the regHREADY signal is equal to 1'b1. When the regHREADY signal is equal to 1'b1, the next step enters step S47. When the regHREADY signal is equal to 1'b0, the next step enters step S410.

[0099] Further, in step S47, the ahb_wr_en signal is ANDed with the regHREADY signal, and the ahb_wr_user_reg_en signal is obtained, so the ahb_wr_user_reg_en signal is assigned as 1'b1.

[0100] Further, in step S48, the register number and the register type are defined. The register number is used for searching by the address of the regHADDR. The register type defines the register parameter data and the bit corresponding to the parameter.

[0101] Further, in step S49, the parameter is written into the corresponding register by the regHWDATA signal in the AHB / APB bus.

[0102] Further, in step S410, because it is judged in step S46 that the regHREADY signal is 1'b0, the ahb_wr_en is ANDed with the regHREADY, and the ahb_wr_user_reg_en signal is assigned as 1'b0.

[0103] Referring to Figure 5 , Figure 5Is the structure diagram of custom register read-write module in the present application, wherein the custom_sel signal is generated by the TEST layer and transmitted to the custom_ahb module through Wrapper (code or module used to describe the packaging of existing functions, interfaces, libraries or systems). As can be seen from steps S43 and S44, the function of the custom_sel signal is to distinguish whether the value of the custom register is read. The ahb_op_en signal is obtained by the combination logic of the regHSELx, regHREADY and regHTRANS signals on the AHB bus. The regHCLK is the working clock of the AHB bus. The regHRESETn is the reset signal of the AHB bus. The regHADDR is the address bus of the AHB bus. The regHWDATA is the write data bus of the AHB bus. The regHRDATA is the read data bus of the AHB bus. The register stack contains a plurality of custom designed registers. The state information in the custom register includes clock enable, reset, parity enable, parity interrupt, ECC interrupt, initialization interrupt, low power interrupt and the like.

[0104] In a further circuit of the above circuit, the parity module comprises a parity generation module and a parity check module, wherein:

[0105] The parity generation module is configured to generate a first parity code on a data link at an input of the peripheral interface IP;

[0106] The parity check module is configured to generate a second parity code on a data link at an output of the peripheral interface IP, and to compare the first parity code and the second parity code.

[0107] It should be noted that, with reference to Figure 6 , Figure 6 Is the parity logic in the present application, comprising steps S61 to S69, which will be described below.

[0108] Step S61, determine whether to send a parity enable signal.

[0109] Step S62, turn on the parity function.

[0110] Step S63, turn off the parity function.

[0111] Step S64, determine whether to transmit write data, address signal and CMD signal.

[0112] Step S65, the Parity Gen module generates parity data according to the W, AW, AR channels.

[0113] Step S66, the Parity Check module generates parity data according to the R, B channels.

[0114] Step S67, whether the parity data generated by the Parity Gen and Parity Check modules is consistent.

[0115] Step S68, no parity error is generated on the AXI channel.

[0116] Step S69, a parity error is generated on the AXI channel.

[0117] Further, in step S61, whether the custom_ahb (custom AHB) sends a parity enable signal is judged, and the parity enable signal is packaged in a custom register. When the parity enable signal is detected, the next step enters step S62. When the parity enable signal is not detected, the next step enters step S63.

[0118] Further, in step S62, the parity function is turned on, and the parity on the AXI channel is turned on.

[0119] Further, in step S63, the parity function is turned off, and the parity on the AXI channel is turned off.

[0120] Further, in step S64, whether the write data, address signal, and CMD signal are transmitted is judged. When it is detected that the write data, address signal, and CMD signal are transmitted, the next step enters step S65. When it is detected that the write data, address signal, and CMD signal are not transmitted, the next step enters step S64.

[0121] Further, in step S65, the Parity Gen module generates parity data according to the W, AW, B channels, and sends the obtained parity data to the Parity Check module, and the parity data is compared in step S67.

[0122] Further, in step S66, the Parity Check module generates parity data according to the R, AR channels. The parity data is compared in step S67.

[0123] Further, in step S67, parity check data generated by the Parity Gen module and the Parity Check module are compared. If the parity check data are consistent, the next step enters step S68. If the parity check data are inconsistent, the next step enters step S69.

[0124] Further, in step S68, data on the AXI path is correct.

[0125] Further, in step S69, a parity error is generated on the AXI path, and the generated error is sent to the custom_ahb module.

[0126] Referring to Figure 7 , Figure 7 is a structure diagram of the parity check module in the present application. Write data, address signals and control signals are sent through the TEST layer. In the Wrapper layer, a Parity enable signal is generated by the Custom_ahb module and transmitted to the Parity Gen module and the Parity Check module. Data, address, control signals are transmitted to the Parity Gen module and the Parity Check module, respectively. The Parity Gen module and the Parity Check module generate parity codes, respectively, and the Parity Gen module transmits the generated parity codes to the Parity Check module for comparison. If the parity codes are inconsistent, a Parity error signal is generated and uploaded to the Custom_ahb module. Data is transmitted to the Parity Gen module and the Parity Check module again through the DDR IP, and the same operation is performed as before the data is transmitted to the DDR IP. Finally, read data and control signals are output. This module performs two parity checks at the entrance and exit of the data, respectively, to ensure the correctness of data transmission on the AXI path.

[0127] The peripheral interface-oriented customized logic circuit provided by the application can efficiently integrate high-speed peripheral interface IP of an SoC chip and improve the flexibility of the SoC chip in integrating the high-speed peripheral interface IP, thereby reducing the complexity of chip design, saving the chip design period and accelerating the integration time of the high-speed peripheral interface IP of the SoC chip.

[0128] The peripheral interface-oriented customized logic circuit design method provided by the application is described below, and the peripheral interface-oriented customized logic circuit design method described below can be referred to in correspondence with the peripheral interface-oriented customized logic circuit described above.

[0129] Figure 8 A flowchart of the peripheral interface-oriented customized logic circuit design method provided by the application is shown, referring to Figure 8 The device comprises the following steps:

[0130] Step 81: generating a clock signal required by different peripheral interface IP according to the input main clock signal.

[0131] Step 82: generating a reset signal required by different peripheral interface IP according to the input main reset signal.

[0132] Step 83: connecting the detection signal of the peripheral interface IP to the status register, so that the chip processor core can read the status register through the bus, and connecting the control signal of the peripheral interface IP to the to-be-configured register, so that the chip processor core can perform configuration operation on the register inside the peripheral interface IP through the bus.

[0133] Step 84: generating parity codes on the data link at the output and input of the peripheral interface IP, and comparing the parity codes.

[0134] The method of the embodiment of the application has the same principle as the above-mentioned embodiment system, and therefore more detailed explanation is not repeated here.

[0135] The application provides a peripheral interface-oriented customized logic circuit design method, which comprises the following steps: generating a clock signal required by different peripheral interface IPs according to a main clock signal; generating a reset signal required by different peripheral interface IPs according to a main reset signal; connecting detection signals of the peripheral interface IPs to a state register, so that a chip processor core can read the state register through a bus; connecting control signals of the peripheral interface IPs to a to-be-configured register, so that the chip processor core can perform configuration operation on registers in the peripheral interface IPs through the bus; generating parity check codes on data links at outputs and inputs of the peripheral interface IPs, and comparing the parity check codes.

[0136] Figure 9 An example of a schematic diagram of a physical structure of an electronic device is shown in Figure 9 The electronic device can include a processor 91, a communications interface 92, a memory 93 and a communications bus 94, wherein the processor 91, the communications interface 92 and the memory 93 complete mutual communication through the communications bus 94. The processor 91 can call logical instructions in the memory 93 to execute a peripheral interface-oriented customized logic circuit design method, which comprises the following steps: generating a clock signal required by different peripheral interface IPs according to an inputted main clock signal; generating a reset signal required by different peripheral interface IPs according to an inputted main reset signal; connecting detection signals of the peripheral interface IPs to a state register, so that a chip processor core can read the state register through a bus; connecting control signals of the peripheral interface IPs to a to-be-configured register, so that the chip processor core can perform configuration operation on registers in the peripheral interface IPs through the bus; generating parity check codes on data links at outputs and inputs of the peripheral interface IPs, and comparing the parity check codes.

[0137] In addition, the logic instructions in the memory 93 described above can be realized in the form of a software function unit and sold or used as an independent product, and can be stored in a computer readable storage medium. Based on such understanding, the technical solutions of the present application essentially or the parts that contribute to the prior art or parts of the technical solutions can be embodied in the form of a software product. The computer software product is stored in a storage medium, and includes a plurality of instructions for causing a computer device (which can be a personal computer, a server, or a network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of the present application. The aforementioned storage medium includes: a U disk, a mobile hard disk, a read-only memory (ROM, Read-Only Memory), a random access memory (RAM, Random Access Memory), a magnetic disk or an optical disk, and various media that can store program codes.

[0138] In another aspect, the present application also provides a computer program product, which comprises a computer program, the computer program can be stored on a non-transitory computer readable storage medium, and the computer program can be executed by a processor to enable a computer to execute the customized logic circuit design method for peripheral interface provided by the above-mentioned methods, and the method comprises: generating clock signals required for adapting different peripheral interface IPs according to an input main clock signal; generating reset signals required for adapting different peripheral interface IPs according to an input main reset signal; connecting detection signals of the peripheral interface IPs to a state register, so that a chip processor core can read the state register through a bus, and connecting control signals of the peripheral interface IPs to a to-be-configured register, so that the chip processor core can perform configuration operation on registers inside the peripheral interface IPs through the bus; and generating parity check codes on data links at outputs and inputs of the peripheral interface IPs, and comparing the parity check codes.

[0139] In another aspect, the present application also provides a non-transitory computer readable storage medium, which stores a computer program, and the computer program is executed by a processor to implement the customized logic circuit design method for peripheral interface provided by the above-mentioned methods, and the method comprises: generating clock signals required for adapting different peripheral interface IPs according to an input main clock signal; generating reset signals required for adapting different peripheral interface IPs according to an input main reset signal; connecting detection signals of the peripheral interface IPs to a state register, so that a chip processor core can read the state register through a bus, and connecting control signals of the peripheral interface IPs to a to-be-configured register, so that the chip processor core can perform configuration operation on registers inside the peripheral interface IPs through the bus; and generating parity check codes on data links at outputs and inputs of the peripheral interface IPs, and comparing the parity check codes.

[0140] The device embodiments described above are merely illustrative, wherein the units described as separate components can or can not be physically separate, and the components displayed as units can or can not be physical units, i.e., can be located in one place, or can be distributed to multiple network units. Part or all of the modules can be selected to achieve the purposes of the embodiments according to actual needs. Those skilled in the art can understand and implement without creative labor.

[0141] Through the description of the above embodiments, those skilled in the art can clearly understand that the embodiments can be realized by means of software and the necessary general hardware platform, and of course can also be realized by hardware. Based on such understanding, the above technical solutions can be embodied in the form of a software product, which can be stored in a computer readable storage medium, such as a ROM / RAM, a magnetic disk, an optical disk, etc., and includes a number of instructions to make a computer device (which can be a personal computer, a server, or a network device, etc.) execute the methods described in each embodiment or some parts of the embodiments.

[0142] Finally, it should be noted that: the above embodiments are only used to illustrate the technical solutions of the present application, and not to limit them; although the present application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that: it can still modify the technical solutions recorded in the foregoing embodiments, or make equivalent replacement to some technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the spirit and scope of the technical solutions of the embodiments of the present application.

Claims

1. A custom logic circuit oriented to a peripheral interface, characterized by, The clock generation module, the synchronous reset module, the self-defined register read-write module and the parity check module are included, wherein: The clock generation module is used for generating clock signals required by different peripheral interface IPs according to input main clock signals; The synchronous reset module is used for generating reset signals required by different peripheral interface IPs according to input main reset signals; The self-defined register read-write module is used for connecting detection signals of the peripheral interface IPs to state registers, so that a chip processor core can read the state registers through a bus, and connecting control signals of the peripheral interface IPs to to-be-configured registers, so that the chip processor core can perform configuration operations on the registers inside the peripheral interface IPs through the bus; The parity check module is used for generating parity check codes on data links at outputs and inputs of the peripheral interface IPs, and comparing the parity check codes.

2. The custom logic circuit facing peripheral interface according to claim 1, characterized in that, The clock generation module is specifically used for: Obtaining multiple input main clock signals; According to preset clock frequency requirements, accessing clock enable signals generated by the self-defined register read-write module; According to the clock enable signals, selecting required main clock signals from the multiple main clock signals; According to the required main clock signals, generating clock signals required by different peripheral interface IPs.

3. The custom logic circuit facing peripheral interface according to claim 1 or 2, characterized in that, The synchronous reset module is specifically used for: Obtaining input main reset signals; According to preset reset requirements, accessing reset enable signals generated by the self-defined register read-write module; According to the reset enable signals, the clock signals required by different peripheral interface IPs and the main reset signals, generating reset signals required by different peripheral interface IPs.

4. The custom logic circuit facing peripheral interface according to claim 3, wherein, The self-defined register read-write module is specifically used for: Obtaining to-be-detected peripheral interface IP identifiers; According to a correspondence between pre-stored peripheral interface IP identifiers and state register labels, determining to-be-read state registers; Reading state information of the to-be-detected peripheral interface IPs from the to-be-read state registers through a bus.

5. The custom logic circuit facing peripheral interface according to claim 4, characterized in that, The self-defined register read-write module is specifically used for: Obtaining register parameter information corresponding to to-be-configured control signal types; Determining labels of to-be-configured registers inside peripheral interface IPs; Performing parameter configuration on the register parameter information on registers corresponding to the labels through a bus.

6. The custom logic circuit facing peripheral interface according to claim 5, wherein, The parity check module includes a parity check generation module and a parity check checking module, wherein: The parity check generation module is used for generating first parity check codes on data links at inputs of peripheral interface IPs; The parity check checking module is used for generating second parity check codes on data links at outputs of the peripheral interface IPs, and comparing the first parity check codes and the second parity check codes.

7. A method for designing custom logic circuits oriented towards peripheral interfaces, characterized in that, The clock generation module, the synchronous reset module, the self-defined register read-write module and the parity check module are included, wherein: The clock generation module is used for generating clock signals required by different peripheral interface IPs according to input main clock signals; The synchronous reset module is used for generating reset signals required by different peripheral interface IPs according to input main reset signals; The self-defined register read-write module is used for connecting detection signals of the peripheral interface IPs to state registers, so that a chip processor core can read the state registers through a bus, and connecting control signals of the peripheral interface IPs to to-be-configured registers, so that the chip processor core can perform configuration operations on the registers inside the peripheral interface IPs through the bus; The parity check module is used for generating parity check codes on data links at outputs and inputs of the peripheral interface IPs, and comparing the parity check codes. The detection signal of the peripheral interface IP is connected to the status register, so that the chip processor core can read the status register through the bus, and the control signal of the peripheral interface IP is connected to the to-be-configured register, so that the chip processor core can perform a configuration operation on the register inside the peripheral interface IP through the bus; Parity check codes are generated on the data links at the output and input of the peripheral interface IP, and comparison of the parity check codes is performed.

8. An electronic device comprising a memory, a processor, and a computer program stored on the memory and executable on the processor, characterized in that, The processor implements the peripheral interface-oriented custom logic circuit design method of claim 7 when executing the program. 9.A non-transitory computer-readable storage medium having stored thereon a computer program, characterized in that, The computer program implements the peripheral interface-oriented custom logic circuit design method of claim 7 when executed by the processor.

10. A computer program product comprising a computer program, characterized in that, The computer program implements the peripheral interface-oriented custom logic circuit design method of claim 7 when executed by the processor.

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