Method for optimizing semiconductor wafer conveying efficiency by using equipment end cache system

Abstract

The invention relates to the field of cache optimization, and discloses a method for optimizing semiconductor wafer conveying efficiency by using an equipment end cache system, so as to realize intelligent collaborative optimization of a whole wafer conveying process. Comprising the steps of collecting wafer arrival timestamps and equipment state data, capturing wafer arrival long-range correlation, generating an enhanced prediction model in combination with physical state marks, constructing a weighted topological graph through a dynamic topology coherence analysis unit, and identifying bottleneck equipment by utilizing a Betti number sequence. The quantum random walk path optimization unit rapidly generates an optimal path selection instruction according to equipment load probability amplitude evolution, and the robust optimization control unit cooperatively adjusts the cache size and the motion trail of the mechanical arm to ensure the conveying precision and stability. The wafer conveying efficiency and the comprehensive efficiency of a production line can be remarkably improved, the wafer damage risk is reduced, the wafer conveying device is suitable for high-speed and high-precision conveying scenes of wafers of 300 mm or above, and key technical support is provided for semiconductor manufacturing intelligent upgrading.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of cache optimization, and particularly relates to a method for optimizing semiconductor wafer conveying efficiency using a device-end cache system. BACKGROUND

[0002] The semiconductor manufacturing industry is the core pillar of modern high-tech fields, and its production efficiency and product quality directly determine the competitiveness of the global electronic information industry. In the semiconductor wafer manufacturing process, the accurate conveying of wafers between multiple process equipment is a key link to ensure production continuity and yield. With the continuous reduction of semiconductor process nodes, the increase in wafer size, and the acceleration of production rhythm, the traditional wafer conveying system faces the following core challenges:

[0003] The wafer arrival time presents a nonlinear, long-period correlation feature, and traditional prediction models based on Markov chains or moving averages cannot capture the long-range dependence between wafer batches, resulting in frequent "starvation" or "overflow" phenomena in the buffer area;

[0004] Existing systems mostly use static device connection graph analysis, which cannot real-time perceive the impact of device load rate changes on the topology structure, resulting in high misjudgment rate of bottleneck devices and causing path planning failure;

[0005] Buffer regulation and robot motion control are often designed independently, lacking collaborative optimization based on physical state, resulting in a decline in conveying success rate in high-speed scenarios.

[0006] Therefore, we propose a method for optimizing semiconductor wafer conveying efficiency using a device-end cache system to solve the above problems. SUMMARY

[0007] The present application provides a method for optimizing semiconductor wafer conveying efficiency using a device-end cache system, realizing intelligent collaborative optimization of the whole wafer conveying process.

[0008] The first aspect of the present application provides a method for optimizing semiconductor wafer delivery efficiency using a device end cache system, the method comprising: collecting wafer arrival timestamp sequences and device state data in real time; inputting the timestamp sequences and device state data into a fractional differential equation prediction unit running in a device end embedded processor, outputting predicted queue values within 5-10 seconds in the future based on long-period correlation characteristics of wafer arrival; inputting a pre-stored device connection topology graph in a device end memory and device state data into a topological homology analysis unit, outputting a bottleneck device identification set by calculating connectivity characteristics between device nodes; inputting the bottleneck device identification set and a pre-defined path weight matrix into a quantum random walk path optimization unit, outputting path selection instructions based on evolution of device load probability amplitude; inputting the predicted queue values, bottleneck device identification set and path selection instructions into a robust optimization control unit to generate cache size instructions and robot control instructions, sending the cache size instructions to a pneumatic telescopic controller of an adjustable cache area, and sending the robot control instructions to a servo driver of a wafer handling robot arm.

[0009] Optionally, in the first implementation manner of the first aspect of the present application, the method further comprises: capturing wafer edge reflected light phase difference through a laser interference unit in the photoelectric sensor to obtain a light phase difference signal, collecting wafer placement vibration waveform through a piezoelectric acoustic sensor attached to a wafer cassette to obtain a vibration waveform signal, and reading device processing state register values in real time through a CAN protocol analyzer connected to a device control bus; inputting the light phase difference signal into a time-frequency conversion module to output wafer arrival timestamp sequences, inputting the vibration waveform signal into a resonance peak extraction module to output wafer placement stability scores, and inputting the device processing state register values into a binary decoding module to output device state parameters; inputting the wafer arrival timestamp sequences and wafer placement stability scores into a sliding window alignment processor to generate enhanced timestamp sequences with physical state markers, and inputting the device state parameters and wafer placement stability scores into an abnormality filtering module to generate device state data with jitter interference removed.

[0010] Optionally, in the second implementation form of the first aspect of the present application, the method comprises: inputting the timestamp sequence into a difference processor to calculate a sequence of adjacent wafer arrival intervals; inputting the stability score in the device state data into a weight allocator to generate a set of interval weights; inputting the sequence of arrival intervals and the set of interval weights into a Hurst index estimator to output a Hurst index based on the weighted range method; inputting the Hurst index into a fractional order mapping table to output a fractional order; inputting the fractional order, the current queue length in the device state data, and the device processing rate into a Grünwald-Letnikov discrete predictor to output a predicted queue value based on the memory dependence characteristic of the historical queue state; and inputting the predicted queue value into a residence effect compensation module to output a final predicted queue value after compensation in combination with the wafer material viscosity coefficient.

[0011] Optionally, in the third implementation form of the first aspect of the present application, the method comprises: inputting the device connection topology pre-stored in the device end memory and the device processing rate in the device state data into an edge weight calculator to generate a weighted topology graph based on the real-time load rate of the device; inputting the weighted topology graph into a threshold filtering module to remove edges with a weight lower than a preset saturation threshold to obtain a simplified topology complex, construct a simple complex structure based on the simplified topology complex to obtain a homology complex; inputting the homology complex into a Betti number calculation unit to output a Betti number sequence, and comparing the Betti number sequence with a preset bottleneck determination rule to generate a bottleneck device identification set; and inputting the bottleneck device identification set into a device feedback loop module to output a final bottleneck device identification set after verification in combination with the real-time queue length change rate of the device end.

[0012] Optionally, in the fourth implementation form of the first aspect of the present application, the method comprises: inputting the bottleneck device identification set into a path mask to disable paths leading to high-load devices in a pre-defined path weight matrix to obtain an optimized path matrix, generating a Hamilton initial ground state of quantum random walk based on the optimized path matrix to obtain an initial probability amplitude distribution; inputting the real-time queue length in the device state data into a potential field generator to output a potential field vector; inputting the initial probability amplitude distribution and the potential field vector into a unitary evolution operator module to perform discrete-time quantum walk iteration to obtain an evolved probability amplitude; inputting the evolved probability amplitude into a de-coherence compensation module to compensate for the probability amplitude attenuation in combination with the wafer surface roughness parameter to obtain a corrected probability amplitude; and inputting the corrected probability amplitude into a maximum probability selector to output a path selection instruction.

[0013] Optionally, in the fifth implementation manner of the first aspect of the present application, the method comprises: inputting the predicted queue value into a buffer margin calculator, combining a wafer thickness parameter to generate a thickness compensation parameter, inputting the thickness compensation parameter and the predicted queue value into an aerodynamic volume mapping module to output an original buffer instruction; inputting the path selection instruction into a kinematics converter to generate an original joint instruction, inputting the bottleneck device identification set into a vibration suppression module to combine a historical vibration spectrum of the robot arm to generate a compensation coefficient set; inputting the original buffer instruction, the original joint instruction and the compensation coefficient set into a Lyapunov stability controller to output a buffer size instruction and a robot control instruction; sending the buffer size instruction to a multi-stage pneumatic cylinder group of the adjustable buffer area to drive the piston to extend or retract to a target position, and sending the robot control instruction to a harmonic reducer servo system of the wafer handling robot arm to move according to the compensated trajectory.

[0014] Optionally, in the sixth implementation manner of the first aspect of the present application, the device-embedded processor comprises a dynamic hardware partitioning architecture, comprising: mapping the fractional differential equation prediction unit to a programmable logic area A of the FPGA, mapping the topological homology analysis unit to a storage optimization area B of the FPGA, and mapping the quantum random walk path optimization unit to a high-precision floating-point area C of the FPGA; storing the timestamp sequence in a dual-port BRAM through an on-chip bus arbiter, synchronizing the device state data to a compressed adjacency matrix memory through a cross-partition DMA engine, and loading the pre-defined path weight matrix to a distributed RAM through a path weight direct connection channel; after the predicted queue value is calculated, triggering the topological homology analysis through a hardware signal trigger, triggering the quantum path optimization through an interrupt priority controller after the bottleneck device identification set is output, and synchronizing to the robust optimization control unit through a parallel output register after the path selection instruction is generated; according to the wafer conveying batch interval, reducing the idle partition power consumption through a dynamic voltage frequency scaling module.

[0015] Advantages:

[0016] Introducing fractional differential into wafer arrival time prediction, breaking through the modeling limitation of long-range memory of traditional integer-order differential;

[0017] Fusing three sources of data of laser interference light phase difference, piezoelectric vibration waveform and device state register, generating an enhanced timestamp sequence through sliding window alignment;

[0018] Based on the bottleneck determination of simplicial complex and Betti sequence, quantifying the topological connectivity between device nodes, combining the real-time load rate of the device to generate a weighted topological graph, removing low-weight edges to construct a simplified topological complex;

[0019] The device load is modeled as a quantum probability amplitude, quantum acceleration of path selection is realized through a unitary evolution operator, and the probability amplitude decay is compensated by combining wafer surface roughness parameters, thereby improving the hardware robustness of the quantum algorithm.

[0020] The synergistic optimization of the fusion cache margin, the mechanical arm vibration compensation and the path selection instruction is realized on the FPGA to achieve parallel calculation of the prediction / topology / quantum three regions, and dynamic voltage frequency scaling is combined. BRIEF DESCRIPTION OF DRAWINGS

[0021] Figure 1 An embodiment of the method for optimizing semiconductor wafer conveying efficiency using a device-side cache system in the embodiment of the application is shown in the figure;

[0022] Figure 2 An embodiment of the device for optimizing semiconductor wafer conveying efficiency using a device-side cache system in the embodiment of the application is shown in the figure. DETAILED DESCRIPTION

[0023] The embodiment of the application provides a method for optimizing semiconductor wafer conveying efficiency using a device-side cache system, and realizes intelligent synergistic optimization of the whole wafer conveying process. The terms "first", "second", "third", "fourth" and the like (if any) in the specification and claims of the application and the above-mentioned drawings are used to distinguish similar objects, and do not have to be used to describe a specific order or sequence. It should be understood that the data thus used can be interchanged under appropriate circumstances, so that the embodiments described herein can be implemented in an order other than that illustrated or described herein. In addition, the terms "include" or "have" and any variations thereof are intended to cover non-exclusive inclusion, for example, a process, method, system, product or device including a series of steps or units does not have to be limited to only those steps or units clearly listed, but can include other steps or units not clearly listed or inherent to the process, method, product or device.

[0024] For the sake of understanding, the specific process of the embodiment of the application is described below. Please refer to Figure 1 An embodiment of the method for optimizing semiconductor wafer conveying efficiency using a device-side cache system in the embodiment of the application includes:

[0025] 101, device-side data acquisition, through photoelectric sensors installed at the wafer conveying inlet, real-time acquisition of wafer arrival timestamp sequence (product ①: timestamp sequence); through a state monitoring interface connected to the device control system, real-time acquisition of device processing rate and current cache queue length (product ②: device state data);

[0026] It can be understood that the execution subject of the present application can be a device for optimizing the semiconductor wafer conveying efficiency using the device end cache system, and can also be a terminal or a server, and the specific embodiments are not limited herein. The server is taken as an example for description of the embodiments of the present application.

[0027] It should be noted that, in step S1.1, the multi-source heterogeneous data is synchronously collected. The laser interference unit in the photoelectric sensor captures the phase difference of the wafer edge reflected light (original input ①: light phase difference signal). The piezoelectric acoustic sensor attached to the wafer cassette collects the wafer placement vibration waveform (original input ②: vibration waveform signal). The CAN protocol parser connected to the device control bus reads the device processing state register value in real time (original input ③: device processing state register value).

[0028] In step S1.2, the physical characteristics are converted. The light phase difference signal of the original input ① is input into the time-frequency conversion module, and the wafer arrival timestamp is output (intermediate product ①: timestamp sequence). The vibration waveform signal of the original input ② is input into the resonance peak extraction module, and the wafer placement stability score is output (intermediate product ②: stability score). The device processing state register value of the original input ③ is input into the binary decoding module, and the device processing rate and the cache queue length are output (intermediate product ③: device state parameter).

[0029] In step S1.3, the data is enhanced and output. The timestamp sequence of the intermediate product ① and the stability score of the intermediate product ② are input into the sliding window alignment processor to generate an enhanced timestamp sequence with physical state markers (product ①: timestamp sequence). The device state parameter of the intermediate product ③ and the stability score of the intermediate product ② are input into the abnormal filtering module to generate device state data excluding jitter interference (product ②: device state data).

[0030] In step S1.3, the data is enhanced and output. The timestamp sequence of the intermediate product ① and the stability score of the intermediate product ② are input into the sliding window alignment processor to generate an enhanced timestamp sequence with physical state markers (product ①: timestamp sequence). The device state parameter of the intermediate product ③ and the stability score of the intermediate product ② are input into the abnormal filtering module to generate device state data excluding jitter interference (product ②: device state data).

[0031] It should be noted that, in step S2.1, the arrival interval sequence is generated. The timestamp sequence of the product ① is input into the difference processor to calculate the time interval of adjacent wafer arrivals (intermediate product ①: arrival interval sequence). The stability score in the device state data of the product ② is input into the weight distributor to generate the reliability weight of each time interval (intermediate product ②: interval weight set).

[0032] Step S2.2: Fractional order degree dynamic calculation, input the inter-arrival sequence of intermediate product ① and the interval weight set of intermediate product ② into a Hurst index estimator, and output a long memory strength value (intermediate product ③: Hurst index) based on the weighted weight difference method; input the Hurst index of intermediate product ③ into a degree mapping table, and output a degree parameter of the fractional order differential equation (intermediate product ④: fractional order degree);

[0033] Step S2.3: Buffer queue prediction, input the fractional order degree of intermediate product ④, the current queue length in the device state data of product ②, and the device processing rate into a Grünwald-Letnikov discrete predictor; based on the memory dependence characteristics of the historical queue state, output a buffer queue prediction value in the next 5-10 seconds (product ③: predicted queue value);

[0034] Step S2.4: Wafer residence compensation, input the predicted queue value of product ③ into a residence effect compensation module, combine the wafer material viscosity coefficient (input source: pre-stored wafer physical property library), and output a final predicted queue value after compensation (updated product ③: predicted queue value).

[0035] 103、Topology bottleneck identification, input the device connection topology graph pre-stored in the device end memory and the device state data of product ② into a topology homology analysis unit; by calculating the connectivity characteristics between device nodes, output a high-load risk device identification set (product ④: bottleneck device identification set);

[0036] It should be noted that step S3.1: dynamic weight topology construction, input the device connection topology graph pre-stored in the device end memory (input source: adjacency matrix storage unit) and the device processing rate in the device state data of product ② into an edge weight calculator; based on the real-time load rate of the device, generate a dynamic weight value of the topology edge (intermediate product ①: weighted topology graph);

[0037] Step S3.2: Simplified homology complex generation, input the weighted topology graph of intermediate product ① into a threshold filtering module, and remove edges with a weight lower than a preset saturation threshold (intermediate product ②: simplified topology complex); based on the simplified topology complex, construct a simple complex structure (intermediate product ③: homology complex);

[0038] Step S3.3: Persistent homology calculation, input the homology complex of intermediate product ③ into a Betti number calculation unit, and output the number of connected components in each dimension (intermediate product ④: Betti number sequence); compare the Betti number sequence of intermediate product ④ with a preset bottleneck determination rule (input source: pre-stored rule library), and generate a high-load risk device identification (product ④: bottleneck device identification set);

[0039] Step S3.4: Bottleneck dynamic verification, input the bottleneck device identifier set of product ④ into the device feedback loop module, combine with the real-time queue length change rate of the device end (input source: the queue length derivative of product ②), output the final bottleneck device identifier set after verification (update product ④: bottleneck device identifier set).

[0040] 104. Transport path decision, input the bottleneck device identifier set of product ④ and the pre-defined path weight matrix into the quantum random walk path optimization unit; based on the evolution of the device load probability amplitude, output the optimal wafer transport path number (product ⑤: path selection instruction);

[0041] It should be noted that step S4.1: probability amplitude evolution ground state construction, input the bottleneck device identifier set of product ④ into the path shield, disable the paths in the pre-defined path weight matrix leading to high load devices (intermediate product ①: optimized path matrix); generate the Hamilton initial ground state of quantum random walk based on the optimized path matrix (intermediate product ②: initial probability amplitude distribution);

[0042] Step S4.2: device load driven evolution, input the real-time queue length in the device state data of product ② into the potential field generator, output the potential energy value of each path node (intermediate product ③: potential field vector); input the initial probability amplitude distribution of intermediate product ② and the potential field vector of intermediate product ③ into the unitary evolution operator module, perform discrete-time quantum walk iteration (intermediate product ④: evolved probability amplitude);

[0043] Step S4.3: wafer physical interference compensation, input the evolved probability amplitude of intermediate product ④ into the de-coherence compensation module, combine with the wafer surface roughness parameter (input source: pre-stored wafer physical property library), compensate the probability amplitude decay (intermediate product ⑤: corrected probability amplitude);

[0044] Step S4.4: path decision output, input the corrected probability amplitude of intermediate product ⑤ into the maximum probability selector, output the optimal path number (product ⑤: path selection instruction).

[0045] 105. Buffer dynamic execution, input the predicted queue value of product ③, the bottleneck device identifier set of product ④, and the path selection instruction of product ⑤ into the robust optimization control unit; generate buffer size adjustment instructions (product ⑥: buffer size instructions) and wafer redirection instructions (product ⑦: robot control instructions); send the buffer size instructions of product ⑥ to the pneumatic telescopic controller of the adjustable buffer area, and send the robot control instructions of product ⑦ to the servo driver of the wafer handling robot.

[0046] It should be noted that step S5.1: buffer robust allocation, the predicted queue value of product ③ is input into the buffer margin calculator, combined with the wafer thickness parameter (input source: pre-stored wafer physical property library), to generate a collision avoidance safety distance (intermediate product ①: thickness compensation parameter); the thickness compensation parameter of intermediate product ① and the predicted queue value of product ③ are input into the pneumatic volume mapping module to output the buffer zone stretching length instruction (intermediate product ②: original buffer instruction);

[0047] Step S5.2: path execution compensation, input the path selection instruction of product ⑤ into the kinematics converter to generate the mechanical arm joint angle sequence (intermediate product ③: original joint instruction); input the bottleneck equipment identification set of product ④ into the vibration suppression module, combined with the historical vibration spectrum of the mechanical arm (input source: servo driver feedback data) to generate the vibration compensation coefficient (intermediate product ④: compensation coefficient set);

[0048] Step S5.3: dynamic coupling optimization, input the original buffer instruction of intermediate product ②, the original joint instruction of intermediate product ③, and the compensation coefficient set of intermediate product ④ into the Lyapunov stability controller; output the anti-interference buffer size instruction (product ⑥: buffer size instruction) and the anti-vibration robot control instruction (product ⑦: robot control instruction);

[0049] Step S5.4: hardware cooperative execution, send the buffer size instruction of product ⑥ to the multi-stage pneumatic cylinder group of the adjustable buffer zone to drive the piston to stretch and retract to the target position; send the robot control instruction of product ⑦ to the harmonic reducer servo system of the wafer handling robot to move according to the compensated trajectory.

[0050] 106、The device-end embedded processor comprises a dynamic hardware partitioning architecture, including:

[0051] Step S7.1: algorithm unit hardware mapping, map the fractional differential equation prediction unit to the programmable logic area A of the FPGA (hardware partition ①: FDE acceleration area); map the topological homology analysis unit to the storage optimization area B of the FPGA (hardware partition ②: TPN acceleration area); map the quantum random walk path optimization unit to the high-precision floating-point area C of the FPGA (hardware partition ③: QRW acceleration area);

[0052] Step S7.2: real-time memory hierarchical scheduling, store the timestamp sequence of product ① into the dual-port BRAM of partition ① through the on-chip bus arbiter (intermediate product ①: FDE input cache); synchronize the device state data of product ② to the compressed adjacency matrix memory of partition ② through the cross-partition DMA engine (intermediate product ②: TPN input cache); load the pre-defined path weight matrix to the distributed RAM of partition ③ through the path weight direct channel (intermediate product ③: QRW input cache);

[0053] Step S7.3: Hardware cascade flow execution, after the completion of the prediction queue value calculation in partition ①, the topology homology analysis of partition ② is started by a hardware signal trigger (intermediate product ④: FDE completion flag); after the output of the bottleneck device identification set in partition ②, the quantum path optimization of partition ③ is triggered by an interrupt priority controller (intermediate product ⑤: TPN completion flag); after the generation of the path selection instruction in partition ③, synchronization to the robust optimization control unit is performed through a parallel output register (intermediate product ⑥: QRW completion flag);

[0054] Step S7.4: Energy efficiency dynamic adjustment, according to the wafer conveying batch interval (input source: MES system clock), the idle partition power consumption is reduced through a dynamic voltage frequency scaling module (product ⑧: energy efficiency optimization state).

[0055] In the embodiment of the present application, through multi-source heterogeneous data acquisition and complex fractional differential equation prediction model, the cache queue situation in the next 5-10 seconds can be accurately predicted, the cache size is adjusted in advance to avoid cache shortage or excess, the wafer waiting time is reduced, and the conveying efficiency is improved; based on the quantum random walk path optimization algorithm, combined with device load probability amplitude evolution and wafer physical interference compensation, the optimal wafer conveying path can be quickly found to avoid high-load devices and reduce delays in the conveying process, further improving the conveying efficiency; through topology homology analysis, high-load risk devices are accurately identified, and measures are taken in time to avoid the occurrence of system bottlenecks, ensuring the stable operation of the entire wafer conveying system; in the dynamic execution process of the cache, the cache instruction, the robot control instruction and the compensation coefficient set are dynamically coupled and optimized, and the anti-interference cache size instruction and the anti-vibration robot control instruction are output, effectively dealing with various interference factors and improving the stability and reliability of the system; different algorithm units are mapped to different hardware partitions of the FPGA to realize reasonable allocation and efficient utilization of hardware resources. At the same time, through real-time memory hierarchical scheduling and hardware cascade flow execution, data transmission and processing delay are reduced, and the overall performance of the system is improved; according to the wafer conveying batch interval, the idle partition power consumption is reduced through a dynamic voltage frequency scaling module to realize dynamic optimization of energy efficiency and reduce system operation cost; a plurality of sensors and interfaces are used to collect multi-source heterogeneous data, and through steps such as physical characteristic conversion, data enhancement and output, the accuracy and availability of the data are improved to provide reliable data support for subsequent prediction and decision-making; complex algorithms such as fractional differential equation prediction unit, topology homology analysis unit and quantum random walk path optimization unit are mapped to different hardware partitions of the FPGA for accelerated processing, greatly improving the data processing capacity and response speed of the system.

[0056] The method for optimizing the semiconductor wafer conveying efficiency by using the device end cache system in the embodiments of the present application is described above, and the device for optimizing the semiconductor wafer conveying efficiency by using the device end cache system in the embodiments of the present application is described below. Please refer to Figure 2 An embodiment of the device for optimizing the semiconductor wafer conveying efficiency by using the device end cache system in the embodiments of the present application includes: an acquisition module 201, configured to collect wafer arrival timestamp sequences and device state data in real time; a processing module 202, configured to input the timestamp sequences and the device state data into a fractional differential equation prediction unit running in a device end embedded processor, output predicted queue values in the future 5-10 seconds based on the long-period correlation characteristics of wafer arrival; a setting module 203, configured to input a device connection topology graph pre-stored in a device end memory and the device state data into a topology homology analysis unit, output a bottleneck device identification set by calculating the connectivity characteristics between device nodes; an execution module 204, configured to input the bottleneck device identification set and a pre-defined path weight matrix into a quantum random walk path optimization unit, output path selection instructions based on the evolution of device load probability amplitude; and an allocation module 205, configured to input the predicted queue values, the bottleneck device identification set and the path selection instructions into a robust optimization control unit, generate cache size instructions and robot control instructions, send the cache size instructions to a pneumatic telescopic controller of an adjustable cache area, and send the robot control instructions to a servo driver of a wafer handling robot arm.

[0057] Compared with the traditional prediction method, the wafer arrival law can be accurately grasped, the queue value in the next 5-10 seconds is obtained in advance, more accurate data basis is provided for subsequent optimization, the device operation strategy is adjusted in advance, the waiting time is reduced, and the conveying efficiency is improved; the bottleneck device is identified by calculating the connectivity characteristics between the device nodes by combining the device connection topology graph and the device state data. This method comprehensively considers the system overall topology structure and the real-time state of the device from two dimensions, can more comprehensively and accurately find out the key bottleneck device affecting the wafer conveying efficiency, and provides a clear target for subsequent path optimization; the quantum random walk path optimization unit is used, and the path selection instruction is output based on the device load probability amplitude evolution. The quantum random walk algorithm has stronger global search ability and randomness, can more efficiently find the optimal path in the complex device connection network, avoid falling into a local optimal solution, further improve the rationality of the wafer conveying path, and reduce the detour and waiting in the conveying process; the predicted queue value, the bottleneck device identification set and the path selection instruction are input into the robust optimization control unit to generate the cache size instruction and the robot control instruction, and the whole process comprehensive optimization from the cache size adjustment to the robot handling is realized. This multi-factor collaborative optimization method can better adapt to the complex changes in the semiconductor wafer conveying process, improve the stability and efficiency of the whole conveying system, and reduce the production delay risk caused by insufficient cache or unreasonable robot scheduling.

[0058] The application further provides a device for optimizing semiconductor wafer conveying efficiency by using a device end cache system, which comprises a memory and a processor, the memory stores computer readable instructions, and the computer readable instructions are executed by the processor to make the processor execute the steps of the method for optimizing semiconductor wafer conveying efficiency by using a device end cache system in each of the embodiments.

[0059] The application further provides a computer readable storage medium, which can be a non-volatile computer readable storage medium or a volatile computer readable storage medium, and the computer readable storage medium stores instructions, and the instructions make the computer execute the steps of the method for optimizing semiconductor wafer conveying efficiency by using a device end cache system when the instructions run on the computer.

[0060] Those skilled in the art can clearly understand that, for the convenience and brevity of description, the specific working process of the system, device and unit described above can refer to the corresponding process in the foregoing method embodiments, and will not be repeated here.

[0061] The integrated unit, if implemented in the form of a software function unit and sold or used as an independent product, can be stored in a computer readable storage medium. Based on such understanding, the technical solutions of the present application or the entire or part of the technical solutions that essentially contribute to the prior art can be embodied in the form of a software product. The computer software product is stored in a storage medium and includes a plurality of instructions for causing a computer device (which can be a personal computer, a server, or a network device, etc.) to execute all or part of the steps of the method described in the various embodiments of the present application. The aforementioned storage medium includes: a U disk, a mobile hard disk, a read-only memory (ROM), a random access memory (RAM), a magnetic disk or an optical disk, and various media that can store program codes.

[0062] The above-described embodiments are merely used to illustrate the technical solutions of the present application, rather than limit them; although the present application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that they can still modify the technical solutions recorded in the foregoing embodiments, or make equivalent replacements for some of the technical features; and these modifications or replacements do not cause the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present application.

Claims

1. A method for optimizing semiconductor wafer delivery efficiency using a device-side buffer system, characterized in that, The method for optimizing semiconductor wafer delivery efficiency using a device-side caching system includes: Real-time acquisition of wafer arrival timestamp sequences and equipment status data; The timestamp sequence and device status data are input into the fractional differential equation prediction unit running in the embedded processor of the device. Based on the long-period correlation characteristics of wafer arrival, the predicted queue value within the next 5-10 seconds is output. The device connection topology map and device status data, which are pre-stored in the device-side memory, are input to the topology coherence analysis unit. By calculating the connectivity characteristics between device nodes, the bottleneck device identifier set is output. The bottleneck device identifier set and the predefined path weight matrix are input into the quantum random walk path optimization unit, and the path selection instruction is output based on the evolution of the device load probability amplitude. The predicted queue value, bottleneck device identifier set, and path selection instruction are input into the robust optimization control unit to generate buffer size instructions and robot control instructions. The buffer size instructions are sent to the pneumatic telescopic controller of the adjustable buffer area, and the robot control instructions are sent to the servo driver of the wafer handling robot arm.

2. The method for optimizing semiconductor wafer transport efficiency using a device-side buffer system according to claim 1, characterized in that, include: The phase difference of the reflected light from the wafer edge is captured by the laser interference unit in the photoelectric sensor to obtain the light phase difference signal. The vibration waveform of the wafer placement is collected by the piezoelectric acoustic wave sensor attached to the wafer cassette to obtain the vibration waveform signal. The device processing status register value is read in real time by the CAN protocol parser connected to the device control bus. The optical phase difference signal is input into the time-frequency conversion module, which outputs the wafer arrival timestamp sequence. The vibration waveform signal is input into the resonance peak extraction module, which outputs the wafer placement stability score. The device processing status register value is input into the binary decoding module, which outputs the device status parameters. The wafer arrival timestamp sequence and wafer placement stability score are input into the sliding window alignment processor to generate an enhanced timestamp sequence with physical state markers. The device status parameters and wafer placement stability score are input into the anomaly filtering module to generate device status data that eliminates jitter interference.

3. The method for optimizing semiconductor wafer transport efficiency using a device-side buffer system according to claim 1, characterized in that, include: The timestamp sequence is input into the differential processor to calculate the arrival interval sequence of adjacent wafers, and the stability score in the device status data is input into the weight allocator to generate the interval weight set. The arrival interval sequence and the interval weight set are input into the Hurst exponent estimator, and the Hurst exponent is output based on the weighted scale range method. The Hurst exponent is input into the order mapping table and the fractional order is output. The fractional order, the current queue length from the device status data, and the device processing rate are input into the Grünwald-Letnikov discrete predictor. Based on the memory dependency of historical queue status, the predicted queue value is output. The predicted queue value is input into the retention effect compensation module, and combined with the wafer material viscosity coefficient, the final predicted queue value after compensation is output.

4. The method for optimizing semiconductor wafer transport efficiency using a device-side buffer system according to claim 1, characterized in that, include: The device connection topology graph pre-stored in the device-side memory, along with the device processing rate in the device status data, are input into the edge weight calculator to generate a weighted topology graph based on the real-time load rate of the devices. The weighted topological graph is input into the threshold filtering module, and edges with weights lower than the preset saturation threshold are removed to obtain a simplified topological complex. Based on the simplified topological complex, a simple complex structure is constructed to obtain a homology complex. The homology complex is input into the Betti number calculation unit, which outputs a Betti number sequence. The Betti number sequence is compared with the preset bottleneck determination rules to generate a bottleneck device identifier set. The bottleneck device identifier set is input into the device feedback loop module, and combined with the real-time queue length change rate at the device end, the final verified bottleneck device identifier set is output.

5. The method for optimizing semiconductor wafer transport efficiency using a device-side buffer system according to claim 1, characterized in that, include: Input the bottleneck device identifier set into the path blocker, disable the paths to high-load devices in the predefined path weight matrix to obtain the optimized path matrix, generate the Hamiltonian initial ground state of quantum random walk based on the optimized path matrix, and obtain the initial probability amplitude distribution. Input the real-time queue length from the device status data into the potential field generator, output the potential field vector, input the initial probability amplitude distribution and the potential field vector into the unitary evolution operator module, perform discrete-time quantum walk iteration, and obtain the evolved probability amplitude. The evolved probability amplitude is input into the decoherence compensation module, and combined with the wafer surface roughness parameter, the probability amplitude attenuation is compensated to obtain the corrected probability amplitude. Input the correction probability amplitude into the maximum probability selector and output the path selection instruction.

6. The method for optimizing semiconductor wafer transport efficiency using a device-side buffer system according to claim 1, characterized in that, include: The predicted queue value is input into the cache margin calculator, combined with the wafer thickness parameter, to generate the thickness compensation parameter. The thickness compensation parameter and the predicted queue value are input into the aerodynamic volume mapping module, and the original cache instruction is output. The path selection command is input into the kinematic converter to generate the original joint command. The bottleneck device identifier set is input into the vibration suppression module and combined with the historical vibration spectrum of the robotic arm to generate a set of compensation coefficients. The original buffer instructions, original joint instructions, and compensation coefficient set are input into the Lyapunov stability controller, which outputs buffer size instructions and robot control instructions. The buffer size command is sent to the multi-stage pneumatic cylinder group of the adjustable buffer area, which drives the piston to extend and retract to the target position. The robot control command is sent to the harmonic reducer servo system of the wafer handling robot arm, which moves according to the compensated trajectory.

7. The method for optimizing semiconductor wafer transport efficiency using a device-side buffer system according to claim 1, characterized in that, The device-side embedded processor includes a dynamic hardware partitioning architecture, comprising: The fractional differential equation prediction unit is mapped to the programmable logic area A of the FPGA, the topological homology analysis unit is mapped to the storage optimization area B of the FPGA, and the quantum random walk path optimization unit is mapped to the high-precision floating-point area C of the FPGA. The timestamp sequence is stored in the dual-port BRAM through the on-chip bus arbitrator, the device status data is synchronized to the compressed adjacency matrix memory through the cross-partition DMA engine, and the predefined path weight matrix is ​​loaded into the distributed RAM through the path weight direct connection channel. After completing the calculation of the predicted queue value, the topology coherence analysis is initiated by a hardware signal trigger. After outputting the bottleneck device identifier set, the quantum path optimization is triggered by the interrupt priority controller. After generating the path selection instruction, it is synchronized to the robust optimization control unit through the parallel output register. Based on the wafer delivery batch interval, the power consumption of the idle partition is reduced by a dynamic voltage frequency scaling module.

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