Active core particle and three-dimensional spiral inductor passive core particle integrated radio frequency chip and preparation method thereof
By separating the planar spiral inductor into a three-dimensional spiral inductor passive chip and integrating it with the active chip of the RF circuit in a three-dimensional stack, the problems of large inductor area and low quality factor in RF chips are solved, realizing a high-performance, small-size RF integrated chip suitable for modern wireless communication circuits.
Patent Information
- Application Number
- CN202510980972.X
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-07-16
- Publication Date
- 2025-11-04
AI Technical Summary
The excessively large area and low quality factor of on-chip inductors in existing RF chips make it difficult to reduce the size of RF chips and improve their performance.
The large-size planar spiral inductor with low quality factor is separated into three-dimensional spiral passive inductor cores with high quality factor, and integrated with active cores of RF circuits through three-dimensional stacking. High resistivity substrates are used to reduce parasitic effects, and bumpless hybrid bonding process is used to achieve electrical interconnection.
It improves the RF performance of RF chips, significantly reduces the footprint, reduces substrate eddy current loss and magnetic leakage, and realizes high-quality RF integrated chips that are compatible with semiconductor processes and can be industrialized.
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Figure CN120897513A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of radio frequency integrated circuit technology, specifically to a radio frequency chip integrating an active radio frequency circuit chip and a passive three-dimensional spiral inductor chip, and its fabrication method. Background Technology
[0002] On-chip inductors are fundamental passive components in radio frequency (RF) integrated circuits, widely used in various RF front-end modules such as low-noise amplifiers, voltage-controlled oscillators, mixers, and filters, forming the basis of modern wireless communication circuits. Driven by applications requiring wider bandwidth and lower power consumption, RF circuits demand smaller, higher-frequency, and higher-performance circuit components. However, the development of on-chip inductors faces two major challenges. First, their area is too large. To meet the design requirement of several nH inductance values in the GHz band, the area of on-chip planar spiral inductors typically occupies more than 50% of the RF circuit area. Such a huge area consumption is unacceptable for increasingly high-density integrated circuits. The other problem is low performance. Due to numerous parasitic effects such as eddy current losses in the semiconductor substrate and dielectric coupling capacitance, the quality factor of on-chip inductors is too low, resulting in poor circuit frequency stability and high noise levels. Therefore, the challenges faced by on-chip inductors have made it difficult to reduce the size of RF chips and improve RF performance, making it one of the main bottlenecks in the current development of RF chips.
[0003] To address this, researchers have developed various MEMS-structured on-chip inductors to improve their quality factor. However, the lack of stability and incompatibility of fabrication processes in MEMS inductors have prevented their practical application. Simultaneously, researchers have developed stacked on-chip inductors to reduce the size of RF chips; however, the parasitic effects between the upper and lower metal layers introduced by the stacked structure still result in a low quality factor for the RF chip. Furthermore, researchers have introduced high-frequency magnetic materials into on-chip inductors to achieve small-size, high-quality-factor inductors; however, the incompatibility between magnetic material fabrication processes and integrated circuit processes prevents the practical application of these inductors. Therefore, the lack of small-size, high-quality-factor on-chip inductors continues to limit the development of RF chips. Summary of the Invention
[0004] The purpose of this invention is to address the problems existing in the prior art by providing an RF chip integrating an active chip and a passive three-dimensional spiral inductor chip, and a method for its fabrication.
[0005] To achieve the above objectives, the technical solution adopted by the present invention is as follows: In a first aspect, a radio frequency (RF) chip integrating an active RF circuit chip and a passive three-dimensional spiral inductor chip is provided. The chip includes an active RF circuit chip and a passive three-dimensional spiral inductor chip stacked together. The active RF circuit chip includes a first substrate and an active circuit region disposed on the first substrate, wherein a first electrical interconnect channel region is further provided within the first substrate. The passive three-dimensional spiral inductor chip includes a second substrate and a three-dimensional spiral inductor region disposed on the second substrate, wherein a second electrical interconnect channel region is further provided within the second substrate. The first substrate is stacked on the second substrate, and the first electrical interconnect channel region and the second electrical interconnect channel region are bonded to form an electrical interconnect.
[0006] This RF chip separates a low-quality-factor, large-size planar spiral inductor from the RF chip and fabricates it into a high-quality-factor three-dimensional spiral inductor core. Simultaneously, the remaining active circuitry from the RF chip is fabricated into active RF circuit cores. These three-dimensional spiral inductor cores and active RF circuit cores are then bonded together in a three-dimensional stack and electrically interconnected, forming a fully functional integrated RF circuit chip. The application of the high-quality-factor three-dimensional spiral inductor passive core solves the problem of low quality factor in existing RF chips caused by the high parasitic loss of planar spiral inductors. Furthermore, the three-dimensional integration of the core solves the problem of excessive area caused by the large size of planar spiral inductors in existing RF chips.
[0007] Furthermore, the first substrate is a semiconductor wafer, and the second substrate is a semiconductor wafer with high resistivity.
[0008] Furthermore, the active circuit region is located on the upper surface of the first substrate and includes a circuit portion of a fully functional radio frequency circuit from which a passive inductor element is separated.
[0009] Furthermore, the first electrical interconnect channel region is located in the first substrate, with one end extending to the upper surface of the first substrate and interconnecting with the active circuit region, and the other end extending to the lower surface of the first substrate and electrically interconnecting with the second electrical interconnect channel region.
[0010] Furthermore, the three-dimensional spiral inductor region includes a passive inductor component separated from a fully functional radio frequency circuit, and its structure is a spatial three-dimensional spiral.
[0011] Furthermore, the three-dimensional spiral inductor region includes a number of spiral coils connected sequentially along the axial direction. The upper layer of the spiral coils is located on the upper surface of the second substrate, and the lower layer is located on the lower surface of the second substrate. The spiral coils at both ends are electrically interconnected with the second electrical interconnection channel region, respectively.
[0012] Furthermore, the second electrical interconnect channel region is located in the second substrate, with one end extending to the upper surface of the second substrate and electrically interconnecting with the first electrical interconnect channel region, and the other end interconnecting with the three-dimensional spiral inductor region on the second substrate.
[0013] Furthermore, the stacking is achieved using a bumpless hybrid bonding process, during which the first electrical interconnect channel region and the second electrical interconnect channel region are aligned.
[0014] Furthermore, the radio frequency chip includes a fully functional radio frequency circuit composed of active circuits on the active core of the radio frequency circuit and passive inductors on the passive core of the three-dimensional spiral inductor.
[0015] Secondly, a method for fabricating an RF chip integrating an active chip and a passive three-dimensional spiral inductor chip is provided, the method comprising the following steps: Take a silicon wafer as the first substrate and a silicon dioxide wafer as the second substrate, clean and dry them for later use; The active circuit portion of the radio frequency circuit, excluding passive inductors, is fabricated on the upper surface of the silicon wafer using standard semiconductor processes. A first electrical interconnect via is fabricated on the silicon wafer using through-silicon via (TSV) technology. Copper is then used to fill the first electrical interconnect via with copper to form a copper interconnect line, thus obtaining the first electrical interconnect channel region. One end of the copper interconnect line is interconnected with the active circuit region, and the other end of the copper interconnect line is located on the lower surface of the silicon wafer, thereby obtaining the active chip of the radio frequency circuit. The upper copper coil of a three-dimensional spiral inductor is fabricated on the upper surface of a silicon dioxide wafer using standard semiconductor processes. Several through-silicon vias (TSVs) are fabricated on the silicon dioxide wafer using through-silicon via (TSV) technology. Copper is then filled into the TSVs using electroplating to form the upper and lower copper interconnects of the three-dimensional spiral inductor and a second electrical interconnect channel region. The lower copper coil of the three-dimensional spiral inductor is fabricated on the lower surface of the silicon dioxide wafer using standard semiconductor processes. The upper and lower copper coils are interconnected with the upper and lower copper coils through the upper and lower copper interconnects to form the three-dimensional spiral inductor region. One end of the second electrical interconnect channel region is interconnected with the three-dimensional spiral inductor region, and the other end is located on the surface of the silicon dioxide wafer, thereby obtaining a passive core of a three-dimensional spiral inductor. The three-dimensional spiral inductor passive chip and the RF circuit active chip are stacked together in three dimensions. The second electrical interconnect channel region is aligned with the first electrical interconnect channel region. The three-dimensional spiral inductor passive chip and the RF circuit active chip are tightly bonded together using a bumpless bonding process to achieve electrical copper interconnect, thereby obtaining an RF chip with complete functions.
[0016] Compared with the prior art, the beneficial effects of the present invention are as follows: 1. The present RF chip uses a high-quality factor three-dimensional passive inductor core to replace the low-quality factor planar spiral inductor element in the RF circuit, thereby improving the RF performance of the RF chip; at the same time, the planar integration method of passive inductor elements and active circuits in the RF circuit is replaced by a three-dimensional stacked integration method, which significantly reduces the footprint of the RF circuit and reduces the size of the RF chip; 2. The three-dimensional spiral inductor passive core of the present invention uses a high-resistivity substrate to reduce many parasitic effects such as substrate eddy current loss and dielectric coupling capacitance; at the same time, it has lower magnetic leakage than the planar spiral inductor structure, and the electromagnetic field generated by the three-dimensional spiral inductor has less impact on the active core of the RF circuit; therefore, the three-dimensional spiral inductor of the present invention has a higher quality factor than the planar spiral inductor, so that the RF integrated chip also has a high quality factor; 3. The active core of the RF circuit and the three-dimensional spiral inductor passive core are integrated by a three-dimensional stacking method. Together, they form an RF integrated chip. The RF integrated chip has the same footprint as the active RF circuit chip, and the footprint of the active RF circuit chip is equal to the footprint of the existing RF chip minus the footprint of the planar spiral inductor. Therefore, compared with the existing RF chips using planar spiral inductors, the RF integrated chip has a smaller footprint. 4. The three-dimensional spiral inductor passive chip of the present invention is an independent module, and its structure is no longer affected by other components in the RF circuit. It is flexible and versatile. Moreover, as long as the electrical interface is standardized, it can be integrated with other active RF circuit chips as needed and applied to various RF chips. 5. The active RF circuit chip and the three-dimensional inductor passive chip of the present invention are both fabricated using standard semiconductor processes. The RF integrated chip is realized by three-dimensionally integrating the two chips using a bumpless bonding process commonly used in semiconductor processes. Therefore, the fabrication process of the RF chip of the present invention is compatible with semiconductor processes and can achieve industrial production. Attached Figure Description
[0017] Figure 1 This is a schematic cross-sectional view of an RF chip integrating an active RF circuit chip and a passive three-dimensional spiral inductor chip according to the present invention. Figure 2 This is a schematic diagram of the passive core structure of the three-dimensional spiral inductor of the present invention; Figure 3 The diagram shows a schematic of the radio frequency integrated chip fabrication process of the present invention. In the diagram: 1. Active chip for RF circuit; 2. Passive chip for three-dimensional spiral inductor; 101. First substrate; 102. Active circuit region; 103. First electrical interconnect channel region; 201. Second substrate; 202. Three-dimensional spiral inductor region; 203. Second electrical interconnect channel region; 2021. Upper copper coil; 2022. Lower copper coil; 2023. Upper and lower copper interconnects; 2024. End region. Detailed Implementation
[0018] The technical solution of the present invention will now be clearly and completely described with reference to the accompanying drawings. Obviously, the described embodiments are merely some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.
[0019] In the description of this invention, it should be noted that the terms "middle," "upper," "lower," "left," "right," "inner," and "outer," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are used only for the convenience of describing this invention and for simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this invention. Furthermore, the terms "first," "second," etc., are used for descriptive purposes only and should not be construed as indicating or implying relative importance. Example 1
[0020] like Figure 1 and Figure 2 As shown, an RF chip integrating an active RF circuit chip and a passive three-dimensional spiral inductor chip includes an active RF circuit chip 1 and a passive three-dimensional spiral inductor chip 2 stacked together. The active RF circuit chip 1 includes a first substrate 101 and an active circuit region 102 disposed on the first substrate 101. The first substrate 101 also has a first electrical interconnect channel region 103. The passive three-dimensional spiral inductor chip 2 includes a second substrate 201 and a three-dimensional spiral inductor region 202 disposed on the second substrate 201. The second substrate 201 also has a second electrical interconnect channel region 203. The first substrate 101 is stacked on the second substrate 201, and the first electrical interconnect channel region 103 and the second electrical interconnect channel region 203 are bonded to form an electrical interconnect.
[0021] This RF (integrated) chip separates a low-quality-factor, large-size planar spiral inductor from the RF chip to fabricate a high-quality-factor, three-dimensional spiral inductor passive chip 2. Simultaneously, the remaining active circuitry from the RF chip is fabricated into an RF circuit active chip 1. Then, the three-dimensional spiral inductor passive chip 2 and the RF circuit active chip 1 are bonded together in a three-dimensional stacking manner and electrically interconnected, thus forming a fully functional RF circuit integrated chip. The application of the high-quality-factor, three-dimensional spiral inductor passive chip solves the problem of low quality factor caused by the high parasitic loss of planar spiral inductors in existing RF chips. The three-dimensional integration of the chip solves the problem of excessive area caused by the excessive size of planar spiral inductors in existing RF chips.
[0022] The basic concept of this RF chip design is to replace the low-quality-factor planar spiral inductor in the RF circuit with a high-quality-factor three-dimensional passive inductor chip, thereby improving the RF performance of the RF chip. At the same time, the planar integration of passive inductors and active circuits in the RF circuit is replaced with a three-dimensional stacked integration method, which significantly reduces the footprint of the RF circuit and the size of the RF chip.
[0023] This invention separates the low-quality-factor planar spiral inductor from the RF chip and fabricates it into a three-dimensional spiral inductor passive chip. Since the inductor chip contains only passive inductors, a high-resistivity substrate can be used to reduce substrate eddy current losses, dielectric coupling capacitance, and many other parasitic effects. Furthermore, the three-dimensional spiral inductor structure used in this invention has lower magnetic leakage than the planar spiral inductor structure, and the electromagnetic field generated by the three-dimensional spiral inductor has less impact on the active chips in the RF circuit. Therefore, the three-dimensional spiral inductor of this invention has a higher quality factor than the planar spiral inductor, enabling the RF integrated chip to also have a high quality factor.
[0024] This invention separates the large-area planar spiral inductor from the RF chip and fabricates it into a three-dimensional spiral inductor passive chip. Then, the active RF circuit chip and the three-dimensional spiral inductor passive chip are integrated together using a three-dimensional stacking method to form an RF integrated chip. As can be seen, the floor area of the RF integrated chip is the same as that of the active RF circuit chip, and the floor area of the active RF circuit chip is equal to the floor area of the existing RF chip minus the area occupied by the planar spiral inductor. Therefore, compared with existing RF chips using planar spiral inductors, the RF integrated chip has a smaller floor area.
[0025] This invention fabricates passive inductor components in radio frequency (RF) circuits into three-dimensional spiral passive inductor cores. These three-dimensional spiral passive inductor cores, as independent modules, are no longer affected by other components in the RF circuit, offering greater flexibility. Furthermore, by standardizing the electrical interfaces, these three-dimensional spiral passive inductor cores can be integrated with other active RF circuit cores and applied to various RF chips as needed. In contrast, existing passive inductors, as part of an RF circuit, can only be integrated into a single RF chip. Therefore, this invention offers the advantage of greater design flexibility.
[0026] Furthermore, both the active RF circuit chip and the passive three-dimensional inductor chip are fabricated using standard semiconductor processes. The RF integrated chip is achieved by three-dimensionally integrating the two chips using a bumpless bonding process commonly used in semiconductor processes. Therefore, this invention is fully compatible with semiconductor processes and can be industrialized.
[0027] Furthermore, the first substrate 101 is a semiconductor wafer, such as silicon, gallium arsenide, gallium nitride, etc.; the second substrate 201 is a high resistivity semiconductor wafer, such as high resistivity silicon, silicon oxide, aluminum oxide, etc.
[0028] Furthermore, the active circuit region 102 is located on the upper surface of the first substrate 101 and includes a circuit portion of a fully functional radio frequency circuit from which a passive inductor element is separated.
[0029] Furthermore, the first electrical interconnect channel region 103 is located in the first substrate 101, with one end extending to the upper surface of the first substrate 101 and interconnecting with the active circuit region 102, and the other end extending to the lower surface of the first substrate 101 and electrically interconnecting with the second electrical interconnect channel region 203. It is connected using a metal with excellent conductivity, such as copper or aluminum.
[0030] Furthermore, the three-dimensional spiral inductor region 202 includes a passive inductor component separated from a fully functional radio frequency circuit. The structure is a three-dimensional spiral in space and uses a metal with excellent conductivity, such as copper or aluminum.
[0031] Furthermore, the three-dimensional spiral inductor region 202 includes a plurality of spiral coils connected sequentially along the axial direction. The upper layer of the plurality of spiral coils is located on the upper surface of the second substrate 201, and the lower layer is located on the lower surface of the second substrate 201. The spiral coils at both ends form end regions 2024, which are electrically interconnected with the second electrical interconnection channel region 203 respectively.
[0032] Specifically, the spiral coils are connected in sequence to form a three-dimensional spiral structure. The upper copper coil 2021 is located on the upper part of the second substrate 201 and is flush with the upper surface. The lower copper coil 2022 is located on the lower surface of the second substrate 201. The lower copper coils 2022 at both ends extend to form end regions 2024 so as to be connected to the second electrical interconnection channel region 203.
[0033] Furthermore, the second electrical interconnect channel region 203 is located in the second substrate 201, with one end extending to the upper surface of the second substrate 201 and electrically interconnected with the first electrical interconnect channel region 103, and the other end interconnected with the three-dimensional spiral inductor region 202 on the second substrate 201, using a metal with excellent conductivity, such as copper or aluminum.
[0034] Furthermore, the stacking is achieved using a bumpless hybrid bonding process, during which the first electrical interconnect channel region and the second electrical interconnect channel region are aligned.
[0035] Furthermore, the radio frequency chip includes a fully functional radio frequency circuit composed of active circuits on the active core of the radio frequency circuit and passive inductors on the passive core of the three-dimensional spiral inductor. Example 2
[0036] This embodiment provides a method for fabricating an RF chip integrating an active RF circuit chip and a passive three-dimensional spiral inductor chip, as described in Embodiment 1. Figure 3 As shown, the preparation method includes the following steps: Step 1: Take a 4-inch silicon wafer with a thickness of 350μm as the first substrate 101 and a 4-inch silicon dioxide wafer with a thickness of 350μm as the second substrate 201. Clean and dry them respectively for later use.
[0037] Step 2: Using standard semiconductor processes, the active circuit portion of the RF circuit, excluding the passive inductor, is fabricated on the upper surface of the silicon wafer. A first electrical interconnect via with a diameter of 20 μm is fabricated on the silicon wafer using through-silicon via (TSV) technology. Copper is then used to fill the first electrical interconnect via with copper to form a copper interconnect line, resulting in the first electrical interconnect channel region 103. One end of the copper interconnect line is interconnected with the active circuit region 102, and the other end of the copper interconnect line is located on the lower surface of the silicon wafer, thereby obtaining the active chip 1 of the RF circuit.
[0038] Step 3: Using standard semiconductor processes, an upper copper coil of a three-dimensional spiral inductor is fabricated on the upper surface of the silicon dioxide wafer. Several through-silicon vias (TSVs) with a diameter of 20 μm are fabricated on the silicon dioxide wafer. Copper is then filled into the TSVs using electroplating to form upper and lower copper interconnects and a second electrical interconnect channel region 203 for the three-dimensional spiral inductor. A lower copper coil of the three-dimensional spiral inductor is fabricated on the lower surface of the silicon dioxide wafer using standard semiconductor processes. The upper and lower copper coils are interconnected with the upper and lower copper coils through the upper and lower copper interconnects to form the three-dimensional spiral inductor region 202. One end of the second electrical interconnect channel region 203 is interconnected with the three-dimensional spiral inductor region 202, and the other end is located on the surface of the silicon dioxide wafer, thus obtaining the passive core 2 of the three-dimensional spiral inductor.
[0039] Step 4: Stack the three-dimensional spiral inductor passive chip 2 and the RF circuit active chip 1 together in three dimensions. Align the second electrical interconnect channel region with the first electrical interconnect channel region. Use a bumpless bonding process to tightly bond the three-dimensional spiral inductor passive chip and the RF circuit active chip together to achieve electrical copper interconnect, thereby obtaining an RF chip with complete functions.
[0040] The preparation method of this invention is well compatible with semiconductor processes and can be industrialized. This preparation method separates the inductive element and the non-inductive circuit part into two separate chips, and then uses a chip bonding process to stack the two separate chips together to form an integrated chip with complete circuit functions. This reduces the chip's footprint and also reduces the negative impact of the inductive element on the non-inductive circuit part on the chip, thereby improving the quality factor of the entire chip circuit.
[0041] Although embodiments of the invention have been shown and described, it will be understood by those skilled in the art that various changes, modifications, substitutions and alterations can be made to these embodiments without departing from the principles and spirit of the invention, the scope of which is defined by the appended claims and their equivalents.
Claims
1. A radio frequency chip integrating an active chip and a passive three-dimensional spiral inductor chip, characterized in that, The device includes an active RF circuit chip and a passive three-dimensional spiral inductor chip stacked together. The active RF circuit chip includes a first substrate and an active circuit region disposed on the first substrate. The first substrate also contains a first electrical interconnect channel region. The passive three-dimensional spiral inductor chip includes a second substrate and a three-dimensional spiral inductor region disposed on the second substrate. The second substrate also contains a second electrical interconnect channel region. The first substrate is stacked on the second substrate, and the first electrical interconnect channel region and the second electrical interconnect channel region are bonded to form an electrical interconnect.
2. The radio frequency chip integrating an active chip and a three-dimensional spiral inductor passive chip according to claim 1, characterized in that, The first substrate is a semiconductor wafer, and the second substrate is a semiconductor wafer with high resistivity.
3. The radio frequency chip integrating the active chip and the three-dimensional spiral inductor passive chip according to claim 1, characterized in that, The active circuit region is located on the upper surface of the first substrate and includes a circuit portion of a fully functional radio frequency circuit from which a passive inductor element is separated.
4. The radio frequency chip integrating the active chip and the three-dimensional spiral inductor passive chip according to claim 1, characterized in that, The first electrical interconnect channel region is located in the first substrate, with one end extending to the upper surface of the first substrate and interconnecting with the active circuit region, and the other end extending to the lower surface of the first substrate and interconnecting with the second electrical interconnect channel region.
5. The radio frequency chip integrating an active chip and a three-dimensional spiral inductor passive chip according to claim 1, characterized in that, The three-dimensional spiral inductor region includes a passive inductor component separated from a fully functional radio frequency circuit, and its structure is a three-dimensional spiral in space.
6. The radio frequency chip integrating the active chip and the three-dimensional spiral inductor passive chip according to claim 5, characterized in that, The three-dimensional spiral inductor region includes a number of spiral coils connected in sequence along the axial direction. The upper layer of the spiral coils is located on the upper surface of the second substrate, and the lower layer is located on the lower surface of the second substrate. The spiral coils at both ends are electrically interconnected with the second electrical interconnection channel region, respectively.
7. The radio frequency chip integrating an active chip and a three-dimensional spiral inductor passive chip according to claim 1, characterized in that, The second electrical interconnect channel region is located in the second substrate, with one end extending to the upper surface of the second substrate and electrically interconnecting with the first electrical interconnect channel region, and the other end interconnecting with the three-dimensional spiral inductor region on the second substrate.
8. The radio frequency chip integrating an active chip and a three-dimensional spiral inductor passive chip according to claim 1, characterized in that, The stacking is achieved using a bumpless hybrid bonding process, during which the first electrical interconnect channel region and the second electrical interconnect channel region are aligned.
9. The radio frequency chip integrating an active chip and a three-dimensional spiral inductor passive chip according to claim 1, characterized in that, The radio frequency chip includes a fully functional radio frequency circuit composed of an active circuit on the active core of the radio frequency circuit and a passive inductor on the passive core of the three-dimensional spiral inductor.
10. The method for fabricating an RF chip integrating an active chip and a three-dimensional spiral inductor passive chip according to any one of claims 1 to 9, characterized in that, The preparation method includes the following steps: Take a silicon wafer as the first substrate and a silicon dioxide wafer as the second substrate, clean and dry them for later use; The active circuit portion of the radio frequency circuit, excluding passive inductors, is fabricated on the upper surface of the silicon wafer using standard semiconductor processes. A first electrical interconnect via is fabricated on the silicon wafer using through-silicon via (TSV) technology. Copper is then used to fill the first electrical interconnect via with copper to form a copper interconnect line, thus obtaining the first electrical interconnect channel region. One end of the copper interconnect line is interconnected with the active circuit region, and the other end of the copper interconnect line is located on the lower surface of the silicon wafer, thereby obtaining the active chip of the radio frequency circuit. The upper copper coil of a three-dimensional spiral inductor is fabricated on the upper surface of a silicon dioxide wafer using standard semiconductor processes. Several through-silicon vias (TSVs) are fabricated on the silicon dioxide wafer using through-silicon via (TSV) technology. Copper is then filled into the TSVs using electroplating to form the upper and lower copper interconnects of the three-dimensional spiral inductor and a second electrical interconnect channel region. The lower copper coil of the three-dimensional spiral inductor is fabricated on the lower surface of the silicon dioxide wafer using standard semiconductor processes. The upper and lower copper coils are interconnected with the upper and lower copper coils through the upper and lower copper interconnects to form the three-dimensional spiral inductor region. One end of the second electrical interconnect channel region is interconnected with the three-dimensional spiral inductor region, and the other end is located on the surface of the silicon dioxide wafer, thereby obtaining a passive core of a three-dimensional spiral inductor. The three-dimensional spiral inductor passive chip and the RF circuit active chip are stacked together in three dimensions. The second electrical interconnect channel region is aligned with the first electrical interconnect channel region. The three-dimensional spiral inductor passive chip and the RF circuit active chip are tightly bonded together using a bumpless bonding process to achieve electrical copper interconnect, thereby obtaining an RF chip with complete functions.