Metal gate and preparation method thereof

Abstract

The invention provides a metal gate and a preparation method thereof, and the preparation method comprises the steps: depositing a first metal material, carrying out the dry etching of the first metal material in a second part of a groove, removing a protrusion, enlarging the size of an opening of the groove, and filling a second metal material to form the metal gate, thereby solving a gap defect in the metal gate, and improving the reliability of the metal gate. According to the invention, the stability of the metal gate can be improved, and the difference of pattern loading (pattern loading effect) can be reduced.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor manufacturing, in particular to a metal gate and a preparation method thereof. BACKGROUND

[0002] With the continuous development of integrated circuit manufacturing technology, the feature size of MOS transistor is also getting smaller and smaller. In the case of continuously reducing the feature size of MOS transistor, in order to reduce the parasitic capacitance of MOS transistor gate and improve the device speed, the gate stack structure of high-K gate dielectric layer and metal gate electrode is introduced into the MOS transistor. In order to avoid the influence of the metal material of the metal gate electrode on other structures of the transistor, the gate stack structure of the metal gate electrode and the high-K gate dielectric layer is usually made by a dummy gate replacement process.

[0003] In the 28nm node, after the dummy gate is removed and the groove is formed, several barrier layers need to be deposited to adjust the threshold voltage, then the metal material is deposited, and finally the metal material is planarized to form the metal gate 1. When the barrier layer is deposited, the deposition rate at the groove opening is faster than that at other positions of the groove due to the easier nucleation at the groove opening, causing the barrier material at the groove opening to protrude, thereby reducing the groove opening size. Thus, when the metal material is deposited, it is easy to leave a gap defect (such as shown in FIG. 1) when the metal material fills the groove. Figure 1 SUMMARY

[0004] The purpose of the present application is to provide a metal gate and a preparation method thereof, which can solve the gap defect in the metal gate.

[0005] In order to solve the above problems, the present application provides a preparation method of a metal gate, comprising the following steps: providing a semiconductor substrate, a dummy gate is formed on the semiconductor substrate, and an interlayer dielectric layer is formed on the semiconductor substrate outside the dummy gate; removing the dummy gate to form a groove, forming a work function layer on the inner wall of the groove, and filling a first metal material in the groove, wherein the groove comprises a first part and a second part which are connected to each other from bottom to top, the work function layer forms a protrusion at the opening of the groove; the first metal material also covers the interlayer dielectric layer, and there is a filling gap in the second part; dry etching the first metal material to expose the second part and also expose the interlayer dielectric layer; depositing a second metal material in the second part, the second metal material also covers the interlayer dielectric layer, and the second metal material is planarized to expose the interlayer dielectric layer, thereby forming a metal gate.​

[0006] Optionally, the depth of the second part is 1 / 3-2 / 3 of the total depth of the groove.

[0007] Optionally, the work function layer comprises a tantalum nitride layer and a titanium aluminum layer, the tantalum nitride layer covers the inner wall of the groove, and the titanium aluminum layer covers the tantalum nitride layer.

[0008] Further, the specific method for dry etching the first metal material is as follows: the first metal material is etched by a physical dry etching process to expose the tantalum nitride layer and remove the protrusion; the first metal material is etched by a chemical dry etching process to expose the second part.

[0009] Further, the process parameters of the physical dry etching process are as follows: the etching gas comprises a mixed gas of HBr and Cl2, the gas flow of HBr is 30-60 sccm, the gas flow of Cl2 is 20-40 sccm, the process voltage is 5-15 mTorr, and the bias power is 100-200 W.

[0010] Further, the process parameters of the chemical dry etching process are as follows: the etching gas comprises a mixed gas of HBr and Cl2, the gas flow of HBr is 60-80 sccm, the gas flow of Cl2 is 10-20 sccm, the process voltage is 20-40 mTorr, and the bias power is 10-50 W.

[0011] Optionally, the specific method for forming the metal gate is as follows: a second metal material is filled in the second part, and the second metal material also covers the interlayer dielectric layer; the surface of the second metal material is planarized by a chemical mechanical polishing process, and the interlayer dielectric layer is exposed.

[0012] Optionally, the material of the first metal material is selected to be the same as the material of the second metal material.

[0013] Further, the material of the first metal material and the material of the second metal material are both aluminum.

[0014] On the other hand, the application also provides a metal gate prepared by the preparation method of the metal gate.

[0015] Compared with the prior art, the application has the following unexpected technical effects: The application provides a metal gate and a preparation method thereof. The preparation method comprises the following steps: providing a semiconductor substrate, a dummy gate is formed on the semiconductor substrate, and an interlayer dielectric layer is formed on the semiconductor substrate outside the dummy gate; removing the dummy gate to form a groove, and forming a work function layer on the inner wall of the groove, while filling a first metal material in the groove, wherein the groove comprises a first part and a second part which are connected to each other from bottom to top, the work function layer is formed with a protrusion at the opening of the groove; the first metal material also covers the interlayer dielectric layer, while there is a filling gap in the second part; dry etching the first metal material to expose the second part, and also expose the interlayer dielectric layer; depositing a second metal material in the second part, the second metal material also covers the interlayer dielectric layer, and performing a planarization treatment on the second metal material to expose the interlayer dielectric layer, so as to form a metal gate. The application solves the gap defect in the metal gate by dry etching the first metal material to remove the protrusion to expand the opening size of the groove, and then filling the second metal material to form the metal gate, so that the stability of the metal gate can be improved, and the difference of pattern loading can be reduced. BRIEF DESCRIPTION OF DRAWINGS

[0016] Figure 1 It is a structural schematic diagram of a metal gate.

[0017] Figure 2 It is a flowchart of a preparation method of a metal gate provided by an embodiment of the application.

[0018] Figure 3 It is a structural schematic diagram of a semiconductor substrate provided by an embodiment of the application.

[0019] Figure 4 It is a structural schematic diagram after forming a work function layer by an embodiment of the application.

[0020] Figure 5 It is a structural schematic diagram after filling a first metal material by an embodiment of the application.

[0021] Figure 6 It is a structural schematic diagram after a dry etching process by an embodiment of the application.

[0022] Figure 7 It is a structural schematic diagram after filling a second metal material by an embodiment of the application.

[0023] Figure 8 It is a structural schematic diagram after forming a metal gate by an embodiment of the application.

[0024] REFERENCE SIGNS: Figure 1middle: Metal gate; a-gap; Figures 3-8 middle: 100 - Substrate; 110 - Dielectric layer; 120 - Interlayer dielectric layer; 130 - Groove; 131 - First portion; 132 - Second portion; 140 - Work function layer; 150 - Metal gate; 151 - First metal material; 152 - Second metal material; b - Fill gap. Detailed Implementation

[0025] The following will provide a more detailed description of a metal gate and its fabrication method according to the present invention. The invention will now be described in more detail with reference to the accompanying drawings, which illustrate preferred embodiments of the invention. It should be understood that those skilled in the art can modify the invention described herein while still achieving its advantageous effects. Therefore, the following description should be understood as being of general knowledge to those skilled in the art and is not intended to limit the invention.

[0026] For clarity, not all features of the actual embodiments are described. In the following description, well-known functions and structures are not detailed in detail, as they would obscure the invention with unnecessary detail. It should be understood that in the development of any actual embodiment, numerous implementation details must be made to achieve the developer's specific objectives, such as changes from one embodiment to another according to limitations related to the system or business. Furthermore, it should be understood that such development work may be complex and time-consuming, but is merely routine work for those skilled in the art.

[0027] To make the objectives and features of the present invention more apparent and understandable, the specific embodiments of the present invention will be further described below with reference to the accompanying drawings. It should be noted that the drawings are all in a very simplified form and use non-precise ratios, and are only used to conveniently and clearly assist in illustrating the objectives of the embodiments of the present invention.

[0028] like Figure 2 As shown, this embodiment provides a method for fabricating a metal gate, including the following steps: Step S1: Provide a semiconductor substrate, on which a dummy gate is formed, and on the semiconductor substrate outside the dummy gate, an interlayer dielectric layer is formed. Step S2: Remove the dummy gate to form a groove, and form a power function layer on the inner wall of the groove, while filling the groove with a first metal material, wherein the groove includes a first part and a second part that are interconnected from bottom to top, and the power function layer has a protrusion at the opening of the groove; the first metal material also covers the interlayer dielectric layer, while there is a filling gap in the second part; Step S3: dry etching the first metal material to expose the second part, while also exposing the interlayer dielectric layer; Step S4: depositing a second metal material in the second part, the second metal material also covering the interlayer dielectric layer, and performing a planarization process on the second metal material to expose the interlayer dielectric layer, thereby forming a metal gate.

[0029] The following will be described in detail Figures 3-8 A method for manufacturing a metal gate according to the embodiment is described in detail.

[0030] As shown in Figure 3 First, step S1 is performed to provide a semiconductor substrate, which has a dummy gate formed thereon, and an interlayer dielectric layer 120 formed on the semiconductor substrate outside the dummy gate.

[0031] This step specifically includes: First, a semiconductor substrate is provided, which includes a substrate 100 and a dielectric layer 110. The substrate 100 can be a single crystal silicon substrate or a silicon-on-insulator. Regions where MOS transistors are formed are defined on the substrate 100, and the MOS transistor regions are insulated by shallow trench isolation (STI).

[0032] Next, a dielectric layer 110 is formed on the surface of the substrate 100. The dielectric layer 110 includes a gate oxide layer and a high-k dielectric layer. The material of the gate oxide layer can be silicon oxide. The high-k dielectric layer can be formed by a deposition method with good step coverage, such as chemical vapor deposition or atomic layer deposition. The high-k dielectric layer 110 can include HfO2, HfSiO, HfON, La2O3, LaAlO, Al2O3, ZrO2, ZrSiO, TiO2, or Y2O3. The high-k dielectric layer 110 can improve the electrical properties of the dielectric layer 110.

[0033] Next, a dummy gate is formed on the dielectric layer 110, and an insulating sidewall is formed on the side surface of the dummy gate. The material of the dummy gate is polysilicon, and the material of the insulating sidewall can be silicon oxide, silicon nitride, or a composite structure thereof, which can be formed by a conventional sidewall process.

[0034] Next, ion implantation is performed in the substrate 100 on both sides of the dummy gate to form source and drain electrodes. Different ion implantation processes of different doping types are performed in the corresponding regions according to the type of MOS transistor. Specifically, a photoresist mask is first made to define the source and drain regions, and then N-type ion implantation is performed on both sides of the dummy gate to form the source and drain electrodes of an NMOS transistor. The above steps are repeated to perform P-type ion implantation to form the source and drain electrodes of a PMOS transistor.

[0035] Then, a dielectric layer 120 is deposited on the surface of the semiconductor substrate (specifically, on the dielectric layer 110), and then the surface of the dielectric layer 120 is planarized to thin the thickness thereof until the dummy gate is exposed. The dielectric layer 120 is made of silicon oxide or silicon nitride, and the dielectric layer 120 is thinned by chemical mechanical polishing.

[0036] Please refer to Figures 3-5 , and then step S2 is performed to remove the dummy gate to form a recess 130, form a work function layer 140 on the inner wall of the recess 130, and fill a first metal material 151 in the recess 130. The recess 130 includes a first portion 131 and a second portion 132 which are connected to each other from bottom to top, the work function layer 140 forms a protrusion at the opening of the recess 130, and the first metal material 151 also covers the dielectric layer 120 while there is a filling gap b in the second portion 132.

[0037] This step specifically includes: As shown in Figure 3 , first, the dummy gate is removed to form a recess 130. Specifically, since the material of the dummy gate in this embodiment is single silicon, and the material of the dielectric layer 120 is silicon oxide or silicon nitride, the dielectric layer 120 can be directly used as a hard mask to remove the dummy gate by selective dry etching until the dielectric layer 110 is exposed, thereby forming the recess 130. The recess 130 includes a first portion 131 and a second portion 132 which are connected to each other from bottom to top, and the depth of the second portion 132 is 1 / 3 to 2 / 3 of the total depth of the recess 130.

[0038] As shown in Figure 4 , then, a work function layer 140 is formed on the inner wall of the recess 130 by a deposition process. The work function layer 140 is a stack of multiple film layers, for example, including a tantalum nitride layer and a titanium aluminum layer. The tantalum nitride layer covers the inner wall of the recess 130, and the titanium aluminum layer covers the tantalum nitride layer.

[0039] Since the process technology node is continuously reduced, for example, reduced to 32 nm, 28 nm, and below 22 nm, the critical dimension (CD) of the recess 130 is continuously reduced. In addition, before the metal gate 150 is filled, the stack of the work function layer 140 is deposited in the recess 130, which further reduces the width of the recess 130 in the filled area of the metal gate 150. In particular, at the opening of the recess 130, the accumulation of the work function layer 140 forms a protrusion.

[0040] As shown in Figure 5As shown, then, the first metal material 151 is filled in the recess 130, the first metal material 151 covers the interlayer dielectric layer 120, and a filling gap b exists in the second part 132 of the recess 130. The material of the first metal material 151 is selected as aluminum.

[0041] Due to the further narrowing of the width of the recess 130, especially at the opening of the recess 130, the accumulation of the work function layer 140 forms a protrusion. Therefore, a filling gap b is formed in the second part 132 of the recess 130, which will affect the device performance and even make the device fail.

[0042] As shown, then, step S3 is performed, the first metal material 151 is dry etched to expose the second part 132, and the interlayer dielectric layer 120 is also exposed. Figure 6

[0043] This step specifically includes: First, the first metal material 151 is etched by a physical dry etching process to expose the work function layer 140 on the interlayer dielectric layer 120, and the titanium aluminum layer in the work function layer 140 is further etched by a physical dry etching process to expose the tantalum nitride layer, while removing the protruding part of the work function layer 140 at the opening of the recess 130 to expand the opening size of the recess 130 which is narrowed due to the deposition of the work function layer 140.

[0044] The process parameters of the physical dry etching process include: the etching gas includes but is not limited to a mixed gas of HBr and Cl2, wherein the gas flow of HBr is 30 sccm ~ 60 sccm, the gas flow of Cl2 is 20 sccm ~ 40 sccm, the process voltage is 5 mTorr ~ 15 mTorr, and the bias power is 100 W ~ 200 W.

[0045] Then, the first metal material 151 layer is etched by a chemical dry etching process to expose the second part 132 of the recess 130. In detail, the first metal material 151 in the second part 132 of the recess 130 is removed by isotropic etching of the chemical dry etching process, and the tantalum nitride layer on the interlayer dielectric layer 120 is also removed to expose the interlayer dielectric layer 120. Since the filling gap b is located in the second part 132 of the recess 130, this step ensures the complete removal of the filling gap b.

[0046] ​The process parameters of the chemical dry etching process are: the etching gas includes but is not limited to a mixed gas of HBr and Cl2, wherein the gas flow of HBr is 60-80 sccm, the gas flow of Cl2 is 10-20 sccm, the process voltage is 20-40 mTorr, and the bias power is 10-50 W.

[0047] The physical dry etching and chemical dry etching in this step are combined by using different ratios of HBr+Cl2 and different bias combinations to prevent the work function layer 140 from being excessively consumed at the sidewall of the groove 130. Meanwhile, the physical dry etching and chemical dry etching in this step have high etching selectivity to the material (such as silicon nitride and silicon oxide) of the interlayer dielectric layer 120, so that the interlayer dielectric layer 120 and the insulating sidewall are not damaged during the dry etching process, and thus the height of the metal gate 150 formed subsequently is not lost.

[0048] Please refer to Figures 7-8 , then step S4 is performed to deposit a second metal material 152 in the second part 132, the second metal material 152 also covers the interlayer dielectric layer 120, and the second metal material 152 is planarized to expose the interlayer dielectric layer 120, thereby forming a metal gate 150.

[0049] This step specifically includes: As shown in Figure 7 , first, the second metal material 152 is filled in the second part 132, and the second metal material 152 also covers the interlayer dielectric layer 120. At this time, since the opening of the groove 130 is opened, there is no filling gap b in the groove 130 after the second metal material filling.

[0050] As shown in Figure 8 , the surface of the second metal material 152 is planarized by a chemical mechanical polishing process to thin the second metal material 152, and the interlayer dielectric layer 120 is also exposed. At this time, only the metal material is retained in the groove 130, that is, the first part 131 retains the first metal material 151, the second part 132 retains the second metal material 152, and the first metal material 151 and the second metal material 152 in the groove 130 jointly form the metal gate 150.

[0051] The material of the first metal material 151 and the material of the second metal material 152 are both aluminum.

[0052] The embodiment also provides a metal gate 150 prepared by the above process.

[0053] In conclusion, the present application provides a metal gate and a preparation method thereof. The preparation method comprises the following steps: providing a semiconductor substrate, a dummy gate is formed on the semiconductor substrate, and an interlayer dielectric layer is formed on the semiconductor substrate outside the dummy gate; removing the dummy gate to form a groove, and forming a work function layer on the inner wall of the groove, and filling a first metal material in the groove, wherein the groove comprises a first part and a second part which are connected to each other from bottom to top, and the work function layer is provided with a protrusion at the opening of the groove; the first metal material also covers the interlayer dielectric layer, and there is a filling gap in the second part; dry etching the first metal material to expose the second part and also expose the interlayer dielectric layer; depositing a second metal material in the second part, the second metal material also covers the interlayer dielectric layer, and performing a planarization treatment on the second metal material to expose the interlayer dielectric layer, thereby forming a metal gate. The present application expands the opening size of the groove by dry etching the first metal material to remove the protrusion, and then forms a metal gate by filling a second metal material, thereby solving the gap defect in the metal gate, increasing the stability of the metal gate, and reducing the difference in pattern loading effect.

[0054] In addition, it should be noted that, unless specifically described or indicated, the terms "first", "second" in the description are only used to distinguish the components, elements, steps, etc. in the description, and do not represent the logical relationship or sequence relationship between the components, elements, steps, etc.

[0055] It can be understood that, although the present application has been disclosed as above with preferred embodiments, the above embodiments are not intended to limit the present application. For any person skilled in the art, many possible changes and modifications, or equivalent embodiments of the above disclosed technical content can be made to the technical solution of the present application without departing from the scope of the technical solution of the present application. Therefore, any simple modification, equivalent change and modification of the above embodiments made according to the technical essence of the present application, without departing from the content of the technical solution of the present application, all still belong to the scope of protection of the technical solution of the present application.

Claims

1. A method of manufacturing a metal gate, characterized by, The method comprises the following steps: providing a semiconductor substrate, a dummy gate is formed on the semiconductor substrate, and an interlayer dielectric layer is formed on the semiconductor substrate outside the dummy gate; removing the dummy gate to form a groove, and forming a work function layer on the inner wall of the groove, while filling a first metal material in the groove, wherein the groove comprises a first part and a second part which are connected to each other from bottom to top, the work function layer is formed with a protrusion at the opening of the groove; the first metal material also covers the interlayer dielectric layer, while there is a filling gap in the second part; dry etching the first metal material to expose the second part, and also expose the interlayer dielectric layer; depositing a second metal material in the second part, the second metal material also covers the interlayer dielectric layer, and performing a planarization treatment on the second metal material to expose the interlayer dielectric layer, thereby forming a metal gate.

2. The method of manufacturing a metal gate according to claim 1, wherein The depth of the second part is 1 / 3-2 / 3 of the total depth of the groove.

3. The method of claim 1, wherein the metal gate is formed by: The work function layer comprises a tantalum nitride layer and a titanium aluminum layer, the tantalum nitride covers the inner wall of the groove, and the titanium aluminum layer covers the tantalum nitride layer.

4. The method of claim 3, wherein the metal gate is formed by: The specific method of dry etching the first metal material is: etching the first metal material by a physical dry etching process to expose the tantalum nitride layer, while removing the protrusion; etching the first metal material by a chemical dry etching process to expose the second part.

5. The method of claim 4, wherein the metal gate is formed by: The process parameters of the physical dry etching process are: the etching gas comprises a mixed gas of HBr and Cl2, wherein the gas flow of HBr is 30 sccm-60 sccm, the gas flow of Cl2 is 20 sccm-40 sccm, the process voltage is 5 mTorr-15 mTorr, and the bias power is 100 W-200 W.

6. The method of claim 4, wherein the metal gate is formed by: The process parameters of the chemical dry etching process are: the etching gas comprises a mixed gas of HBr and Cl2, wherein the gas flow of HBr is 60 sccm-80 sccm, the gas flow of Cl2 is 10 sccm-20 sccm, the process voltage is 20 mTorr-40 mTorr, and the bias power is 10 W-50 W.

7. The method of claim 1, wherein the metal gate is formed by: The specific method of forming the metal gate is: filling a second metal material in the second part, the second metal material also covers the interlayer dielectric layer; performing a planarization treatment on the surface of the second metal material by a chemical mechanical polishing process, and exposing the interlayer dielectric layer.

8. The method of claim 1, wherein the metal gate is formed by: The material selection of the first metal material is the same as that of the second metal material.

9. The method of claim 8, wherein the metal gate is formed by: The material selection of the first metal material and the second metal material is aluminum.

10. A metal gate, characterized by, The metal gate is prepared by the preparation method of any one of claims 1-9.

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