Chip testing method based on ATE platform

Abstract

The invention provides a chip testing method based on an ATE platform, and relates to the technical field of chip manufacturing and testing. According to the method, multiple advanced test technologies and intelligent algorithms are creatively integrated, test environment parameters are accurately controlled through an intelligent environment regulation and control system, radio frequency and digital signals are efficiently processed in cooperation with a test engine, a test execution stream optimizes a high-speed interface test by using a chip built-in Loopback function and an adaptive algorithm, and the test efficiency is improved. The intelligent control and analysis system dynamically adjusts a test process and accurately predicts chip defects based on a federal learning framework, and realizes Chiplet interconnection verification and closed-loop data analysis feedback optimization of a test program at the same time. The chip testing efficiency and precision are effectively improved, the testing cost is reduced, dependence on expensive equipment is reduced, the method can be widely applied to various chip testing scenes, and remarkable economic benefits and technical advantages are brought to chip manufacturing enterprises.

Description

Technical Field

[0001] This invention relates to the field of chip manufacturing and testing technology, specifically to a chip testing method based on the ATE platform. Background Technology

[0002] In the field of chip manufacturing and testing, chip testing equipment and technology are crucial for ensuring product quality and performance. With the rapid development of chip technology, chip integration is increasing, functions are becoming more complex, and testing difficulty is growing exponentially. Traditional chip testing methods mainly rely on large-scale automated test equipment (ATE), which performs functional and performance tests on chips through complex hardware connections and pre-set test programs. However, with the emergence of high-speed interface chips (such as 56Gbps SerDes and above) and advanced packaging technologies (such as 3D packaging, Chiplet, etc.), chip testing faces a triple challenge: efficiency bottlenecks, soaring costs, and insufficient coverage. Specifically:

[0003] 1. Low testing efficiency: Traditional ATE platforms use a serial testing process. Bit error rate (BER) testing of high-speed SerDes interfaces (such as 112GPAM4) requires millions of samples, and the single-chip testing time is more than 120 seconds. Advanced packaging (Chiplet / 3D IC) requires step-by-step die testing and interconnect verification, which increases the test cycle by 50%-80%.

[0004] 2. High testing costs: RF testing relies on high-end vector signal analyzers (unit price > $500,000), and multiple devices are required to work together for multiple frequency bands such as 5G / millimeter wave. System-level testing (SLT) accounts for 30% of the total chip cost, but the fault detection rate is less than 60%.

[0005] 3. Defect coverage blind spots: Existing methods cannot capture transient power supply faults at the nanosecond level (such as short circuit events with dV / dt>1V / ns), resulting in a missed detection rate of power supply-related defects >15%. Timing margin testing of Chiplet interconnects relies on indirect calculations with errors as high as ±0.5UI, which poses a risk of system-level failure.

[0006] Existing technologies attempt to improve chip testing through parallel test optimization, machine learning assistance, and built-in self-test. However, while parallel test optimization increases throughput, it does not solve the data bandwidth bottleneck (e.g., raw RF data > 10Gbps) and has poor multi-site synchronization accuracy. When using machine learning assistance, traditional centralized models need to upload sensitive test data, which violates the wafer fab's data isolation policy and is difficult to implement. Built-in self-test (BIST) increases chip area by 5%-10% and cannot cover cross-die signal integrity verification. Summary of the Invention

[0007] (a) Technical problems to be solved

[0008] To address the shortcomings of existing technologies, this invention provides a chip testing method based on the ATE platform, which solves the problems mentioned in the background.

[0009] (II) Technical Solution

[0010] To achieve the above objectives, the present invention provides the following technical solution: a chip testing method based on an ATE platform, comprising the following steps:

[0011] Step 1, Intelligent Environmental Control: By monitoring the chip's dynamic power consumption peak in real time, the temperature control unit and electromagnetic shielding strength are controlled to ensure that the fluctuation range of environmental parameters is ≤±0.5℃ / ±2%RH, eliminating the impact of temperature / humidity drift on high-speed interface testing, increasing the eye diagram jitter tolerance of 56Gbps SerDes testing by 40%, and reducing the bit error rate to below 1E-12.

[0012] Step 2, Collaborative Test Engine Construction: Integrate the FPGA test module, develop programmable signal processing algorithms through hardware description language, link with the RF test module, realize digital down-conversion of RF signals within the FPGA, compress the original data bandwidth by more than 90%, break through the ATE data transmission bottleneck, shorten the 5GNREVM test time from 15ms to 5ms, and increase the throughput by 200%.

[0013] Step 3, Test Execution Flow: High-speed digital interface testing utilizes the chip's built-in Loopback function to verify the SerDes link and employs an adaptive algorithm to optimize test parameters. Chiplet interconnect verification simulates the UCIe protocol through the ATE digital channel, performing parallel testing of cross-die signal integrity. SerDes link calibration and Chiplet interconnect testing are completed in a single run, reducing the test cycle of advanced packaged chips by 50%, achieving UCIe protocol simulation accuracy of ±0.1UI, and improving bit error detection sensitivity by 10 times.

[0014] Step 4, Intelligent Control and Analysis: Adaptive test flow control aggregates historical data based on a federated learning framework to train a defect prediction model, dynamically skips redundant test items, and uses ns-level timestamp logs to build a power supply transient response model, which is fed back to the test program generation module in real time, reducing the number of test items for low-risk chips by 40% and reducing the overall test cost by 35%; the speed of power supply fault location is reduced from hours to minutes, and the analysis efficiency is improved by 5 times.

[0015] Step 5, Chiplet Interconnect Verification: Simulate the UCIe protocol through the ATE digital channel and test the eye diagram opening and jitter tolerance of the cross-die signal in the 3D packaged chip in parallel.

[0016] Step 6: Closed-loop data analysis: Using the ns-level timestamp logs provided by the ATE platform, construct a correlation model between the chip power supply transient response and faults, and feed it back to the test program generation module in real time.

[0017] Preferably, the FPGA signal processing algorithm in step two includes using the CORDIC algorithm to implement quadrature demodulation within the FPGA, reducing the RF error vector amplitude measurement delay to below 10μs; and achieving 16-bit resolution at a sampling rate of 200MS / s through time-interleaved sampling technology.

[0018] Preferably, the defect prediction model in step four includes an input layer and an output layer. The input layer consists of wafer coordinates, neighborhood chip parameter distribution, and power supply transient response characteristics. The output layer consists of chip failure probability and defect type classification with a classification accuracy of ≥95%. Redundant items skipped in dynamic testing include low-risk power supply test items and interconnection test items where adjacent chips pass all tests.

[0019] Preferably, the Chiplet interconnect verification in step five specifically includes injecting pseudo-random jitter on the ATE digital channel, measuring the bit error rate at the receiver to be ≤1E-12, and simulating a timing offset of 0.1UI steps using a phase interpolator to verify a timing margin >0.3UI.

[0020] Preferably, the power transient response model construction method in step six is ​​to extract the dV / dt>1V / ns event during the dynamic power consumption switching process as the key feature; and to use the isolated forest algorithm to identify abnormal power consumption transients and locate potential short-circuit defects.

[0021] Preferably, the RF test module integrates a software-defined radio unit, supports RF front-end reconfiguration, and has a frequency range of 400MHz to 40GHz; the modulation scheme is QAM256 / 1024 or OFDM802.11ax; and the automatic calibration error is ≤0.1dB.

[0022] Preferably, in step three, the high-speed digital interface test uses a PLL phase offset compensation algorithm to calibrate the Loopback path delay, achieving a measurement accuracy of <0.5ps; the BER convergence point is predicted by an LSTM model, and sampling is terminated when the confidence level is >99%, reducing the number of samplings to 20% of the traditional method.

[0023] Preferably, in step six, the test program generation step includes: parsing the scan chain structure in the chip design specification; automatically inserting boundary scan test vectors with a fault coverage rate ≥99.5%.

[0024] (III) Beneficial Effects

[0025] This invention provides a chip testing method based on an ATE platform, which has the following advantages:

[0026] 1. The chip testing method based on the ATE platform of this invention significantly improves testing efficiency and reduces costs. By utilizing the chip's built-in Loopback function and combining statistical models and machine learning algorithms to optimize the sampling process, the reliance on expensive high-speed instruments and complex fixtures is reduced, resulting in a 30%-40% reduction in single-chip testing costs, a significant reduction in testing time, and an efficiency increase of over 50%.

[0027] 2. This method improves testing accuracy and the ability to detect system-level problems. The intelligent environmental control system ensures a stable testing environment, while advanced algorithms in the collaborative testing engine improve the accuracy of RF signal processing. Deep integration of SLT elements into the ATE (Automatic Test Equipment) enables real-world application scenario testing, allowing for early detection of system-level interaction problems and reducing later failure risks and repair costs. Compared to traditional methods, this method increases the number of system-level problems detected in advance by 60%-70%. Attached Figure Description

[0028] Figure 1 This is a schematic diagram of the process of the present invention. Detailed Implementation

[0029] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0030] Example:

[0031] like Figure 1 As shown, this embodiment of the invention provides a chip testing method based on an ATE platform, including the following steps:

[0032] Step 1, Intelligent Environmental Control: By monitoring the chip's dynamic power consumption peak in real time, the temperature control unit and electromagnetic shielding strength are controlled to ensure that the fluctuation range of environmental parameters is ≤±0.5℃ / ±2%RH, eliminating the impact of temperature / humidity drift on high-speed interface testing, increasing the eye diagram jitter tolerance of 56Gbps SerDes testing by 40%, and reducing the bit error rate to below 1E-12.

[0033] Step 2, Collaborative Test Engine Construction: Integrate the FPGA test module, develop programmable signal processing algorithms through hardware description language, link with the RF test module, realize digital down-conversion of RF signals within the FPGA, compress the original data bandwidth by more than 90%, break through the ATE data transmission bottleneck, shorten the 5GNREVM test time from 15ms to 5ms, and increase the throughput by 200%.

[0034] Step 3, Test Execution Flow: High-speed digital interface testing utilizes the chip's built-in Loopback function to verify the SerDes link and employs an adaptive algorithm to optimize test parameters. Chiplet interconnect verification simulates the UCIe protocol through the ATE digital channel, performing parallel testing of cross-die signal integrity. SerDes link calibration and Chiplet interconnect testing are completed in a single run, reducing the test cycle of advanced packaged chips by 50%, achieving UCIe protocol simulation accuracy of ±0.1UI, and improving bit error detection sensitivity by 10 times.

[0035] Step 4, Intelligent Control and Analysis: Adaptive test flow control aggregates historical data based on a federated learning framework to train a defect prediction model, dynamically skips redundant test items, and uses ns-level timestamp logs to build a power supply transient response model, which is fed back to the test program generation module in real time, reducing the number of test items for low-risk chips by 40% and reducing the overall test cost by 35%; the speed of power supply fault location is reduced from hours to minutes, and the analysis efficiency is improved by 5 times.

[0036] Step 5, Chiplet Interconnect Verification: Simulate the UCIe protocol through the ATE digital channel and test the eye diagram opening and jitter tolerance of the cross-die signal in the 3D packaged chip in parallel.

[0037] Step 6: Closed-loop data analysis: Using the ns-level timestamp logs provided by the ATE platform, construct a correlation model between the chip power supply transient response and faults, and feed it back to the test program generation module in real time.

[0038] Implementing the above steps requires at least an intelligent environmental control system, a collaborative testing engine, a test execution flow system, an intelligent control and analysis system, a Chiplet interconnect verification system, and a closed-loop data analysis system.

[0039] The intelligent environment control system is the foundation of the entire chip testing methodology. Its main function is to ensure the accuracy and reliability of chip testing through precise control of the testing environment. This system consists of the following key components:

[0040] Real-time monitoring module: Employs high-precision temperature and humidity sensors to monitor the chip's dynamic power consumption peaks during testing. These sensors achieve accuracies of ±0.1℃ and ±1%RH, enabling them to detect minute changes in environmental parameters.

[0041] Temperature control unit: Based on data feedback from the real-time monitoring module, the temperature control unit precisely adjusts the temperature of the test environment using a PID control algorithm. This unit employs semiconductor cooling and heating technology to ensure that temperature fluctuations are controlled within ±0.5℃.

[0042] Electromagnetic shielding unit: Composed of multiple layers of electromagnetic shielding material, it can effectively shield external electromagnetic interference. At the same time, it ensures the stability of the electromagnetic environment by intelligently adjusting the electromagnetic shielding strength, with the fluctuation range controlled within ±2%RH.

[0043] In actual testing, the system can significantly eliminate the impact of temperature and humidity drift on high-speed interface testing. For example, in the 56Gbps SerDes test, the eye diagram jitter tolerance is improved by 40%, and the bit error rate is reduced to below 1E-12, thus providing a stable environmental foundation for subsequent chip testing.

[0044] The collaborative test engine is the core component of chip testing methodologies, responsible for integrating various test functions and achieving efficient signal processing. This engine primarily consists of an FPGA test module and an RF test module.

[0045] FPGA Test Module: Programmable signal processing algorithms are developed using advanced hardware description languages ​​(such as Verilog or VHDL). Specifically, quadrature demodulation is implemented within the FPGA using the CORDIC algorithm, reducing the RF error vector amplitude (EVM) measurement delay to below 10μs. Furthermore, time-interleaved sampling technology is utilized to achieve 16-bit resolution at a sampling rate of 200MS / s, effectively improving the accuracy and efficiency of signal processing.

[0046] RF Test Module: Integrates a software-defined radio (SDR) unit, supporting a frequency range from 400MHz to 40GHz and compatible with various modulation standards such as QAM256 / 1024 and OFDM802.11 ax. This module features automatic calibration with an error control within ±0.1dB.

[0047] In collaborative working mode, the FPGA test module and the RF test module work closely together, compressing the original data bandwidth by more than 90% through digital down-conversion of the RF signal within the FPGA. This innovation breaks through the data transmission bottleneck of traditional ATE platforms. For example, in 5GNREVM testing, the test time is reduced from 15ms to 5ms, and the throughput is increased by 200%, significantly improving test efficiency.

[0048] The test execution flow system is responsible for efficiently executing various chip test tasks, including high-speed digital interface testing and chiplet interconnect verification.

[0049] High-speed digital interface testing: The SerDes link is verified using the chip's built-in Loopback function. Loopback path delay is calibrated using a PLL phase offset compensation algorithm, achieving a measurement accuracy of ±0.5 ps. The bit error rate (BER) convergence point is predicted using an LSTM model, and sampling is automatically terminated when the confidence level exceeds 99%, reducing the number of samples to 20% of traditional methods and significantly shortening the testing time.

[0050] Chiplet interconnect verification: The UCIe protocol is simulated through the ATE digital channel to test the integrity and reliability of signals across dies in parallel. Specific methods include injecting pseudo-random jitter into the ATE digital channel, measuring the bit error rate at the receiver, and simulating a 0.1UI step timing offset using a phase interpolator to verify timing margin.

[0051] Through parallel testing and intelligent algorithm optimization, this system can complete SerDes link calibration and Chiplet interconnect testing in a single test, reducing the testing cycle of advanced packaged chips by 50%. Simultaneously, the UCIe protocol simulation accuracy reaches ±0.1 UI, and the error detection sensitivity is improved tenfold, effectively enhancing the accuracy and efficiency of testing.

[0052] Intelligent control and analysis systems are the intelligent core of chip testing methods, primarily used to optimize testing processes and analyze test data, including:

[0053] Adaptive test flow control: Based on a federated learning framework, historical test data is aggregated to train a defect prediction model. The input layer of this model includes wafer coordinates, neighborhood chip parameter distribution, and power supply transient response characteristics. The output layer provides chip failure probability and defect type classification, achieving a classification accuracy of over 95%. Redundant testing is reduced by dynamically skipping low-risk power supply test items and interconnection test items where adjacent chips pass all tests.

[0054] Closed-loop data analysis: Utilizing the ns-level timestamp logs provided by the ATE platform, a correlation model between chip power supply transient response and faults is constructed. By extracting dV / dt>1V / ns events during dynamic power switching as key features, the isolated forest algorithm is employed to identify abnormal power consumption transients and accurately locate potential short-circuit defects.

[0055] In practical applications, this system can reduce the number of test items for low-risk chips by 40% and lower the overall testing cost by 35%. At the same time, the speed of power supply fault location is reduced from hours to minutes, and the analysis efficiency is improved by 5 times, significantly improving the economy of testing and fault diagnosis capabilities.

[0056] The Chiplet interconnect verification system focuses on integrity testing of signals across dies in 3D packaged chips, including:

[0057] Pseudo-random jitter injection module: Injects pseudo-random jitter into the ATE digital channel to simulate signal interference in the actual working environment;

[0058] Eye Diagram Opening and Jitter Tolerance Measurement Module: Using a high-precision signal analyzer, the module measures the eye diagram opening and jitter tolerance at the receiving end to ensure reliable transmission of signals across dies.

[0059] This system can effectively verify the eye diagram opening and jitter tolerance of signals across dies in 3D packaged chips through parallel testing and precise measurement, ensuring the signal integrity and reliability of chiplet interconnects.

[0060] The closed-loop data analysis system is a feedback optimization module for chip testing methods. It is primarily used to construct power supply transient response models and feed them back to the test program generation module in real time. It mainly includes:

[0061] Power transient response feature extraction module: Extracts key features during dynamic power consumption switching process;

[0062] Abnormal power consumption transient identification module: It uses the isolated forest algorithm to identify abnormal power consumption transients and accurately locate potential short-circuit defects;

[0063] Test program optimization module: Feeds back the analysis results to the test program generation module in real time to dynamically adjust the test process.

[0064] During testing, the system constructs a correlation model between the chip's power supply transient response and faults, enabling real-time optimization of the test program. For example, the speed of power supply fault location has been reduced from hours to minutes, and the analysis efficiency has been improved by 5 times, significantly enhancing the accuracy and efficiency of the test.

[0065] Although embodiments of the invention have been shown and described, it will be understood by those skilled in the art that various changes, modifications, substitutions and alterations can be made to these embodiments without departing from the principles and spirit of the invention, the scope of which is defined by the appended claims and their equivalents.

Claims

1. A chip testing method based on an ATE platform, characterized in that, Includes the following steps: Step 1, Intelligent Environmental Control: By monitoring the chip's dynamic power consumption peak in real time, the temperature control unit and electromagnetic shielding strength are controlled to ensure that the fluctuation range of environmental parameters is ≤ ±0.5℃ / ±2%RH; Step 2, Collaborative Test Engine Construction: Integrate the FPGA test module, develop programmable signal processing algorithms through hardware description language, link with the RF test module, and realize digital down-conversion of RF signals within the FPGA to compress the original data bandwidth by more than 90%; Step 3, Test Execution Flow: High-speed digital interface testing utilizes the chip's built-in Loopback function to verify the SerDes link and employs an adaptive algorithm to optimize test parameters. Chiplet interconnect verification simulates the UCIe protocol through the ATE digital channel, and parallel testing of cross-die signal integrity is performed. Step 4, Intelligent Control and Analysis: Adaptive test flow control uses a federated learning framework to aggregate historical data to train a defect prediction model, dynamically skips redundant test items, and uses ns-level timestamp logs to build a power supply transient response model, which is fed back to the test program generation module in real time. Step 5, Chiplet Interconnect Verification: Simulate the UCIe protocol through the ATE digital channel and test the eye diagram opening and jitter tolerance of the cross-die signal in the 3D packaged chip in parallel. Step 6: Closed-loop data analysis: Using the ns-level timestamp logs provided by the ATE platform, construct a correlation model between the chip power supply transient response and faults, and feed it back to the test program generation module in real time.

2. The chip testing method based on the ATE platform according to claim 1, characterized in that: The FPGA signal processing algorithm described in step two includes using the CORDIC algorithm to implement quadrature demodulation within the FPGA, reducing the RF error vector amplitude measurement delay to below 10μs; and achieving 16-bit resolution at a sampling rate of 200MS / s through time-interleaved sampling technology.

3. The chip testing method based on the ATE platform according to claim 1, characterized in that: The defect prediction model described in step four includes an input layer and an output layer. The input layer consists of wafer coordinates, neighborhood chip parameter distribution, and power supply transient response characteristics. The output layer classifies chip failure probability and defect type with a classification accuracy of ≥95%; redundant items skipped by dynamic testing include low-risk power supply test items and interconnection test items that pass all adjacent chips.

4. The chip testing method based on the ATE platform according to claim 1, characterized in that: The Chiplet interconnect verification described in step five specifically includes injecting pseudo-random jitter into the ATE digital channel, measuring the bit error rate at the receiver to be ≤1E-12, and simulating a timing offset of 0.1UI steps using a phase interpolator to verify a timing margin >0.3UI.

5. The chip testing method based on the ATE platform according to claim 1, characterized in that: The power transient response model construction method described in step six is ​​to extract the dV / dt>1V / ns event during the dynamic power consumption switching process as the key feature; and to use the isolated forest algorithm to identify abnormal power consumption transients and locate potential short-circuit defects.

6. The chip testing method based on the ATE platform according to claim 1, characterized in that: The radio frequency test module integrates a software-defined radio unit, and supports frequency range of 400MHz to 40GHz through reconfiguration of the radio frequency front end; the modulation system is QAM256 / 1024, OFDM802.11ax; the automatic calibration error is ≤0.1dB.

7. The chip testing method based on the ATE platform according to claim 1, characterized in that: In step three, the high-speed digital interface test uses the PLL phase offset compensation algorithm to calibrate the Loopback path delay, achieving a measurement accuracy of <0.5ps; the BER convergence point is predicted by the LSTM model, and sampling is terminated when the confidence level is >99%, reducing the number of samplings to 20% of the traditional method.

8. The chip testing method based on the ATE platform according to claim 1, characterized in that: In step six, the test program generation step includes: parsing the scan chain structure in the chip design specification; automatically inserting boundary scan test vectors with a fault coverage rate of ≥99.5%.

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