Design method based on multi-stage FPGA (Field Programmable Gate Array) communication of test machine

Abstract

The invention relates to the technical field of FPGA (Field Programmable Gate Array) communication, and particularly discloses a design method based on multi-stage FPGA communication of a test machine, which comprises the following steps of: setting board card areas, and respectively setting a back board and a mother board in each board card area; each board card area is provided with a preset number of digital board cards and power supply board cards matched with the digital board cards; all board card areas are divided into two continuous areas, and the two continuous areas are respectively defined as a main area and a slave area; the general input / output interface on the host / slave is connected to the intermediate adapter plate through the backboard, then is connected to the mother board through the intermediate adapter plate, then is connected to the interface board card of the calibration board card through a cable, and finally reaches the main field programmable gate array of the calibration board card.

Description

Technical Field

[0001] This invention relates to the field of FPGA communication technology, and more specifically to a design method for multi-level FPGA communication based on a test machine. Background Technology

[0002] With the development of testing equipment and the continuous improvement of instrument precision, stringent requirements have been placed on the synchronization of multi-channel digital signals. Specifically, this means ensuring that multiple channels of digital signals are accurately applied to the device under test (DUT) at the same time to guarantee the accuracy and reliability of test results. To achieve this goal, the industry commonly uses calibration boards to perform AC calibration on digital signals. This automatic calibration mechanism eliminates signal differences between multiple channels, thereby meeting the technical requirement of synchronous application.

[0003] However, existing calibration board designs based on Field-Programmable Gate Arrays (FPGAs) as control chips face a significant conflict between hardware resources and design specifications. Specifically, the input / output (I / O) port resources of existing FPGA control chips are already saturated, making it impossible to allocate additional I / O ports for calibration functions, thus hindering the integration of calibration designs into existing hardware architectures. To address this issue, the two existing conventional solutions both have significant drawbacks and fail to meet practical application requirements: Firstly, replace the FPGA control chip with one that has more I / O ports. While this solution can fundamentally solve the problem of insufficient I / O ports, it will significantly increase the cost of component procurement. Furthermore, it requires a complete redesign of the printed circuit board (PCB) layout and routing based on the new chip, which not only consumes a lot of manpower but also extends the product development cycle, resulting in high time and economic costs.

[0004] Secondly, the calibration and testing functions are compiled into two separate firmware versions, and firmware is flashed separately during the calibration and testing phases of the device. While this approach avoids I / O port resource limitations, it directly violates the company's internal design specification of "single firmware version control and unified flashing process"—the parallel existence of multiple firmware versions significantly increases the complexity of version management, and problems such as incorrect or missed firmware flashing are prone to occur during the switching flashing process at different stages, significantly increasing the debugging risk before the device leaves the factory and the difficulty of subsequent maintenance. Summary of the Invention

[0005] The purpose of this invention is to provide a design method based on multi-level FPGA communication in a test machine to solve the above-mentioned technical problems: The objective of this invention can be achieved through the following technical solutions: A design method based on multi-level FPGA communication of a test machine includes the following steps: Define the board area, and set up a backplane and a motherboard for each board area; Each board area is configured with a preset number of digital boards and their matching power boards, wherein the signals of the digital boards are respectively plugged into the backplane and motherboard of the corresponding board area. All board areas are divided into two consecutive areas, which are defined as the master area and the slave area respectively. The board areas in the master area share a synchronization board with a CPU for synchronization, and the synchronization board is defined as the master. The board areas in the slave area share a synchronization board with a CPU for synchronization, and the synchronization board is defined as the slave. The general-purpose input / output interfaces on the host / slave are first connected to the intermediate adapter board via the backplane, then connected to the motherboard via the intermediate adapter board, and then connected to the interface board of the calibration board via cables, finally reaching the main field-programmable gate array of the calibration board.

[0006] As a further aspect of the present invention: the main field-programmable gate array of the calibration board communicates with 16 calibration field-programmable gate arrays, each calibration field-programmable gate array can calibrate the digital signals of 2 digital boards, and each digital board corresponds to 640 channels.

[0007] As a further aspect of the present invention: the host / slave provides several general-purpose input / output interfaces, and the general-purpose input / output interface resources are divided into two categories of uses: One part is used to configure the main field-programmable gate array of the calibration board on the calibration board; The other part interacts with the FIFO memory interface of the calibration board's main FPGA to further distribute data to the calibration FPGA, thereby enabling configuration operations on the calibration FPGA.

[0008] As a further aspect of the present invention: a register module for controlling the general-purpose input / output interface mode is designed on the host / slave control chip, thereby realizing the multiplexing function of the input / output interface, as detailed below: With the support of the input / output interface multiplexing mechanism, some general-purpose input / output interfaces are not only used for configuration operations, but also extended to support the communication functions of improved serial peripheral interfaces. The data from the digital board is first transmitted to the calibration field-programmable gate array (FPGA) via the serial peripheral interface. The calibration FPGA then interacts with the calibration board's main FPGA and finally transmits the data back to the intermediate FPGA on the system host / slave via a multiplexed general-purpose input / output interface. Furthermore, the intermediate-level field-programmable gate array uploads data to the central processing unit via a high-speed serial computer expansion bus standard interface, which is then received and processed by the host computer, thus completing the data interaction process of the entire multi-level field-programmable gate array.

[0009] As a further aspect of the present invention, the communication process for configuration is as follows: The intermediate-level field-programmable gate array on the master / slave device interacts with the central processing unit through the high-speed serial computer expansion bus standard interface, and is equipped with multiple registers internally; The host computer writes data to the register address, and the system extracts the lower 8 bits of the corresponding register and writes them to the first-in-first-out memory of the main field-programmable gate array of the configuration calibration board. By designing the serial configuration timing, the intermediate-level field-programmable gate array will output 1 bit of configuration data signal, 1 bit of configuration clock signal and 1 bit of configuration programming signal at its interface, and transmit these signals to the calibration board's main field-programmable gate array. The calibration board's main field-programmable gate array outputs a 1-bit configuration initialization signal and a 1-bit configuration completion signal, which are then sent back to the intermediate-level field-programmable gate array to complete the entire configuration.

[0010] As a further aspect of the present invention, the communication process for calibration is as follows: The intermediate-level field-programmable gate array integrates multiple registers for register read and write operations between the intermediate-level field-programmable gate array and the main field-programmable gate array of the calibration board; An improved serial peripheral interface master module is instantiated in an intermediate-level field-programmable gate array (FPGA). Inside this improved serial peripheral interface master module, the FPGA shifts the contents of the registers and transmits them serially.

[0011] The beneficial effects of this invention are as follows: This invention implements an improved SPI communication mechanism for data interaction between multi-level FPGAs. Using this mechanism, only one CPU needs to be added to the existing master control board to reliably and in real-time transmit the data collected by the calibration board back to the host computer, without requiring an additional CPU on each calibration board. Compared to the traditional SPI protocol, the improved SPI supports multi-level communication topologies, enabling chain-like multi-endpoint communication through a flexible master-slave mechanism. Furthermore, the number of interfaces in the improved SPI communication protocol can be flexibly changed to suit different application scenarios, exhibiting strong versatility and good portability.

[0012] The IO multiplexing solution effectively avoids redundant waste of hardware resources and PCB redesign, while the improved SPI communication greatly simplifies the system architecture, improves data transmission efficiency and scalability. The overall solution takes into account cost, reliability and ease of maintenance, and is more in line with the design specifications for mass production. Attached Figure Description

[0013] The invention will now be further described with reference to the accompanying drawings.

[0014] Figure 1 This is a schematic diagram of the overall framework of a design method based on multi-level FPGA communication of a test machine according to the present invention; Figure 2 This is a schematic diagram illustrating the data flow between multiple boards in an embodiment of the present invention; Figure 3 This is a communication diagram illustrating the configuration aspects in an embodiment of the present invention; Figure 4 This is a communication illustration for calibration in an embodiment of the present invention. Figure 1 ; Figure 5 This is a communication illustration for calibration in an embodiment of the present invention. Figure 2 ; Figure 6 This is a schematic diagram of the I / O multiplexing structure in an embodiment of the present invention. Detailed Implementation

[0015] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0016] The overall frame of the testing machine of the present invention is as follows Figure 1 As shown, the entire design is divided into four areas: A, B, C, and D. Each area is equipped with eight HSU320 digital boards and an optional PSU power supply board. The signals from the digital and power boards are partially connected to the backplane (BP Board) and partially to the motherboard. Areas A and B are synchronized using a single synchronization board with a CPU (SCM024 Master); similarly, areas C and D are synchronized using a single synchronization board with a CPU (SCM024 Slave). AC calibration is required for 32 of the digital boards.

[0017] like Figure 2As shown, the general purpose input / output (GPIO) ports on the master / slave (SCM board) are first connected to the intermediate adapter board (MBJ board) via the backplane (BP board), then connected to the mother board via the intermediate adapter board, and subsequently connected to the interface board (LIF CON) of the calibration board via a cable (HI-FIX cable), finally transmitting the signal to the calibration board's main field-programmable gate array (CT FPGA). The calibration board's main CT FPGA communicates with 16 calibration FPGAs (CAL FPGAs). Each calibration FPGA can calibrate the digital signals of two digital boards (HSU320), each digital board (HSU320) corresponding to 640 channels (640ch).

[0018] The SCM board provides 32 available general-purpose input / output (GPIO) ports. These GPIO resources are divided into two main uses: one part is used to configure the calibration board master field-programmable gate array (CT FPGA) on the calibration board; the other part interacts with the CT FPGA's first-in-first-out (FIFO) memory interface to further distribute data to 16 calibration field-programmable gate arrays (CAL FPGAs), thereby enabling configuration operations on the calibration field-programmable gate arrays (CAL FPGAs).

[0019] To improve the utilization of general purpose input / output interface (GPIO) resources, reduce device costs, and avoid the additional expenses incurred by replacing control chips and redesigning printed circuit boards (PCBs), we designed a register module inside the control chip (intermediate level field programmable gate array, MID FPGA) of the master / slave (SCM board) to control the mode of general purpose input / output interface (GPIO), thereby realizing the multiplexing function of input / output interface (IO port).

[0020] With the support of input / output interface (I / O) multiplexing mechanisms, some general-purpose I / O interfaces are not only used for configuration operations, but also extended to support improved serial peripheral interface communication functions. Data from the digital board (HSU320) is first transmitted to the calibration field-programmable gate array (CAL FPGA) through this improved serial peripheral interface communication method. The calibration field-programmable gate array then interacts with the calibration board's master field-programmable gate array (CT FPGA), and finally transmits the data back to the intermediate-level field-programmable gate array (MIDFPGA) on the master / slave (SCM board) through the multiplexed general-purpose I / O interface. Subsequently, the intermediate-level field-programmable gate array uploads the data to the central processing unit through the high-speed serial computer extended bus standard interface, and finally receives and processes it on the host computer (PC), thus completing the entire multi-level field-programmable gate array data interaction process.

[0021] This design not only meets the multifunctional needs under limited general-purpose input / output interface resources, but also ensures the efficiency and scalability of the system communication process.

[0022] The present invention also specifically includes the following three aspects: 1. First, let's discuss communication configuration: like Figure 3 As shown, the intermediate-level field-programmable gate array (MID FPGA) on the master / slave (SCM board) can interact with the central processing unit (CPU) through the high-speed serial computer expansion bus standard (PCIe) interface. It is configured with multiple registers, among which the register address used to configure the calibration board master field-programmable gate array (CT FPGA) is 0x0000_0804. The host computer (PC) writes data to this address, and the system extracts the lower 8 bits of the register and writes them into the first-in-first-out (CFCT) memory of the main field-programmable gate array (CFCT FIFO) of the calibration board. By designing the slave serial configuration timing, the MID FPGA outputs a 1-bit configuration data signal (CONF_DATA, corresponding to the general purpose input / output interface GPIO

[31] ), a 1-bit configuration clock signal (CONF_DCLK, corresponding to GPIO

[27] ), and a 1-bit configuration programming signal (CONF_nPROGRAM, corresponding to GPIO

[23] ) on its interface and transmits these signals to the CT FPGA of the calibration board. At the same time, the CT FPGA outputs a 1-bit configuration initialization signal (CONF_nINIT, corresponding to GPIO

[24] ) and a 1-bit configuration completion signal (CONF_DONE, corresponding to GPIO

[28] ) and sends them back to the MID FPGA. At this point, the configuration work for the CT FPGA is completed.

[0023] 2. Secondly, there is communication regarding calibration: In the entire system, only the master / slave (SCM board) integrates a central processing unit (CPU). The host computer (PC) and this CPU communicate via Gigabit Ethernet. Therefore, if the calibration board's main field-programmable gate array (CT FPGA) and calibration field-programmable gate array (CAL FPGA) need to interact with the host computer (PC), the communication process must be completed through an intermediate-level field-programmable gate array (MID FPGA). In this multi-level communication architecture, the improved Serial Peripheral Interface (SPI) communication protocol of this invention plays a crucial role, efficiently supporting data transmission between multiple endpoints.

[0024] like Figure 4 and Figure 5 As shown, the intermediate-level field-programmable gate array (MID FPGA) integrates multiple registers for control and data interaction. Specifically, the CT_ADDR register (address 0x0000_0944), the CT_WDAT register (address 0x0000_0948), and the CT_RDAT register (address 0x0000_0960) are dedicated to register read / write operations between the MID FPGA and the calibration board's main field-programmable gate array (CT FPGA). To implement this communication function, a self-designed improved serial peripheral interface master module (SPIMx) is instantiated within the MID FPGA. Within this improved SPIMx, the MID FPGA shifts the contents of the CT_ADDR and CT_WDAT registers and transmits them serially.

[0025] Specifically: the highest bit of the CT_ADDR register serves as the operation type flag, clearly indicating whether the operation is a write or read operation; the remaining bits of the CT_ADDR register represent the address of the target register; and the CT_WDAT register stores the actual data to be written to the calibration board's main field-programmable gate array (CT FPGA) register. The shifted data is output to the calibration board's main field-programmable gate array (CT FPGA) through the following four general purpose input / output (GPIO) signal lines: Calibrate the synchronization / chip select signal (CAL_nSYNC, corresponding to the general-purpose input / output interface GPIO[0]); calibrate the serial clock signal (CAL_SCLK, corresponding to the general-purpose input / output interface GPIO[3]); calibrate the master transmit / slave receive line (CAL_SDI, corresponding to the general-purpose input / output interface GPIO[4]); calibrate the master receive / slave transmit line (CAL_SDO, corresponding to the general-purpose input / output interface GPIO[7]).

[0026] The calibration master receive / slave transmit line (CAL_SDO) is the data return signal from the calibration board's master field-programmable gate array (CTFPGA) to the intermediate-level field-programmable gate array (MID FPGA), and its bit width is configurable. In this design, due to limited general-purpose input / output interface (GPIO) resources, the calibration master receive / slave transmit line (CAL_SDO) is set to 1-bit transmission. Although this affects the transmission rate to some extent, it still meets the current system's data bandwidth requirements. On the calibration board's master field-programmable gate array (CTFPGA) side, a corresponding serial peripheral interface slave module (SPISx) is instantiated. This module is responsible for receiving serial signals from the serial peripheral interface master module (SPIMx), correctly concatenating and parsing the serial data into complete register addresses and data, and ultimately realizing write or read operations on the internal registers of the calibration board's master field-programmable gate array (CTFPGA).

[0027] Similarly, if the intermediate-level field-programmable gate array (MID FPGA) writes the corresponding address and data to the CAL_ADD register at address 0x0000_0901 and the CAL_WDAT register at address 0x0000_0902 of the calibration board's main field-programmable gate array (CT FPGA), then the 16 serial peripheral interface master modules (SPIMx) instantiated by the calibration board's main field-programmable gate array (CT FPGA) can write data to the registers in the 16 calibration field-programmable gate arrays (CAL FPGA) respectively (each of the 16 calibration field-programmable gate arrays (CAL FPGA) instantiates a serial peripheral interface slave module (SPISx) to receive serial data and parse it into register address and data, consistent with the above principle). Similarly, the 16 calibration field-programmable gate arrays (CAL FPGAs) transmit data back to the calibration board's main field-programmable gate array (CT FPGA) at addresses 0x0000_0908, 0x0000_0909, ..., 0x0000_0917, specifically to the 16 registers CAL_RDAT0, CAL_RDAT1, ..., CAL_RDAT15. Through the improved Serial Peripheral Interface (SPI) communication protocol, with only one central processing unit (CPU), it is possible to write to or read from the registers of multiple levels of FPGAs, enabling control and data interaction for the entire system. The design logic is clear, and the code has high reusability.

[0028] While the improved Serial Peripheral Interface (SPI) communication protocol described above enables precise control of registers in multi-level Field Programmable Gate Arrays (FPGAs) (such as calibration FPGAs (CAL FPGAs) and calibration board master FPGAs (CTFPGAs)), relying solely on register read / write operations is inefficient for large-scale data transmission and cannot meet calibration bandwidth requirements. Especially in the current system architecture, each calibration FPGA (CAL FPGA) corresponds to two digital boards (HSU320), generating a large amount of data during calibration operations, reaching 32 bits × 640 channels. Therefore, a more efficient transmission mechanism is necessary.

[0029] To address this, the present invention incorporates a data exchange mechanism based on First-In-First-Out (FIFO) memory to achieve efficient backhaul of large volumes of calibration data from the calibration field-programmable gate array (CAL FPGA) to the intermediate-level field-programmable gate array (MID FPGA). Within the calibration field-programmable gate array (CAL FPGA), a dedicated multi-channel transmission (MT) control module is designed. This module, controlled by an internal state machine, divides each 32-bit calibration data into eight sub-transmissions, transmitting four bits of data at a time. The transmission is accomplished using the following signal lines: Serial Peripheral Interface Transmission Control Signal (SPI_TCT): Transmission control signal (SPI_FCA in the calibration board's main field-programmable gate array (CT FPGA)); Serial peripheral interface data transmission lines (SPI_DCT[3:0]): Data transmission lines (SPI_DCA[3:0] in the calibration board master field programmable gate array (CT FPGA)); Serial Peripheral Interface Data Read Enable Signal (SPI_FCT): The data read enable signal (SPI_TCA in the calibration board's main field-programmable gate array (CT FPGA)) is used to indicate that the target calibration data first-in-first-out memory (MRCALFIFO, FIFO1 to FIFO16) is not full and data can be received.

[0030] The above signals, when used in combination, enable high-speed data writing from the calibration field-programmable gate array (CAL FPGA) to the calibration data first-in-first-out memory (MRCAL FIFO) inside the calibration board's main field-programmable gate array (CT FPGA).

[0031] Subsequently, to further transmit this data back to the intermediate-level field-programmable gate array (MID FPGA) and upload it to the host computer (PC), the system uses the CAL_SELECT register with control address 0x0000_0904 to select the target calibration field-programmable gate array (CAL FPGA) from which the data needs to be read. Data feedback is accomplished through the following general-purpose input / output interface (GPIO port) signals: Data write enable signal (RF_WEN, corresponding to general-purpose input / output interface GPIO

[12] , and SPI_TSC in the calibration board main field programmable gate array (CT FPGA): data write enable signal; data write channel (RF_WEQ, corresponding to general-purpose input / output interface GPIO

[15] , GPIO

[16] , GPIO

[19] , GPIO

[20] , and SPI_DSC[3:0] in the calibration board main field programmable gate array (CT FPGA): data write channel; calibration data first-in-first-out memory not full indicator signal (CT_REN, corresponding to general-purpose input / output interface GPIO

[11] , and SPI_FSC in the calibration board main field programmable gate array (CT FPGA): calibration data first-in-first-out memory 0 (MRCAL FIFO0) in the system control module board (SCM board) is not full, used to notify the calibration board main field programmable gate array (CT FPGA) that it can send data to the intermediate level field programmable gate array (MID FPGA).

[0032] Upon receiving the enable signal, the calibration board's main field-programmable gate array (CT FPGA) reads calibration data from the selected calibration data first-in-first-out (MRCAL FIFO) of the CAL FPGA and transmits the data to the intermediate-level field-programmable gate array (MID FPGA) via the aforementioned signal lines. Finally, this returned calibration data is sequentially stored in registers at addresses 0x0010_0000, 0x0010_0004, ..., 0x0010_0280 of the MID FPGA. The host computer (PC) can then read out a large batch of calibration data from this area at once via the high-speed serial computer expansion bus standard (PCIe) interface for subsequent analysis and processing.

[0033] 3. Finally, there is the multiplexing of I / O ports: Combination Figure 4 and Figure 5It is known that by using the improved serial peripheral interface (SPI) communication protocol, read and write operations on the registers of each level of field programmable gate array (FPGA) can be realized. Specifically, when “CF” is written from the host computer (PC) to the general input / output interface mode register (GPIO MODE register, address 0x0000_067c) of the intermediate-level field-programmable gate array (MID FPGA), the general input / output interface (GPIO port) will switch to configuration function: among which, the general input / output interface GPIO

[11] is used as the first write valid signal (WF_VLD_SD); the general input / output interfaces GPIO

[15] , GPIO

[16] , GPIO

[19] , and GPIO

[20] are used as the first write data signal (WF_RDQ_SD[3:0]) to write data to the second configuration calibration first-in-first-out memory (CFCAL FIFO2) of the calibration board main field-programmable gate array (CT FPGA) to complete the configuration of the calibration field-programmable gate array (CAL FPGA); the general input / output interface GPIO

[12] is used as the first read enable signal (WF_REN) to characterize the CFCAL in the CT FPGA. When FIFO2 is empty, data can be requested from the first configuration calibration first-in-first-out memory (CFCAL FIFO1) of the MID FPGA.

[0034] If “CA” is written to the GPIO MODE register, the GPIO port is switched to calibration function: At this time, the general-purpose input / output interface GPIO

[11] is used as the system control module board calibration data first-in-first-out memory not full indication signal (CT_REN), which is used to indicate that the calibration data first-in-first-out memory 0 (MRCAL FIFO0) in the MID FPGA is empty, and can request data from the calibration data first-in-first-out memory 1-15 (MRCAL FIFO1-15) of the CT FPGA; the general-purpose input / output interfaces GPIO

[15] , GPIO

[16] , GPIO

[19] , and GPIO

[20] are used as data writing channels (RF_WDQ[3:0]), and the general-purpose input / output interface GPIO

[12] is used as the data write enable signal (RF_REN). These two signals work together to write the calibration data into the MRCAL FIFO0 of the MID FPGA.

[0035] Therefore, for MID FPGA, GPIO ports are sometimes used as output signals and sometimes as input signals. The core component that controls the input / output direction of GPIO ports is the general purpose input / output interface direction register (GPIO DIRECTION register, address 0x0000_0644): writing "1" to this register indicates that the corresponding GPIO port is an output signal; writing "0" indicates that the corresponding GPIO port is an input signal.

[0036] If no data is written to the GPIO MODE register, the GPIO port will default to normal GPIO mode. At this time, the general purpose input / output interface write data register (GPIO WDATA register, address 0x0000_0640) is used to control the output value of the GPIO port to be "1" or "0"; by reading the value of the general purpose input / output interface read data register (GPIO RDATA register, address 0x0000_0648), the input value of the GPIO port can be obtained as "1" or "0".

[0037] In addition, to ensure consistency between communication and functional logic, the configuration of the mode selection register (MODESELECT register, address 0x0000_091F) in the CT FPGA must be completely consistent with the configuration of the GPIO MODE register in the MID FPGA.

[0038] This mechanism fully leverages the multiplexing capability of GPIO ports, significantly reducing the need for independent signal lines. In systems with limited input / output (IO) resources, it can provide flexible and efficient data and control signal interaction capabilities.

[0039] The foregoing has provided a detailed description of one embodiment of the present invention, but this description is merely a preferred embodiment and should not be construed as limiting the scope of the invention. All equivalent variations and modifications made within the scope of the present invention should still fall within the scope of the present invention.

Claims

1. A design method based on multi-level FPGA communication of a test machine, characterized in that, Includes the following steps: Define the board area, and set up a backplane and a motherboard for each board area; Each board area is configured with a preset number of digital boards and their matching power boards, wherein the signals of the digital boards are respectively plugged into the backplane and motherboard of the corresponding board area. All board areas are divided into two consecutive areas, which are defined as the master area and the slave area respectively. The board areas in the master area share a synchronization board with a CPU for synchronization, and the synchronization board is defined as the master. The board areas in the slave area share a synchronization board with a CPU for synchronization, and the synchronization board is defined as the slave. The general-purpose input / output interfaces on the host / slave are first connected to the intermediate adapter board via the backplane, then connected to the motherboard via the intermediate adapter board, and then connected to the interface board of the calibration board via cables, finally reaching the main field-programmable gate array of the calibration board.

2. The design method based on multi-level FPGA communication of a test machine according to claim 1, characterized in that, The calibration board's main field-programmable gate array communicates with 16 calibration field-programmable gate arrays. Each calibration field-programmable gate array can calibrate the digital signals of two digital boards, and each digital board corresponds to 640 channels.

3. The design method based on multi-level FPGA communication of a test machine according to claim 1, characterized in that, The host / slave provides several general-purpose input / output interfaces, which are divided into two categories: One part is used to configure the main field-programmable gate array of the calibration board on the calibration board; The other part interacts with the FIFO memory interface of the calibration board's main FPGA to further distribute data to the calibration FPGA, thereby enabling configuration operations on the calibration FPGA.

4. The design method based on multi-level FPGA communication of a test machine according to claim 3, characterized in that, A register module for controlling the general-purpose input / output interface mode is designed on the host / slave control chip to realize the multiplexing function of the input / output interface, as detailed below: With the support of input / output interface multiplexing mechanism, some general-purpose input / output interfaces are not only used for configuration operations, but also extended to support improved serial peripheral interface communication functions; The data from the digital board is first transmitted to the calibration field-programmable gate array (FPGA) via the serial peripheral interface. The calibration FPGA then interacts with the calibration board's main FPGA and finally transmits the data back to the intermediate FPGA on the system host / slave via a multiplexed general-purpose input / output interface. Furthermore, the intermediate-level field-programmable gate array uploads data to the central processing unit via a high-speed serial computer expansion bus standard interface, which is then received and processed by the host computer, thus completing the data interaction process of the entire multi-level field-programmable gate array.

5. The design method based on multi-level FPGA communication of a test machine according to claim 1, characterized in that, The specific communication process for configuration is as follows: The intermediate-level field-programmable gate array on the master / slave device interacts with the central processing unit through the high-speed serial computer expansion bus standard interface, and is equipped with multiple registers internally; The host computer writes data to the register address, and the system extracts the lower 8 bits of the corresponding register and writes them to the first-in-first-out memory of the main field-programmable gate array of the configuration calibration board. By designing the serial configuration timing, the intermediate-level field-programmable gate array will output 1 bit of configuration data signal, 1 bit of configuration clock signal and 1 bit of configuration programming signal at its interface, and transmit these signals to the calibration board's main field-programmable gate array. The calibration board's main field-programmable gate array outputs a 1-bit configuration initialization signal and a 1-bit configuration completion signal, which are then sent back to the intermediate-level field-programmable gate array to complete the entire configuration.

6. The design method based on multi-level FPGA communication of a test machine according to claim 1, characterized in that, The specific communication process for calibration is as follows: The intermediate-level field-programmable gate array integrates multiple registers for register read and write operations between the intermediate-level field-programmable gate array and the main field-programmable gate array of the calibration board; An improved serial peripheral interface master module is instantiated in an intermediate-level field-programmable gate array (FPGA). Inside this improved serial peripheral interface master module, the FPGA shifts the contents of the registers and transmits them serially.

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